2025-04-12 23:24:42 +03:00
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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/// Handler for floating-point load, store, and control operations (D9 opcode)
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/// </summary>
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2025-04-13 23:06:52 +03:00
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public class LoadStoreControlHandler : InstructionHandler
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2025-04-12 23:24:42 +03:00
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{
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// D9 opcode - load, store, and control operations
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private static readonly string[] Mnemonics =
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[
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"fld",
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"??",
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"fst",
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"fstp",
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"fldenv",
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"fldcw",
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"fnstenv",
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"fnstcw"
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];
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/// <summary>
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/// Initializes a new instance of the LoadStoreControlHandler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public LoadStoreControlHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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{
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}
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/// <summary>
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/// Checks if this handler can decode the given opcode
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/// </summary>
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/// <param name="opcode">The opcode to check</param>
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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return opcode == 0xD9;
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}
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/// <summary>
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/// Decodes a floating-point instruction for load, store, and control operations
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/// </summary>
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/// <param name="opcode">The opcode of the instruction</param>
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/// <param name="instruction">The instruction object to populate</param>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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{
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int position = Decoder.GetPosition();
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if (position >= Length)
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{
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return false;
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}
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
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// Set the mnemonic based on the opcode and reg field
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instruction.Mnemonic = Mnemonics[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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{
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// Different operand types based on the instruction
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
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{
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2025-04-12 23:33:40 +03:00
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// Keep the dword ptr prefix from ModRMDecoder
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instruction.Operands = destOperand;
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}
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else // fldenv, fldcw, fnstenv, fnstcw
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{
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if (reg == RegisterIndex.Di) // fldcw - should use word ptr
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{
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instruction.Operands = destOperand.Replace("dword ptr", "word ptr");
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}
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else // fldenv, fnstenv, fnstcw
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{
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// Remove the dword ptr prefix for other control operations
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instruction.Operands = destOperand.Replace("dword ptr ", "");
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}
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}
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}
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else // Register operand (ST(i))
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{
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// Special handling for D9C0-D9FF (register-register operations)
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if (reg == RegisterIndex.A) // FLD ST(i)
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{
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instruction.Operands = $"st({(int)rm})";
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}
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else if (reg == RegisterIndex.B) // FXCH ST(i)
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{
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instruction.Mnemonic = "fxch";
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instruction.Operands = $"st({(int)rm})";
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}
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else if (reg == RegisterIndex.Si)
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{
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// D9E0-D9EF special instructions
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switch (rm)
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{
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case RegisterIndex.A:
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instruction.Mnemonic = "fchs";
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instruction.Operands = "";
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break;
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case RegisterIndex.B:
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instruction.Mnemonic = "fabs";
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instruction.Operands = "";
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break;
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case RegisterIndex.Si:
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instruction.Mnemonic = "ftst";
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instruction.Operands = "";
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break;
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case RegisterIndex.Di:
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instruction.Mnemonic = "fxam";
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instruction.Operands = "";
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break;
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default:
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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break;
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}
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}
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else if (reg == RegisterIndex.Di)
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{
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// D9F0-D9FF special instructions
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switch (rm)
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{
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case RegisterIndex.A:
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instruction.Mnemonic = "f2xm1";
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instruction.Operands = "";
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break;
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case RegisterIndex.B:
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instruction.Mnemonic = "fyl2x";
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instruction.Operands = "";
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break;
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case RegisterIndex.C:
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instruction.Mnemonic = "fptan";
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instruction.Operands = "";
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break;
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case RegisterIndex.D:
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instruction.Mnemonic = "fpatan";
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instruction.Operands = "";
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break;
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case RegisterIndex.Si:
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instruction.Mnemonic = "fxtract";
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instruction.Operands = "";
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break;
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case RegisterIndex.Di:
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instruction.Mnemonic = "fprem1";
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instruction.Operands = "";
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break;
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case RegisterIndex.Sp:
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instruction.Mnemonic = "fdecstp";
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instruction.Operands = "";
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break;
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case RegisterIndex.Bp:
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instruction.Mnemonic = "fincstp";
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instruction.Operands = "";
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break;
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default:
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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break;
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}
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}
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else if (reg == RegisterIndex.Sp)
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{
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// D9F0-D9FF more special instructions
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switch (rm)
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{
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case RegisterIndex.A:
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instruction.Mnemonic = "fprem";
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instruction.Operands = "";
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break;
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case RegisterIndex.B:
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instruction.Mnemonic = "fyl2xp1";
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instruction.Operands = "";
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break;
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case RegisterIndex.C:
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instruction.Mnemonic = "fsqrt";
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instruction.Operands = "";
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break;
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case RegisterIndex.D:
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instruction.Mnemonic = "fsincos";
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instruction.Operands = "";
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break;
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case RegisterIndex.Si:
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instruction.Mnemonic = "frndint";
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instruction.Operands = "";
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break;
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case RegisterIndex.Di:
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instruction.Mnemonic = "fscale";
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instruction.Operands = "";
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break;
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case RegisterIndex.Sp:
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instruction.Mnemonic = "fsin";
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instruction.Operands = "";
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break;
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case RegisterIndex.Bp:
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instruction.Mnemonic = "fcos";
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instruction.Operands = "";
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break;
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default:
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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break;
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}
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}
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}
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return true;
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}
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}
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