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61 lines
1.8 KiB
CSV
61 lines
1.8 KiB
CSV
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# Group 3 instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# Group 3 instructions (opcode F6-F7 /0-/7)
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# TEST, NOT, NEG, MUL, IMUL, DIV, IDIV
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# Group 3 with 8-bit register/memory (opcode F6)
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# TEST r/m8, imm8 (opcode F6 /0)
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F6C042;[{ "Type": "Test", "Operands": ["al", "0x42"] }]
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# NOT r/m8 (opcode F6 /2)
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F6D0;[{ "Type": "Not", "Operands": ["al"] }]
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# NEG r/m8 (opcode F6 /3)
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F6D8;[{ "Type": "Neg", "Operands": ["al"] }]
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# MUL r/m8 (opcode F6 /4)
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F6E0;[{ "Type": "Mul", "Operands": ["al"] }]
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# IMUL r/m8 (opcode F6 /5)
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F6E8;[{ "Type": "Imul", "Operands": ["al"] }]
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# DIV r/m8 (opcode F6 /6)
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F6F0;[{ "Type": "Div", "Operands": ["al"] }]
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# IDIV r/m8 (opcode F6 /7)
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F6F8;[{ "Type": "Idiv", "Operands": ["al"] }]
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# Group 3 with 32-bit register/memory (opcode F7)
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# TEST r/m32, imm32 (opcode F7 /0)
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F7C078563412;[{ "Type": "Test", "Operands": ["eax", "0x12345678"] }]
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# NOT r/m32 (opcode F7 /2)
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F7D0;[{ "Type": "Not", "Operands": ["eax"] }]
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# NEG r/m32 (opcode F7 /3)
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F7D8;[{ "Type": "Neg", "Operands": ["eax"] }]
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# MUL r/m32 (opcode F7 /4)
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F7E0;[{ "Type": "Mul", "Operands": ["eax"] }]
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# IMUL r/m32 (opcode F7 /5)
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F7E8;[{ "Type": "Imul", "Operands": ["eax"] }]
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# DIV r/m32 (opcode F7 /6)
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F7F0;[{ "Type": "Div", "Operands": ["eax"] }]
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# IDIV r/m32 (opcode F7 /7)
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F7F8;[{ "Type": "Idiv", "Operands": ["eax"] }]
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# Group 3 with memory operands
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F6042542;[{ "Type": "Test", "Operands": ["byte ptr [eax]", "0x42"] }]
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F7042578563412;[{ "Type": "Test", "Operands": ["dword ptr [eax]", "0x12345678"] }]
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F71425;[{ "Type": "Not", "Operands": ["dword ptr [eax]"] }]
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F71C25;[{ "Type": "Neg", "Operands": ["dword ptr [eax]"] }]
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F72425;[{ "Type": "Mul", "Operands": ["dword ptr [eax]"] }]
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F72C25;[{ "Type": "Imul", "Operands": ["dword ptr [eax]"] }]
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F73425;[{ "Type": "Div", "Operands": ["dword ptr [eax]"] }]
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F73C25;[{ "Type": "Idiv", "Operands": ["dword ptr [eax]"] }]
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