2025-04-15 22:20:46 +03:00
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# SHR instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# SHR r/m8, 1 (opcode D0 /5)
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D0E8;[{ "Type": "Shr", "Operands": ["al", "0x01"] }]
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D0EB;[{ "Type": "Shr", "Operands": ["bl", "0x01"] }]
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# SHR r/m32, 1 (opcode D1 /5)
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D1E8;[{ "Type": "Shr", "Operands": ["eax", "0x01"] }]
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D1EB;[{ "Type": "Shr", "Operands": ["ebx", "0x01"] }]
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# SHR r/m8, CL (opcode D2 /5)
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D2E8;[{ "Type": "Shr", "Operands": ["al", "cl"] }]
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D2EB;[{ "Type": "Shr", "Operands": ["bl", "cl"] }]
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# SHR r/m32, CL (opcode D3 /5)
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D3E8;[{ "Type": "Shr", "Operands": ["eax", "cl"] }]
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D3EB;[{ "Type": "Shr", "Operands": ["ebx", "cl"] }]
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# SHR r/m8, imm8 (opcode C0 /5)
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C0E805;[{ "Type": "Shr", "Operands": ["al", "0x05"] }]
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C0EB05;[{ "Type": "Shr", "Operands": ["bl", "0x05"] }]
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# SHR r/m32, imm8 (opcode C1 /5)
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C1E805;[{ "Type": "Shr", "Operands": ["eax", "0x05"] }]
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C1EB05;[{ "Type": "Shr", "Operands": ["ebx", "0x05"] }]
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2025-04-17 21:35:49 +03:00
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# SHR with memory operands (fixed)
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D06810;[{ "Type": "Shr", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
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D328;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "cl"] }]
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C12805;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "0x05"] }]
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