From 0a2d551cb41f239fa246a306583ee94b08244a91 Mon Sep 17 00:00:00 2001 From: bird_egop Date: Tue, 15 Apr 2025 22:40:09 +0300 Subject: [PATCH] Enhanced test coverage for floating-point instructions --- X86DisassemblerTests/TestData/fpu_tests.csv | 253 +++++++++++++++++++- 1 file changed, 250 insertions(+), 3 deletions(-) diff --git a/X86DisassemblerTests/TestData/fpu_tests.csv b/X86DisassemblerTests/TestData/fpu_tests.csv index 6736007..7fb94ce 100644 --- a/X86DisassemblerTests/TestData/fpu_tests.csv +++ b/X86DisassemblerTests/TestData/fpu_tests.csv @@ -4,88 +4,329 @@ RawBytes;Instructions # Basic FPU instructions -# FNSTSW AX - Store FPU status word in AX without checking for pending unmasked exceptions -DFE0;[{ "Type": "Fnstsw", "Operands": ["ax"] }] - # FADD - Add floating point values +# ST(0), ST(i) form (D8 C0+i) D8C0;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(0)"] }] D8C1;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(1)"] }] +D8C2;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(2)"] }] +D8C3;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(3)"] }] +D8C4;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(4)"] }] +D8C5;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(5)"] }] +D8C6;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(6)"] }] +D8C7;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(7)"] }] + +# ST(i), ST(0) form (DC C0+i) DCC0;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(0)"] }] DCC1;[{ "Type": "Fadd", "Operands": ["ST(1)", "ST(0)"] }] +DCC2;[{ "Type": "Fadd", "Operands": ["ST(2)", "ST(0)"] }] +DCC3;[{ "Type": "Fadd", "Operands": ["ST(3)", "ST(0)"] }] +DCC4;[{ "Type": "Fadd", "Operands": ["ST(4)", "ST(0)"] }] +DCC5;[{ "Type": "Fadd", "Operands": ["ST(5)", "ST(0)"] }] +DCC6;[{ "Type": "Fadd", "Operands": ["ST(6)", "ST(0)"] }] +DCC7;[{ "Type": "Fadd", "Operands": ["ST(7)", "ST(0)"] }] + +# Memory operands D8042510000000;[{ "Type": "Fadd", "Operands": ["dword ptr [0x10]"] }] DC042510000000;[{ "Type": "Fadd", "Operands": ["qword ptr [0x10]"] }] +D80425;[{ "Type": "Fadd", "Operands": ["dword ptr [eax]"] }] +DC0425;[{ "Type": "Fadd", "Operands": ["qword ptr [eax]"] }] +D8041D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebx]"] }] +DC041D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebx]"] }] +D8042D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebp]"] }] +DC042D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebp]"] }] + +# With segment override prefixes +26D80425;[{ "Type": "Fadd", "Operands": ["dword ptr es:[eax]"] }] +2ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr cs:[eax]"] }] +36D80425;[{ "Type": "Fadd", "Operands": ["dword ptr ss:[eax]"] }] +3ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr ds:[eax]"] }] +64D80425;[{ "Type": "Fadd", "Operands": ["dword ptr fs:[eax]"] }] +65D80425;[{ "Type": "Fadd", "Operands": ["dword ptr gs:[eax]"] }] + +# FADDP - Add floating point values and pop +DEC0;[{ "Type": "Faddp", "Operands": ["ST(0)", "ST(0)"] }] +DEC1;[{ "Type": "Faddp", "Operands": ["ST(1)", "ST(0)"] }] +DEC2;[{ "Type": "Faddp", "Operands": ["ST(2)", "ST(0)"] }] +DEC3;[{ "Type": "Faddp", "Operands": ["ST(3)", "ST(0)"] }] +DEC4;[{ "Type": "Faddp", "Operands": ["ST(4)", "ST(0)"] }] +DEC5;[{ "Type": "Faddp", "Operands": ["ST(5)", "ST(0)"] }] +DEC6;[{ "Type": "Faddp", "Operands": ["ST(6)", "ST(0)"] }] +DEC7;[{ "Type": "Faddp", "Operands": ["ST(7)", "ST(0)"] }] + +# FIADD - Add integer to floating point +DA042510000000;[{ "Type": "Fiadd", "Operands": ["dword ptr [0x10]"] }] +DE042510000000;[{ "Type": "Fiadd", "Operands": ["word ptr [0x10]"] }] +DA0425;[{ "Type": "Fiadd", "Operands": ["dword ptr [eax]"] }] +DE0425;[{ "Type": "Fiadd", "Operands": ["word ptr [eax]"] }] +DA041D;[{ "Type": "Fiadd", "Operands": ["dword ptr [ebx]"] }] +DE041D;[{ "Type": "Fiadd", "Operands": ["word ptr [ebx]"] }] +# Floating Point instruction tests (continued) +# Format: RawBytes;Instructions +RawBytes;Instructions # FSUB - Subtract floating point values +# ST(0), ST(i) form (D8 E0+i) D8E0;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(0)"] }] D8E1;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(1)"] }] +D8E2;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(2)"] }] +D8E3;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(3)"] }] +D8E4;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(4)"] }] +D8E5;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(5)"] }] +D8E6;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(6)"] }] +D8E7;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(7)"] }] + +# ST(i), ST(0) form (DC E8+i) DCE8;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(0)"] }] DCE9;[{ "Type": "Fsub", "Operands": ["ST(1)", "ST(0)"] }] +DCEA;[{ "Type": "Fsub", "Operands": ["ST(2)", "ST(0)"] }] +DCEB;[{ "Type": "Fsub", "Operands": ["ST(3)", "ST(0)"] }] +DCEC;[{ "Type": "Fsub", "Operands": ["ST(4)", "ST(0)"] }] +DCED;[{ "Type": "Fsub", "Operands": ["ST(5)", "ST(0)"] }] +DCEE;[{ "Type": "Fsub", "Operands": ["ST(6)", "ST(0)"] }] +DCEF;[{ "Type": "Fsub", "Operands": ["ST(7)", "ST(0)"] }] + +# Memory operands D8242510000000;[{ "Type": "Fsub", "Operands": ["dword ptr [0x10]"] }] DC242510000000;[{ "Type": "Fsub", "Operands": ["qword ptr [0x10]"] }] +D82425;[{ "Type": "Fsub", "Operands": ["dword ptr [eax]"] }] +DC2425;[{ "Type": "Fsub", "Operands": ["qword ptr [eax]"] }] + +# FSUBP - Subtract floating point values and pop +DEE8;[{ "Type": "Fsubp", "Operands": ["ST(0)", "ST(0)"] }] +DEE9;[{ "Type": "Fsubp", "Operands": ["ST(1)", "ST(0)"] }] +DEEA;[{ "Type": "Fsubp", "Operands": ["ST(2)", "ST(0)"] }] +DEEB;[{ "Type": "Fsubp", "Operands": ["ST(3)", "ST(0)"] }] + +# FISUB - Subtract integer from floating point +DA242510000000;[{ "Type": "Fisub", "Operands": ["dword ptr [0x10]"] }] +DE242510000000;[{ "Type": "Fisub", "Operands": ["word ptr [0x10]"] }] +DA2425;[{ "Type": "Fisub", "Operands": ["dword ptr [eax]"] }] +DE2425;[{ "Type": "Fisub", "Operands": ["word ptr [eax]"] }] # FSUBR - Subtract floating point values (reversed) +# ST(0), ST(i) form (D8 E8+i) D8E8;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(0)"] }] D8E9;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(1)"] }] +D8EA;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(2)"] }] +D8EB;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(3)"] }] + +# ST(i), ST(0) form (DC E0+i) DCE0;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(0)"] }] DCE1;[{ "Type": "Fsubr", "Operands": ["ST(1)", "ST(0)"] }] +DCE2;[{ "Type": "Fsubr", "Operands": ["ST(2)", "ST(0)"] }] +DCE3;[{ "Type": "Fsubr", "Operands": ["ST(3)", "ST(0)"] }] + +# Memory operands D82C2510000000;[{ "Type": "Fsubr", "Operands": ["dword ptr [0x10]"] }] DC2C2510000000;[{ "Type": "Fsubr", "Operands": ["qword ptr [0x10]"] }] +D82C25;[{ "Type": "Fsubr", "Operands": ["dword ptr [eax]"] }] +DC2C25;[{ "Type": "Fsubr", "Operands": ["qword ptr [eax]"] }] + +# FSUBRP - Subtract floating point values (reversed) and pop +DEE0;[{ "Type": "Fsubrp", "Operands": ["ST(0)", "ST(0)"] }] +DEE1;[{ "Type": "Fsubrp", "Operands": ["ST(1)", "ST(0)"] }] +DEE2;[{ "Type": "Fsubrp", "Operands": ["ST(2)", "ST(0)"] }] +DEE3;[{ "Type": "Fsubrp", "Operands": ["ST(3)", "ST(0)"] }] +# Floating Point instruction tests (continued) +# Format: RawBytes;Instructions +RawBytes;Instructions # FMUL - Multiply floating point values +# ST(0), ST(i) form (D8 C8+i) D8C8;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(0)"] }] D8C9;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(1)"] }] +D8CA;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(2)"] }] +D8CB;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(3)"] }] +D8CC;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(4)"] }] +D8CD;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(5)"] }] +D8CE;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(6)"] }] +D8CF;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(7)"] }] + +# ST(i), ST(0) form (DC C8+i) DCC8;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(0)"] }] DCC9;[{ "Type": "Fmul", "Operands": ["ST(1)", "ST(0)"] }] +DCCA;[{ "Type": "Fmul", "Operands": ["ST(2)", "ST(0)"] }] +DCCB;[{ "Type": "Fmul", "Operands": ["ST(3)", "ST(0)"] }] +DCCC;[{ "Type": "Fmul", "Operands": ["ST(4)", "ST(0)"] }] +DCCD;[{ "Type": "Fmul", "Operands": ["ST(5)", "ST(0)"] }] +DCCE;[{ "Type": "Fmul", "Operands": ["ST(6)", "ST(0)"] }] +DCCF;[{ "Type": "Fmul", "Operands": ["ST(7)", "ST(0)"] }] + +# Memory operands D80C2510000000;[{ "Type": "Fmul", "Operands": ["dword ptr [0x10]"] }] DC0C2510000000;[{ "Type": "Fmul", "Operands": ["qword ptr [0x10]"] }] +D80C25;[{ "Type": "Fmul", "Operands": ["dword ptr [eax]"] }] +DC0C25;[{ "Type": "Fmul", "Operands": ["qword ptr [eax]"] }] + +# FMULP - Multiply floating point values and pop +DEC8;[{ "Type": "Fmulp", "Operands": ["ST(0)", "ST(0)"] }] +DEC9;[{ "Type": "Fmulp", "Operands": ["ST(1)", "ST(0)"] }] +DECA;[{ "Type": "Fmulp", "Operands": ["ST(2)", "ST(0)"] }] +DECB;[{ "Type": "Fmulp", "Operands": ["ST(3)", "ST(0)"] }] + +# FIMUL - Multiply integer with floating point +DA0C2510000000;[{ "Type": "Fimul", "Operands": ["dword ptr [0x10]"] }] +DE0C2510000000;[{ "Type": "Fimul", "Operands": ["word ptr [0x10]"] }] +DA0C25;[{ "Type": "Fimul", "Operands": ["dword ptr [eax]"] }] +DE0C25;[{ "Type": "Fimul", "Operands": ["word ptr [eax]"] }] # FDIV - Divide floating point values +# ST(0), ST(i) form (D8 F0+i) D8F0;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(0)"] }] D8F1;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(1)"] }] +D8F2;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(2)"] }] +D8F3;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(3)"] }] +D8F4;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(4)"] }] +D8F5;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(5)"] }] +D8F6;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(6)"] }] +D8F7;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(7)"] }] + +# ST(i), ST(0) form (DC F8+i) DCF8;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(0)"] }] DCF9;[{ "Type": "Fdiv", "Operands": ["ST(1)", "ST(0)"] }] +DCFA;[{ "Type": "Fdiv", "Operands": ["ST(2)", "ST(0)"] }] +DCFB;[{ "Type": "Fdiv", "Operands": ["ST(3)", "ST(0)"] }] +DCFC;[{ "Type": "Fdiv", "Operands": ["ST(4)", "ST(0)"] }] +DCFD;[{ "Type": "Fdiv", "Operands": ["ST(5)", "ST(0)"] }] +DCFE;[{ "Type": "Fdiv", "Operands": ["ST(6)", "ST(0)"] }] +DCFF;[{ "Type": "Fdiv", "Operands": ["ST(7)", "ST(0)"] }] + +# Memory operands D8342510000000;[{ "Type": "Fdiv", "Operands": ["dword ptr [0x10]"] }] DC342510000000;[{ "Type": "Fdiv", "Operands": ["qword ptr [0x10]"] }] +D83425;[{ "Type": "Fdiv", "Operands": ["dword ptr [eax]"] }] +DC3425;[{ "Type": "Fdiv", "Operands": ["qword ptr [eax]"] }] +# Floating Point instruction tests (continued) +# Format: RawBytes;Instructions +RawBytes;Instructions + +# FDIVP - Divide floating point values and pop +DEF8;[{ "Type": "Fdivp", "Operands": ["ST(0)", "ST(0)"] }] +DEF9;[{ "Type": "Fdivp", "Operands": ["ST(1)", "ST(0)"] }] +DEFA;[{ "Type": "Fdivp", "Operands": ["ST(2)", "ST(0)"] }] +DEFB;[{ "Type": "Fdivp", "Operands": ["ST(3)", "ST(0)"] }] + +# FIDIV - Divide integer by floating point +DA342510000000;[{ "Type": "Fidiv", "Operands": ["dword ptr [0x10]"] }] +DE342510000000;[{ "Type": "Fidiv", "Operands": ["word ptr [0x10]"] }] +DA3425;[{ "Type": "Fidiv", "Operands": ["dword ptr [eax]"] }] +DE3425;[{ "Type": "Fidiv", "Operands": ["word ptr [eax]"] }] # FDIVR - Divide floating point values (reversed) +# ST(0), ST(i) form (D8 F8+i) D8F8;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(0)"] }] D8F9;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(1)"] }] +D8FA;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(2)"] }] +D8FB;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(3)"] }] + +# ST(i), ST(0) form (DC F0+i) DCF0;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(0)"] }] DCF1;[{ "Type": "Fdivr", "Operands": ["ST(1)", "ST(0)"] }] +DCF2;[{ "Type": "Fdivr", "Operands": ["ST(2)", "ST(0)"] }] +DCF3;[{ "Type": "Fdivr", "Operands": ["ST(3)", "ST(0)"] }] + +# Memory operands D83C2510000000;[{ "Type": "Fdivr", "Operands": ["dword ptr [0x10]"] }] DC3C2510000000;[{ "Type": "Fdivr", "Operands": ["qword ptr [0x10]"] }] +D83C25;[{ "Type": "Fdivr", "Operands": ["dword ptr [eax]"] }] +DC3C25;[{ "Type": "Fdivr", "Operands": ["qword ptr [eax]"] }] + +# FDIVRP - Divide floating point values (reversed) and pop +DEF0;[{ "Type": "Fdivrp", "Operands": ["ST(0)", "ST(0)"] }] +DEF1;[{ "Type": "Fdivrp", "Operands": ["ST(1)", "ST(0)"] }] +DEF2;[{ "Type": "Fdivrp", "Operands": ["ST(2)", "ST(0)"] }] +DEF3;[{ "Type": "Fdivrp", "Operands": ["ST(3)", "ST(0)"] }] + +# FIDIVR - Divide floating point by integer (reversed) +DA3C2510000000;[{ "Type": "Fidivr", "Operands": ["dword ptr [0x10]"] }] +DE3C2510000000;[{ "Type": "Fidivr", "Operands": ["word ptr [0x10]"] }] +DA3C25;[{ "Type": "Fidivr", "Operands": ["dword ptr [eax]"] }] +DE3C25;[{ "Type": "Fidivr", "Operands": ["word ptr [eax]"] }] # FLD - Load floating point value D9C0;[{ "Type": "Fld", "Operands": ["ST(0)"] }] D9C1;[{ "Type": "Fld", "Operands": ["ST(1)"] }] +D9C2;[{ "Type": "Fld", "Operands": ["ST(2)"] }] +D9C3;[{ "Type": "Fld", "Operands": ["ST(3)"] }] +D9C4;[{ "Type": "Fld", "Operands": ["ST(4)"] }] +D9C5;[{ "Type": "Fld", "Operands": ["ST(5)"] }] +D9C6;[{ "Type": "Fld", "Operands": ["ST(6)"] }] +D9C7;[{ "Type": "Fld", "Operands": ["ST(7)"] }] + +# Memory operands D9042510000000;[{ "Type": "Fld", "Operands": ["dword ptr [0x10]"] }] DD042510000000;[{ "Type": "Fld", "Operands": ["qword ptr [0x10]"] }] DB2C25;[{ "Type": "Fld", "Operands": ["tbyte ptr [eax]"] }] +D90425;[{ "Type": "Fld", "Operands": ["dword ptr [eax]"] }] +DD0425;[{ "Type": "Fld", "Operands": ["qword ptr [eax]"] }] +# Floating Point instruction tests (continued) +# Format: RawBytes;Instructions +RawBytes;Instructions # FST - Store floating point value D9D0;[{ "Type": "Fst", "Operands": ["ST(0)"] }] D9D1;[{ "Type": "Fst", "Operands": ["ST(1)"] }] +D9D2;[{ "Type": "Fst", "Operands": ["ST(2)"] }] +D9D3;[{ "Type": "Fst", "Operands": ["ST(3)"] }] +D9D4;[{ "Type": "Fst", "Operands": ["ST(4)"] }] +D9D5;[{ "Type": "Fst", "Operands": ["ST(5)"] }] +D9D6;[{ "Type": "Fst", "Operands": ["ST(6)"] }] +D9D7;[{ "Type": "Fst", "Operands": ["ST(7)"] }] + +# Memory operands D9142510000000;[{ "Type": "Fst", "Operands": ["dword ptr [0x10]"] }] DD142510000000;[{ "Type": "Fst", "Operands": ["qword ptr [0x10]"] }] +D91425;[{ "Type": "Fst", "Operands": ["dword ptr [eax]"] }] +DD1425;[{ "Type": "Fst", "Operands": ["qword ptr [eax]"] }] # FSTP - Store floating point value and pop D9D8;[{ "Type": "Fstp", "Operands": ["ST(0)"] }] D9D9;[{ "Type": "Fstp", "Operands": ["ST(1)"] }] +D9DA;[{ "Type": "Fstp", "Operands": ["ST(2)"] }] +D9DB;[{ "Type": "Fstp", "Operands": ["ST(3)"] }] +D9DC;[{ "Type": "Fstp", "Operands": ["ST(4)"] }] +D9DD;[{ "Type": "Fstp", "Operands": ["ST(5)"] }] +D9DE;[{ "Type": "Fstp", "Operands": ["ST(6)"] }] +D9DF;[{ "Type": "Fstp", "Operands": ["ST(7)"] }] + +# Memory operands D91C2510000000;[{ "Type": "Fstp", "Operands": ["dword ptr [0x10]"] }] DD1C2510000000;[{ "Type": "Fstp", "Operands": ["qword ptr [0x10]"] }] DB3C25;[{ "Type": "Fstp", "Operands": ["tbyte ptr [eax]"] }] +D91C25;[{ "Type": "Fstp", "Operands": ["dword ptr [eax]"] }] +DD1C25;[{ "Type": "Fstp", "Operands": ["qword ptr [eax]"] }] # FCOM - Compare floating point values D8D0;[{ "Type": "Fcom", "Operands": ["ST(0)"] }] D8D1;[{ "Type": "Fcom", "Operands": ["ST(1)"] }] +D8D2;[{ "Type": "Fcom", "Operands": ["ST(2)"] }] +D8D3;[{ "Type": "Fcom", "Operands": ["ST(3)"] }] +D8D4;[{ "Type": "Fcom", "Operands": ["ST(4)"] }] +D8D5;[{ "Type": "Fcom", "Operands": ["ST(5)"] }] +D8D6;[{ "Type": "Fcom", "Operands": ["ST(6)"] }] +D8D7;[{ "Type": "Fcom", "Operands": ["ST(7)"] }] + +# Memory operands D8142510000000;[{ "Type": "Fcom", "Operands": ["dword ptr [0x10]"] }] DC142510000000;[{ "Type": "Fcom", "Operands": ["qword ptr [0x10]"] }] +D81425;[{ "Type": "Fcom", "Operands": ["dword ptr [eax]"] }] +DC1425;[{ "Type": "Fcom", "Operands": ["qword ptr [eax]"] }] # FCOMP - Compare floating point values and pop D8D8;[{ "Type": "Fcomp", "Operands": ["ST(0)"] }] D8D9;[{ "Type": "Fcomp", "Operands": ["ST(1)"] }] +D8DA;[{ "Type": "Fcomp", "Operands": ["ST(2)"] }] +D8DB;[{ "Type": "Fcomp", "Operands": ["ST(3)"] }] +D8DC;[{ "Type": "Fcomp", "Operands": ["ST(4)"] }] +D8DD;[{ "Type": "Fcomp", "Operands": ["ST(5)"] }] +D8DE;[{ "Type": "Fcomp", "Operands": ["ST(6)"] }] +D8DF;[{ "Type": "Fcomp", "Operands": ["ST(7)"] }] + +# Memory operands D81C2510000000;[{ "Type": "Fcomp", "Operands": ["dword ptr [0x10]"] }] DC1C2510000000;[{ "Type": "Fcomp", "Operands": ["qword ptr [0x10]"] }] +D81C25;[{ "Type": "Fcomp", "Operands": ["dword ptr [eax]"] }] +DC1C25;[{ "Type": "Fcomp", "Operands": ["qword ptr [eax]"] }] # FCOMPP - Compare floating point values and pop twice DED9;[{ "Type": "Fcompp", "Operands": [] }] @@ -107,3 +348,9 @@ D9E5;[{ "Type": "Fxam", "Operands": [] }] # FNINIT - Initialize FPU without checking for pending unmasked exceptions DBE3;[{ "Type": "Fninit", "Operands": [] }] + +# FNSTSW AX - Store FPU status word in AX without checking for pending unmasked exceptions +DFE0;[{ "Type": "Fnstsw", "Operands": ["ax"] }] + +# FSTSW AX - Store FPU status word in AX +9BDFE0;[{ "Type": "Fstsw", "Operands": ["ax"] }]