mirrors/ParkanPlayground
0
Fork 0
mirror of https://github.com/sampletext32/ParkanPlayground.git synced 2025-05-19 11:51:17 +03:00
Code Issues Releases Activity

Simplified Int32OperationHandler by replacing complex if-else logic with a dictionary-based approach

Browse Source
This commit is contained in:
bird_egop 2025-04-13 23:48:45 +03:00
parent 46a4696481
commit 0ff20494e1
1 changed files with 69 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

112
X86Disassembler/X86/Handlers/FloatingPoint/Int32OperationHandler.cs
View File

@ -5,18 +5,65 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// </summary> /// </summary>
public class Int32OperationHandler : InstructionHandler public class Int32OperationHandler : InstructionHandler
{ {
// DA opcode - operations on int32 // Memory operand mnemonics for DA opcode - operations on int32
private static readonly string[] Mnemonics = private static readonly string[] MemoryMnemonics =
[ [
"fiadd", "fiadd", // 0
"fimul", "fimul", // 1
"ficom", "ficom", // 2
"ficomp", "ficomp", // 3
"fisub", "fisub", // 4
"fisubr", "fisubr", // 5
"fidiv", "fidiv", // 6
"fidivr" "fidivr" // 7
]; ];
// Register-register operations mapping (mod=3)
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
{
// FCMOVB st(0), st(i)
{ (RegisterIndex.A, RegisterIndex.A), ("fcmovb", "st(0), st(0)") },
{ (RegisterIndex.A, RegisterIndex.C), ("fcmovb", "st(0), st(1)") },
{ (RegisterIndex.A, RegisterIndex.D), ("fcmovb", "st(0), st(2)") },
{ (RegisterIndex.A, RegisterIndex.B), ("fcmovb", "st(0), st(3)") },
{ (RegisterIndex.A, RegisterIndex.Sp), ("fcmovb", "st(0), st(4)") },
{ (RegisterIndex.A, RegisterIndex.Bp), ("fcmovb", "st(0), st(5)") },
{ (RegisterIndex.A, RegisterIndex.Si), ("fcmovb", "st(0), st(6)") },
{ (RegisterIndex.A, RegisterIndex.Di), ("fcmovb", "st(0), st(7)") },
// FCMOVE st(0), st(i)
{ (RegisterIndex.B, RegisterIndex.A), ("fcmove", "st(0), st(0)") },
{ (RegisterIndex.B, RegisterIndex.C), ("fcmove", "st(0), st(1)") },
{ (RegisterIndex.B, RegisterIndex.D), ("fcmove", "st(0), st(2)") },
{ (RegisterIndex.B, RegisterIndex.B), ("fcmove", "st(0), st(3)") },
{ (RegisterIndex.B, RegisterIndex.Sp), ("fcmove", "st(0), st(4)") },
{ (RegisterIndex.B, RegisterIndex.Bp), ("fcmove", "st(0), st(5)") },
{ (RegisterIndex.B, RegisterIndex.Si), ("fcmove", "st(0), st(6)") },
{ (RegisterIndex.B, RegisterIndex.Di), ("fcmove", "st(0), st(7)") },
// FCMOVBE st(0), st(i)
{ (RegisterIndex.C, RegisterIndex.A), ("fcmovbe", "st(0), st(0)") },
{ (RegisterIndex.C, RegisterIndex.C), ("fcmovbe", "st(0), st(1)") },
{ (RegisterIndex.C, RegisterIndex.D), ("fcmovbe", "st(0), st(2)") },
{ (RegisterIndex.C, RegisterIndex.B), ("fcmovbe", "st(0), st(3)") },
{ (RegisterIndex.C, RegisterIndex.Sp), ("fcmovbe", "st(0), st(4)") },
{ (RegisterIndex.C, RegisterIndex.Bp), ("fcmovbe", "st(0), st(5)") },
{ (RegisterIndex.C, RegisterIndex.Si), ("fcmovbe", "st(0), st(6)") },
{ (RegisterIndex.C, RegisterIndex.Di), ("fcmovbe", "st(0), st(7)") },
// FCMOVU st(0), st(i)
{ (RegisterIndex.D, RegisterIndex.A), ("fcmovu", "st(0), st(0)") },
{ (RegisterIndex.D, RegisterIndex.C), ("fcmovu", "st(0), st(1)") },
{ (RegisterIndex.D, RegisterIndex.D), ("fcmovu", "st(0), st(2)") },
{ (RegisterIndex.D, RegisterIndex.B), ("fcmovu", "st(0), st(3)") },
{ (RegisterIndex.D, RegisterIndex.Sp), ("fcmovu", "st(0), st(4)") },
{ (RegisterIndex.D, RegisterIndex.Bp), ("fcmovu", "st(0), st(5)") },
{ (RegisterIndex.D, RegisterIndex.Si), ("fcmovu", "st(0), st(6)") },
{ (RegisterIndex.D, RegisterIndex.Di), ("fcmovu", "st(0), st(7)") },
// Special case
{ (RegisterIndex.Di, RegisterIndex.B), ("fucompp", "") }
};
/// <summary> /// <summary>
/// Initializes a new instance of the Int32OperationHandler class /// Initializes a new instance of the Int32OperationHandler class
@ -47,51 +94,30 @@ public class Int32OperationHandler : InstructionHandler
/// <returns>True if the instruction was successfully decoded</returns> /// <returns>True if the instruction was successfully decoded</returns>
public override bool Decode(byte opcode, Instruction instruction) public override bool Decode(byte opcode, Instruction instruction)
{ {
int position = Decoder.GetPosition(); if (!Decoder.CanReadByte())
if (position >= Length)
{ {
return false; return false;
} }
// Read the ModR/M byte // Read the ModR/M byte
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM(); var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
// Set the mnemonic based on the opcode and reg field // Handle based on addressing mode
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand if (mod != 3) // Memory operand
{ {
instruction.Operands = destOperand; // Set the mnemonic based on the reg field
instruction.Mnemonic = MemoryMnemonics[(int)reg];
// Set the operands (already has dword ptr prefix for int32)
instruction.Operands = memOperand;
} }
else // Register operand (ST(i)) else // Register operand (ST(i))
{ {
// Special handling for register-register operations // Look up the register operation in our dictionary
if (reg == RegisterIndex.A) // FCMOVB if (RegisterOperations.TryGetValue((reg, rm), out var operation))
{ {
instruction.Mnemonic = "fcmovb"; instruction.Mnemonic = operation.Mnemonic;
instruction.Operands = $"st(0), st({(int)rm})"; instruction.Operands = operation.Operands;
}
else if (reg == RegisterIndex.B) // FCMOVE
{
instruction.Mnemonic = "fcmove";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.C) // FCMOVBE
{
instruction.Mnemonic = "fcmovbe";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.D) // FCMOVU
{
instruction.Mnemonic = "fcmovu";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.Di && rm == RegisterIndex.B) // FUCOMPP
{
instruction.Mnemonic = "fucompp";
instruction.Operands = "";
} }
else else
{ {