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nice big refactor

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This commit is contained in:
bird_egop
2025-04-13 23:06:52 +03:00
parent 59df064ca4
commit 11a2cfada4
92 changed files with 981 additions and 1509 deletions
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17
X86Disassembler/X86/Handlers/FloatingPoint/Float32OperationHandler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point operations on float32 (D8 opcode)
/// </summary>
public class Float32OperationHandler : FloatingPointBaseHandler
public class Float32OperationHandler : InstructionHandler
{
// D8 opcode - operations on float32
private static readonly string[] Mnemonics =
@ -55,27 +55,20 @@ public class Float32OperationHandler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte) ((modRM & 0xC0) >> 6);
byte reg = (byte) ((modRM & 0x38) >> 3);
byte rm = (byte) (modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
instruction.Operands = operand;
instruction.Operands = destOperand;
}
else // Register operand (ST(i))
{
// For register operands, we need to handle the stack registers
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
return true;

17
X86Disassembler/X86/Handlers/FloatingPoint/Float64OperationHandler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point operations on float64 (DC opcode)
/// </summary>
public class Float64OperationHandler : FloatingPointBaseHandler
public class Float64OperationHandler : InstructionHandler
{
// DC opcode - operations on float64
private static readonly string[] Mnemonics =
@ -55,27 +55,20 @@ public class Float64OperationHandler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte)((modRM & 0xC0) >> 6);
byte reg = (byte)((modRM & 0x38) >> 3);
byte rm = (byte)(modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM(true); // true for 64-bit operand
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, true); // true for 64-bit operand
instruction.Operands = operand;
instruction.Operands = destOperand;
}
else // Register operand (ST(i))
{
// For DC C0-DC FF, the operands are reversed: ST(i), ST(0)
instruction.Operands = $"st({rm}), st(0)";
instruction.Operands = $"st({(int)rm}), st(0)";
}
return true;

18
X86Disassembler/X86/Handlers/FloatingPoint/FloatingPointBaseHandler.cs
View File

@ -1,18 +0,0 @@
namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Base class for floating-point instruction handlers
/// </summary>
public abstract class FloatingPointBaseHandler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FloatingPointBaseHandler class
/// </summary>
/// <param name="codeBuffer">The buffer containing the code to decode</param>
/// <param name="decoder">The instruction decoder that owns this handler</param>
/// <param name="length">The length of the buffer</param>
protected FloatingPointBaseHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
: base(codeBuffer, decoder, length)
{
}
}

44
X86Disassembler/X86/Handlers/FloatingPoint/Int16OperationHandler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point operations on int16 (DE opcode)
/// </summary>
public class Int16OperationHandler : FloatingPointBaseHandler
public class Int16OperationHandler : InstructionHandler
{
// DE opcode - operations on int16
private static readonly string[] Mnemonics =
@ -55,67 +55,59 @@ public class Int16OperationHandler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte) ((modRM & 0xC0) >> 6);
byte reg = (byte) ((modRM & 0x38) >> 3);
byte rm = (byte) (modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
// Need to modify the default dword ptr to word ptr for 16-bit integers
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
operand = operand.Replace("dword ptr", "word ptr");
instruction.Operands = operand;
instruction.Operands = destOperand.Replace("dword ptr", "word ptr");
}
else // Register operand (ST(i))
{
// Special handling for register-register operations
if (reg == 0) // FADDP
if (reg == RegisterIndex.A) // FADDP
{
instruction.Mnemonic = "faddp";
instruction.Operands = $"st({rm}), st(0)";
instruction.Operands = $"st({(int)rm}), st(0)";
}
else if (reg == 1) // FMULP
else if (reg == RegisterIndex.B) // FMULP
{
instruction.Mnemonic = "fmulp";
instruction.Operands = $"st({rm}), st(0)";
instruction.Operands = $"st({(int)rm}), st(0)";
}
else if (reg == 2 && rm == 1) // FCOMP
else if (reg == RegisterIndex.C && rm == RegisterIndex.B) // FCOMP
{
instruction.Mnemonic = "fcomp";
instruction.Operands = "";
}
else if (reg == 3 && rm == 1) // FCOMPP
else if (reg == RegisterIndex.D && rm == RegisterIndex.B) // FCOMPP
{
instruction.Mnemonic = "fcompp";
instruction.Operands = "";
}
else if (reg == 4) // FSUBP
else if (reg == RegisterIndex.Si) // FSUBP
{
instruction.Mnemonic = "fsubp";
instruction.Operands = $"st({rm}), st(0)";
instruction.Operands = $"st({(int)rm}), st(0)";
}
else if (reg == 5) // FSUBRP
else if (reg == RegisterIndex.Di) // FSUBRP
{
instruction.Mnemonic = "fsubrp";
instruction.Operands = $"st({rm}), st(0)";
instruction.Operands = $"st({(int)rm}), st(0)";
}
else if (reg == 6) // FDIVP
else if (reg == RegisterIndex.Sp) // FDIVP
{
instruction.Mnemonic = "fdivp";
instruction.Operands = $"st({rm}), st(0)";
instruction.Operands = $"st({(int)rm}), st(0)";
}
else if (reg == 7) // FDIVRP
else if (reg == RegisterIndex.Bp) // FDIVRP
{
instruction.Mnemonic = "fdivrp";
instruction.Operands = $"st({rm}), st(0)";
instruction.Operands = $"st({(int)rm}), st(0)";
}
else
{

33
X86Disassembler/X86/Handlers/FloatingPoint/Int32OperationHandler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point operations on int32 (DA opcode)
/// </summary>
public class Int32OperationHandler : FloatingPointBaseHandler
public class Int32OperationHandler : InstructionHandler
{
// DA opcode - operations on int32
private static readonly string[] Mnemonics =
@ -55,47 +55,40 @@ public class Int32OperationHandler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte) ((modRM & 0xC0) >> 6);
byte reg = (byte) ((modRM & 0x38) >> 3);
byte rm = (byte) (modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
instruction.Operands = operand;
instruction.Operands = destOperand;
}
else // Register operand (ST(i))
{
// Special handling for register-register operations
if (reg == 0) // FCMOVB
if (reg == RegisterIndex.A) // FCMOVB
{
instruction.Mnemonic = "fcmovb";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 1) // FCMOVE
else if (reg == RegisterIndex.B) // FCMOVE
{
instruction.Mnemonic = "fcmove";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 2) // FCMOVBE
else if (reg == RegisterIndex.C) // FCMOVBE
{
instruction.Mnemonic = "fcmovbe";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 3) // FCMOVU
else if (reg == RegisterIndex.D) // FCMOVU
{
instruction.Mnemonic = "fcmovu";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 5 && rm == 1) // FUCOMPP
else if (reg == RegisterIndex.Di && rm == RegisterIndex.B) // FUCOMPP
{
instruction.Mnemonic = "fucompp";
instruction.Operands = "";

78
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreControlHandler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point load, store, and control operations (D9 opcode)
/// </summary>
public class LoadStoreControlHandler : FloatingPointBaseHandler
public class LoadStoreControlHandler : InstructionHandler
{
// D9 opcode - load, store, and control operations
private static readonly string[] Mnemonics =
@ -55,71 +55,63 @@ public class LoadStoreControlHandler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte)((modRM & 0xC0) >> 6);
byte reg = (byte)((modRM & 0x38) >> 3);
byte rm = (byte)(modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
// Different operand types based on the instruction
if (reg == 0 || reg == 2 || reg == 3) // fld, fst, fstp
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
{
// Keep the dword ptr prefix from ModRMDecoder
instruction.Operands = operand;
instruction.Operands = destOperand;
}
else // fldenv, fldcw, fnstenv, fnstcw
{
if (reg == 5) // fldcw - should use word ptr
if (reg == RegisterIndex.Di) // fldcw - should use word ptr
{
instruction.Operands = operand.Replace("dword ptr", "word ptr");
instruction.Operands = destOperand.Replace("dword ptr", "word ptr");
}
else // fldenv, fnstenv, fnstcw
{
// Remove the dword ptr prefix for other control operations
instruction.Operands = operand.Replace("dword ptr ", "");
instruction.Operands = destOperand.Replace("dword ptr ", "");
}
}
}
else // Register operand (ST(i))
{
// Special handling for D9C0-D9FF (register-register operations)
if (reg == 0) // FLD ST(i)
if (reg == RegisterIndex.A) // FLD ST(i)
{
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else if (reg == 1) // FXCH ST(i)
else if (reg == RegisterIndex.B) // FXCH ST(i)
{
instruction.Mnemonic = "fxch";
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else if (reg == 4)
else if (reg == RegisterIndex.Si)
{
// D9E0-D9EF special instructions
switch (rm)
{
case 0:
case RegisterIndex.A:
instruction.Mnemonic = "fchs";
instruction.Operands = "";
break;
case 1:
case RegisterIndex.B:
instruction.Mnemonic = "fabs";
instruction.Operands = "";
break;
case 4:
case RegisterIndex.Si:
instruction.Mnemonic = "ftst";
instruction.Operands = "";
break;
case 5:
case RegisterIndex.Di:
instruction.Mnemonic = "fxam";
instruction.Operands = "";
break;
@ -129,40 +121,40 @@ public class LoadStoreControlHandler : FloatingPointBaseHandler
break;
}
}
else if (reg == 5)
else if (reg == RegisterIndex.Di)
{
// D9F0-D9FF special instructions
switch (rm)
{
case 0:
case RegisterIndex.A:
instruction.Mnemonic = "f2xm1";
instruction.Operands = "";
break;
case 1:
case RegisterIndex.B:
instruction.Mnemonic = "fyl2x";
instruction.Operands = "";
break;
case 2:
case RegisterIndex.C:
instruction.Mnemonic = "fptan";
instruction.Operands = "";
break;
case 3:
case RegisterIndex.D:
instruction.Mnemonic = "fpatan";
instruction.Operands = "";
break;
case 4:
case RegisterIndex.Si:
instruction.Mnemonic = "fxtract";
instruction.Operands = "";
break;
case 5:
case RegisterIndex.Di:
instruction.Mnemonic = "fprem1";
instruction.Operands = "";
break;
case 6:
case RegisterIndex.Sp:
instruction.Mnemonic = "fdecstp";
instruction.Operands = "";
break;
case 7:
case RegisterIndex.Bp:
instruction.Mnemonic = "fincstp";
instruction.Operands = "";
break;
@ -172,40 +164,40 @@ public class LoadStoreControlHandler : FloatingPointBaseHandler
break;
}
}
else if (reg == 6)
else if (reg == RegisterIndex.Sp)
{
// D9F0-D9FF more special instructions
switch (rm)
{
case 0:
case RegisterIndex.A:
instruction.Mnemonic = "fprem";
instruction.Operands = "";
break;
case 1:
case RegisterIndex.B:
instruction.Mnemonic = "fyl2xp1";
instruction.Operands = "";
break;
case 2:
case RegisterIndex.C:
instruction.Mnemonic = "fsqrt";
instruction.Operands = "";
break;
case 3:
case RegisterIndex.D:
instruction.Mnemonic = "fsincos";
instruction.Operands = "";
break;
case 4:
case RegisterIndex.Si:
instruction.Mnemonic = "frndint";
instruction.Operands = "";
break;
case 5:
case RegisterIndex.Di:
instruction.Mnemonic = "fscale";
instruction.Operands = "";
break;
case 6:
case RegisterIndex.Sp:
instruction.Mnemonic = "fsin";
instruction.Operands = "";
break;
case 7:
case RegisterIndex.Bp:
instruction.Mnemonic = "fcos";
instruction.Operands = "";
break;

40
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreFloat64Handler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point load/store float64 operations (DD opcode)
/// </summary>
public class LoadStoreFloat64Handler : FloatingPointBaseHandler
public class LoadStoreFloat64Handler : InstructionHandler
{
// DD opcode - load/store float64
private static readonly string[] Mnemonics =
@ -55,59 +55,51 @@ public class LoadStoreFloat64Handler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte) ((modRM & 0xC0) >> 6);
byte reg = (byte) ((modRM & 0x38) >> 3);
byte rm = (byte) (modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM(true);// true for 64-bit operand
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, true); // true for 64-bit operand
if (reg == 0 || reg == 2 || reg == 3) // fld, fst, fstp
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
{
instruction.Operands = operand;
instruction.Operands = destOperand;
}
else // frstor, fnsave, fnstsw
{
// Remove the qword ptr prefix for these operations
instruction.Operands = operand.Replace("qword ptr ", "");
instruction.Operands = destOperand.Replace("qword ptr ", "");
}
}
else // Register operand (ST(i))
{
// Special handling for register-register operations
if (reg == 0) // FFREE
if (reg == RegisterIndex.A) // FFREE
{
instruction.Mnemonic = "ffree";
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else if (reg == 2) // FST
else if (reg == RegisterIndex.C) // FST
{
instruction.Mnemonic = "fst";
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else if (reg == 3) // FSTP
else if (reg == RegisterIndex.D) // FSTP
{
instruction.Mnemonic = "fstp";
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else if (reg == 4) // FUCOM
else if (reg == RegisterIndex.Si) // FUCOM
{
instruction.Mnemonic = "fucom";
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else if (reg == 5) // FUCOMP
else if (reg == RegisterIndex.Di) // FUCOMP
{
instruction.Mnemonic = "fucomp";
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else
{

40
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt16Handler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point load/store int16 and miscellaneous operations (DF opcode)
/// </summary>
public class LoadStoreInt16Handler : FloatingPointBaseHandler
public class LoadStoreInt16Handler : InstructionHandler
{
// DF opcode - load/store int16, misc
private static readonly string[] Mnemonics =
@ -55,32 +55,26 @@ public class LoadStoreInt16Handler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte) ((modRM & 0xC0) >> 6);
byte reg = (byte) ((modRM & 0x38) >> 3);
byte rm = (byte) (modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
// Check for FNSTSW AX (DF E0)
if (mod == 3 && reg == 7 && rm == 0)
if (mod == 3 && reg == RegisterIndex.Bp && rm == RegisterIndex.A)
{
// This is handled by the FnstswHandler, so we should not handle it here
return false;
}
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
if (reg == 0 || reg == 2 || reg == 3 || reg == 5 || reg == 7) // fild, fist, fistp, fild, fistp
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D || reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fild, fist, fistp, fild, fistp
{
if (reg == 5 || reg == 7) // 64-bit integer
if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 64-bit integer
{
// Replace dword ptr with qword ptr for 64-bit integers
operand = operand.Replace("dword ptr", "qword ptr");
@ -93,7 +87,7 @@ public class LoadStoreInt16Handler : FloatingPointBaseHandler
instruction.Operands = operand;
}
}
else if (reg == 4 || reg == 6) // fbld, fbstp
else if (reg == RegisterIndex.Si || reg == RegisterIndex.Sp) // fbld, fbstp
{
// Replace dword ptr with tbyte ptr for 80-bit packed BCD
operand = operand.Replace("dword ptr", "tbyte ptr");
@ -107,41 +101,41 @@ public class LoadStoreInt16Handler : FloatingPointBaseHandler
else // Register operand (ST(i))
{
// Special handling for register-register operations
if (reg == 0) // FFREEP
if (reg == RegisterIndex.A) // FFREEP
{
instruction.Mnemonic = "ffreep";
instruction.Operands = $"st({rm})";
instruction.Operands = $"st({(int)rm})";
}
else if (reg == 1 && rm == 0) // FXCH
else if (reg == RegisterIndex.B && rm == RegisterIndex.A) // FXCH
{
instruction.Mnemonic = "fxch";
instruction.Operands = "";
}
else if (reg == 2 && rm == 0) // FSTP
else if (reg == RegisterIndex.C && rm == RegisterIndex.A) // FSTP
{
instruction.Mnemonic = "fstp";
instruction.Operands = "st(1)";
}
else if (reg == 3 && rm == 0) // FSTP
else if (reg == RegisterIndex.D && rm == RegisterIndex.A) // FSTP
{
instruction.Mnemonic = "fstp";
instruction.Operands = "st(1)";
}
else if (reg == 4) // FNSTSW
else if (reg == RegisterIndex.Si) // FNSTSW
{
// This should not happen as FNSTSW AX is handled by FnstswHandler
instruction.Mnemonic = "??";
instruction.Operands = "";
}
else if (reg == 5) // FUCOMIP
else if (reg == RegisterIndex.Di) // FUCOMIP
{
instruction.Mnemonic = "fucomip";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 6) // FCOMIP
else if (reg == RegisterIndex.Sp) // FCOMIP
{
instruction.Mnemonic = "fcomip";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else
{

55
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt32Handler.cs
View File

@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
/// <summary>
/// Handler for floating-point load/store int32 and miscellaneous operations (DB opcode)
/// </summary>
public class LoadStoreInt32Handler : FloatingPointBaseHandler
public class LoadStoreInt32Handler : InstructionHandler
{
// DB opcode - load/store int32, misc
private static readonly string[] Mnemonics =
@ -55,69 +55,60 @@ public class LoadStoreInt32Handler : FloatingPointBaseHandler
}
// Read the ModR/M byte
byte modRM = CodeBuffer[position++];
Decoder.SetPosition(position);
// Extract the fields from the ModR/M byte
byte mod = (byte) ((modRM & 0xC0) >> 6);
byte reg = (byte) ((modRM & 0x38) >> 3);
byte rm = (byte) (modRM & 0x07);
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[reg];
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
if (reg == 0 || reg == 2 || reg == 3) // fild, fist, fistp
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fild, fist, fistp
{
// Keep the dword ptr prefix for integer operations
instruction.Operands = operand;
instruction.Operands = destOperand;
}
else if (reg == 5 || reg == 7) // fld, fstp (extended precision)
else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fld, fstp (extended precision)
{
// Replace dword ptr with tword ptr for extended precision
operand = operand.Replace("dword ptr", "tword ptr");
instruction.Operands = operand;
instruction.Operands = destOperand.Replace("dword ptr", "tword ptr");
}
else
{
instruction.Operands = operand;
instruction.Operands = destOperand;
}
}
else // Register operand (ST(i))
{
// Special handling for register-register operations
if (reg == 0) // FCMOVNB
if (reg == RegisterIndex.A) // FCMOVNB
{
instruction.Mnemonic = "fcmovnb";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 1) // FCMOVNE
else if (reg == RegisterIndex.B) // FCMOVNE
{
instruction.Mnemonic = "fcmovne";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 2) // FCMOVNBE
else if (reg == RegisterIndex.C) // FCMOVNBE
{
instruction.Mnemonic = "fcmovnbe";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 3) // FCMOVNU
else if (reg == RegisterIndex.D) // FCMOVNU
{
instruction.Mnemonic = "fcmovnu";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 4)
else if (reg == RegisterIndex.Si)
{
if (rm == 2) // FCLEX
if (rm == RegisterIndex.C) // FCLEX
{
instruction.Mnemonic = "fclex";
instruction.Operands = "";
}
else if (rm == 3) // FINIT
else if (rm == RegisterIndex.D) // FINIT
{
instruction.Mnemonic = "finit";
instruction.Operands = "";
@ -128,15 +119,15 @@ public class LoadStoreInt32Handler : FloatingPointBaseHandler
instruction.Operands = "";
}
}
else if (reg == 5) // FUCOMI
else if (reg == RegisterIndex.Di) // FUCOMI
{
instruction.Mnemonic = "fucomi";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == 6) // FCOMI
else if (reg == RegisterIndex.Sp) // FCOMI
{
instruction.Mnemonic = "fcomi";
instruction.Operands = $"st(0), st({rm})";
instruction.Operands = $"st(0), st({(int)rm})";
}
else
{