mirror of
https://github.com/sampletext32/ParkanPlayground.git
synced 2025-06-19 16:08:02 +03:00
Fixes to tests and ModRM + SIB
This commit is contained in:
bird_egop
@ -23,7 +23,14 @@ public class AddEaxImmHandler : InstructionHandler
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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return opcode == 0x05;
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// ADD EAX, imm32 is encoded as 0x05 without 0x66 prefix
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if (opcode != 0x05)
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{
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return false;
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}
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// Only handle when the operand size prefix is NOT present
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return !Decoder.HasOperandSizePrefix();
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}
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/// <summary>
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@ -23,7 +23,14 @@ public class AndEaxImmHandler : InstructionHandler
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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return opcode == 0x25;
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// AND EAX, imm32 is encoded as 0x25 without 0x66 prefix
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if (opcode != 0x25)
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{
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return false;
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}
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// Only handle when the operand size prefix is NOT present
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return !Decoder.HasOperandSizePrefix();
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}
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/// <summary>
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@ -23,16 +23,19 @@ public class IdivRm32Handler : InstructionHandler
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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// IDIV r/m32 is encoded as 0xF7 with reg field 7
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if (opcode != 0xF7)
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return false;
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// Check if the reg field of the ModR/M byte is 7 (IDIV)
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// Check if we can read the ModR/M byte
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if (!Decoder.CanReadByte())
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return false;
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// Check if the reg field of the ModR/M byte is 7 (IDIV)
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var reg = ModRMDecoder.PeakModRMReg();
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return reg == 7; // 7 = IDIV
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// reg = 7 means IDIV operation
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return reg == 7;
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}
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/// <summary>
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@ -54,7 +57,13 @@ public class IdivRm32Handler : InstructionHandler
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// Read the ModR/M byte
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// For IDIV r/m32 (0xF7 /7):
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// - The r/m field with mod specifies the operand (register or memory)
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var (_, _, _, operand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
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// Verify that the reg field is 7 (IDIV)
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if (reg != RegisterIndex.Di)
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{
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return false;
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}
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// Set the structured operands
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// IDIV has only one operand
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@ -80,21 +80,22 @@ public class InstructionHandlerFactory
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RegisterImulHandlers(); // IMUL instructions
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RegisterDivHandlers(); // DIV instructions
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RegisterIdivHandlers(); // IDIV instructions
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RegisterDataTransferHandlers();
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RegisterJumpHandlers();
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RegisterCallHandlers();
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RegisterReturnHandlers();
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RegisterDecHandlers();
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RegisterDataTransferHandlers(); // MOV, MOVZX, MOVSX
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RegisterJumpHandlers(); // JMP instructions
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RegisterCallHandlers(); // CALL instructions
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RegisterReturnHandlers(); // RET instructions
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RegisterDecHandlers(); // DEC instructions
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RegisterIncHandlers(); // INC/DEC handlers after Group 1 handlers
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RegisterPushHandlers();
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RegisterPopHandlers();
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RegisterLeaHandlers();
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RegisterFloatingPointHandlers();
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RegisterStringHandlers();
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RegisterMovHandlers();
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RegisterPushHandlers(); // PUSH instructions
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RegisterPopHandlers(); // POP instructions
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RegisterLeaHandlers(); // LEA instructions
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RegisterFloatingPointHandlers(); // FPU instructions
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RegisterStringHandlers(); // String instructions
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RegisterMovHandlers(); // MOV instructions
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RegisterSubHandlers(); // Register SUB handlers
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RegisterNopHandlers(); // Register NOP handlers
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RegisterBitHandlers(); // Register bit manipulation handlers
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RegisterAndHandlers(); // Register AND handlers
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}
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/// <summary>
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@ -168,9 +169,9 @@ public class InstructionHandlerFactory
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_handlers.Add(new JmpRm32Handler(_decoder)); // JMP r/m32 (opcode FF /4)
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// Conditional jump handlers
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_handlers.Add(new JgeRel8Handler(_decoder));
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_handlers.Add(new ConditionalJumpHandler(_decoder));
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_handlers.Add(new TwoByteConditionalJumpHandler(_decoder));
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_handlers.Add(new JgeRel8Handler(_decoder)); // JGE rel8 (opcode 0F 8D)
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_handlers.Add(new ConditionalJumpHandler(_decoder)); // Short conditional jumps
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_handlers.Add(new TwoByteConditionalJumpHandler(_decoder)); // Long conditional jumps
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}
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/// <summary>
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@ -179,12 +180,12 @@ public class InstructionHandlerFactory
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private void RegisterTestHandlers()
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{
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// TEST handlers
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_handlers.Add(new TestImmWithRm32Handler(_decoder));
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_handlers.Add(new TestImmWithRm8Handler(_decoder));
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_handlers.Add(new TestRegMem8Handler(_decoder));
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_handlers.Add(new TestRegMemHandler(_decoder));
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_handlers.Add(new TestAlImmHandler(_decoder));
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_handlers.Add(new TestEaxImmHandler(_decoder));
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_handlers.Add(new TestImmWithRm32Handler(_decoder)); // TEST r/m32, imm32 (opcode A9)
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_handlers.Add(new TestImmWithRm8Handler(_decoder)); // TEST r/m8, imm8 (opcode F6 /0)
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_handlers.Add(new TestRegMem8Handler(_decoder)); // TEST r8, r/m8 (opcode 84 /0)
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_handlers.Add(new TestRegMemHandler(_decoder)); // TEST r32, r/m32 (opcode 85 /0)
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_handlers.Add(new TestAlImmHandler(_decoder)); // TEST AL, imm8 (opcode A8)
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_handlers.Add(new TestEaxImmHandler(_decoder)); // TEST EAX, imm32 (opcode A9)
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}
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/// <summary>
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@ -243,7 +244,7 @@ public class InstructionHandlerFactory
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private void RegisterLeaHandlers()
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{
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// Add Lea handlers
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_handlers.Add(new LeaR32MHandler(_decoder));
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_handlers.Add(new LeaR32MHandler(_decoder)); // LEA r32, m (opcode 8D)
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}
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/// <summary>
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@ -252,21 +253,21 @@ public class InstructionHandlerFactory
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private void RegisterCmpHandlers()
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{
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// Add Cmp handlers for 32-bit operands
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_handlers.Add(new CmpR32Rm32Handler(_decoder));
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_handlers.Add(new CmpRm32R32Handler(_decoder));
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_handlers.Add(new CmpR32Rm32Handler(_decoder)); // CMP r32, r/m32 (opcode 3B)
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_handlers.Add(new CmpRm32R32Handler(_decoder)); // CMP r/m32, r32 (opcode 39)
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// Add Cmp handlers for 8-bit operands
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_handlers.Add(new CmpRm8R8Handler(_decoder)); // CMP r/m8, r8 (opcode 38)
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_handlers.Add(new CmpR8Rm8Handler(_decoder)); // CMP r8, r/m8 (opcode 3A)
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// Add Cmp handlers for immediate operands
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_handlers.Add(new CmpImmWithRm8Handler(_decoder));
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_handlers.Add(new CmpImmWithRm8Handler(_decoder)); // CMP r/m8, imm8 (opcode 80 /7)
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_handlers.Add(new CmpAlImmHandler(_decoder)); // CMP AL, imm8 (opcode 3C)
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_handlers.Add(new CmpEaxImmHandler(_decoder)); // CMP EAX, imm32 (opcode 3D)
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// Add CMP immediate handlers from ArithmeticImmediate namespace
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_handlers.Add(new CmpImmWithRm32Handler(_decoder));
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_handlers.Add(new CmpImmWithRm32SignExtendedHandler(_decoder));
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_handlers.Add(new CmpImmWithRm32Handler(_decoder)); // CMP r/m32, imm32 (opcode 81 /7)
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_handlers.Add(new CmpImmWithRm32SignExtendedHandler(_decoder)); // CMP r/m32, imm8 (opcode 83 /7)
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}
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/// <summary>
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@ -275,7 +276,9 @@ public class InstructionHandlerFactory
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private void RegisterDecHandlers()
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{
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// Add Dec handlers
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_handlers.Add(new DecRegHandler(_decoder));
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_handlers.Add(new DecRegHandler(_decoder)); // DEC r/m8 (opcode FE)
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// _handlers.Add(new DecMem8Handler(_decoder)); // DEC r/m16 (opcode FF /1) and DEC r/m32 (opcode FF /1)
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}
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/// <summary>
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@ -284,7 +287,9 @@ public class InstructionHandlerFactory
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private void RegisterIncHandlers()
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{
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// Add Inc handlers
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_handlers.Add(new IncRegHandler(_decoder));
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_handlers.Add(new IncRegHandler(_decoder)); // INC r/m8 (opcode FE)
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// _handlers.Add(new IncMem8Handler(_decoder)); // INC r/m16 (opcode FF /0) and INC r/m32 (opcode FF /0)
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}
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/// <summary>
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@ -295,7 +300,8 @@ public class InstructionHandlerFactory
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// Add ADD register-to-register handlers (32-bit)
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_handlers.Add(new AddR32Rm32Handler(_decoder)); // ADD r32, r/m32 (opcode 03)
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_handlers.Add(new AddRm32R32Handler(_decoder)); // ADD r/m32, r32 (opcode 01)
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_handlers.Add(new AddEaxImmHandler(_decoder)); // ADD EAX, imm32 (opcode 05)
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_handlers.Add(new AddEaxImmHandler(_decoder)); // ADD EAX, imm32 (opcode 05 without 0x66 prefix)
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_handlers.Add(new AddAxImmHandler(_decoder)); // ADD AX, imm16 (opcode 05 with 0x66 prefix)
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// Add ADD register-to-register handlers (16-bit)
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_handlers.Add(new AddR16Rm16Handler(_decoder)); // ADD r16, r/m16 (opcode 03 with 0x66 prefix)
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@ -320,17 +326,17 @@ public class InstructionHandlerFactory
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private void RegisterDataTransferHandlers()
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{
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// Add MOV handlers
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_handlers.Add(new MovRegMemHandler(_decoder));
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_handlers.Add(new MovMemRegHandler(_decoder));
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_handlers.Add(new MovRegImm32Handler(_decoder));
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_handlers.Add(new MovRegImm8Handler(_decoder));
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_handlers.Add(new MovEaxMoffsHandler(_decoder));
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_handlers.Add(new MovMoffsEaxHandler(_decoder));
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_handlers.Add(new MovRm32Imm32Handler(_decoder));
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_handlers.Add(new MovRm8Imm8Handler(_decoder));
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_handlers.Add(new MovRegMemHandler(_decoder)); // MOV r32, r/m32 (opcode 8B)
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_handlers.Add(new MovMemRegHandler(_decoder)); // MOV r/m32, r32 (opcode 89)
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_handlers.Add(new MovRegImm32Handler(_decoder)); // MOV r32, imm32 (opcode B8 + register)
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_handlers.Add(new MovRegImm8Handler(_decoder)); // MOV r32, imm8 (opcode B0 + register)
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_handlers.Add(new MovEaxMoffsHandler(_decoder)); // MOV EAX, moffs32 (opcode A1)
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_handlers.Add(new MovMoffsEaxHandler(_decoder)); // MOV moffs32, EAX (opcode A3)
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_handlers.Add(new MovRm32Imm32Handler(_decoder)); // MOV r/m32, imm32 (opcode C7 /0)
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_handlers.Add(new MovRm8Imm8Handler(_decoder)); // MOV r/m8, imm8 (opcode C6 /0)
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// Add XCHG handlers
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_handlers.Add(new XchgEaxRegHandler(_decoder));
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_handlers.Add(new XchgEaxRegHandler(_decoder)); // XCHG EAX, r32 (opcode 90 + register)
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}
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/// <summary>
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@ -339,15 +345,15 @@ public class InstructionHandlerFactory
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private void RegisterFloatingPointHandlers()
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{
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// Add Floating Point handlers
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_handlers.Add(new FnstswHandler(_decoder));
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_handlers.Add(new Float32OperationHandler(_decoder));
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_handlers.Add(new LoadStoreControlHandler(_decoder));
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_handlers.Add(new Int32OperationHandler(_decoder));
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_handlers.Add(new LoadStoreInt32Handler(_decoder));
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_handlers.Add(new Float64OperationHandler(_decoder));
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_handlers.Add(new LoadStoreFloat64Handler(_decoder));
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_handlers.Add(new Int16OperationHandler(_decoder));
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_handlers.Add(new LoadStoreInt16Handler(_decoder));
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_handlers.Add(new FnstswHandler(_decoder)); // FSTSW (opcode DF /7)
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_handlers.Add(new Float32OperationHandler(_decoder)); // Floating Point operations on 32-bit values
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_handlers.Add(new LoadStoreControlHandler(_decoder)); // Load and store control words (opcode D9 /0)
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_handlers.Add(new Int32OperationHandler(_decoder)); // Integer operations on 32-bit values
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_handlers.Add(new LoadStoreInt32Handler(_decoder)); // Load and store 32-bit values
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_handlers.Add(new Float64OperationHandler(_decoder)); // Floating Point operations on 64-bit values
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_handlers.Add(new LoadStoreFloat64Handler(_decoder)); // Load and store 64-bit values
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_handlers.Add(new Int16OperationHandler(_decoder)); // Integer operations on 16-bit values
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_handlers.Add(new LoadStoreInt16Handler(_decoder)); // Load and store 16-bit values
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}
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/// <summary>
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@ -407,24 +413,29 @@ public class InstructionHandlerFactory
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}
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/// <summary>
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/// Registers all And instruction handlers
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/// Registers all AND instruction handlers
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/// </summary>
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private void RegisterAndHandlers()
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{
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// Add AND immediate handlers
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_handlers.Add(new AndImmToRm8Handler(_decoder)); // AND r/m8, imm8 (opcode 80 /4)
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_handlers.Add(new AndImmToRm32Handler(_decoder)); // AND r/m32, imm32 (opcode 81 /4)
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_handlers.Add(new AndImmToRm32SignExtendedHandler(_decoder)); // AND r/m32, imm8 (opcode 83 /4)
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// Add AND register handlers
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// 16-bit handlers with operand size prefix (must come first)
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_handlers.Add(new AndAxImmHandler(_decoder)); // AND AX, imm16 (opcode 25 with 0x66 prefix)
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_handlers.Add(new AndImmToRm16Handler(_decoder)); // AND r/m16, imm16 (opcode 81 /4 with 0x66 prefix)
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_handlers.Add(new AndImmToRm16SignExtendedHandler(_decoder)); // AND r/m16, imm8 (opcode 83 /4 with 0x66 prefix)
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_handlers.Add(new AndRm16R16Handler(_decoder)); // AND r/m16, r16 (opcode 21 with 0x66 prefix)
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_handlers.Add(new AndR16Rm16Handler(_decoder)); // AND r16, r/m16 (opcode 23 with 0x66 prefix)
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// 8-bit handlers
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_handlers.Add(new AndAlImmHandler(_decoder)); // AND AL, imm8 (opcode 24)
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_handlers.Add(new AndR8Rm8Handler(_decoder)); // AND r8, r/m8 (opcode 22)
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_handlers.Add(new AndRm8R8Handler(_decoder)); // AND r/m8, r8 (opcode 20)
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_handlers.Add(new AndImmToRm8Handler(_decoder)); // AND r/m8, imm8 (opcode 80 /4)
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// 32-bit handlers
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_handlers.Add(new AndEaxImmHandler(_decoder)); // AND EAX, imm32 (opcode 25 without 0x66 prefix)
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_handlers.Add(new AndR32Rm32Handler(_decoder)); // AND r32, r/m32 (opcode 23)
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_handlers.Add(new AndMemRegHandler(_decoder)); // AND r/m32, r32 (opcode 21)
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// Add AND immediate with accumulator handlers
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_handlers.Add(new AndAlImmHandler(_decoder)); // AND AL, imm8 (opcode 24)
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_handlers.Add(new AndEaxImmHandler(_decoder)); // AND EAX, imm32 (opcode 25)
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_handlers.Add(new AndImmToRm32Handler(_decoder)); // AND r/m32, imm32 (opcode 81 /4)
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_handlers.Add(new AndImmToRm32SignExtendedHandler(_decoder)); // AND r/m32, imm8 (opcode 83 /4)
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}
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/// <summary>
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@ -435,23 +446,23 @@ public class InstructionHandlerFactory
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// Register SUB handlers
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// 16-bit handlers with operand size prefix (must come first)
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_handlers.Add(new SubAxImm16Handler(_decoder));
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_handlers.Add(new SubImmFromRm16Handler(_decoder));
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_handlers.Add(new SubImmFromRm16SignExtendedHandler(_decoder));
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_handlers.Add(new SubRm16R16Handler(_decoder));
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_handlers.Add(new SubR16Rm16Handler(_decoder));
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_handlers.Add(new SubAxImm16Handler(_decoder)); // SUB AX, imm16 (opcode 0x66 0x83 /5)
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_handlers.Add(new SubImmFromRm16Handler(_decoder)); // SUB r/m16, imm16 (opcode 0x66 0x81 /5)
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_handlers.Add(new SubImmFromRm16SignExtendedHandler(_decoder)); // SUB r/m16, imm8 (opcode 0x66 0x83 /5)
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_handlers.Add(new SubRm16R16Handler(_decoder)); // SUB r/m16, r16 (opcode 0x66 0x29)
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_handlers.Add(new SubR16Rm16Handler(_decoder)); // SUB r16, r/m16 (opcode 0x66 0x2B)
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// 32-bit handlers
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_handlers.Add(new SubRm32R32Handler(_decoder));
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_handlers.Add(new SubR32Rm32Handler(_decoder));
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_handlers.Add(new SubImmFromRm32Handler(_decoder));
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_handlers.Add(new SubImmFromRm32SignExtendedHandler(_decoder));
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_handlers.Add(new SubRm32R32Handler(_decoder)); // SUB r/m32, r32 (opcode 0x29)
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_handlers.Add(new SubR32Rm32Handler(_decoder)); // SUB r32, r/m32 (opcode 0x2B)
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_handlers.Add(new SubImmFromRm32Handler(_decoder)); // SUB r/m32, imm32 (opcode 0x81 /5)
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_handlers.Add(new SubImmFromRm32SignExtendedHandler(_decoder)); // SUB r/m32, imm8 (opcode 0x83 /5)
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// 8-bit handlers
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_handlers.Add(new SubRm8R8Handler(_decoder));
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_handlers.Add(new SubR8Rm8Handler(_decoder));
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_handlers.Add(new SubAlImm8Handler(_decoder));
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_handlers.Add(new SubImmFromRm8Handler(_decoder));
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_handlers.Add(new SubRm8R8Handler(_decoder)); // SUB r/m8, r8 (opcode 0x28)
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_handlers.Add(new SubR8Rm8Handler(_decoder)); // SUB r8, r/m8 (opcode 0x2A)
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_handlers.Add(new SubAlImm8Handler(_decoder)); // SUB AL, imm8 (opcode 0x2C)
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_handlers.Add(new SubImmFromRm8Handler(_decoder)); // SUB r/m8, imm8 (opcode 0x80 /5)
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}
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/// <summary>
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@ -460,9 +471,9 @@ public class InstructionHandlerFactory
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private void RegisterNopHandlers()
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{
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// Register NOP handlers
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_handlers.Add(new NopHandler(_decoder));
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_handlers.Add(new TwoByteNopHandler(_decoder));
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_handlers.Add(new MultiByteNopHandler(_decoder));
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_handlers.Add(new NopHandler(_decoder)); // NOP (opcode 0x90)
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_handlers.Add(new TwoByteNopHandler(_decoder)); // 2-byte NOP (opcode 0x66 0x90)
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_handlers.Add(new MultiByteNopHandler(_decoder)); // Multi-byte NOP (opcode 0F 1F /0)
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}
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/// <summary>
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@ -491,16 +502,15 @@ public class InstructionHandlerFactory
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_handlers.Add(new BsrR32Rm32Handler(_decoder)); // BSR r32, r/m32 (0F BD)
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}
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/// <summary>
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/// Registers all NEG instruction handlers
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/// </summary>
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private void RegisterNegHandlers()
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{
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// NEG r/m8 handler (F6 /3)
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_handlers.Add(new NegRm8Handler(_decoder));
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// NEG r/m32 handler (F7 /3)
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_handlers.Add(new NegRm32Handler(_decoder));
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_handlers.Add(new NegRm8Handler(_decoder)); // NEG r/m8 handler (F6 /3)
|
||||
_handlers.Add(new NegRm32Handler(_decoder)); // NEG r/m32 handler (F7 /3)
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
@ -508,11 +518,8 @@ public class InstructionHandlerFactory
|
||||
/// </summary>
|
||||
private void RegisterMulHandlers()
|
||||
{
|
||||
// MUL r/m8 handler (F6 /4)
|
||||
_handlers.Add(new MulRm8Handler(_decoder));
|
||||
|
||||
// MUL r/m32 handler (F7 /4)
|
||||
_handlers.Add(new MulRm32Handler(_decoder));
|
||||
_handlers.Add(new MulRm8Handler(_decoder)); // MUL r/m8 handler (F6 /4)
|
||||
_handlers.Add(new MulRm32Handler(_decoder)); // MUL r/m32 handler (F7 /4)
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
@ -520,11 +527,8 @@ public class InstructionHandlerFactory
|
||||
/// </summary>
|
||||
private void RegisterNotHandlers()
|
||||
{
|
||||
// NOT r/m8 handler (F6 /2)
|
||||
_handlers.Add(new NotRm8Handler(_decoder));
|
||||
|
||||
// NOT r/m32 handler (F7 /2)
|
||||
_handlers.Add(new NotRm32Handler(_decoder));
|
||||
_handlers.Add(new NotRm8Handler(_decoder)); // NOT r/m8 handler (F6 /2)
|
||||
_handlers.Add(new NotRm32Handler(_decoder)); // NOT r/m32 handler (F7 /2)
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
@ -532,20 +536,12 @@ public class InstructionHandlerFactory
|
||||
/// </summary>
|
||||
private void RegisterImulHandlers()
|
||||
{
|
||||
// IMUL r/m8 handler (F6 /5)
|
||||
_handlers.Add(new ImulRm8Handler(_decoder));
|
||||
_handlers.Add(new ImulRm8Handler(_decoder)); // IMUL r/m8 handler (F6 /5)
|
||||
_handlers.Add(new ImulRm32Handler(_decoder)); // IMUL r/m32 handler (F7 /5)
|
||||
|
||||
// IMUL r/m32 handler (F7 /5)
|
||||
_handlers.Add(new ImulRm32Handler(_decoder));
|
||||
|
||||
// IMUL r32, r/m32 handler (0F AF /r)
|
||||
_handlers.Add(new ImulR32Rm32Handler(_decoder));
|
||||
|
||||
// IMUL r32, r/m32, imm8 handler (6B /r ib)
|
||||
_handlers.Add(new ImulR32Rm32Imm8Handler(_decoder));
|
||||
|
||||
// IMUL r32, r/m32, imm32 handler (69 /r id)
|
||||
_handlers.Add(new ImulR32Rm32Imm32Handler(_decoder));
|
||||
_handlers.Add(new ImulR32Rm32Handler(_decoder)); // IMUL r32, r/m32 handler (0F AF /r)
|
||||
_handlers.Add(new ImulR32Rm32Imm8Handler(_decoder)); // IMUL r32, r/m32, imm8 handler (6B /r ib)
|
||||
_handlers.Add(new ImulR32Rm32Imm32Handler(_decoder)); // IMUL r32, r/m32, imm32 handler (69 /r id)
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
@ -553,11 +549,8 @@ public class InstructionHandlerFactory
|
||||
/// </summary>
|
||||
private void RegisterDivHandlers()
|
||||
{
|
||||
// DIV r/m8 handler (F6 /6)
|
||||
_handlers.Add(new DivRm8Handler(_decoder));
|
||||
|
||||
// DIV r/m32 handler (F7 /6)
|
||||
_handlers.Add(new DivRm32Handler(_decoder));
|
||||
_handlers.Add(new DivRm8Handler(_decoder)); // DIV r/m8 handler (F6 /6)
|
||||
_handlers.Add(new DivRm32Handler(_decoder)); // DIV r/m32 handler (F7 /6)
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
@ -565,11 +558,8 @@ public class InstructionHandlerFactory
|
||||
/// </summary>
|
||||
private void RegisterIdivHandlers()
|
||||
{
|
||||
// IDIV r/m8 handler (F6 /7)
|
||||
_handlers.Add(new IdivRm8Handler(_decoder));
|
||||
|
||||
// IDIV r/m32 handler (F7 /7)
|
||||
_handlers.Add(new IdivRm32Handler(_decoder));
|
||||
_handlers.Add(new IdivRm8Handler(_decoder)); // IDIV r/m8 handler (F6 /7)
|
||||
_handlers.Add(new IdivRm32Handler(_decoder)); // IDIV r/m32 handler (F7 /7)
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
|
||||
@ -43,7 +43,6 @@ public class InstructionDecoder
|
||||
|
||||
// Create specialized decoders
|
||||
_prefixDecoder = new PrefixDecoder();
|
||||
new ModRMDecoder(this);
|
||||
|
||||
// Create the instruction handler factory
|
||||
_handlerFactory = new InstructionHandlerFactory(_codeBuffer, this, _length);
|
||||
@ -101,7 +100,7 @@ public class InstructionDecoder
|
||||
|
||||
Printer.WriteLine?.Invoke($"Resolved handler {handler?.GetType().Name}");
|
||||
|
||||
bool handlerSuccess = false;
|
||||
bool handlerSuccess;
|
||||
|
||||
// Try to decode with a handler first
|
||||
if (handler != null)
|
||||
@ -115,6 +114,11 @@ public class InstructionDecoder
|
||||
// Decode the instruction
|
||||
handlerSuccess = handler.Decode(opcode, instruction);
|
||||
|
||||
if (!handlerSuccess)
|
||||
{
|
||||
Printer.WriteLine?.Invoke($"Handler {handler.GetType().Name} failed!");
|
||||
}
|
||||
|
||||
// Apply segment override prefix to the structured operands if needed
|
||||
if (handlerSuccess && hasSegmentOverride)
|
||||
{
|
||||
|
||||
@ -77,7 +77,7 @@ public class ModRMDecoder
|
||||
if (_decoder.CanReadByte())
|
||||
{
|
||||
byte sib = _decoder.ReadByte();
|
||||
return _sibDecoder.DecodeSIB(sib, 0, operandSize);
|
||||
return _sibDecoder.DecodeSIB(sib, 0, operandSize, mod);
|
||||
}
|
||||
|
||||
// Fallback for incomplete data
|
||||
@ -95,7 +95,7 @@ public class ModRMDecoder
|
||||
{
|
||||
byte sib = _decoder.ReadByte();
|
||||
sbyte disp8 = (sbyte)(_decoder.CanReadByte() ? _decoder.ReadByte() : 0);
|
||||
return _sibDecoder.DecodeSIB(sib, (uint)disp8, operandSize);
|
||||
return _sibDecoder.DecodeSIB(sib, (uint)disp8, operandSize, mod);
|
||||
}
|
||||
|
||||
// Fallback for incomplete data
|
||||
@ -108,6 +108,7 @@ public class ModRMDecoder
|
||||
sbyte disp8 = (sbyte)_decoder.ReadByte();
|
||||
|
||||
// Always create a displacement memory operand for mod=1, even if displacement is 0
|
||||
// This ensures we show exactly what's encoded in the ModR/M byte
|
||||
return OperandFactory.CreateDisplacementMemoryOperand(rmIndex, disp8, operandSize);
|
||||
}
|
||||
|
||||
@ -123,7 +124,7 @@ public class ModRMDecoder
|
||||
{
|
||||
byte sib = _decoder.ReadByte();
|
||||
uint disp32 = _decoder.ReadUInt32();
|
||||
return _sibDecoder.DecodeSIB(sib, disp32, operandSize);
|
||||
return _sibDecoder.DecodeSIB(sib, disp32, operandSize, mod);
|
||||
}
|
||||
|
||||
// Fallback for incomplete data
|
||||
@ -143,11 +144,7 @@ public class ModRMDecoder
|
||||
return OperandFactory.CreateDisplacementMemoryOperand(rmIndex, (long)disp32, operandSize);
|
||||
}
|
||||
|
||||
// Only show displacement if it's not zero
|
||||
if (disp32 == 0)
|
||||
{
|
||||
return OperandFactory.CreateBaseRegisterMemoryOperand(rmIndex, operandSize);
|
||||
}
|
||||
// Always include the displacement, even if it's zero, to match the encoding
|
||||
|
||||
// Cast to long to preserve the unsigned value for large displacements
|
||||
return OperandFactory.CreateDisplacementMemoryOperand(rmIndex, (long)disp32, operandSize);
|
||||
|
||||
@ -24,8 +24,9 @@ public class SIBDecoder
|
||||
/// <param name="sib">The SIB byte</param>
|
||||
/// <param name="displacement">The displacement value</param>
|
||||
/// <param name="operandSize">The size of the operand in bits (8, 16, 32, or 64)</param>
|
||||
/// <param name="mod">The mod field from the ModR/M byte</param>
|
||||
/// <returns>The decoded SIB operand</returns>
|
||||
public Operand DecodeSIB(byte sib, uint displacement, int operandSize)
|
||||
public Operand DecodeSIB(byte sib, uint displacement, int operandSize, byte mod = 0)
|
||||
{
|
||||
// Extract fields from SIB byte
|
||||
byte scale = (byte)((sib & Constants.SIB_SCALE_MASK) >> 6);
|
||||
@ -39,8 +40,8 @@ public class SIBDecoder
|
||||
// Special case: ESP/SP (4) in index field means no index register
|
||||
if (index == RegisterIndex.Sp)
|
||||
{
|
||||
// Special case: EBP/BP (5) in base field with no displacement means disp32 only
|
||||
if (@base == RegisterIndex.Bp && displacement == 0)
|
||||
// Special case: EBP/BP (5) in base field with mod=00 means disp32 only
|
||||
if (@base == RegisterIndex.Bp && mod == 0)
|
||||
{
|
||||
if (_decoder.CanReadUInt())
|
||||
{
|
||||
@ -56,16 +57,12 @@ public class SIBDecoder
|
||||
}
|
||||
|
||||
// When index is ESP (no index), we just have a base register with optional displacement
|
||||
if (displacement == 0)
|
||||
{
|
||||
return OperandFactory.CreateBaseRegisterMemoryOperand(@base, operandSize);
|
||||
}
|
||||
|
||||
// Always include the displacement, even if it's zero, to match the encoding
|
||||
return OperandFactory.CreateDisplacementMemoryOperand(@base, (int)displacement, operandSize);
|
||||
}
|
||||
|
||||
// Special case: EBP/BP (5) in base field with no displacement means disp32 only
|
||||
if (@base == RegisterIndex.Bp && displacement == 0)
|
||||
// Special case: EBP/BP (5) in base field with mod=00 means disp32 only
|
||||
if (@base == RegisterIndex.Bp && mod == 0 && displacement == 0)
|
||||
{
|
||||
if (_decoder.CanReadUInt())
|
||||
{
|
||||
@ -98,6 +95,22 @@ public class SIBDecoder
|
||||
operandSize);
|
||||
}
|
||||
|
||||
// Special case: When base is EBP/BP and mod is 01 or 10
|
||||
// This is a special case in x86 addressing.
|
||||
if (@base == RegisterIndex.Bp && (mod == 1 || mod == 2))
|
||||
{
|
||||
int scaleFactorBp = 1 << scale; // 1, 2, 4, or 8
|
||||
|
||||
// Always include the displacement for EBP, even if it's zero
|
||||
// This ensures we show exactly what's encoded in the ModR/M and SIB bytes
|
||||
return OperandFactory.CreateScaledIndexMemoryOperand(
|
||||
index,
|
||||
scaleFactorBp,
|
||||
@base,
|
||||
(int)displacement,
|
||||
operandSize);
|
||||
}
|
||||
|
||||
// Normal case with base and index registers
|
||||
int scaleFactor = 1 << scale; // 1, 2, 4, or 8
|
||||
|
||||
|
||||
Reference in New Issue
Block a user