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add tons of tests

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bird_egop
2025-04-15 22:20:46 +03:00
parent abe4d38d4b
commit 2123ed2c5d
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X86DisassemblerTests/TestData/shr_tests.csv Normal file
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# SHR instruction tests
# Format: RawBytes;Instructions
RawBytes;Instructions
# SHR r/m8, 1 (opcode D0 /5)
D0E8;[{ "Type": "Shr", "Operands": ["al", "0x01"] }]
D0EB;[{ "Type": "Shr", "Operands": ["bl", "0x01"] }]
# SHR r/m32, 1 (opcode D1 /5)
D1E8;[{ "Type": "Shr", "Operands": ["eax", "0x01"] }]
D1EB;[{ "Type": "Shr", "Operands": ["ebx", "0x01"] }]
# SHR r/m8, CL (opcode D2 /5)
D2E8;[{ "Type": "Shr", "Operands": ["al", "cl"] }]
D2EB;[{ "Type": "Shr", "Operands": ["bl", "cl"] }]
# SHR r/m32, CL (opcode D3 /5)
D3E8;[{ "Type": "Shr", "Operands": ["eax", "cl"] }]
D3EB;[{ "Type": "Shr", "Operands": ["ebx", "cl"] }]
# SHR r/m8, imm8 (opcode C0 /5)
C0E805;[{ "Type": "Shr", "Operands": ["al", "0x05"] }]
C0EB05;[{ "Type": "Shr", "Operands": ["bl", "0x05"] }]
# SHR r/m32, imm8 (opcode C1 /5)
C1E805;[{ "Type": "Shr", "Operands": ["eax", "0x05"] }]
C1EB05;[{ "Type": "Shr", "Operands": ["ebx", "0x05"] }]
# SHR with memory operands
D02C2510;[{ "Type": "Shr", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
D32C25;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "cl"] }]
C12C2505;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "0x05"] }]
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