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Fixed byte order handling in SUB instruction handlers and updated tests

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Implemented SUB r32, r/m32 instruction handlers and tests

Added comprehensive tests for Push/Pop, Xchg, Sub instructions and enhanced segment override tests
This commit is contained in:
bird_egop
2025-04-13 14:25:27 +03:00
parent 44c73321ea
commit 2c85192d13
9 changed files with 959 additions and 3 deletions
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11
X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs
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@ -77,6 +77,7 @@ public class InstructionHandlerFactory
RegisterFloatingPointHandlers();
RegisterStringHandlers();
RegisterMovHandlers();
RegisterSubHandlers(); // Register SUB handlers
}
/// <summary>
@ -367,6 +368,16 @@ public class InstructionHandlerFactory
_handlers.Add(new AndEaxImmHandler(_codeBuffer, _decoder, _length));
}
/// <summary>
/// Registers all SUB instruction handlers
/// </summary>
private void RegisterSubHandlers()
{
// Add SUB register/memory handlers
_handlers.Add(new Sub.SubRm32R32Handler(_codeBuffer, _decoder, _length));
_handlers.Add(new Sub.SubR32Rm32Handler(_codeBuffer, _decoder, _length));
}
/// <summary>
/// Gets the handler that can decode the given opcode
/// </summary>