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Code Issues Releases Activity

Split FloatingPointHandler into specialized handlers for each instruction type and fixed FLDCW instruction formatting

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This commit is contained in:
bird_egop
2025-04-12 23:33:40 +03:00
parent 82653f96f2
commit 3cc6d27e33
9 changed files with 260 additions and 18 deletions
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2
X86Disassembler/X86/Handlers/FloatingPoint/Float32OperationHandler.cs
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@ -70,7 +70,7 @@ public class Float32OperationHandler : FloatingPointBaseHandler
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
instruction.Operands = $"dword ptr {operand}";
instruction.Operands = operand;
}
else // Register operand (ST(i))
{

4
X86Disassembler/X86/Handlers/FloatingPoint/Float64OperationHandler.cs
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@ -69,8 +69,8 @@ public class Float64OperationHandler : FloatingPointBaseHandler
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
instruction.Operands = $"qword ptr {operand}";
string operand = ModRMDecoder.DecodeModRM(mod, rm, true); // true for 64-bit operand
instruction.Operands = operand;
}
else // Register operand (ST(i))
{

4
X86Disassembler/X86/Handlers/FloatingPoint/Int16OperationHandler.cs
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@ -69,8 +69,10 @@ public class Int16OperationHandler : FloatingPointBaseHandler
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
// Need to modify the default dword ptr to word ptr for 16-bit integers
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
instruction.Operands = $"word ptr {operand}";
operand = operand.Replace("dword ptr", "word ptr");
instruction.Operands = operand;
}
else // Register operand (ST(i))
{

2
X86Disassembler/X86/Handlers/FloatingPoint/Int32OperationHandler.cs
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@ -70,7 +70,7 @@ public class Int32OperationHandler : FloatingPointBaseHandler
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
instruction.Operands = $"dword ptr {operand}";
instruction.Operands = operand;
}
else // Register operand (ST(i))
{

13
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreControlHandler.cs
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@ -74,11 +74,20 @@ public class LoadStoreControlHandler : FloatingPointBaseHandler
// Different operand types based on the instruction
if (reg == 0 || reg == 2 || reg == 3) // fld, fst, fstp
{
instruction.Operands = $"dword ptr {operand}";
// Keep the dword ptr prefix from ModRMDecoder
instruction.Operands = operand;
}
else // fldenv, fldcw, fnstenv, fnstcw
{
instruction.Operands = operand;
if (reg == 5) // fldcw - should use word ptr
{
instruction.Operands = operand.Replace("dword ptr", "word ptr");
}
else // fldenv, fnstenv, fnstcw
{
// Remove the dword ptr prefix for other control operations
instruction.Operands = operand.Replace("dword ptr ", "");
}
}
}
else // Register operand (ST(i))

9
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreFloat64Handler.cs
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@ -68,15 +68,16 @@ public class LoadStoreFloat64Handler : FloatingPointBaseHandler
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
string operand = ModRMDecoder.DecodeModRM(mod, rm, true); // true for 64-bit operand
if (reg == 0 || reg == 2 || reg == 3) // fld, fst, fstp
{
instruction.Operands = $"qword ptr {operand}";
instruction.Operands = operand;
}
else // frstor, fnsave, fnstsw
{
instruction.Operands = operand;
// Remove the qword ptr prefix for these operations
instruction.Operands = operand.Replace("qword ptr ", "");
}
}
else // Register operand (ST(i))

14
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt16Handler.cs
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@ -77,21 +77,27 @@ public class LoadStoreInt16Handler : FloatingPointBaseHandler
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
if (reg == 0 || reg == 2 || reg == 3 || reg == 5 || reg == 7) // fild, fist, fistp, fild, fistp
{
if (reg == 5 || reg == 7) // 64-bit integer
{
instruction.Operands = $"qword ptr {operand}";
// Replace dword ptr with qword ptr for 64-bit integers
operand = operand.Replace("dword ptr", "qword ptr");
instruction.Operands = operand;
}
else // 16-bit integer
{
instruction.Operands = $"word ptr {operand}";
// Replace dword ptr with word ptr for 16-bit integers
operand = operand.Replace("dword ptr", "word ptr");
instruction.Operands = operand;
}
}
else if (reg == 4 || reg == 6) // fbld, fbstp
{
instruction.Operands = $"tbyte ptr {operand}";
// Replace dword ptr with tbyte ptr for 80-bit packed BCD
operand = operand.Replace("dword ptr", "tbyte ptr");
instruction.Operands = operand;
}
else
{

9
X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt32Handler.cs
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@ -70,14 +70,17 @@ public class LoadStoreInt32Handler : FloatingPointBaseHandler
if (mod != 3) // Memory operand
{
string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
if (reg == 0 || reg == 2 || reg == 3) // fild, fist, fistp
{
instruction.Operands = $"dword ptr {operand}";
// Keep the dword ptr prefix for integer operations
instruction.Operands = operand;
}
else if (reg == 5 || reg == 7) // fld, fstp (extended precision)
{
instruction.Operands = $"tword ptr {operand}";
// Replace dword ptr with tword ptr for extended precision
operand = operand.Replace("dword ptr", "tword ptr");
instruction.Operands = operand;
}
else
{