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Fix x86 disassembler issues with direct memory addressing and immediate value formatting

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This commit is contained in:
bird_egop
2025-04-15 02:29:32 +03:00
parent d351f41808
commit 3ea327064a
67 changed files with 854 additions and 453 deletions
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7
X86Disassembler/X86/Handlers/ArithmeticUnary/DivRm32Handler.cs
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@ -56,6 +56,13 @@ public class DivRm32Handler : InstructionHandler
// For DIV r/m32 (0xF7 /6):
// - The r/m field with mod specifies the operand (register or memory)
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
// Verify this is a DIV instruction
// The reg field should be 6 (DIV), which maps to RegisterIndex.Si in our enum
if (reg != RegisterIndex.Si)
{
return false;
}
// Set the structured operands
// DIV has only one operand

7
X86Disassembler/X86/Handlers/ArithmeticUnary/IdivRm32Handler.cs
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@ -56,6 +56,13 @@ public class IdivRm32Handler : InstructionHandler
// For IDIV r/m32 (0xF7 /7):
// - The r/m field with mod specifies the operand (register or memory)
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
// Verify this is an IDIV instruction
// The reg field should be 7 (IDIV)
if (reg != RegisterIndex.Di)
{
return false;
}
// Set the structured operands
// IDIV has only one operand

10
X86Disassembler/X86/Handlers/ArithmeticUnary/ImulRm32Handler.cs
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@ -53,9 +53,19 @@ public class ImulRm32Handler : InstructionHandler
}
// Read the ModR/M byte
// For IMUL r/m32 (0xF7 /5):
// - The r/m field with mod specifies the operand (register or memory)
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
// Verify this is an IMUL instruction
// The reg field should be 5 (IMUL), which maps to RegisterIndex.Bp in our enum
if (reg != RegisterIndex.Bp)
{
return false;
}
// Set the structured operands
// IMUL has only one operand
instruction.StructuredOperands =
[
operand

7
X86Disassembler/X86/Handlers/ArithmeticUnary/MulRm32Handler.cs
View File

@ -56,6 +56,13 @@ public class MulRm32Handler : InstructionHandler
// For MUL r/m32 (0xF7 /4):
// - The r/m field with mod specifies the operand (register or memory)
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
// Verify this is a MUL instruction
// The reg field should be 4 (MUL), which maps to RegisterIndex.Sp in our enum
if (reg != RegisterIndex.Sp)
{
return false;
}
// Set the structured operands
// MUL has only one operand

7
X86Disassembler/X86/Handlers/ArithmeticUnary/NegRm32Handler.cs
View File

@ -56,6 +56,13 @@ public class NegRm32Handler : InstructionHandler
// For NEG r/m32 (0xF7 /3):
// - The r/m field with mod specifies the operand (register or memory)
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
// Verify this is a NEG instruction
// The reg field should be 3 (NEG), which maps to RegisterIndex.B in our enum
if (reg != RegisterIndex.B)
{
return false;
}
// Set the structured operands
// NEG has only one operand

3
X86Disassembler/X86/Handlers/ArithmeticUnary/NotRm32Handler.cs
View File

@ -59,7 +59,8 @@ public class NotRm32Handler : InstructionHandler
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
// Verify this is a NOT instruction
if (reg != RegisterIndex.C)
// The reg field should be 2 (NOT), which maps to RegisterIndex.D in our enum
if (reg != RegisterIndex.D)
{
return false;
}