mirror of
https://github.com/sampletext32/ParkanPlayground.git
synced 2025-06-20 08:18:36 +03:00
Fix x86 disassembler issues with direct memory addressing and immediate value formatting
This commit is contained in:
bird_egop
@ -66,8 +66,8 @@ public class Float64OperationHandler : InstructionHandler
|
||||
}
|
||||
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM(true); // true for 64-bit operand
|
||||
|
||||
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM64(); // Use the 64-bit version
|
||||
|
||||
// Set the instruction type based on the reg field
|
||||
instruction.Type = InstructionTypes[(int)reg];
|
||||
|
||||
|
||||
@ -10,61 +10,61 @@ public class Int32OperationHandler : InstructionHandler
|
||||
// Memory operand instruction types for DA opcode - operations on int32
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
InstructionType.Unknown, // fiadd - not in enum
|
||||
InstructionType.Unknown, // fimul - not in enum
|
||||
InstructionType.Unknown, // ficom - not in enum
|
||||
InstructionType.Unknown, // ficomp - not in enum
|
||||
InstructionType.Unknown, // fisub - not in enum
|
||||
InstructionType.Unknown, // fisubr - not in enum
|
||||
InstructionType.Unknown, // fidiv - not in enum
|
||||
InstructionType.Unknown // fidivr - not in enum
|
||||
InstructionType.Fiadd, // fiadd dword ptr [r/m]
|
||||
InstructionType.Fimul, // fimul dword ptr [r/m]
|
||||
InstructionType.Ficom, // ficom dword ptr [r/m]
|
||||
InstructionType.Ficomp, // ficomp dword ptr [r/m]
|
||||
InstructionType.Fisub, // fisub dword ptr [r/m]
|
||||
InstructionType.Fisubr, // fisubr dword ptr [r/m]
|
||||
InstructionType.Fidiv, // fidiv dword ptr [r/m]
|
||||
InstructionType.Fidivr // fidivr dword ptr [r/m]
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex SrcIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FCMOVB st(0), st(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Fcmovb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVE st(0), st(i)
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Fcmove, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVBE st(0), st(i)
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Fcmovbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVU st(0), st(i)
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// Special case
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) }
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Fcmovu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
|
||||
@ -10,14 +10,14 @@ public class LoadStoreControlHandler : InstructionHandler
|
||||
// Memory operand instruction types for D9 opcode - load, store, and control operations
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
InstructionType.Fld, // 0
|
||||
InstructionType.Unknown, // 1
|
||||
InstructionType.Fst, // 2
|
||||
InstructionType.Fstp, // 3
|
||||
InstructionType.Unknown, // 4 - fldenv not in enum
|
||||
InstructionType.Fldcw, // 5
|
||||
InstructionType.Unknown, // 6 - fnstenv not in enum
|
||||
InstructionType.Fnstcw // 7
|
||||
InstructionType.Fld, // 0 - fld dword ptr [r/m]
|
||||
InstructionType.Unknown, // 1 - (reserved)
|
||||
InstructionType.Fst, // 2 - fst dword ptr [r/m]
|
||||
InstructionType.Fstp, // 3 - fstp dword ptr [r/m]
|
||||
InstructionType.Fldenv, // 4 - fldenv [r/m]
|
||||
InstructionType.Fldcw, // 5 - fldcw [r/m]
|
||||
InstructionType.Fnstenv, // 6 - fnstenv [r/m]
|
||||
InstructionType.Fnstcw // 7 - fnstcw [r/m]
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
@ -50,28 +50,28 @@ public class LoadStoreControlHandler : InstructionHandler
|
||||
{ (RegisterIndex.Si, RegisterIndex.Di), (InstructionType.Fxam, null) },
|
||||
|
||||
// D9F0-D9FF special instructions (reg=7)
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, null) }, // f2xm1 not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, null) }, // fyl2x not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, null) }, // fptan not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, null) }, // fpatan not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, null) }, // fxtract not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, null) }, // fprem1 not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, null) }, // fdecstp not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, null) }, // fincstp not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.F2xm1, null) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Fyl2x, null) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Fptan, null) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Fpatan, null) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Fxtract, null) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Fprem1, null) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Fdecstp, null) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Fincstp, null) },
|
||||
|
||||
// D9D0-D9DF special instructions (reg=5)
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, null) }, // fprem not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, null) }, // fyl2xp1 not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, null) }, // fsqrt not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, null) }, // fsincos not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, null) }, // frndint not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, null) }, // fscale not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, null) }, // fsin not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, null) }, // fcos not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Fprem, null) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Fyl2xp1, null) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Fsqrt, null) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Fsincos, null) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Frndint, null) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Fscale, null) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Fsin, null) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Fcos, null) },
|
||||
|
||||
// D9C8-D9CF special instructions (reg=4)
|
||||
{ (RegisterIndex.Bp, RegisterIndex.A), (InstructionType.Unknown, null) }, // fnop not in enum
|
||||
{ (RegisterIndex.Bp, RegisterIndex.C), (InstructionType.Unknown, null) } // fwait not in enum
|
||||
{ (RegisterIndex.Bp, RegisterIndex.A), (InstructionType.Fnop, null) },
|
||||
{ (RegisterIndex.Bp, RegisterIndex.C), (InstructionType.Fwait, null) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
|
||||
@ -23,28 +23,28 @@ public class LoadStoreFloat64Handler : InstructionHandler
|
||||
// Memory operand instruction types for DD opcode
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
InstructionType.Fld, // 0
|
||||
InstructionType.Unknown, // 1
|
||||
InstructionType.Fst, // 2
|
||||
InstructionType.Fstp, // 3
|
||||
InstructionType.Unknown, // 4 - frstor not in enum
|
||||
InstructionType.Unknown, // 5
|
||||
InstructionType.Unknown, // 6 - fnsave not in enum
|
||||
InstructionType.Fnstsw // 7
|
||||
InstructionType.Fld, // 0 - fld qword ptr [r/m]
|
||||
InstructionType.Unknown, // 1 - (reserved)
|
||||
InstructionType.Fst, // 2 - fst qword ptr [r/m]
|
||||
InstructionType.Fstp, // 3 - fstp qword ptr [r/m]
|
||||
InstructionType.Frstor, // 4 - frstor [r/m]
|
||||
InstructionType.Unknown, // 5 - (reserved)
|
||||
InstructionType.Fnsave, // 6 - fnsave [r/m]
|
||||
InstructionType.Fnstsw // 7 - fnstsw [r/m]
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex OperandIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FFREE ST(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Ffree, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Ffree, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Ffree, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Ffree, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Ffree, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Ffree, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Ffree, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Ffree, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FST ST(i)
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Fst, FpuRegisterIndex.ST0) },
|
||||
@ -67,24 +67,24 @@ public class LoadStoreFloat64Handler : InstructionHandler
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Fstp, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FUCOM ST(i)
|
||||
{ (RegisterIndex.Si, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.A), (InstructionType.Fucom, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Fucom, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Fucom, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.B), (InstructionType.Fucom, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Sp), (InstructionType.Fucom, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Bp), (InstructionType.Fucom, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Si), (InstructionType.Fucom, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Di), (InstructionType.Fucom, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FUCOMP ST(i)
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) }
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Fucomp, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Fucomp, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Fucomp, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Fucomp, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Fucomp, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Fucomp, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Fucomp, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Fucomp, FpuRegisterIndex.ST7) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
|
||||
@ -11,13 +11,13 @@ public class LoadStoreInt16Handler : InstructionHandler
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
InstructionType.Fild, // fild word ptr [r/m]
|
||||
InstructionType.Unknown, // fistt word ptr [r/m] (not implemented)
|
||||
InstructionType.Fst, // fist word ptr [r/m]
|
||||
InstructionType.Fstp, // fistp word ptr [r/m]
|
||||
InstructionType.Fld, // fbld packed BCD [r/m]
|
||||
InstructionType.Fisttp, // fistt word ptr [r/m]
|
||||
InstructionType.Fist, // fist word ptr [r/m]
|
||||
InstructionType.Fistp, // fistp word ptr [r/m]
|
||||
InstructionType.Fbld, // fbld packed BCD [r/m]
|
||||
InstructionType.Fild, // fild qword ptr [r/m] (64-bit integer)
|
||||
InstructionType.Fst, // fbstp packed BCD [r/m]
|
||||
InstructionType.Fstp // fistp qword ptr [r/m] (64-bit integer)
|
||||
InstructionType.Fbstp, // fbstp packed BCD [r/m]
|
||||
InstructionType.Fistp // fistp qword ptr [r/m] (64-bit integer)
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
@ -94,13 +94,6 @@ public class LoadStoreInt16Handler : InstructionHandler
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
|
||||
|
||||
// Check for FNSTSW AX (DF E0)
|
||||
if (mod == 3 && reg == RegisterIndex.Bp && rm == RegisterIndex.A)
|
||||
{
|
||||
// This is handled by the FnstswHandler, so we should not handle it here
|
||||
return false;
|
||||
}
|
||||
|
||||
// Handle based on addressing mode
|
||||
if (mod != 3) // Memory operand
|
||||
{
|
||||
|
||||
@ -10,82 +10,82 @@ public class LoadStoreInt32Handler : InstructionHandler
|
||||
// Memory operand instruction types for DB opcode - load/store int32, misc
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
InstructionType.Unknown, // fild - not in enum
|
||||
InstructionType.Unknown, // ??
|
||||
InstructionType.Unknown, // fist - not in enum
|
||||
InstructionType.Unknown, // fistp - not in enum
|
||||
InstructionType.Unknown, // ??
|
||||
InstructionType.Fld, // fld - 80-bit extended precision
|
||||
InstructionType.Unknown, // ??
|
||||
InstructionType.Fstp // fstp - 80-bit extended precision
|
||||
InstructionType.Fild, // fild dword ptr [r/m]
|
||||
InstructionType.Unknown, // fisttp dword ptr [r/m] (not implemented)
|
||||
InstructionType.Fist, // fist dword ptr [r/m]
|
||||
InstructionType.Fistp, // fistp dword ptr [r/m]
|
||||
InstructionType.Unknown, // (reserved)
|
||||
InstructionType.Fld, // fld extended-precision [r/m]
|
||||
InstructionType.Unknown, // (reserved)
|
||||
InstructionType.Fstp // fstp extended-precision [r/m]
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FCMOVNB ST(0), ST(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Fcmovnb, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVNE ST(0), ST(i)
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Fcmovne, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVNBE ST(0), ST(i)
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Fcmovnbe, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVNU ST(0), ST(i)
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Fcmovnu, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// Special cases
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) }, // fclex
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) }, // finit
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Fclex, FpuRegisterIndex.ST0, null) }, // fclex
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Finit, FpuRegisterIndex.ST0, null) }, // finit
|
||||
|
||||
// FUCOMI ST(0), ST(i)
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Fucomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCOMI ST(0), ST(i)
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) }
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Fcomi, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
|
||||
Reference in New Issue
Block a user