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Unified ADC accumulator handlers into a single handler
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@ -23,40 +23,9 @@ public class XchgEaxRegHandler : InstructionHandler
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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return opcode >= 0x91 && opcode <= 0x97;
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}
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/// <summary>
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/// Maps the register index from the opcode to the RegisterIndex enum value expected by tests
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/// </summary>
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/// <param name="opcodeRegIndex">The register index from the opcode (0-7)</param>
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/// <returns>The corresponding RegisterIndex enum value</returns>
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private RegisterIndex MapOpcodeToRegisterIndex(int opcodeRegIndex)
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{
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// The mapping from opcode register index to RegisterIndex enum is:
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// 0 -> A (EAX)
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// 1 -> C (ECX)
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// 2 -> D (EDX)
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// 3 -> B (EBX)
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// 4 -> Sp (ESP)
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// 5 -> Bp (EBP)
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// 6 -> Si (ESI)
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// 7 -> Di (EDI)
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// This mapping is based on the x86 instruction encoding
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// but we need to map to the RegisterIndex enum values that the tests expect
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return opcodeRegIndex switch
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{
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0 => RegisterIndex.A, // EAX
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1 => RegisterIndex.C, // ECX
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2 => RegisterIndex.D, // EDX
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3 => RegisterIndex.B, // EBX
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4 => RegisterIndex.Sp, // ESP
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5 => RegisterIndex.Bp, // EBP
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6 => RegisterIndex.Si, // ESI
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7 => RegisterIndex.Di, // EDI
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_ => RegisterIndex.A // Default case, should never happen
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};
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// Only handle opcodes 0x91-0x97 when the operand size prefix is NOT present
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// This ensures 16-bit handlers get priority when the prefix is present
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return opcode >= 0x91 && opcode <= 0x97 && !Decoder.HasOperandSizePrefix();
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}
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/// <summary>
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@ -71,10 +40,7 @@ public class XchgEaxRegHandler : InstructionHandler
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instruction.Type = InstructionType.Xchg;
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// Register is encoded in the low 3 bits of the opcode
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int opcodeRegIndex = opcode & 0x07;
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// Map the opcode register index to the RegisterIndex enum value
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RegisterIndex reg = MapOpcodeToRegisterIndex(opcodeRegIndex);
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RegisterIndex reg = (RegisterIndex)(opcode & 0x07);
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// Create the register operands
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var eaxOperand = OperandFactory.CreateRegisterOperand(RegisterIndex.A);
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