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Simplified Int16OperationHandler by replacing complex if-else logic with a dictionary-based approach
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bird_egop
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@ -5,18 +5,86 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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/// </summary>
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public class Int16OperationHandler : InstructionHandler
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public class Int16OperationHandler : InstructionHandler
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{
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{
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// DE opcode - operations on int16
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// Memory operand mnemonics for DE opcode - operations on int16
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private static readonly string[] Mnemonics =
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private static readonly string[] MemoryMnemonics =
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[
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[
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"fiadd",
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"fiadd", // 0
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"fimul",
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"fimul", // 1
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"ficom",
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"ficom", // 2
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"ficomp",
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"ficomp", // 3
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"fisub",
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"fisub", // 4
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"fisubr",
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"fisubr", // 5
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"fidiv",
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"fidiv", // 6
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"fidivr"
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"fidivr" // 7
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];
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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{
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// FADDP st(i), st(0)
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{ (RegisterIndex.A, RegisterIndex.A), ("faddp", "st(0), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("faddp", "st(1), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("faddp", "st(2), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("faddp", "st(3), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("faddp", "st(4), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("faddp", "st(5), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("faddp", "st(6), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("faddp", "st(7), st(0)") },
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// FMULP st(i), st(0)
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{ (RegisterIndex.B, RegisterIndex.A), ("fmulp", "st(0), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.C), ("fmulp", "st(1), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.D), ("fmulp", "st(2), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.B), ("fmulp", "st(3), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Sp), ("fmulp", "st(4), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Bp), ("fmulp", "st(5), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Si), ("fmulp", "st(6), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Di), ("fmulp", "st(7), st(0)") },
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// Special cases
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{ (RegisterIndex.C, RegisterIndex.B), ("fcomp", "") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fcompp", "") },
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// FSUBP st(i), st(0)
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{ (RegisterIndex.Si, RegisterIndex.A), ("fsubp", "st(0), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.C), ("fsubp", "st(1), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.D), ("fsubp", "st(2), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.B), ("fsubp", "st(3), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Sp), ("fsubp", "st(4), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Bp), ("fsubp", "st(5), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Si), ("fsubp", "st(6), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Di), ("fsubp", "st(7), st(0)") },
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// FSUBRP st(i), st(0)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fsubrp", "st(0), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fsubrp", "st(1), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fsubrp", "st(2), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fsubrp", "st(3), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fsubrp", "st(4), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fsubrp", "st(5), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fsubrp", "st(6), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fsubrp", "st(7), st(0)") },
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// FDIVP st(i), st(0)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fdivp", "st(0), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fdivp", "st(1), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fdivp", "st(2), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fdivp", "st(3), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fdivp", "st(4), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fdivp", "st(5), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("fdivp", "st(6), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fdivp", "st(7), st(0)") },
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// FDIVRP st(i), st(0)
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{ (RegisterIndex.Bp, RegisterIndex.A), ("fdivrp", "st(0), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.C), ("fdivrp", "st(1), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.D), ("fdivrp", "st(2), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.B), ("fdivrp", "st(3), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Sp), ("fdivrp", "st(4), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Bp), ("fdivrp", "st(5), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Si), ("fdivrp", "st(6), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Di), ("fdivrp", "st(7), st(0)") }
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};
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/// <summary>
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/// <summary>
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/// Initializes a new instance of the Int16OperationHandler class
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/// Initializes a new instance of the Int16OperationHandler class
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@ -47,67 +115,30 @@ public class Int16OperationHandler : InstructionHandler
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/// <returns>True if the instruction was successfully decoded</returns>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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public override bool Decode(byte opcode, Instruction instruction)
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{
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{
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int position = Decoder.GetPosition();
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if (!Decoder.CanReadByte())
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if (position >= Length)
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{
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{
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return false;
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return false;
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}
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}
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// Read the ModR/M byte
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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// Set the mnemonic based on the opcode and reg field
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// Handle based on addressing mode
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instruction.Mnemonic = Mnemonics[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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if (mod != 3) // Memory operand
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{
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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// Need to modify the default dword ptr to word ptr for 16-bit integers
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// Need to modify the default dword ptr to word ptr for 16-bit integers
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instruction.Operands = destOperand.Replace("dword ptr", "word ptr");
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instruction.Operands = memOperand.Replace("dword ptr", "word ptr");
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}
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}
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else // Register operand (ST(i))
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else // Register operand (ST(i))
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{
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{
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// Special handling for register-register operations
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// Look up the register operation in our dictionary
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if (reg == RegisterIndex.A) // FADDP
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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{
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instruction.Mnemonic = "faddp";
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = $"st({(int)rm}), st(0)";
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instruction.Operands = operation.Operands;
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}
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else if (reg == RegisterIndex.B) // FMULP
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{
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instruction.Mnemonic = "fmulp";
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instruction.Operands = $"st({(int)rm}), st(0)";
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}
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else if (reg == RegisterIndex.C && rm == RegisterIndex.B) // FCOMP
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{
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instruction.Mnemonic = "fcomp";
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instruction.Operands = "";
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}
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else if (reg == RegisterIndex.D && rm == RegisterIndex.B) // FCOMPP
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{
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instruction.Mnemonic = "fcompp";
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instruction.Operands = "";
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}
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else if (reg == RegisterIndex.Si) // FSUBP
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{
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instruction.Mnemonic = "fsubp";
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instruction.Operands = $"st({(int)rm}), st(0)";
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}
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else if (reg == RegisterIndex.Di) // FSUBRP
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{
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instruction.Mnemonic = "fsubrp";
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instruction.Operands = $"st({(int)rm}), st(0)";
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}
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else if (reg == RegisterIndex.Sp) // FDIVP
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{
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instruction.Mnemonic = "fdivp";
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instruction.Operands = $"st({(int)rm}), st(0)";
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}
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else if (reg == RegisterIndex.Bp) // FDIVRP
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{
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instruction.Mnemonic = "fdivrp";
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instruction.Operands = $"st({(int)rm}), st(0)";
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}
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}
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else
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else
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{
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{
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