diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FaddFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FaddFloat64Handler.cs index 83e0c95..9830693 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FaddFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FaddFloat64Handler.cs @@ -51,8 +51,8 @@ public class FaddFloat64Handler : InstructionHandler return false; } - // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + // Read the ModR/M byte using the specialized FPU method for 64-bit operands + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Verify reg field is 0 (FADD) if (reg != 0) diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivFloat64Handler.cs index 7a5e304..28ca789 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivFloat64Handler.cs @@ -52,7 +52,7 @@ public class FdivFloat64Handler : InstructionHandler } // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Set the instruction type instruction.Type = InstructionType.Fdiv; diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivrFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivrFloat64Handler.cs index 9619587..78e7156 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivrFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivrFloat64Handler.cs @@ -52,7 +52,7 @@ public class FdivrFloat64Handler : InstructionHandler } // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Set the instruction type instruction.Type = InstructionType.Fdivr; diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FmulFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FmulFloat64Handler.cs index b9b8306..6a9d56d 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FmulFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FmulFloat64Handler.cs @@ -51,8 +51,8 @@ public class FmulFloat64Handler : InstructionHandler return false; } - // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + // Read the ModR/M byte using the specialized FPU method for 64-bit operands + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Set the instruction type instruction.Type = InstructionType.Fmul; diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubFloat64Handler.cs index 36960d6..5c2a301 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubFloat64Handler.cs @@ -52,7 +52,7 @@ public class FsubFloat64Handler : InstructionHandler } // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Set the instruction type instruction.Type = InstructionType.Fsub; diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubrFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubrFloat64Handler.cs index 6efedc8..46c84db 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubrFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubrFloat64Handler.cs @@ -52,7 +52,7 @@ public class FsubrFloat64Handler : InstructionHandler } // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Set the instruction type instruction.Type = InstructionType.Fsubr; diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomFloat64Handler.cs index 5835869..fe4fa6d 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomFloat64Handler.cs @@ -52,7 +52,7 @@ public class FcomFloat64Handler : InstructionHandler } // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Set the instruction type instruction.Type = InstructionType.Fcom; diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomSt0Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomSt0Handler.cs new file mode 100644 index 0000000..c93cf0b --- /dev/null +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomSt0Handler.cs @@ -0,0 +1,89 @@ +namespace X86Disassembler.X86.Handlers.FloatingPoint.Comparison; + +using X86Disassembler.X86.Operands; + +/// +/// Handler for FCOM ST(0), ST(i) instruction (D8 D0-D7) +/// +public class FcomSt0Handler : InstructionHandler +{ + /// + /// Initializes a new instance of the FcomSt0Handler class + /// + /// The instruction decoder that owns this handler + public FcomSt0Handler(InstructionDecoder decoder) + : base(decoder) + { + } + + /// + /// Checks if this handler can decode the given opcode + /// + /// The opcode to check + /// True if this handler can decode the opcode + public override bool CanHandle(byte opcode) + { + // FCOM ST(0), ST(i) is D8 D0-D7 + if (opcode != 0xD8) return false; + + if (!Decoder.CanReadByte()) + { + return false; + } + + // Check if the ModR/M byte has reg field = 2 and mod = 3 + byte modRm = Decoder.PeakByte(); + byte reg = (byte)((modRm >> 3) & 0x7); + byte mod = (byte)((modRm >> 6) & 0x3); + + // Only handle register operands (mod = 3) with reg = 2 + return reg == 2 && mod == 3; + } + + /// + /// Decodes a FCOM ST(0), ST(i) instruction + /// + /// The opcode of the instruction + /// The instruction object to populate + /// True if the instruction was successfully decoded + public override bool Decode(byte opcode, Instruction instruction) + { + if (!Decoder.CanReadByte()) + { + return false; + } + + // Read the ModR/M byte + var (mod, reg, rm, _) = ModRMDecoder.ReadModRMFpu(); + + // Set the instruction type + instruction.Type = InstructionType.Fcom; + + // Map rm field to FPU register index + FpuRegisterIndex stIndex = rm switch + { + FpuRegisterIndex.ST0 => FpuRegisterIndex.ST0, + FpuRegisterIndex.ST1 => FpuRegisterIndex.ST1, + FpuRegisterIndex.ST2 => FpuRegisterIndex.ST2, + FpuRegisterIndex.ST3 => FpuRegisterIndex.ST3, + FpuRegisterIndex.ST4 => FpuRegisterIndex.ST4, + FpuRegisterIndex.ST5 => FpuRegisterIndex.ST5, + FpuRegisterIndex.ST6 => FpuRegisterIndex.ST6, + FpuRegisterIndex.ST7 => FpuRegisterIndex.ST7, + _ => FpuRegisterIndex.ST0 // Default case, should not happen + }; + + // Create the FPU register operands + var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0); + var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex); + + // Set the structured operands + instruction.StructuredOperands = + [ + st0Operand, + stiOperand + ]; + + return true; + } +} diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompFloat64Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompFloat64Handler.cs index ea62835..aeeba44 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompFloat64Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompFloat64Handler.cs @@ -52,7 +52,7 @@ public class FcompFloat64Handler : InstructionHandler } // Read the ModR/M byte using the specialized FPU method - var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu(); + var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64(); // Set the instruction type instruction.Type = InstructionType.Fcomp; diff --git a/X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs b/X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs index 3147715..59ba2f3 100644 --- a/X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs +++ b/X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs @@ -458,15 +458,26 @@ public class InstructionHandlerFactory _handlers.Add(new FloatingPoint.Comparison.FucomiHandler(_decoder)); // FUCOMI (DB E8-EF) _handlers.Add(new FloatingPoint.Comparison.FcomiHandler(_decoder)); // FCOMI (DB F0-F7) + // D8 opcode handlers (register operations) + _handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(0), ST(i) (D8 C0-C7) + _handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(0), ST(i) (D8 C8-CF) + _handlers.Add(new FloatingPoint.Comparison.FcomSt0Handler(_decoder)); // FCOM ST(0), ST(i) (D8 D0-D7) + _handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(0), ST(i) (D8 E0-E7) + _handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(0), ST(i) (D8 E8-EF) + _handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(0), ST(i) (D8 F0-F7) + _handlers.Add(new FloatingPoint.Arithmetic.FdivrRegisterHandler(_decoder)); // FDIVR ST(0), ST(i) (D8 F8-FF) + // DC opcode handlers (register-register operations) - _handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(i), ST(0) (DC C0-C7) - _handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(i), ST(0) (DC C8-CF) + _handlers.Add(new FloatingPoint.Arithmetic.FaddFloat64Handler(_decoder)); // FADD float64 (DC /0) + _handlers.Add(new FloatingPoint.Arithmetic.FmulFloat64Handler(_decoder)); // FMUL float64 (DC /1) + _handlers.Add(new FloatingPoint.Comparison.FcomFloat64Handler(_decoder)); // FCOM float64 (DC /2) + _handlers.Add(new FloatingPoint.Comparison.FcompFloat64Handler(_decoder)); // FCOMP float64 (DC /3) + _handlers.Add(new FloatingPoint.Arithmetic.FsubFloat64Handler(_decoder)); // FSUB float64 (DC /4) + _handlers.Add(new FloatingPoint.Arithmetic.FsubrFloat64Handler(_decoder)); // FSUBR float64 (DC /5) + _handlers.Add(new FloatingPoint.Arithmetic.FdivFloat64Handler(_decoder)); // FDIV float64 (DC /6) + _handlers.Add(new FloatingPoint.Arithmetic.FdivrFloat64Handler(_decoder)); // FDIVR float64 (DC /7) _handlers.Add(new FloatingPoint.Comparison.FcomRegisterHandler(_decoder)); // FCOM ST(i), ST(0) (DC D0-D7) _handlers.Add(new FloatingPoint.Comparison.FcompRegisterHandler(_decoder)); // FCOMP ST(i), ST(0) (DC D8-DF) - _handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(i), ST(0) (DC E0-E7) - _handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(i), ST(0) (DC E8-EF) - _handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(i), ST(0) (DC F0-F7) - _handlers.Add(new FloatingPoint.Arithmetic.FdivrRegisterHandler(_decoder)); // FDIVR ST(i), ST(0) (DC F8-FF) // DD opcode handlers (register operations) _handlers.Add(new FloatingPoint.Control.FfreeHandler(_decoder)); // FFREE ST(i) (DD C0-C7) diff --git a/X86Disassembler/X86/ModRMDecoder.cs b/X86Disassembler/X86/ModRMDecoder.cs index 6c85c65..e906fd7 100644 --- a/X86Disassembler/X86/ModRMDecoder.cs +++ b/X86Disassembler/X86/ModRMDecoder.cs @@ -207,17 +207,33 @@ public class ModRMDecoder public (byte mod, RegisterIndex reg, RegisterIndex rm, Operand operand) ReadModRM64() => ReadModRMInternal(true); /// - /// Reads and decodes a ModR/M byte for FPU instructions + /// Reads and decodes a ModR/M byte for FPU instructions with 32-bit memory operands /// /// A tuple containing the mod, reg, rm fields (with rm as FpuRegisterIndex) and the decoded operand - public (byte mod, RegisterIndex reg, FpuRegisterIndex fpuRm, Operand operand) ReadModRMFpu() + public (byte mod, FpuRegisterIndex reg, FpuRegisterIndex rm, Operand operand) ReadModRMFpu() { var (mod, reg, rm, operand) = ReadModRMInternal(false); // Convert the RegisterIndex rm to FpuRegisterIndex - FpuRegisterIndex fpuRm = (FpuRegisterIndex)(int)rm; + FpuRegisterIndex regIndex = (FpuRegisterIndex)reg; + FpuRegisterIndex rmIndex = (FpuRegisterIndex)rm; - return (mod, reg, fpuRm, operand); + return (mod, regIndex, rmIndex, operand); + } + + /// + /// Reads and decodes a ModR/M byte for FPU instructions with 64-bit memory operands + /// + /// A tuple containing the mod, reg, rm fields (with rm as FpuRegisterIndex) and the decoded operand + public (byte mod, FpuRegisterIndex reg, FpuRegisterIndex rm, Operand operand) ReadModRMFpu64() + { + var (mod, reg, rm, operand) = ReadModRMInternal(true); // Use is64Bit=true for 64-bit operands + + // Convert the RegisterIndex rm to FpuRegisterIndex + FpuRegisterIndex regIndex = (FpuRegisterIndex)reg; + FpuRegisterIndex rmIndex = (FpuRegisterIndex)rm; + + return (mod, regIndex, rmIndex, operand); } /// diff --git a/X86DisassemblerTests/TestData/fadd_tests.csv b/X86DisassemblerTests/TestData/fadd_tests.csv index 823330e..a51c76d 100644 --- a/X86DisassemblerTests/TestData/fadd_tests.csv +++ b/X86DisassemblerTests/TestData/fadd_tests.csv @@ -24,22 +24,22 @@ DCC6;[{ "Type": "Fadd", "Operands": ["ST(6)", "ST(0)"] }] DCC7;[{ "Type": "Fadd", "Operands": ["ST(7)", "ST(0)"] }] # Memory operands -D8042510000000;[{ "Type": "Fadd", "Operands": ["dword ptr [0x10]"] }] -DC042510000000;[{ "Type": "Fadd", "Operands": ["qword ptr [0x10]"] }] -D80425;[{ "Type": "Fadd", "Operands": ["dword ptr [eax]"] }] -DC0425;[{ "Type": "Fadd", "Operands": ["qword ptr [eax]"] }] -D8041D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebx]"] }] -DC041D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebx]"] }] -D8042D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebp]"] }] -DC042D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebp]"] }] +D80510000000;[{ "Type": "Fadd", "Operands": ["dword ptr [0x10]"] }] +DC0510000000;[{ "Type": "Fadd", "Operands": ["qword ptr [0x10]"] }] +D800;[{ "Type": "Fadd", "Operands": ["dword ptr [eax]"] }] +DC00;[{ "Type": "Fadd", "Operands": ["qword ptr [eax]"] }] +D803;[{ "Type": "Fadd", "Operands": ["dword ptr [ebx]"] }] +DC03;[{ "Type": "Fadd", "Operands": ["qword ptr [ebx]"] }] +D84500;[{ "Type": "Fadd", "Operands": ["dword ptr [ebp+0x00]"] }] +DC4500;[{ "Type": "Fadd", "Operands": ["qword ptr [ebp+0x00]"] }] # With segment override prefixes -26D80425;[{ "Type": "Fadd", "Operands": ["dword ptr es:[eax]"] }] -2ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr cs:[eax]"] }] -36D80425;[{ "Type": "Fadd", "Operands": ["dword ptr ss:[eax]"] }] -3ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr ds:[eax]"] }] -64D80425;[{ "Type": "Fadd", "Operands": ["dword ptr fs:[eax]"] }] -65D80425;[{ "Type": "Fadd", "Operands": ["dword ptr gs:[eax]"] }] +26D800;[{ "Type": "Fadd", "Operands": ["dword ptr es:[eax]"] }] +2ED800;[{ "Type": "Fadd", "Operands": ["dword ptr cs:[eax]"] }] +36D800;[{ "Type": "Fadd", "Operands": ["dword ptr ss:[eax]"] }] +3ED800;[{ "Type": "Fadd", "Operands": ["dword ptr ds:[eax]"] }] +64D800;[{ "Type": "Fadd", "Operands": ["dword ptr fs:[eax]"] }] +65D800;[{ "Type": "Fadd", "Operands": ["dword ptr gs:[eax]"] }] # FADDP - Add floating point values and pop DEC0;[{ "Type": "Faddp", "Operands": ["ST(0)", "ST(0)"] }] @@ -54,7 +54,9 @@ DEC7;[{ "Type": "Faddp", "Operands": ["ST(7)", "ST(0)"] }] # FIADD - Add integer to floating point DA042510000000;[{ "Type": "Fiadd", "Operands": ["dword ptr [0x10]"] }] DE042510000000;[{ "Type": "Fiadd", "Operands": ["word ptr [0x10]"] }] -DA0425;[{ "Type": "Fiadd", "Operands": ["dword ptr [eax]"] }] -DE0425;[{ "Type": "Fiadd", "Operands": ["word ptr [eax]"] }] -DA041D;[{ "Type": "Fiadd", "Operands": ["dword ptr [ebx]"] }] -DE041D;[{ "Type": "Fiadd", "Operands": ["word ptr [ebx]"] }] + +# Corrected FIADD tests +DA00;[{ "Type": "Fiadd", "Operands": ["dword ptr [eax]"] }] +DE00;[{ "Type": "Fiadd", "Operands": ["word ptr [eax]"] }] +DA03;[{ "Type": "Fiadd", "Operands": ["dword ptr [ebx]"] }] +DE03;[{ "Type": "Fiadd", "Operands": ["word ptr [ebx]"] }]