diff --git a/X86DisassemblerTests/TestData/div_tests.csv b/X86DisassemblerTests/TestData/div_tests.csv
index b37bbcb..7b9d056 100644
--- a/X86DisassemblerTests/TestData/div_tests.csv
+++ b/X86DisassemblerTests/TestData/div_tests.csv
@@ -7,6 +7,10 @@ F6F0;[{ "Type": "Div", "Operands": ["al"] }]
 F6F3;[{ "Type": "Div", "Operands": ["bl"] }]
 F6F1;[{ "Type": "Div", "Operands": ["cl"] }]
 F6F2;[{ "Type": "Div", "Operands": ["dl"] }]
+F6F4;[{ "Type": "Div", "Operands": ["ah"] }]
+F6F5;[{ "Type": "Div", "Operands": ["ch"] }]
+F6F6;[{ "Type": "Div", "Operands": ["dh"] }]
+F6F7;[{ "Type": "Div", "Operands": ["bh"] }]
 
 # DIV r/m32 (opcode F7 /6)
 F7F0;[{ "Type": "Div", "Operands": ["eax"] }]
@@ -19,6 +23,29 @@ F7F6;[{ "Type": "Div", "Operands": ["esi"] }]
 F7F7;[{ "Type": "Div", "Operands": ["edi"] }]
 
 # DIV with memory operands
+# Basic memory addressing
 F63425;[{ "Type": "Div", "Operands": ["byte ptr [eax]"] }]
+F63C25;[{ "Type": "Div", "Operands": ["byte ptr [ebp]"] }]
+F63825;[{ "Type": "Div", "Operands": ["byte ptr [eax]"] }]
 F73425;[{ "Type": "Div", "Operands": ["dword ptr [eax]"] }]
-F7342510000000;[{ "Type": "Div", "Operands": ["dword ptr [eax+0x10]"] }]
+F73C25;[{ "Type": "Div", "Operands": ["dword ptr [ebp]"] }]
+F73825;[{ "Type": "Div", "Operands": ["dword ptr [eax]"] }]
+
+# With displacement
+F7742510000000;[{ "Type": "Div", "Operands": ["dword ptr [eax+0x10]"] }]
+F7742520000000;[{ "Type": "Div", "Operands": ["dword ptr [eax+0x20]"] }]
+F7742530000000;[{ "Type": "Div", "Operands": ["dword ptr [eax+0x30]"] }]
+
+# With SIB addressing
+F7341C;[{ "Type": "Div", "Operands": ["dword ptr [esp+ebx*1]"] }]
+F7345C;[{ "Type": "Div", "Operands": ["dword ptr [esp+ebx*2]"] }]
+F7349C;[{ "Type": "Div", "Operands": ["dword ptr [esp+ebx*4]"] }]
+F734DC;[{ "Type": "Div", "Operands": ["dword ptr [esp+ebx*8]"] }]
+
+# With segment override prefixes
+26F73425;[{ "Type": "Div", "Operands": ["dword ptr es:[eax]"] }]
+2EF73425;[{ "Type": "Div", "Operands": ["dword ptr cs:[eax]"] }]
+36F73425;[{ "Type": "Div", "Operands": ["dword ptr ss:[eax]"] }]
+3EF73425;[{ "Type": "Div", "Operands": ["dword ptr ds:[eax]"] }]
+64F73425;[{ "Type": "Div", "Operands": ["dword ptr fs:[eax]"] }]
+65F73425;[{ "Type": "Div", "Operands": ["dword ptr gs:[eax]"] }]
diff --git a/X86DisassemblerTests/TestData/flag_tests.csv b/X86DisassemblerTests/TestData/flag_tests.csv
index 1893c22..15c26e3 100644
--- a/X86DisassemblerTests/TestData/flag_tests.csv
+++ b/X86DisassemblerTests/TestData/flag_tests.csv
@@ -28,3 +28,37 @@ FA;[{ "Type": "Cli", "Operands": [] }]
 
 # LAHF - Load Flags into AH
 9F;[{ "Type": "Lahf", "Operands": [] }]
+
+# Flag instructions with prefixes (should be ignored by disassembler)
+# Operand size override prefix
+66F9;[{ "Type": "Stc", "Operands": [] }]
+66F8;[{ "Type": "Clc", "Operands": [] }]
+66F5;[{ "Type": "Cmc", "Operands": [] }]
+66FD;[{ "Type": "Std", "Operands": [] }]
+66FC;[{ "Type": "Cld", "Operands": [] }]
+66FB;[{ "Type": "Sti", "Operands": [] }]
+66FA;[{ "Type": "Cli", "Operands": [] }]
+669E;[{ "Type": "Sahf", "Operands": [] }]
+669F;[{ "Type": "Lahf", "Operands": [] }]
+
+# Address size override prefix
+67F9;[{ "Type": "Stc", "Operands": [] }]
+67F8;[{ "Type": "Clc", "Operands": [] }]
+67F5;[{ "Type": "Cmc", "Operands": [] }]
+67FD;[{ "Type": "Std", "Operands": [] }]
+67FC;[{ "Type": "Cld", "Operands": [] }]
+67FB;[{ "Type": "Sti", "Operands": [] }]
+67FA;[{ "Type": "Cli", "Operands": [] }]
+679E;[{ "Type": "Sahf", "Operands": [] }]
+679F;[{ "Type": "Lahf", "Operands": [] }]
+
+# LOCK prefix (invalid but should be parsed)
+F0F9;[{ "Type": "Stc", "Operands": [] }]
+F0F8;[{ "Type": "Clc", "Operands": [] }]
+F0F5;[{ "Type": "Cmc", "Operands": [] }]
+F0FD;[{ "Type": "Std", "Operands": [] }]
+F0FC;[{ "Type": "Cld", "Operands": [] }]
+F0FB;[{ "Type": "Sti", "Operands": [] }]
+F0FA;[{ "Type": "Cli", "Operands": [] }]
+F09E;[{ "Type": "Sahf", "Operands": [] }]
+F09F;[{ "Type": "Lahf", "Operands": [] }]
diff --git a/X86DisassemblerTests/TestData/fnstsw_tests.csv b/X86DisassemblerTests/TestData/fnstsw_tests.csv
index 70236e6..979e6fb 100644
--- a/X86DisassemblerTests/TestData/fnstsw_tests.csv
+++ b/X86DisassemblerTests/TestData/fnstsw_tests.csv
@@ -10,6 +10,50 @@ DFE0;[{ "Type": "Fnstsw", "Operands": ["ax"] }]
 
 # FSTSW m2byte - Store FPU status word to memory
 9BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr [eax]"] }]
+9BDD3C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
+9BDD3C2C;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
+9BDD3C23;[{ "Type": "Fstsw", "Operands": ["word ptr [ebx]"] }]
+9BDD3C21;[{ "Type": "Fstsw", "Operands": ["word ptr [ecx]"] }]
+9BDD3C22;[{ "Type": "Fstsw", "Operands": ["word ptr [edx]"] }]
+9BDD3C26;[{ "Type": "Fstsw", "Operands": ["word ptr [esi]"] }]
+9BDD3C27;[{ "Type": "Fstsw", "Operands": ["word ptr [edi]"] }]
 
 # FNSTSW m2byte - Store FPU status word to memory without checking for pending unmasked exceptions
 DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr [eax]"] }]
+DD3C24;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp]"] }]
+DD3C2C;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp]"] }]
+DD3C23;[{ "Type": "Fnstsw", "Operands": ["word ptr [ebx]"] }]
+DD3C21;[{ "Type": "Fnstsw", "Operands": ["word ptr [ecx]"] }]
+DD3C22;[{ "Type": "Fnstsw", "Operands": ["word ptr [edx]"] }]
+DD3C26;[{ "Type": "Fnstsw", "Operands": ["word ptr [esi]"] }]
+DD3C27;[{ "Type": "Fnstsw", "Operands": ["word ptr [edi]"] }]
+
+# FSTSW/FNSTSW with displacement
+9BDD7C2510000000;[{ "Type": "Fstsw", "Operands": ["word ptr [eax+0x10]"] }]
+9BDD7C2520000000;[{ "Type": "Fstsw", "Operands": ["word ptr [eax+0x20]"] }]
+DD7C2510000000;[{ "Type": "Fnstsw", "Operands": ["word ptr [eax+0x10]"] }]
+DD7C2520000000;[{ "Type": "Fnstsw", "Operands": ["word ptr [eax+0x20]"] }]
+
+# FSTSW/FNSTSW with SIB addressing
+9BDD3C04;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+eax*1]"] }]
+9BDD3C4C;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+ecx*2]"] }]
+9BDD3C94;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+edx*4]"] }]
+9BDD3CDC;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+ebx*8]"] }]
+DD3C04;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+eax*1]"] }]
+DD3C4C;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+ecx*2]"] }]
+DD3C94;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+edx*4]"] }]
+DD3CDC;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+ebx*8]"] }]
+
+# FSTSW/FNSTSW with segment override prefixes
+269BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr es:[eax]"] }]
+2E9BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr cs:[eax]"] }]
+369BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr ss:[eax]"] }]
+3E9BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr ds:[eax]"] }]
+649BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr fs:[eax]"] }]
+659BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr gs:[eax]"] }]
+26DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr es:[eax]"] }]
+2EDD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr cs:[eax]"] }]
+36DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr ss:[eax]"] }]
+3EDD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr ds:[eax]"] }]
+64DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr fs:[eax]"] }]
+65DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr gs:[eax]"] }]