implement shift and rotate handlers. Fix tests

X86DisassemblerTests/TestData/misc_tests.csv

@@ -34,19 +34,6 @@ F4;[{ "Type": "Hlt", "Operands": [] }]
 
 # LOCK prefix
 F0;[{ "Type": "Lock", "Operands": [] }]
-# SPECIAL CASE: When Mod=00 and R/M=101 (EBP), this doesn't actually refer to [EBP].
-# Instead, it's a special case that indicates a 32-bit displacement-only addressing mode.
-# The correct encoding for instructions with [ebp] would use Mod=01 and a zero displacement.
-# F0FE05;[{ "Type": "Inc", "Operands": ["byte ptr [ebp]"], "Prefix": "Lock" }]
-# F0FF05;[{ "Type": "Inc", "Operands": ["dword ptr [ebp]"], "Prefix": "Lock" }]
-# F0FE0D;[{ "Type": "Dec", "Operands": ["byte ptr [ebp]"], "Prefix": "Lock" }]
-# F0FF0D;[{ "Type": "Dec", "Operands": ["dword ptr [ebp]"], "Prefix": "Lock" }]
-
-# Adding the correct test cases:
-F0FE4500;[{ "Type": "Inc", "Operands": ["byte ptr [ebp+0x0]"], "Prefix": "Lock" }]
-F0FF4500;[{ "Type": "Inc", "Operands": ["dword ptr [ebp+0x0]"], "Prefix": "Lock" }]
-F0FE4D00;[{ "Type": "Dec", "Operands": ["byte ptr [ebp+0x0]"], "Prefix": "Lock" }]
-F0FF4D00;[{ "Type": "Dec", "Operands": ["dword ptr [ebp+0x0]"], "Prefix": "Lock" }]
 
 # IN - Input from Port
 E410;[{ "Type": "In", "Operands": ["al", "0x10"] }]

X86DisassemblerTests/TestData/rcl_tests.csv

@@ -26,7 +26,7 @@ C0D305;[{ "Type": "Rcl", "Operands": ["bl", "0x05"] }]
 C1D005;[{ "Type": "Rcl", "Operands": ["eax", "0x05"] }]
 C1D305;[{ "Type": "Rcl", "Operands": ["ebx", "0x05"] }]
 
-# RCL with memory operands
-D0142510;[{ "Type": "Rcl", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
-D31425;[{ "Type": "Rcl", "Operands": ["dword ptr [eax]", "cl"] }]
-C1142505;[{ "Type": "Rcl", "Operands": ["dword ptr [eax]", "0x05"] }]
+# RCL with memory operands (properly encoded)
+D05010;[{ "Type": "Rcl", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
+D310;[{ "Type": "Rcl", "Operands": ["dword ptr [eax]", "cl"] }]
+C11005;[{ "Type": "Rcl", "Operands": ["dword ptr [eax]", "0x05"] }]

X86DisassemblerTests/TestData/rcr_tests.csv

@@ -27,6 +27,6 @@ C1D805;[{ "Type": "Rcr", "Operands": ["eax", "0x05"] }]
 C1DB05;[{ "Type": "Rcr", "Operands": ["ebx", "0x05"] }]
 
 # RCR with memory operands
-D01C2510;[{ "Type": "Rcr", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
-D31C25;[{ "Type": "Rcr", "Operands": ["dword ptr [eax]", "cl"] }]
-C11C2505;[{ "Type": "Rcr", "Operands": ["dword ptr [eax]", "0x05"] }]
+D05810;[{ "Type": "Rcr", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
+D318;[{ "Type": "Rcr", "Operands": ["dword ptr [eax]", "cl"] }]
+C11805;[{ "Type": "Rcr", "Operands": ["dword ptr [eax]", "0x05"] }]

X86DisassemblerTests/TestData/rol_tests.csv

@@ -26,7 +26,7 @@ C0C305;[{ "Type": "Rol", "Operands": ["bl", "0x05"] }]
 C1C005;[{ "Type": "Rol", "Operands": ["eax", "0x05"] }]
 C1C305;[{ "Type": "Rol", "Operands": ["ebx", "0x05"] }]
 
-# ROL with memory operands
-D0042510;[{ "Type": "Rol", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
-D3042510;[{ "Type": "Rol", "Operands": ["dword ptr [eax+0x10]", "cl"] }]
-C1042505;[{ "Type": "Rol", "Operands": ["dword ptr [eax+0x10]", "0x05"] }]
+# ROL with memory operands (fixed)
+D04010;[{ "Type": "Rol", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
+D34010;[{ "Type": "Rol", "Operands": ["dword ptr [eax+0x10]", "cl"] }]
+C1401005;[{ "Type": "Rol", "Operands": ["dword ptr [eax+0x10]", "0x05"] }]

X86DisassemblerTests/TestData/ror_tests.csv

@@ -26,7 +26,7 @@ C0CB05;[{ "Type": "Ror", "Operands": ["bl", "0x05"] }]
 C1C805;[{ "Type": "Ror", "Operands": ["eax", "0x05"] }]
 C1CB05;[{ "Type": "Ror", "Operands": ["ebx", "0x05"] }]
 
-# ROR with memory operands
-D00C2510;[{ "Type": "Ror", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
-D30C2510;[{ "Type": "Ror", "Operands": ["dword ptr [eax+0x10]", "cl"] }]
-C10C2505;[{ "Type": "Ror", "Operands": ["dword ptr [eax+0x10]", "0x05"] }]
+# ROR with memory operands (fixed)
+D04810;[{ "Type": "Ror", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
+D34810;[{ "Type": "Ror", "Operands": ["dword ptr [eax+0x10]", "cl"] }]
+C1481005;[{ "Type": "Ror", "Operands": ["dword ptr [eax+0x10]", "0x05"] }]

X86DisassemblerTests/TestData/sar_tests.csv

@@ -26,7 +26,7 @@ C0FB05;[{ "Type": "Sar", "Operands": ["bl", "0x05"] }]
 C1F805;[{ "Type": "Sar", "Operands": ["eax", "0x05"] }]
 C1FB05;[{ "Type": "Sar", "Operands": ["ebx", "0x05"] }]
 
-# SAR with memory operands
-D03C2510;[{ "Type": "Sar", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
-D33C25;[{ "Type": "Sar", "Operands": ["dword ptr [eax]", "cl"] }]
-C13C2505;[{ "Type": "Sar", "Operands": ["dword ptr [eax]", "0x05"] }]
+# SAR with memory operands (fixed)
+D07810;[{ "Type": "Sar", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
+D338;[{ "Type": "Sar", "Operands": ["dword ptr [eax]", "cl"] }]
+C13805;[{ "Type": "Sar", "Operands": ["dword ptr [eax]", "0x05"] }]

X86DisassemblerTests/TestData/shl_tests.csv

@@ -28,5 +28,5 @@ C1E305;[{ "Type": "Shl", "Operands": ["ebx", "0x05"] }]
 
 # SHL with memory operands
 D0242510000000;[{ "Type": "Shl", "Operands": ["byte ptr [0x10]", "0x01"] }]
-D32425;[{ "Type": "Shl", "Operands": ["dword ptr [eax]", "cl"] }]
-C1242510000005;[{ "Type": "Shl", "Operands": ["dword ptr [0x10]", "0x05"] }]
+D320;[{ "Type": "Shl", "Operands": ["dword ptr [eax]", "cl"] }]
+C1251000000005;[{ "Type": "Shl", "Operands": ["dword ptr [0x10]", "0x05"] }]

X86DisassemblerTests/TestData/shr_tests.csv

@@ -26,7 +26,7 @@ C0EB05;[{ "Type": "Shr", "Operands": ["bl", "0x05"] }]
 C1E805;[{ "Type": "Shr", "Operands": ["eax", "0x05"] }]
 C1EB05;[{ "Type": "Shr", "Operands": ["ebx", "0x05"] }]
 
-# SHR with memory operands
-D02C2510;[{ "Type": "Shr", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
-D32C25;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "cl"] }]
-C12C2505;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "0x05"] }]
+# SHR with memory operands (fixed)
+D06810;[{ "Type": "Shr", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
+D328;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "cl"] }]
+C12805;[{ "Type": "Shr", "Operands": ["dword ptr [eax]", "0x05"] }]