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Simplified LoadStoreControlHandler by replacing complex switch statements with a dictionary-based approach
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bird_egop
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0ff20494e1
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@ -5,19 +5,73 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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/// </summary>
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public class LoadStoreControlHandler : InstructionHandler
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public class LoadStoreControlHandler : InstructionHandler
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{
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{
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// D9 opcode - load, store, and control operations
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// Memory operand mnemonics for D9 opcode - load, store, and control operations
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private static readonly string[] Mnemonics =
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private static readonly string[] MemoryMnemonics =
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[
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[
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"fld",
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"fld", // 0
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"??",
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"??", // 1
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"fst",
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"fst", // 2
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"fstp",
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"fstp", // 3
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"fldenv",
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"fldenv", // 4
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"fldcw",
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"fldcw", // 5
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"fnstenv",
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"fnstenv", // 6
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"fnstcw"
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"fnstcw" // 7
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];
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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{
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// FLD ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("fld", "st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("fld", "st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("fld", "st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("fld", "st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("fld", "st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("fld", "st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("fld", "st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("fld", "st(7)") },
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// FXCH ST(i)
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{ (RegisterIndex.B, RegisterIndex.A), ("fxch", "st(0)") },
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{ (RegisterIndex.B, RegisterIndex.C), ("fxch", "st(1)") },
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{ (RegisterIndex.B, RegisterIndex.D), ("fxch", "st(2)") },
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{ (RegisterIndex.B, RegisterIndex.B), ("fxch", "st(3)") },
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{ (RegisterIndex.B, RegisterIndex.Sp), ("fxch", "st(4)") },
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{ (RegisterIndex.B, RegisterIndex.Bp), ("fxch", "st(5)") },
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{ (RegisterIndex.B, RegisterIndex.Si), ("fxch", "st(6)") },
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{ (RegisterIndex.B, RegisterIndex.Di), ("fxch", "st(7)") },
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// D9E0-D9EF special instructions (reg=6)
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{ (RegisterIndex.Si, RegisterIndex.A), ("fchs", "") },
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{ (RegisterIndex.Si, RegisterIndex.B), ("fabs", "") },
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{ (RegisterIndex.Si, RegisterIndex.Si), ("ftst", "") },
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{ (RegisterIndex.Si, RegisterIndex.Di), ("fxam", "") },
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// D9F0-D9FF special instructions (reg=7)
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{ (RegisterIndex.Di, RegisterIndex.A), ("f2xm1", "") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fyl2x", "") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fptan", "") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fpatan", "") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fxtract", "") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fprem1", "") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fdecstp", "") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fincstp", "") },
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// D9D0-D9DF special instructions (reg=5)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fprem", "") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fyl2xp1", "") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fsqrt", "") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fsincos", "") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("frndint", "") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fscale", "") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fsin", "") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcos", "") },
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// D9C8-D9CF special instructions (reg=4)
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{ (RegisterIndex.Bp, RegisterIndex.A), ("fnop", "") },
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{ (RegisterIndex.Bp, RegisterIndex.C), ("fwait", "") }
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};
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/// <summary>
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/// <summary>
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/// Initializes a new instance of the LoadStoreControlHandler class
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/// Initializes a new instance of the LoadStoreControlHandler class
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/// </summary>
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/// </summary>
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@ -47,165 +101,52 @@ public class LoadStoreControlHandler : InstructionHandler
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/// <returns>True if the instruction was successfully decoded</returns>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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public override bool Decode(byte opcode, Instruction instruction)
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{
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{
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int position = Decoder.GetPosition();
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if (!Decoder.CanReadByte())
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if (position >= Length)
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{
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{
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return false;
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return false;
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}
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}
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// Read the ModR/M byte
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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// Set the mnemonic based on the opcode and reg field
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// Handle based on addressing mode
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instruction.Mnemonic = Mnemonics[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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if (mod != 3) // Memory operand
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{
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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// Different operand types based on the instruction
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// Different operand types based on the instruction
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
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{
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{
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// Keep the dword ptr prefix from ModRMDecoder
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// Keep the dword ptr prefix from ModRMDecoder
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instruction.Operands = destOperand;
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instruction.Operands = memOperand;
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}
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}
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else // fldenv, fldcw, fnstenv, fnstcw
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else // fldenv, fldcw, fnstenv, fnstcw
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{
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{
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if (reg == RegisterIndex.Di) // fldcw - should use word ptr
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if (reg == RegisterIndex.Di) // fldcw - should use word ptr
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{
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{
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instruction.Operands = destOperand.Replace("dword ptr", "word ptr");
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instruction.Operands = memOperand.Replace("dword ptr", "word ptr");
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}
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}
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else // fldenv, fnstenv, fnstcw
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else // fldenv, fnstenv, fnstcw
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{
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{
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// Remove the dword ptr prefix for other control operations
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// Remove the dword ptr prefix for other control operations
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instruction.Operands = destOperand.Replace("dword ptr ", "");
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instruction.Operands = memOperand.Replace("dword ptr ", "");
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}
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}
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}
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}
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}
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}
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else // Register operand (ST(i))
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else // Register operand (ST(i))
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{
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{
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// Special handling for D9C0-D9FF (register-register operations)
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// Look up the register operation in our dictionary
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if (reg == RegisterIndex.A) // FLD ST(i)
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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{
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instruction.Operands = $"st({(int)rm})";
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = operation.Operands;
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}
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}
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else if (reg == RegisterIndex.B) // FXCH ST(i)
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else
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{
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{
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instruction.Mnemonic = "fxch";
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// Unknown instruction
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instruction.Operands = $"st({(int)rm})";
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instruction.Mnemonic = "??";
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}
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instruction.Operands = "";
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else if (reg == RegisterIndex.Si)
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{
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// D9E0-D9EF special instructions
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switch (rm)
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{
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case RegisterIndex.A:
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instruction.Mnemonic = "fchs";
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instruction.Operands = "";
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break;
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case RegisterIndex.B:
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instruction.Mnemonic = "fabs";
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instruction.Operands = "";
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break;
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case RegisterIndex.Si:
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instruction.Mnemonic = "ftst";
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instruction.Operands = "";
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break;
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case RegisterIndex.Di:
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instruction.Mnemonic = "fxam";
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instruction.Operands = "";
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break;
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default:
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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break;
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}
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}
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else if (reg == RegisterIndex.Di)
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{
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// D9F0-D9FF special instructions
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switch (rm)
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{
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case RegisterIndex.A:
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instruction.Mnemonic = "f2xm1";
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instruction.Operands = "";
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break;
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case RegisterIndex.B:
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instruction.Mnemonic = "fyl2x";
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instruction.Operands = "";
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break;
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case RegisterIndex.C:
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instruction.Mnemonic = "fptan";
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instruction.Operands = "";
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break;
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case RegisterIndex.D:
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instruction.Mnemonic = "fpatan";
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instruction.Operands = "";
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break;
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case RegisterIndex.Si:
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instruction.Mnemonic = "fxtract";
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instruction.Operands = "";
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break;
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case RegisterIndex.Di:
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instruction.Mnemonic = "fprem1";
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instruction.Operands = "";
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break;
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case RegisterIndex.Sp:
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instruction.Mnemonic = "fdecstp";
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instruction.Operands = "";
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break;
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case RegisterIndex.Bp:
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instruction.Mnemonic = "fincstp";
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instruction.Operands = "";
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break;
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default:
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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break;
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}
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}
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else if (reg == RegisterIndex.Sp)
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{
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// D9F0-D9FF more special instructions
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switch (rm)
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{
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case RegisterIndex.A:
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instruction.Mnemonic = "fprem";
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instruction.Operands = "";
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break;
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case RegisterIndex.B:
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instruction.Mnemonic = "fyl2xp1";
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instruction.Operands = "";
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break;
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case RegisterIndex.C:
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instruction.Mnemonic = "fsqrt";
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instruction.Operands = "";
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break;
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case RegisterIndex.D:
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instruction.Mnemonic = "fsincos";
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instruction.Operands = "";
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break;
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case RegisterIndex.Si:
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instruction.Mnemonic = "frndint";
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instruction.Operands = "";
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break;
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case RegisterIndex.Di:
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instruction.Mnemonic = "fscale";
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instruction.Operands = "";
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break;
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case RegisterIndex.Sp:
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instruction.Mnemonic = "fsin";
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instruction.Operands = "";
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break;
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case RegisterIndex.Bp:
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instruction.Mnemonic = "fcos";
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instruction.Operands = "";
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break;
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default:
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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break;
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}
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}
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}
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}
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}
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