mirrors/ParkanPlayground
0
Fork 0
mirror of https://github.com/sampletext32/ParkanPlayground.git synced 2025-06-19 16:08:02 +03:00
Code Issues Releases Activity

fixes

Browse Source
This commit is contained in:
bird_egop
2025-04-17 22:54:19 +03:00
parent 4d2db05a07
commit df453b930f
14 changed files with 340 additions and 192 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
X86DisassemblerTests/InstructionTests/Int3InstructionTests.cs
View File

@ -24,7 +24,7 @@ public class Int3InstructionTests
// Assert
Assert.NotNull(instruction);
Assert.Equal(InstructionType.Int, instruction.Type);
Assert.Equal(InstructionType.Int3, instruction.Type);
// Check that we have no operands
Assert.Empty(instruction.StructuredOperands);

12
X86DisassemblerTests/InstructionTests/StringInstructionHandlerTests.cs
View File

@ -154,9 +154,9 @@ public class StringInstructionHandlerTests
// Check the second operand (AL)
var alOperand = instruction.StructuredOperands[1];
Assert.IsType<RegisterOperand>(alOperand);
var registerOperand = (RegisterOperand)alOperand;
Assert.Equal(RegisterIndex.A, registerOperand.Register);
Assert.IsType<Register8Operand>(alOperand);
var registerOperand = (Register8Operand)alOperand;
Assert.Equal(RegisterIndex8.AL, registerOperand.Register);
Assert.Equal(8, registerOperand.Size); // Validate that it's an 8-bit register (AL)
}
@ -223,9 +223,9 @@ public class StringInstructionHandlerTests
// Check the first operand (AL)
var alOperand = instruction.StructuredOperands[0];
Assert.IsType<RegisterOperand>(alOperand);
var registerOperand = (RegisterOperand)alOperand;
Assert.Equal(RegisterIndex.A, registerOperand.Register);
Assert.IsType<Register8Operand>(alOperand);
var registerOperand = (Register8Operand)alOperand;
Assert.Equal(RegisterIndex8.AL, registerOperand.Register);
Assert.Equal(8, registerOperand.Size); // Validate that it's an 8-bit register (AL)
// Check the second operand (memory operand)

8
X86DisassemblerTests/TestData/ret_tests.csv
View File

@ -16,8 +16,8 @@ C2FFFF;[{ "Type": "Ret", "Operands": ["0xFFFF"] }]
CB;[{ "Type": "Retf", "Operands": [] }]
# RETF imm16 (opcode CA) - Far return to calling procedure and pop imm16 bytes from stack
CA0000;[{ "Type": "Retf", "Operands": ["0x0000"] }]
CA0400;[{ "Type": "Retf", "Operands": ["0x0004"] }]
CA0800;[{ "Type": "Retf", "Operands": ["0x0008"] }]
CA1000;[{ "Type": "Retf", "Operands": ["0x0010"] }]
CA0000;[{ "Type": "Retf", "Operands": ["0x00"] }]
CA0400;[{ "Type": "Retf", "Operands": ["0x04"] }]
CA0800;[{ "Type": "Retf", "Operands": ["0x08"] }]
CA1000;[{ "Type": "Retf", "Operands": ["0x10"] }]
CAFFFF;[{ "Type": "Retf", "Operands": ["0xFFFF"] }]

Can't render this file because it contains an unexpected character in line 6 and column 7.

2
X86DisassemblerTests/TestData/sbb_tests.csv
View File

@ -12,7 +12,7 @@ RawBytes;Instructions
83D842;[{ "Type": "Sbb", "Operands": ["eax", "0x42"] }]
# SBB with memory operands
811C2578563412;[{ "Type": "Sbb", "Operands": ["dword ptr [eax]", "0x12345678"] }]
811878563412;[{ "Type": "Sbb", "Operands": ["dword ptr [eax]", "0x12345678"] }]
# SBB r/m32, r32 (opcode 19)
19D8;[{ "Type": "Sbb", "Operands": ["eax", "ebx"] }]

Can't render this file because it contains an unexpected character in line 6 and column 11.

6
X86DisassemblerTests/TestData/string_tests.csv
View File

@ -18,9 +18,9 @@ AF;[{ "Type": "ScasD", "Operands": ["eax", "dword ptr es:[edi]"] }]
66AF;[{ "Type": "ScasW", "Operands": ["ax", "word ptr es:[edi]"] }]
# LODS - Load string
AC;[{ "Type": "LodsB", "Operands": ["al", "byte ptr es:[esi]"] }]
AD;[{ "Type": "LodsD", "Operands": ["eax", "dword ptr es:[esi]"] }]
66AD;[{ "Type": "LodsW", "Operands": ["ax", "byte ptr es:[esi]"] }]
AC;[{ "Type": "LodsB", "Operands": ["al", "byte ptr ds:[esi]"] }]
AD;[{ "Type": "LodsD", "Operands": ["eax", "dword ptr ds:[esi]"] }]
66AD;[{ "Type": "LodsW", "Operands": ["ax", "byte ptr ds:[esi]"] }]
# STOS - Store string
AA;[{ "Type": "StosB", "Operands": ["byte ptr es:[edi]", "al"] }]

Can't render this file because it contains an unexpected character in line 6 and column 7.