diff --git a/X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt16Handler.cs b/X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt16Handler.cs index 20785c3..16ccf74 100644 --- a/X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt16Handler.cs +++ b/X86Disassembler/X86/Handlers/FloatingPoint/LoadStoreInt16Handler.cs @@ -5,18 +5,57 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint; /// public class LoadStoreInt16Handler : InstructionHandler { - // DF opcode - load/store int16, misc - private static readonly string[] Mnemonics = + // Memory operand mnemonics for DF opcode - load/store int16, misc + private static readonly string[] MemoryMnemonics = [ - "fild", - "??", - "fist", - "fistp", - "fbld", - "fild", - "fbstp", - "fistp" + "fild", // 0 - 16-bit integer + "??", // 1 + "fist", // 2 - 16-bit integer + "fistp", // 3 - 16-bit integer + "fbld", // 4 - 80-bit packed BCD + "fild", // 5 - 64-bit integer + "fbstp", // 6 - 80-bit packed BCD + "fistp" // 7 - 64-bit integer ]; + + // Register-register operations mapping (mod=3) + private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new() + { + // FFREEP ST(i) + { (RegisterIndex.A, RegisterIndex.A), ("ffreep", "st(0)") }, + { (RegisterIndex.A, RegisterIndex.C), ("ffreep", "st(1)") }, + { (RegisterIndex.A, RegisterIndex.D), ("ffreep", "st(2)") }, + { (RegisterIndex.A, RegisterIndex.B), ("ffreep", "st(3)") }, + { (RegisterIndex.A, RegisterIndex.Sp), ("ffreep", "st(4)") }, + { (RegisterIndex.A, RegisterIndex.Bp), ("ffreep", "st(5)") }, + { (RegisterIndex.A, RegisterIndex.Si), ("ffreep", "st(6)") }, + { (RegisterIndex.A, RegisterIndex.Di), ("ffreep", "st(7)") }, + + // Special cases + { (RegisterIndex.B, RegisterIndex.A), ("fxch", "") }, + { (RegisterIndex.C, RegisterIndex.A), ("fstp", "st(1)") }, + { (RegisterIndex.D, RegisterIndex.A), ("fstp", "st(1)") }, + + // FUCOMIP ST(0), ST(i) + { (RegisterIndex.Di, RegisterIndex.A), ("fucomip", "st(0), st(0)") }, + { (RegisterIndex.Di, RegisterIndex.C), ("fucomip", "st(0), st(1)") }, + { (RegisterIndex.Di, RegisterIndex.D), ("fucomip", "st(0), st(2)") }, + { (RegisterIndex.Di, RegisterIndex.B), ("fucomip", "st(0), st(3)") }, + { (RegisterIndex.Di, RegisterIndex.Sp), ("fucomip", "st(0), st(4)") }, + { (RegisterIndex.Di, RegisterIndex.Bp), ("fucomip", "st(0), st(5)") }, + { (RegisterIndex.Di, RegisterIndex.Si), ("fucomip", "st(0), st(6)") }, + { (RegisterIndex.Di, RegisterIndex.Di), ("fucomip", "st(0), st(7)") }, + + // FCOMIP ST(0), ST(i) + { (RegisterIndex.Sp, RegisterIndex.A), ("fcomip", "st(0), st(0)") }, + { (RegisterIndex.Sp, RegisterIndex.C), ("fcomip", "st(0), st(1)") }, + { (RegisterIndex.Sp, RegisterIndex.D), ("fcomip", "st(0), st(2)") }, + { (RegisterIndex.Sp, RegisterIndex.B), ("fcomip", "st(0), st(3)") }, + { (RegisterIndex.Sp, RegisterIndex.Sp), ("fcomip", "st(0), st(4)") }, + { (RegisterIndex.Sp, RegisterIndex.Bp), ("fcomip", "st(0), st(5)") }, + { (RegisterIndex.Sp, RegisterIndex.Si), ("fcomip", "st(0), st(6)") }, + { (RegisterIndex.Sp, RegisterIndex.Di), ("fcomip", "st(0), st(7)") } + }; /// /// Initializes a new instance of the LoadStoreInt16Handler class @@ -47,15 +86,13 @@ public class LoadStoreInt16Handler : InstructionHandler /// True if the instruction was successfully decoded public override bool Decode(byte opcode, Instruction instruction) { - int position = Decoder.GetPosition(); - - if (position >= Length) + if (!Decoder.CanReadByte()) { return false; } // Read the ModR/M byte - var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM(); + var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM(); // Check for FNSTSW AX (DF E0) if (mod == 3 && reg == RegisterIndex.Bp && rm == RegisterIndex.A) @@ -64,78 +101,40 @@ public class LoadStoreInt16Handler : InstructionHandler return false; } - // Set the mnemonic based on the opcode and reg field - instruction.Mnemonic = Mnemonics[(int)reg]; - - // For memory operands, set the operand + // Handle based on addressing mode if (mod != 3) // Memory operand { - string operand = ModRMDecoder.DecodeModRM(mod, rm, false); + // Set the mnemonic based on the reg field + instruction.Mnemonic = MemoryMnemonics[(int)reg]; - if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D || reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fild, fist, fistp, fild, fistp + // Get the base operand without size prefix + string baseOperand = memOperand.Replace("dword ptr ", ""); + + // Apply the appropriate size prefix based on the operation + if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // 16-bit integer operations { - if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 64-bit integer - { - // Replace dword ptr with qword ptr for 64-bit integers - operand = operand.Replace("dword ptr", "qword ptr"); - instruction.Operands = operand; - } - else // 16-bit integer - { - // Replace dword ptr with word ptr for 16-bit integers - operand = operand.Replace("dword ptr", "word ptr"); - instruction.Operands = operand; - } + instruction.Operands = $"word ptr {baseOperand}"; } - else if (reg == RegisterIndex.Si || reg == RegisterIndex.Sp) // fbld, fbstp + else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 64-bit integer operations { - // Replace dword ptr with tbyte ptr for 80-bit packed BCD - operand = operand.Replace("dword ptr", "tbyte ptr"); - instruction.Operands = operand; + instruction.Operands = $"qword ptr {baseOperand}"; } - else + else if (reg == RegisterIndex.Si || reg == RegisterIndex.Sp) // 80-bit packed BCD operations { - instruction.Operands = operand; + instruction.Operands = $"tbyte ptr {baseOperand}"; + } + else // Other operations + { + instruction.Operands = memOperand; } } else // Register operand (ST(i)) { - // Special handling for register-register operations - if (reg == RegisterIndex.A) // FFREEP + // Look up the register operation in our dictionary + if (RegisterOperations.TryGetValue((reg, rm), out var operation)) { - instruction.Mnemonic = "ffreep"; - instruction.Operands = $"st({(int)rm})"; - } - else if (reg == RegisterIndex.B && rm == RegisterIndex.A) // FXCH - { - instruction.Mnemonic = "fxch"; - instruction.Operands = ""; - } - else if (reg == RegisterIndex.C && rm == RegisterIndex.A) // FSTP - { - instruction.Mnemonic = "fstp"; - instruction.Operands = "st(1)"; - } - else if (reg == RegisterIndex.D && rm == RegisterIndex.A) // FSTP - { - instruction.Mnemonic = "fstp"; - instruction.Operands = "st(1)"; - } - else if (reg == RegisterIndex.Si) // FNSTSW - { - // This should not happen as FNSTSW AX is handled by FnstswHandler - instruction.Mnemonic = "??"; - instruction.Operands = ""; - } - else if (reg == RegisterIndex.Di) // FUCOMIP - { - instruction.Mnemonic = "fucomip"; - instruction.Operands = $"st(0), st({(int)rm})"; - } - else if (reg == RegisterIndex.Sp) // FCOMIP - { - instruction.Mnemonic = "fcomip"; - instruction.Operands = $"st(0), st({(int)rm})"; + instruction.Mnemonic = operation.Mnemonic; + instruction.Operands = operation.Operands; } else {