using X86Disassembler.X86.Operands;
namespace X86Disassembler.X86.Handlers.And;
///
/// Handler for AND r/m32, r32 instruction (0x21)
///
public class AndMemRegHandler : InstructionHandler
{
///
/// Initializes a new instance of the AndMemRegHandler class
///
/// The instruction decoder that owns this handler
public AndMemRegHandler(InstructionDecoder decoder)
: base(decoder)
{
}
///
/// Checks if this handler can decode the given opcode
///
/// The opcode to check
/// True if this handler can decode the opcode
public override bool CanHandle(byte opcode)
{
// Only handle opcode 0x21 when the operand size prefix is NOT present
// This ensures 16-bit handlers get priority when the prefix is present
return opcode == 0x21 && !Decoder.HasOperandSizePrefix();
}
///
/// Decodes an AND r/m32, r32 instruction
///
/// The opcode of the instruction
/// The instruction object to populate
/// True if the instruction was successfully decoded
public override bool Decode(byte opcode, Instruction instruction)
{
// Set the instruction type
instruction.Type = InstructionType.And;
if (!Decoder.CanReadByte())
{
return false;
}
// Read the ModR/M byte
// For AND r/m32, r32 (0x21):
// - The r/m field with mod specifies the destination operand (register or memory)
// - The reg field specifies the source register
var (_, reg, _, destinationOperand) = ModRMDecoder.ReadModRM();
// Create the source register operand
var sourceOperand = OperandFactory.CreateRegisterOperand(reg, 32);
// Set the structured operands
instruction.StructuredOperands =
[
destinationOperand,
sourceOperand
];
return true;
}
}