namespace X86Disassembler.X86.Handlers.FloatingPoint.Arithmetic;
using X86Disassembler.X86.Operands;
///
/// Handler for FADD float64 instruction (DC /0)
///
public class FaddFloat64Handler : InstructionHandler
{
///
/// Initializes a new instance of the FaddFloat64Handler class
///
/// The instruction decoder that owns this handler
public FaddFloat64Handler(InstructionDecoder decoder)
: base(decoder)
{
}
///
/// Checks if this handler can decode the given opcode
///
/// The opcode to check
/// True if this handler can decode the opcode
public override bool CanHandle(byte opcode)
{
// FADD is DC /0
if (opcode != 0xDC) return false;
if (!Decoder.CanReadByte())
{
return false;
}
// Check if the ModR/M byte has reg field = 0
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7);
return reg == 0;
}
///
/// Decodes a FADD float64 instruction
///
/// The opcode of the instruction
/// The instruction object to populate
/// True if the instruction was successfully decoded
public override bool Decode(byte opcode, Instruction instruction)
{
if (!Decoder.CanReadByte())
{
return false;
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
// Verify reg field is 0 (FADD)
if (reg != 0)
{
return false;
}
// Set the instruction type
instruction.Type = InstructionType.Fadd;
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
// Set the structured operands - the operand already has the correct size from ReadModRM64
instruction.StructuredOperands =
[
rawOperand
];
}
else // Register operand (ST(i))
{
// For DC C0-DC FF, the operands are reversed: ST(i), ST(0)
var stiOperand = OperandFactory.CreateFPURegisterOperand(fpuRm); // ST(i)
var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0); // ST(0)
// Set the structured operands
instruction.StructuredOperands =
[
stiOperand,
st0Operand
];
}
return true;
}
}