namespace X86Disassembler.X86.Handlers.FloatingPoint;
///
/// Handler for floating-point load/store int32 and miscellaneous operations (DB opcode)
///
public class LoadStoreInt32Handler : InstructionHandler
{
// DB opcode - load/store int32, misc
private static readonly string[] Mnemonics =
[
"fild",
"??",
"fist",
"fistp",
"??",
"fld",
"??",
"fstp",
];
///
/// Initializes a new instance of the LoadStoreInt32Handler class
///
/// The buffer containing the code to decode
/// The instruction decoder that owns this handler
/// The length of the buffer
public LoadStoreInt32Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
: base(codeBuffer, decoder, length)
{
}
///
/// Checks if this handler can decode the given opcode
///
/// The opcode to check
/// True if this handler can decode the opcode
public override bool CanHandle(byte opcode)
{
return opcode == 0xDB;
}
///
/// Decodes a floating-point instruction for load/store int32 and miscellaneous operations
///
/// The opcode of the instruction
/// The instruction object to populate
/// True if the instruction was successfully decoded
public override bool Decode(byte opcode, Instruction instruction)
{
int position = Decoder.GetPosition();
if (position >= Length)
{
return false;
}
// Read the ModR/M byte
var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
// Set the mnemonic based on the opcode and reg field
instruction.Mnemonic = Mnemonics[(int)reg];
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fild, fist, fistp
{
// Keep the dword ptr prefix for integer operations
instruction.Operands = destOperand;
}
else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fld, fstp (extended precision)
{
// Replace dword ptr with tword ptr for extended precision
instruction.Operands = destOperand.Replace("dword ptr", "tword ptr");
}
else
{
instruction.Operands = destOperand;
}
}
else // Register operand (ST(i))
{
// Special handling for register-register operations
if (reg == RegisterIndex.A) // FCMOVNB
{
instruction.Mnemonic = "fcmovnb";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.B) // FCMOVNE
{
instruction.Mnemonic = "fcmovne";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.C) // FCMOVNBE
{
instruction.Mnemonic = "fcmovnbe";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.D) // FCMOVNU
{
instruction.Mnemonic = "fcmovnu";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.Si)
{
if (rm == RegisterIndex.C) // FCLEX
{
instruction.Mnemonic = "fclex";
instruction.Operands = "";
}
else if (rm == RegisterIndex.D) // FINIT
{
instruction.Mnemonic = "finit";
instruction.Operands = "";
}
else
{
instruction.Mnemonic = "??";
instruction.Operands = "";
}
}
else if (reg == RegisterIndex.Di) // FUCOMI
{
instruction.Mnemonic = "fucomi";
instruction.Operands = $"st(0), st({(int)rm})";
}
else if (reg == RegisterIndex.Sp) // FCOMI
{
instruction.Mnemonic = "fcomi";
instruction.Operands = $"st(0), st({(int)rm})";
}
else
{
// Unknown instruction
instruction.Mnemonic = "??";
instruction.Operands = "";
}
}
return true;
}
}