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179 lines
8.6 KiB
C#
179 lines
8.6 KiB
C#
using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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/// Handler for floating-point operations on int16 (DE opcode)
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/// </summary>
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public class Int16OperationHandler : InstructionHandler
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{
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// Memory operand instruction types for DE opcode - operations on int16
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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InstructionType.Fiadd, // fiadd word ptr [r/m]
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InstructionType.Fmul, // fimul word ptr [r/m]
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InstructionType.Fcom, // ficom word ptr [r/m]
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InstructionType.Fcomp, // ficomp word ptr [r/m]
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InstructionType.Fsub, // fisub word ptr [r/m]
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InstructionType.Fsubr, // fisubr word ptr [r/m]
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InstructionType.Fdiv, // fidiv word ptr [r/m]
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InstructionType.Fdivr // fidivr word ptr [r/m]
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(int Reg, int Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
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{
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// FADDP st(i), st(0)
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{ (0, 0), (InstructionType.Fadd, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (0, 1), (InstructionType.Fadd, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (0, 2), (InstructionType.Fadd, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (0, 3), (InstructionType.Fadd, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (0, 4), (InstructionType.Fadd, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (0, 5), (InstructionType.Fadd, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (0, 6), (InstructionType.Fadd, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (0, 7), (InstructionType.Fadd, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FMULP st(i), st(0)
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{ (1, 0), (InstructionType.Fmul, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (1, 1), (InstructionType.Fmul, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (1, 2), (InstructionType.Fmul, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (1, 3), (InstructionType.Fmul, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (1, 4), (InstructionType.Fmul, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (1, 5), (InstructionType.Fmul, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (1, 6), (InstructionType.Fmul, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (1, 7), (InstructionType.Fmul, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// Special cases
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{ (2, 3), (InstructionType.Fcomp, FpuRegisterIndex.ST0, null) },
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{ (3, 3), (InstructionType.Fcompp, FpuRegisterIndex.ST0, null) },
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// FSUBP st(i), st(0)
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{ (6, 0), (InstructionType.Fsub, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (6, 1), (InstructionType.Fsub, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (6, 2), (InstructionType.Fsub, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (6, 3), (InstructionType.Fsub, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (6, 4), (InstructionType.Fsub, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (6, 5), (InstructionType.Fsub, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (6, 6), (InstructionType.Fsub, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (6, 7), (InstructionType.Fsub, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FSUBRP st(i), st(0)
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{ (7, 0), (InstructionType.Fsubr, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (7, 1), (InstructionType.Fsubr, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (7, 2), (InstructionType.Fsubr, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (7, 3), (InstructionType.Fsubr, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (7, 4), (InstructionType.Fsubr, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (7, 5), (InstructionType.Fsubr, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (7, 6), (InstructionType.Fsubr, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (7, 7), (InstructionType.Fsubr, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FDIVP st(i), st(0)
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{ (4, 0), (InstructionType.Fdiv, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (4, 1), (InstructionType.Fdiv, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (4, 2), (InstructionType.Fdiv, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (4, 3), (InstructionType.Fdiv, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (4, 4), (InstructionType.Fdiv, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (4, 5), (InstructionType.Fdiv, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (4, 6), (InstructionType.Fdiv, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (4, 7), (InstructionType.Fdiv, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FDIVRP st(i), st(0)
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{ (5, 0), (InstructionType.Fdivr, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (5, 1), (InstructionType.Fdivr, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (5, 2), (InstructionType.Fdivr, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (5, 3), (InstructionType.Fdivr, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (5, 4), (InstructionType.Fdivr, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (5, 5), (InstructionType.Fdivr, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (5, 6), (InstructionType.Fdivr, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (5, 7), (InstructionType.Fdivr, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) }
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};
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/// <summary>
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/// Initializes a new instance of the Int16OperationHandler class
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/// </summary>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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public Int16OperationHandler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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/// <summary>
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/// Checks if this handler can decode the given opcode
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/// </summary>
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/// <param name="opcode">The opcode to check</param>
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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return opcode == 0xDE;
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}
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/// <summary>
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/// Decodes a floating-point instruction for int16 operations
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/// </summary>
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/// <param name="opcode">The opcode of the instruction</param>
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/// <param name="instruction">The instruction object to populate</param>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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{
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if (!Decoder.CanReadByte())
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{
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return false;
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}
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// Read the ModR/M byte, specifying that we're dealing with 16-bit operands
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var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM16();
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// Handle based on addressing mode
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if (mod != 3) // Memory operand
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{
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// Set the instruction type based on the reg field
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instruction.Type = MemoryInstructionTypes[(int)reg];
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// Note: The operand size is already set to 16-bit by the ReadModRM16 method
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var int16Operand = memoryOperand;
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// Set the structured operands
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instruction.StructuredOperands =
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[
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int16Operand
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];
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}
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else // Register operand (ST(i))
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{
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// Look up the instruction type in the register operations dictionary
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if (RegisterOperations.TryGetValue(((int)reg, (int)rm), out var operation))
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{
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instruction.Type = operation.Type;
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// Create the FPU register operands
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var destOperand = OperandFactory.CreateFPURegisterOperand(operation.DestIndex);
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// Set the structured operands
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if (operation.SrcIndex.HasValue)
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{
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var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex.Value);
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instruction.StructuredOperands =
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[
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destOperand,
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srcOperand
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];
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}
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else
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{
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instruction.StructuredOperands =
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[
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destOperand
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];
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}
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}
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else
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{
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// Unknown instruction
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instruction.Type = InstructionType.Unknown;
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instruction.StructuredOperands = [];
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}
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}
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return true;
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}
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} |