New clock switch schema, fixes random core2 crashes (#3008)

* Updated stack to 1.17.0

* hal: ble: Fixed stack config

* Bumped stack version in config

* scripts: added validation of copro stack version in update bundles

* Copro: update to 1.17.2

* FuriHal: adjust tick frequency for HSE as sys clk

* FuriHal: adjust systick reload on sys clock change

* Sync api and format sources

* scripts: updated ob.data for newer stack

* FuriHal: return core2 hse pll transition on deep sleep

* FuriHal: cleanup ble glue

* FuriHal: rework ble glue, allow shci_send in critical section

* FuriHal: sync api symbols

* FuriHal: cleanup BLE glue, remove unused garbage and duplicate declarations

* FuriHal: BLE glue cleanup, 2nd iteration

* FuriHal: hide tick drift reports under FURI_HAL_OS_DEBUG

* Lib: sync stm32wb_copro with latest dev

* FuriHal: ble-glue, slightly less editable device name and duplicate definition cleanup

* FuriHal: update ble config options, enable some optimizations and ext adv

* FuriHal: update clock switch method documentation

* FuriHal: better SNBRSA bug workaround fix

* FuriHal: complete comment about tick skew

* FuriHal: proper condition in clock hsi2hse transition

* FuriHal: move PLL start to hse2pll routine, fix lockup caused by core2 switching to HSE before us

* FuriHal: explicit HSE start before switch

* FuriHal: fix documentation and move flash latency change to later stage, remove duplicate LL_RCC_SetRFWKPClockSource call

---------

Co-authored-by: hedger <hedger@nanode.su>
Co-authored-by: hedger <hedger@users.noreply.github.com>

scripts/ob.data

@@ -14,15 +14,15 @@ IWDGSTOP:0x1:rw
 IWDGSW:0x1:rw
 IPCCDBA:0x0:rw
 ESE:0x1:r
-SFSA:0xD5:r
+SFSA:0xD7:r
 FSD:0x0:r
 DDS:0x1:r
 C2OPT:0x1:r
 NBRSD:0x0:r
-SNBRSA:0xD:r
+SNBRSA:0xB:r
 BRSD:0x0:r
 SBRSA:0x12:r
-SBRV:0x35400:r
+SBRV:0x35C00:r
 PCROP1A_STRT:0x1FF:r
 PCROP1A_END:0x0:r
 PCROP_RDP:0x1:rw