From 5ba5a887a523d1019edd9a0a91ed97eba5d65c7c Mon Sep 17 00:00:00 2001 From: bricky149 Date: Sat, 28 Oct 2023 19:10:35 +0100 Subject: [PATCH 1/2] feature: enable wfi --- bsp/dp32g030/syscon.h | 19 ++++++++++++++++++- hardware/dp32g030/syscon.def | 1 + main.c | 9 +++++++++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/bsp/dp32g030/syscon.h b/bsp/dp32g030/syscon.h index 92d638a..1c57f6f 100644 --- a/bsp/dp32g030/syscon.h +++ b/bsp/dp32g030/syscon.h @@ -343,6 +343,23 @@ #define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU) #define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR) +#define SYSCON_REGISTER_ADDR (SYSCON_BASE_ADDR + 0x0100U) +#define SYSCON_REGISTER (*(volatile uint32_t *)SYSCON_REGISTER_ADDR) + +#define SYSCON_REGISTER_SLEEPONEXIT_SHIFT 1 +#define SYSCON_REGISTER_SLEEPONEXIT_WIDTH 1 +#define SYSCON_REGISTER_SLEEPONEXIT_MASK (((1U << SYSCON_REGISTER_SLEEPONEXIT_WIDTH) - 1U) << SYSCON_REGISTER_SLEEPONEXIT_SHIFT) +#define SYSCON_REGISTER_SLEEPONEXIT_VALUE_ENABLE 1U +#define SYSCON_REGISTER_SLEEPONEXIT_BITS_ENABLE (SYSCON_REGISTER_SLEEPONEXIT_VALUE_ENABLE << SYSCON_REGISTER_SLEEPONEXIT_SHIFT) +#define SYSCON_REGISTER_SLEEPONEXIT_VALUE_DISABLE 0U +#define SYSCON_REGISTER_SLEEPONEXIT_BITS_DISABLE (SYSCON_REGISTER_SLEEPONEXIT_VALUE_DISABLE << SYSCON_REGISTER_SLEEPONEXIT_SHIFT) + +#define SYSCON_REGISTER_SLEEPDEEP_SHIFT 2 +#define SYSCON_REGISTER_SLEEPDEEP_WIDTH 1 +#define SYSCON_REGISTER_SLEEPDEEP_MASK (((1U << SYSCON_REGISTER_SLEEPDEEP_WIDTH) - 1U) << SYSCON_REGISTER_SLEEPDEEP_SHIFT) +#define SYSCON_REGISTER_SLEEPDEEP_VALUE_ENABLE 1U +#define SYSCON_REGISTER_SLEEPDEEP_BITS_ENABLE (SYSCON_REGISTER_SLEEPDEEP_VALUE_ENABLE << SYSCON_REGISTER_SLEEPDEEP_SHIFT) +#define SYSCON_REGISTER_SLEEPDEEP_VALUE_DISABLE 0U +#define SYSCON_REGISTER_SLEEPDEEP_BITS_DISABLE (SYSCON_REGISTER_SLEEPDEEP_VALUE_DISABLE << SYSCON_REGISTER_SLEEPDEEP_SHIFT) #endif - diff --git a/hardware/dp32g030/syscon.def b/hardware/dp32g030/syscon.def index 7587e0c..4666378 100644 --- a/hardware/dp32g030/syscon.def +++ b/hardware/dp32g030/syscon.def @@ -176,3 +176,4 @@ CHIP_ID1 = 0x0084 CHIP_ID2 = 0x0088 CHIP_ID3 = 0x008C +SCR = 0x0100 diff --git a/main.c b/main.c index 2197966..13719f4 100644 --- a/main.c +++ b/main.c @@ -236,8 +236,17 @@ void Main(void) #endif } + // Everything is initialised, set SLEEP* bits + SYSCON_REGISTER |= SYSCON_REGISTER_SLEEPONEXIT_BITS_ENABLE; + SYSCON_REGISTER |= SYSCON_REGISTER_SLEEPDEEP_BITS_ENABLE; + while (1) { + if (!g_next_time_slice && !g_next_time_slice_500ms) + // Idle condition, hint the MCU to sleep + // CMSIS suggests GCC reorders memory and is undesired + __asm volatile ("wfi":::"memory"); + APP_process(); if (g_next_time_slice) From 071b0eee8ccb82f85361e896360990b302acac65 Mon Sep 17 00:00:00 2001 From: bricky149 Date: Sat, 28 Oct 2023 19:42:26 +0100 Subject: [PATCH 2/2] Know it's working by not unmasking interrupts --- main.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/main.c b/main.c index 13719f4..5660593 100644 --- a/main.c +++ b/main.c @@ -242,10 +242,14 @@ void Main(void) while (1) { - if (!g_next_time_slice && !g_next_time_slice_500ms) + // Mask interrupts + __asm volatile ("cpsid i"); + if (!g_next_time_slice) // Idle condition, hint the MCU to sleep - // CMSIS suggests GCC reorders memory and is undesired + // CMSIS suggests GCC reorders memory and is undesirable __asm volatile ("wfi":::"memory"); + // Unmask interrupts + __asm volatile ("cpsie i"); APP_process();