mirror of
https://github.com/OneOfEleven/uv-k5-firmware-custom.git
synced 2025-06-19 14:48:03 +03:00
updated MDC1200
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OneOfEleven
134
driver/bk4819.c
134
driver/bk4819.c
@ -292,10 +292,10 @@ void BK4819_DisableAGC(void)
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// <7:5> LNA Gain
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// 7 = 0dB
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// 6 = -2dB
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// 5 = -4dB
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// 5 = -4dB <<<
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// 4 = -6dB
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// 3 = -9dB
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// 2 = -14dB <<<
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// 2 = -14dB
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// 1 = -19dB
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// 0 = -24dB
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//
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@ -321,61 +321,63 @@ void BK4819_DisableAGC(void)
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BK4819_WriteRegister(0x10, 0x007A); // 000000 00 011 11 010
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BK4819_WriteRegister(0x14, 0x0019); // 000000 00 000 11 001
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// undocumented ?
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// ??
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BK4819_WriteRegister(0x49, 0x2A38);
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BK4819_WriteRegister(0x7B, 0x8420);
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}
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void BK4819_EnableAGC(void)
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{
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// TODO: See if this attenuates overloading
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// signals as well as boosting weak ones
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//
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// REG_7E
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//
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// <15> 0 AGC Fix Mode.
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// 1=Fix; 0=Auto.
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//
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// <14:12> 0b011 AGC Fix Index.
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// 011=Max, then 010,001,000,111,110,101,100(min).
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//
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// <5:3> 0b101 DC Filter Band Width for Tx (MIC In).
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// 000=Bypass DC filter;
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//
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// <2:0> 0b110 DC Filter Band Width for Rx (IF In).
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// 000=Bypass DC filter;
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BK4819_WriteRegister(0x7E,
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(0u << 15) | // 0 AGC fix mode
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(3u << 12) | // 3 AGC fix index
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(5u << 3) | // 5 DC Filter band width for Tx (MIC In)
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(6u << 0)); // 6 DC Filter band width for Rx (I.F In)
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// TBR: fagci has this listed as two values, agc_rssi and lna_peak_rssi
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// This is why AGC appeared to do nothing as-is for Rx
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//
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// REG_62
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//
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// <15:8> 0xFF AGC RSSI
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//
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// <7:0> 0xFF LNA Peak RSSI
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//
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// TBR: Using S9+30 (173) and S9 (143) as suggested values
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BK4819_WriteRegister(0x62, (173u << 8) | (143u << 0));
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// AGC auto-adjusts the following LNA values, no need to set them ourselves
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//BK4819_WriteRegister(0x13, (3u << 8) | (5u << 5) | (3u << 3) | (6u << 0)); // 000000 11 101 11 110
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//BK4819_WriteRegister(0x12, 0x037B); // 000000 11 011 11 011
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//BK4819_WriteRegister(0x11, 0x027B); // 000000 10 011 11 011
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//BK4819_WriteRegister(0x10, 0x007A); // 000000 00 011 11 010
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//BK4819_WriteRegister(0x14, 0x0019); // 000000 00 000 11 001
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BK4819_WriteRegister(0x49, 0x2A38);
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BK4819_WriteRegister(0x7B, 0x8420);
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for (unsigned int i = 0; i < 8; i++)
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BK4819_WriteRegister(0x06, ((i & 7u) << 13) | (0x4A << 7) | (0x36 << 0));
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}
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#ifndef ENABLE_AM_FIX
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void BK4819_EnableAGC(void)
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{
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// TODO: See if this attenuates overloading
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// signals as well as boosting weak ones
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//
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// REG_7E
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//
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// <15> 0 AGC Fix Mode.
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// 1=Fix; 0=Auto.
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//
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// <14:12> 0b011 AGC Fix Index.
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// 011=Max, then 010,001,000,111,110,101,100(min).
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//
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// <5:3> 0b101 DC Filter Band Width for Tx (MIC In).
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// 000=Bypass DC filter;
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//
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// <2:0> 0b110 DC Filter Band Width for Rx (IF In).
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// 000=Bypass DC filter;
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BK4819_WriteRegister(0x7E,
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(0u << 15) | // 0 AGC fix mode
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(3u << 12) | // 3 AGC fix index
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(5u << 3) | // 5 DC Filter band width for Tx (MIC In)
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(6u << 0)); // 6 DC Filter band width for Rx (I.F In)
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// TBR: fagci has this listed as two values, agc_rssi and lna_peak_rssi
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// This is why AGC appeared to do nothing as-is for Rx
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//
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// REG_62
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//
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// <15:8> 0xFF AGC RSSI
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//
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// <7:0> 0xFF LNA Peak RSSI
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//
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// TBR: Using S9+30 (173) and S9 (143) as suggested values
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BK4819_WriteRegister(0x62, (173u << 8) | (143u << 0));
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// AGC auto-adjusts the following LNA values, no need to set them ourselves
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//BK4819_WriteRegister(0x13, (3u << 8) | (5u << 5) | (3u << 3) | (6u << 0)); // 000000 11 101 11 110
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//BK4819_WriteRegister(0x12, 0x037B); // 000000 11 011 11 011
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//BK4819_WriteRegister(0x11, 0x027B); // 000000 10 011 11 011
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//BK4819_WriteRegister(0x10, 0x007A); // 000000 00 011 11 010
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//BK4819_WriteRegister(0x14, 0x0019); // 000000 00 000 11 001
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BK4819_WriteRegister(0x49, 0x2A38);
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BK4819_WriteRegister(0x7B, 0x8420);
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for (unsigned int i = 0; i < 8; i++)
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BK4819_WriteRegister(0x06, ((i & 7u) << 13) | (0x4A << 7) | (0x36 << 0));
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}
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#endif
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void BK4819_set_GPIO_pin(bk4819_gpio_pin_t Pin, bool bSet)
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{
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@ -1939,6 +1941,9 @@ void BK4819_reset_fsk(void)
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BK4819_WriteRegister(0x02, 0); // clear interrupt flags
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// set the almost full threshold
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BK4819_WriteRegister(0x5E, (64u << 3) | (1u << 0)); // 0 ~ 127, 0 ~ 7
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// set the packet size
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BK4819_WriteRegister(0x5D, ((packet_size - 1) << 8));
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@ -2141,7 +2146,7 @@ void BK4819_reset_fsk(void)
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(3u << 8) | // 0 FSK RX gain
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// 0 ~ 3
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//
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(3u << 6) | // 0 ???
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(0u << 6) | // 0 ???
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// 0 ~ 3
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//
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(0u << 4) | // 0 FSK preamble type selection
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@ -2177,11 +2182,16 @@ void BK4819_reset_fsk(void)
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BK4819_WriteRegister(0x5B, ((uint16_t)mdc1200_sync_suc_xor[2] << 8) | (mdc1200_sync_suc_xor[3] << 0));
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// disable CRC
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BK4819_WriteRegister(0x5C, 0x5625);
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BK4819_WriteRegister(0x5C, 0x5625); // 010101100 0 100101
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// BK4819_WriteRegister(0x5C, 0xAA30); // 101010100 0 110000
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{ // packet size .. 14 bytes - size of a single mdc1200 packet
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uint16_t size = sizeof(mdc1200_sync_suc_xor) + 14;
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// set the almost full threshold
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BK4819_WriteRegister(0x5E, (64u << 3) | (1u << 0)); // 0 ~ 127, 0 ~ 7
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{ // packet size .. sync + 14 bytes - size of a single mdc1200 packet
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uint16_t size = sizeof(mdc1200_sync_suc_xor) + (MDC1200_FEC_K * 2);
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size -= (fsk_reg59 & (1u << 3)) ? 4 : 2;
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size = ((size + 1) / 2) * 2; // round up to even, else FSK RX doesn't work
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BK4819_WriteRegister(0x5D, ((size - 1) << 8));
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}
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@ -2250,7 +2260,7 @@ void BK4819_reset_fsk(void)
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const uint16_t tx_dev = BK4819_ReadRegister(0x40);
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// BK4819_WriteRegister(0x40, (0u << 12) | (1232 << 0)); // 000 0 010011010000
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BK4819_WriteRegister(0x40, (tx_dev & 0xf000) | (1050 << 0)); // reduce the deviation a little
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BK4819_WriteRegister(0x40, (tx_dev & 0xf000) | (1000 << 0)); // reduce the deviation a little
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// REG_2B 0
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//
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@ -2294,7 +2304,7 @@ void BK4819_reset_fsk(void)
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(1u << 1) | // enable TX DSP
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(0u << 0)); // disable RX DSP
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SYSTEM_DelayMs(20);
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SYSTEM_DelayMs(10);
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// *******************************************
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@ -2464,8 +2474,8 @@ void BK4819_reset_fsk(void)
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//
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// disable CRC
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//
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// BK4819_WriteRegister(0x5C, 0xAA30); // 101010100 0 110000
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BK4819_WriteRegister(0x5C, 0); // setting to '0' doesn't make any difference !
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// BK4819_WriteRegister(0x5C, 0x5625); // 010101100 0 100101
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BK4819_WriteRegister(0x5C, 0xAA30); // 101010100 0 110000
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{ // load the entire packet data into the TX FIFO buffer
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unsigned int i;
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@ -2477,7 +2487,7 @@ void BK4819_reset_fsk(void)
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// enable tx interrupt
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BK4819_WriteRegister(0x3F, BK4819_REG_3F_FSK_TX_FINISHED);
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// enable TX
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// enable FSK TX
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BK4819_WriteRegister(0x59, (1u << 11) | fsk_reg59);
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{ // packet time is ..
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