Initial commit

external/CMSIS_5/.gitattributes

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+# Set the default behavior, in case people don't have core.autocrlf set.
+* text=auto
+# Explicitly declare text files you want to always be normalized and converted
+# to native line endings on checkout.
+*.c text
+*.h text
+*.txt text
+*.xsd text
+*.pdsc text
+*.svd text
+*.bat text
+# Declare files that will always have CRLF line endings on checkout.
+*.uvproj text eol=crlf
+*.uvproj text eol=crlf
+# Denote all files that are truly binary and should not be modified.
+*.png binary
+*.jpg binary
+# Script files
+*.py text eol=lf
+*.sh text eol=lf

external/CMSIS_5/.github/fileheader.json

@@ -0,0 +1,16 @@
+{
+	"problemMatcher": [
+		{
+			"owner": "fileheader",
+			"severity": "error",
+			"pattern": [
+				{
+					"regexp": "^(.*):(\\d+):(.*)$",
+					"file": 1,
+					"line": 2,
+					"message": 3
+				}
+			]
+		}
+	]
+}

external/CMSIS_5/.github/linkchecker.json

@@ -0,0 +1,16 @@
+{
+	"problemMatcher": [
+		{
+			"owner": "fileheader",
+			"severity": "error",
+			"pattern": [
+				{
+					"regexp": "^(.*):(\\d+);(.*);(.*)$",
+					"file": 1,
+					"line": 2,
+					"message": 4
+				}
+			]
+		}
+	]
+}

external/CMSIS_5/.github/workflows/caller-corevalidation.yml

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+name: Caller CoreValidation
+on:
+  push:
+    branches: [ main ]
+  pull_request:
+    paths:
+      - .github/workflows/caller-corevalidation.yml
+      - CMSIS/Core/**/*
+      - CMSIS/Core_A/**/*
+      - CMSIS/CoreValidation/**/*
+      - Device/ARM/**/*
+  workflow_dispatch:
+
+jobs:
+  upload_pr_number:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Save PR number
+        env:
+          PR_NUMBER: ${{ github.event.number }}
+        run: |
+          mkdir -p ./pr
+          echo -n $PR_NUMBER > ./pr/pr_number
+      - uses: actions/upload-artifact@v3
+        with:
+          name: pr_number
+          path: pr/

external/CMSIS_5/.github/workflows/codeql-analysis.yml

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+name: "CodeQL"
+
+on:
+  workflow_dispatch:
+  push:
+    branches: [ develop ]
+    paths:
+      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_A/**'
+      - 'CMSIS/CoreValidation/**'
+      - 'Device/ARM/**'
+  pull_request:
+    branches: [ develop ]
+    paths:
+      - '.github/workflows/codeql-analysis.yml'
+      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_A/**'
+      - 'CMSIS/CoreValidation/**'
+      - 'Device/ARM/**'
+jobs:
+  analyze:
+    name: Analyze
+    runs-on: ubuntu-latest
+    permissions:
+      actions: read
+      contents: read
+      security-events: write
+    env:
+      CMSIS_PACK_ROOT: /tmp/.packs-${{ github.run_id }}
+
+    steps:
+    - name: Checkout repository
+      uses: actions/checkout@v3
+
+    - name: Install build dependencies
+      run: |
+        sudo apt install gcc-arm-none-eabi ninja-build cmake
+
+    - name: Cache pack folder
+      id: cache-packs
+      uses: actions/cache@v3
+      with:
+        key: packs-${{ github.run_id }}
+        restore-keys: |
+          packs-
+        path: /tmp/.packs-${{ github.run_id }}
+
+    - name: Install CMSIS-Toolbox
+      run: |
+        wget https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases/download/1.5.0/cmsis-toolbox.sh
+        chmod +x cmsis-toolbox.sh
+        sudo ./cmsis-toolbox.sh <<EOI
+        /opt/ctools
+        $CMSIS_PACK_ROOT
+
+
+        $(dirname $(which arm-none-eabi-gcc 2>/dev/null))
+
+        EOI
+        echo "/opt/ctools/bin" >> $GITHUB_PATH
+        echo "cpackget : $(which cpackget)"
+        echo "csolution: $(which csolution)"
+        echo "cbuild   : $(which cbuild)"
+
+    - name: Initialize packs folder
+      if: steps.cache-packs.outputs.cache-hit != 'true'
+      run: cpackget init https://www.keil.com/pack/index.pidx
+
+    - name: Update pack index
+      if: steps.cache-packs.outputs.cache-hit == 'true'
+      run: cpackget update-index
+
+    - name: Install build.py requirements
+      run: pip install -r requirements.txt
+      working-directory: CMSIS/CoreValidation/Project
+
+    # Initializes the CodeQL tools for scanning.
+    - name: Initialize CodeQL
+      uses: github/codeql-action/init@v2
+      with:
+        languages: cpp
+        queries: security-and-quality
+
+    - name: Build projects
+      working-directory: CMSIS/CoreValidation/Project
+      run: |
+        pip install -r requirements.txt
+        cpackget add -a -f cpacklist.txt
+        python build.py --verbose -c GCC -d "CM[047]*" -d "CM[23]3*" -o low build || echo "Something failed!"
+
+    - name: Perform CodeQL Analysis
+      uses: github/codeql-action/analyze@v2

external/CMSIS_5/.github/workflows/corevalidation-report.yml

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+name: Publish CoreValidation Test Results
+
+on:
+  workflow_run:
+    workflows: ["CoreValidation"]
+    branches-ignore: ["develop"]
+    types:
+      - completed
+
+jobs:
+  publish-test-results:
+    name: Publish CoreValidation Test Results
+    runs-on: ubuntu-latest
+    permissions:
+      contents: read
+      issues: read
+      checks: write
+      pull-requests: write
+    if: github.event.workflow_run.conclusion != 'skipped'
+
+    steps:
+      - name: Download test results
+        env:
+          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+        run: |
+           mkdir -p artifacts && cd artifacts
+
+           artifacts_url=${{ github.event.workflow_run.artifacts_url }}
+
+           gh api "$artifacts_url" -q '.artifacts[] | select(.name=="tests" or .name=="EventFile") | [.name, .archive_download_url] | @tsv' | \
+           while read artifact; do
+             IFS=$'\t' read name url <<< "$artifact"
+             gh api $url > "$name.zip"
+             unzip -d "$name" "$name.zip"
+           done
+
+      - name: Publish Test Results
+        uses: EnricoMi/publish-unit-test-result-action@v2
+        with:
+          commit: ${{ github.event.workflow_run.head_sha }}
+          event_file: artifacts/EventFile/event.json
+          report_individual_runs: true
+          event_name: ${{ github.event.workflow_run.event }}
+          junit_files: "artifacts/**/*.junit"

external/CMSIS_5/.github/workflows/corevalidation.yml

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+# This workflow is triggered whenever "Caller CoreValidation" workflow is completed (which is called by PR).
+# This workflow ideally should be triggered also by PR, but forked PR has limited permissions which does not
+# allow to use `configure-aws-credentials` actions and using secrets.
+# It will update its status back to the caller PR as "CoreValidation" check name
+name: CoreValidation
+on:
+  workflow_run:
+    workflows:
+      - Caller CoreValidation
+    types:
+      - completed
+
+# The env variables relate to an ARM AWS account for CMSIS_5
+# If you are forking CMSIS_5 repo, please use your own info.
+env:
+  AWS_ASSUME_ROLE: ${{ secrets.AWS_ASSUME_ROLE }}
+  AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }}
+  AWS_IAM_PROFILE: ${{ secrets.AWS_IAM_PROFILE }}
+  AWS_S3_BUCKET_NAME: ${{ secrets.AWS_S3_BUCKET_NAME }}
+  AWS_SECURITY_GROUP_ID: ${{ secrets.AWS_SECURITY_GROUP_ID }}
+  AWS_SUBNET_ID: ${{ secrets.AWS_SUBNET_ID }}
+
+jobs:
+  set_pending_status_to_pr:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Set a pending status to the PR
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        run: |
+          curl --request POST \
+            --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \
+            --header "authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
+            --header 'content-type: application/json' \
+            --data '{
+              "state": "pending",
+              "context": "CoreValidation",
+              "target_url": "https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id	}}"
+              }' \
+            --fail
+
+  ci_test:
+    runs-on: ubuntu-latest
+    needs: set_pending_status_to_pr
+    permissions:
+      id-token: write
+      contents: read
+    outputs:
+      avhresult: ${{ steps.avh.conclusion }}
+      testbadge: ${{ steps.avh.outputs.badge }}
+    steps:
+    - name: Download workflow artifact
+      uses: dawidd6/action-download-artifact@v2
+      with:
+        github_token: ${{ secrets.GITHUB_TOKEN }}
+        workflow: caller-corevalidation.yml
+        run_id: ${{ github.event.workflow_run.id }}
+
+    - name: Read the pr_num file
+      id: pr_num_reader
+      uses: juliangruber/read-file-action@v1.1.6
+      with:
+        path: ./pr_number/pr_number
+        trim: true
+
+    - name: Clone this repo
+      uses: actions/checkout@v3
+      with:
+        fetch-depth: 0
+
+    - name: Checkout PR
+      env:
+        GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+      run: |
+        gh pr checkout ${{ steps.pr_num_reader.outputs.content }}
+
+    - name: Set up Python 3.10
+      uses: actions/setup-python@v4
+      with:
+        python-version: '3.10'
+
+    - name: Install AVH Client for Python
+      run: |
+        pip install git+https://github.com/ARM-software/avhclient.git@v0.1
+
+    - uses: ammaraskar/gcc-problem-matcher@master
+
+    - name: Configure AWS Credentials
+      uses: aws-actions/configure-aws-credentials@v1-node16
+      with:
+        role-to-assume: ${{ env.AWS_ASSUME_ROLE }}
+        aws-region: ${{ env.AWS_DEFAULT_REGION }}
+
+    - name: Run tests
+      id: avh
+      run: |
+        avhclient -b aws execute --specfile CMSIS/CoreValidation/Project/avh.yml
+
+    - name: Archive build results
+      uses: actions/upload-artifact@v3
+      with:
+        name: builds
+        path: CMSIS/CoreValidation/Project/Core_Validation-*.zip
+        retention-days: 1
+        if-no-files-found: error
+      if: always()
+
+    - name: Archive test results
+      uses: actions/upload-artifact@v3
+      with:
+        name: tests
+        path: CMSIS/CoreValidation/Project/Core_Validation-*.junit
+        retention-days: 1
+        if-no-files-found: error
+      if: always()
+
+    - name: Archive event file
+      uses: actions/upload-artifact@v3
+      with:
+        name: EventFile
+        path: ${{ github.event_path }}
+
+  set_success_status_to_pr:
+    runs-on: ubuntu-latest
+    needs: ci_test
+    if: ${{ success() }}
+    steps:
+      - name: Set success status to the PR
+        env:
+          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+        run: |
+          curl --request POST \
+            --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \
+            --header "authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
+            --header 'content-type: application/json' \
+            --data '{
+              "state": "success",
+              "context": "CoreValidation",
+              "target_url": "https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id	}}"
+              }' \
+            --fail
+
+  set_failure_status_to_pr:
+    runs-on: ubuntu-latest
+    needs: ci_test
+    if: ${{ failure() }}
+    steps:
+      - name: Set failure status to the PR
+        env:
+          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+        run: |
+          curl --request POST \
+            --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \
+            --header "authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
+            --header 'content-type: application/json' \
+            --data '{
+              "state": "failure",
+              "context": "CoreValidation",
+              "target_url": "https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id	}}"
+              }' \
+            --fail

external/CMSIS_5/.github/workflows/fileheader.yml

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+name: File header
+
+on:
+  pull_request:
+    branches: [ develop ]
+    paths:
+      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_A/**'
+      - 'CMSIS/RTOS2/Include/**'
+      - 'CMSIS/RTOS2/Source/**'
+      - 'Device/**'
+
+permissions:
+  contents: read
+  pull-requests: write
+
+jobs:
+  check:
+    name: Check file header
+    runs-on: ubuntu-latest
+    steps:
+    - name: Calculate depth
+      id: depth
+      run: |
+        echo ::set-output name=GIT_COMMITS::$((${{ github.event.pull_request.commits }} + 1))
+    - name: Checkout repository
+      uses: actions/checkout@v2
+      with:
+        ref: ${{ github.event.pull_request.head.sha }}
+        fetch-depth: ${{ steps.depth.outputs.GIT_COMMITS }}
+    - id: files
+      uses: jitterbit/get-changed-files@v1
+    - name: Check changed files
+      run: |
+        echo "GIT_COMMITS=${{ steps.depth.outputs.GIT_COMMITS }}"
+        echo "::add-matcher::.github/fileheader.json"
+        RC=0
+        for changed_file in ${{ steps.files.outputs.added_modified }}; do
+          ./CMSIS/Utilities/check_header.sh -v -b HEAD~${{ github.event.pull_request.commits }} ${changed_file} || RC=1
+        done
+        echo "::remove-matcher owner=fileheader::"
+        exit $RC

external/CMSIS_5/.github/workflows/gh-pages.yaml

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+name: Publish Documentation
+on:
+  workflow_dispatch:
+  pull_request:
+    branches: [ develop ]
+    paths:
+      - '.github/workflows/gh-pages.yaml'
+      - 'CMSIS/Utilities/check_links.sh'
+      - 'CMSIS/DoxyGen/**'
+  push:
+    branches: [ develop ]
+    paths:
+      - '.github/workflows/gh-pages.yaml'
+      - 'CMSIS/Utilities/check_links.sh'
+      - 'CMSIS/DoxyGen/**'
+jobs:
+  docs:
+    name: Build develop documentation
+    runs-on: ubuntu-20.04
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions/setup-node@v1
+      - name: Install Doxygen 1.8.6
+        run: |
+          wget http://archive.ubuntu.com/ubuntu/pool/main/d/doxygen/doxygen_1.8.6-2_amd64.deb
+          sudo dpkg -i doxygen_1.8.6-2_amd64.deb
+      - name: Install mscgen 0.20
+        run: |
+          sudo apt-get update
+          sudo apt-get install --no-install-recommends -y mscgen=0.20-12
+      - name: Install linkchecker
+        run: |
+          sudo pip install LinkChecker
+      - name: Generate doxygen
+        run: CMSIS/DoxyGen/gen_doc.sh
+      - name: Run linkchecker
+        run: |
+          echo "::add-matcher::.github/linkchecker.json"
+          CMSIS/Utilities/check_links.sh CMSIS/Documentation/index.html
+      - name: Upload documentation
+        if: ${{ github.event_name == 'pull_request' }}
+        uses: actions/upload-artifact@v2
+        with:
+          path: CMSIS/Documentation/**
+      - name: Archive documentation
+        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}
+        run: |
+          cd CMSIS/Documentation
+          tar -cvjf /tmp/doc.tbz2 .
+      - uses: actions/checkout@v2
+        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}
+        with:
+          ref: gh-pages
+      - name: Publish documentation
+        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}
+        run: |
+          rm -r develop
+          mkdir develop
+          cd develop
+          tar -xvjf /tmp/doc.tbz2
+          git config user.name github-actions
+          git config user.email github-actions@github.com
+          git add .
+          git commit -m "Update develop documentation"
+          git push

external/CMSIS_5/.github/workflows/packdesc.yml

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+name: Pack Description
+
+on:
+  pull_request:
+    branches: [ develop ]
+    paths:
+      - 'ARM.CMSIS.pdsc'
+
+permissions:
+  contents: read
+  pull-requests: write
+
+jobs:
+  check:
+    name: Check pack description schema
+    runs-on: ubuntu-latest
+    steps:
+    - name: Install xmllint
+      run: |
+        sudo apt-get update
+        sudo apt-get install libxml2-utils
+    - name: Checkout repository
+      uses: actions/checkout@v2
+      with:
+        ref: ${{ github.event.pull_request.head.sha }}
+    - name: Run xmllint
+      run: |
+        curl https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/main/schema/PACK.xsd -o CMSIS/Utilities/PACK.xsd
+        echo "::add-matcher::.github/xmllint.json"
+        xmllint --noout --schema "$(realpath -m ./CMSIS/Utilities/PACK.xsd)" "ARM.CMSIS.pdsc"
+        echo "::remove-matcher owner=xmllint::"

external/CMSIS_5/.github/workflows/release.yaml

@@ -0,0 +1,41 @@
+name: Release Documentation
+on:
+  release:
+    types: [published]
+jobs:
+  docs:
+    name: Build release documentation
+    runs-on: ubuntu-20.04
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions/setup-node@v1
+      - name: Install Doxygen 1.8.6
+        run: |
+          wget http://archive.ubuntu.com/ubuntu/pool/main/d/doxygen/doxygen_1.8.6-2_amd64.deb
+          sudo dpkg -i doxygen_1.8.6-2_amd64.deb
+      - name: Install mscgen 0.20
+        run: |
+          sudo apt-get update
+          sudo apt-get install --no-install-recommends -y mscgen=0.20-12
+      - name: Generate doxygen
+        run: CMSIS/DoxyGen/gen_doc.sh
+      - name: Archive documentation
+        run: |
+          cd CMSIS/Documentation
+          tar -cvjf /tmp/doc.tbz2 .
+      - uses: actions/checkout@v2
+        with:
+          ref: gh-pages
+      - name: Publish documentation
+        run: |
+          RELEASE=$(echo $GITHUB_REF | sed 's/refs\/tags\///')
+          mkdir ${RELEASE}
+          rm latest
+          ln -s ${RELEASE} latest
+          cd ${RELEASE}
+          tar -xvjf /tmp/doc.tbz2
+          git config user.name github-actions
+          git config user.email github-actions@github.com
+          git add . ../latest
+          git commit -m "Update documentation for release ${RELEASE}"
+          git push

external/CMSIS_5/.github/xmllint.json

@@ -0,0 +1,16 @@
+{
+  "problemMatcher": [
+    {
+      "owner": "xmllint",
+      "severity": "error",
+      "pattern": [
+        {
+          "regexp": "^(.*):(\\d+):(.*)$",
+          "file": 1,
+          "line": 2,
+          "message": 3
+        }
+      ]
+    }
+  ]
+}

external/CMSIS_5/.gitignore

@@ -0,0 +1,24 @@
+*.breadcrumb
+*.junit
+**/__pycache__
+Local_Release/
+CMSIS/Documentation/
+CMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvguix.*
+CMSIS/CoreValidation/Project/*.zip
+CMSIS/CoreValidation/Project/*.junit
+CMSIS/CoreValidation/Project/Validation.*/
+CMSIS/CoreValidation/Project/Bootloader.*/
+*.uvguix.*
+*.uvmpw.uvgui.*
+*.zip
+docker/dependenciesFiles
+CMSIS/RTOS/RTX/LIB/**/*.a
+CMSIS/RTOS/RTX/LIB/**/*.lib
+CMSIS/RTOS2/RTX/Library/**/*.a
+CMSIS/RTOS2/RTX/Library/**/*.lib
+output
+.DS_Store
+internal.cp310-win_amd64.pyd
+CMSIS/Utilities/Darwin64
+CMSIS/Utilities/Linux64
+CMSIS/Utilities/Win32

external/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h

@@ -0,0 +1,441 @@
+/******************************************************************************
+ * @file     cachel1_armv7.h
+ * @brief    CMSIS Level 1 Cache API for Armv7-M and later
+ * @version  V1.0.3
+ * @date     17. March 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_CACHEL1_ARMV7_H
+#define ARM_CACHEL1_ARMV7_H
+
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   I-Cache Invalidate by address
+  \details Invalidates I-Cache for the given address.
+           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           I-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   isize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if ( isize > 0 ) {
+       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_ICACHE_LINE_SIZE;
+        op_size -= __SCB_ICACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    struct {
+      uint32_t ccsidr;
+      uint32_t sets;
+      uint32_t ways;
+    } locals
+    #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
+       __ALIGNED(__SCB_DCACHE_LINE_SIZE)
+    #endif
+    ;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    #if !defined(__OPTIMIZE__)
+      /*
+       * For the endless loop issue with no optimization builds.
+       * More details, see https://github.com/ARM-software/CMSIS_5/issues/620
+       *
+       * The issue only happens when local variables are in stack. If
+       * local variables are saved in general purpose register, then the function
+       * is OK.
+       *
+       * When local variables are in stack, after disabling the cache, flush the
+       * local variables cache line for data consistency.
+       */
+      /* Clean and invalidate the local variable cache. */
+    #if defined(__ICCARM__)
+    /* As we can't align the stack to the cache line size, invalidate each of the variables */
+      SCB->DCCIMVAC = (uint32_t)&locals.sets;
+      SCB->DCCIMVAC = (uint32_t)&locals.ways;
+      SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
+    #else
+      SCB->DCCIMVAC = (uint32_t)&locals;
+    #endif
+      __DSB();
+      __ISB();
+    #endif
+
+    locals.ccsidr = SCB->CCSIDR;
+                                            /* clean & invalidate D-Cache */
+    locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
+    do {
+      locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
+      do {
+        SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (locals.ways-- != 0U);
+    } while(locals.sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address.
+           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr +=          __SCB_DCACHE_LINE_SIZE;
+        op_size -=          __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_CACHEL1_ARMV7_H */

external/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h

@@ -0,0 +1,894 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.4.0
+ * @date     20. January 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+#ifndef __NO_INIT
+  #define __NO_INIT                              __attribute__ ((section (".bss.noinit"), zero_init))
+#endif
+#ifndef __ALIAS
+  #define __ALIAS(x)                             __attribute__ ((alias(x)))
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+  __ISB();
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

external/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,303 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.3.0
+ * @date     04. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+/*
+ * TI Arm Clang Compiler (tiarmclang)
+ */
+#elif defined (__ti__)
+  #include "cmsis_tiarmclang.h"
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler (armcl)
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".bss.noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".bss.noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".bss.noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

external/CMSIS_5/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.5
+ * @date     02. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

external/CMSIS_5/CMSIS/Core/Include/core_cm0.h

@@ -0,0 +1,957 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.1.0
+ * @date     04. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ti__)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to access vector */
+  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to access vector */
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

external/CMSIS_5/CMSIS/Core/Include/core_cm1.h

@@ -0,0 +1,984 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.1.0
+ * @date     04. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ti__)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

external/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h

@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.2
+ * @date     25. May 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

external/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h

@@ -0,0 +1,423 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.9.0
+ * @date     11. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for Normal memory, Outer and Inner cacheability.
+* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
+* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
+* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Normal memory outer-cacheable and inner-cacheable attributes
+* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
+*/
+#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
+#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA      (0b0010)
+#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA      (0b0001)
+#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA   (0b0011)
+#define MPU_ATTR_NORMAL_OUTER_WT_RA         (0b1010)
+#define MPU_ATTR_NORMAL_OUTER_WT_WA         (0b1001)
+#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA      (0b1011)
+#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA      (0b0101)
+#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA      (0b0110)
+#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA   (0b0111)
+#define MPU_ATTR_NORMAL_OUTER_WB_RA         (0b1101)
+#define MPU_ATTR_NORMAL_OUTER_WB_WA         (0b1110)
+#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA      (0b1111)
+#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
+#define MPU_ATTR_NORMAL_INNER_WT_TR_RA      (0b0010)
+#define MPU_ATTR_NORMAL_INNER_WT_TR_WA      (0b0001)
+#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA   (0b0011)
+#define MPU_ATTR_NORMAL_INNER_WT_RA         (0b1010)
+#define MPU_ATTR_NORMAL_INNER_WT_WA         (0b1001)
+#define MPU_ATTR_NORMAL_INNER_WT_RA_WA      (0b1011)
+#define MPU_ATTR_NORMAL_INNER_WB_TR_RA      (0b0101)
+#define MPU_ATTR_NORMAL_INNER_WB_TR_WA      (0b0110)
+#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA   (0b0111)
+#define MPU_ATTR_NORMAL_INNER_WB_RA         (0b1101)
+#define MPU_ATTR_NORMAL_INNER_WB_WA         (0b1110)
+#define MPU_ATTR_NORMAL_INNER_WB_RA_WA      (0b1111)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/* \brief Specifies MAIR_ATTR number */
+#define MAIR_ATTR(x)						((x > 7 || x < 0) ? 0 : x)
+
+/**
+ * Shareability
+ */
+/** \brief Normal memory, non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory, outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory, inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/**
+ * Access permissions
+ * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
+ */
+/** \brief Normal memory, read/write */
+#define ARM_MPU_AP_RW (0U)
+
+/** \brief Normal memory, read-only */
+#define ARM_MPU_AP_RO (1U)
+
+/** \brief Normal memory, any privilege level */
+#define ARM_MPU_AP_NP (1U)
+
+/** \brief Normal memory, privileged access only */
+#define ARM_MPU_AP_PO (0U)
+
+/*
+ * Execute-never
+ * XN = Execute-never, EX = Executable
+ */
+/** \brief Normal memory, Execution only permitted if read permitted */
+#define ARM_MPU_XN (1U)
+
+/** \brief Normal memory, Execution only permitted if read permitted */
+#define ARM_MPU_EX (0U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
+* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/**
+  \brief  Read MPU Type Register
+  \return Number of MPU regions
+*/
+__STATIC_INLINE uint32_t ARM_MPU_TYPE()
+{
+  return ((MPU->TYPE) >> 8);
+}
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

external/CMSIS_5/CMSIS/Core/Include/pac_armv81.h

@@ -0,0 +1,206 @@
+/******************************************************************************
+ * @file     pac_armv81.h
+ * @brief    CMSIS PAC key functions for Armv8.1-M PAC extension
+ * @version  V1.0.0
+ * @date     23. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef PAC_ARMV81_H
+#define PAC_ARMV81_H
+
+
+/* ###################  PAC Key functions  ########################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
+  \brief    Functions that access the PAC keys.
+  @{
+ */
+
+#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
+
+/**
+  \brief   read the PAC key used for privileged mode
+  \details Reads the PAC key stored in the PAC_KEY_P registers.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_p_0\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_p_1\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_p_2\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_p_3\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for privileged mode
+  \details writes the given PAC key to the PAC_KEY_P registers.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_p_0, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_p_1, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_p_2, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_p_3, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   read the PAC key used for unprivileged mode
+  \details Reads the PAC key stored in the PAC_KEY_U registers.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_u_0\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_u_1\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_u_2\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_u_3\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for unprivileged mode
+  \details writes the given PAC key to the PAC_KEY_U registers.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_u_0, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_u_1, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_u_2, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_u_3, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+
+/**
+  \brief   read the PAC key used for privileged mode (non-secure)
+  \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_p_0_ns\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_p_1_ns\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_p_2_ns\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_p_3_ns\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for privileged mode (non-secure)
+  \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_p_0_ns, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_p_1_ns, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_p_2_ns, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_p_3_ns, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   read the PAC key used for unprivileged mode (non-secure)
+  \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_u_0_ns\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_u_1_ns\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_u_2_ns\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_u_3_ns\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for unprivileged mode (non-secure)
+  \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_u_0_ns, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_u_1_ns, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_u_2_ns, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_u_3_ns, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
+
+#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
+
+/*@} end of CMSIS_Core_PacKeyFunctions */
+
+
+#endif /* PAC_ARMV81_H */

external/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h

@@ -0,0 +1,337 @@
+/******************************************************************************
+ * @file     pmu_armv8.h
+ * @brief    CMSIS PMU API for Armv8.1-M PMU
+ * @version  V1.0.1
+ * @date     15. April 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_PMU_ARMV8_H
+#define ARM_PMU_ARMV8_H
+
+/**
+ * \brief PMU Events
+ * \note  See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
+ * */
+
+#define ARM_PMU_SW_INCR                              0x0000             /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
+#define ARM_PMU_L1I_CACHE_REFILL                     0x0001             /*!< L1 I-Cache refill */
+#define ARM_PMU_L1D_CACHE_REFILL                     0x0003             /*!< L1 D-Cache refill */
+#define ARM_PMU_L1D_CACHE                            0x0004             /*!< L1 D-Cache access */
+#define ARM_PMU_LD_RETIRED                           0x0006             /*!< Memory-reading instruction architecturally executed and condition code check pass */
+#define ARM_PMU_ST_RETIRED                           0x0007             /*!< Memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_INST_RETIRED                         0x0008             /*!< Instruction architecturally executed */
+#define ARM_PMU_EXC_TAKEN                            0x0009             /*!< Exception entry */
+#define ARM_PMU_EXC_RETURN                           0x000A             /*!< Exception return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_PC_WRITE_RETIRED                     0x000C             /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
+#define ARM_PMU_BR_IMMED_RETIRED                     0x000D             /*!< Immediate branch architecturally executed */
+#define ARM_PMU_BR_RETURN_RETIRED                    0x000E             /*!< Function return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_UNALIGNED_LDST_RETIRED               0x000F             /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BR_MIS_PRED                          0x0010             /*!< Mispredicted or not predicted branch speculatively executed */
+#define ARM_PMU_CPU_CYCLES                           0x0011             /*!< Cycle */
+#define ARM_PMU_BR_PRED                              0x0012             /*!< Predictable branch speculatively executed */
+#define ARM_PMU_MEM_ACCESS                           0x0013             /*!< Data memory access */
+#define ARM_PMU_L1I_CACHE                            0x0014             /*!< Level 1 instruction cache access */
+#define ARM_PMU_L1D_CACHE_WB                         0x0015             /*!< Level 1 data cache write-back */
+#define ARM_PMU_L2D_CACHE                            0x0016             /*!< Level 2 data cache access */
+#define ARM_PMU_L2D_CACHE_REFILL                     0x0017             /*!< Level 2 data cache refill */
+#define ARM_PMU_L2D_CACHE_WB                         0x0018             /*!< Level 2 data cache write-back */
+#define ARM_PMU_BUS_ACCESS                           0x0019             /*!< Bus access */
+#define ARM_PMU_MEMORY_ERROR                         0x001A             /*!< Local memory error */
+#define ARM_PMU_INST_SPEC                            0x001B             /*!< Instruction speculatively executed */
+#define ARM_PMU_BUS_CYCLES                           0x001D             /*!< Bus cycles */
+#define ARM_PMU_CHAIN                                0x001E             /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
+#define ARM_PMU_L1D_CACHE_ALLOCATE                   0x001F             /*!< Level 1 data cache allocation without refill */
+#define ARM_PMU_L2D_CACHE_ALLOCATE                   0x0020             /*!< Level 2 data cache allocation without refill */
+#define ARM_PMU_BR_RETIRED                           0x0021             /*!< Branch instruction architecturally executed */
+#define ARM_PMU_BR_MIS_PRED_RETIRED                  0x0022             /*!< Mispredicted branch instruction architecturally executed */
+#define ARM_PMU_STALL_FRONTEND                       0x0023             /*!< No operation issued because of the frontend */
+#define ARM_PMU_STALL_BACKEND                        0x0024             /*!< No operation issued because of the backend */
+#define ARM_PMU_L2I_CACHE                            0x0027             /*!< Level 2 instruction cache access */
+#define ARM_PMU_L2I_CACHE_REFILL                     0x0028             /*!< Level 2 instruction cache refill */
+#define ARM_PMU_L3D_CACHE_ALLOCATE                   0x0029             /*!< Level 3 data cache allocation without refill */
+#define ARM_PMU_L3D_CACHE_REFILL                     0x002A             /*!< Level 3 data cache refill */
+#define ARM_PMU_L3D_CACHE                            0x002B             /*!< Level 3 data cache access */
+#define ARM_PMU_L3D_CACHE_WB                         0x002C             /*!< Level 3 data cache write-back */
+#define ARM_PMU_LL_CACHE_RD                          0x0036             /*!< Last level data cache read */
+#define ARM_PMU_LL_CACHE_MISS_RD                     0x0037             /*!< Last level data cache read miss */
+#define ARM_PMU_L1D_CACHE_MISS_RD                    0x0039             /*!< Level 1 data cache read miss */
+#define ARM_PMU_OP_COMPLETE                          0x003A             /*!< Operation retired */
+#define ARM_PMU_OP_SPEC                              0x003B             /*!< Operation speculatively executed */
+#define ARM_PMU_STALL                                0x003C             /*!< Stall cycle for instruction or operation not sent for execution */
+#define ARM_PMU_STALL_OP_BACKEND                     0x003D             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
+#define ARM_PMU_STALL_OP_FRONTEND                    0x003E             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
+#define ARM_PMU_STALL_OP                             0x003F             /*!< Instruction or operation slots not occupied each cycle */
+#define ARM_PMU_L1D_CACHE_RD                         0x0040             /*!< Level 1 data cache read */
+#define ARM_PMU_LE_RETIRED                           0x0100             /*!< Loop end instruction executed */
+#define ARM_PMU_LE_SPEC                              0x0101             /*!< Loop end instruction speculatively executed */
+#define ARM_PMU_BF_RETIRED                           0x0104             /*!< Branch future instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BF_SPEC                              0x0105             /*!< Branch future instruction speculatively executed and condition code check pass */
+#define ARM_PMU_LE_CANCEL                            0x0108             /*!< Loop end instruction not taken */
+#define ARM_PMU_BF_CANCEL                            0x0109             /*!< Branch future instruction not taken */
+#define ARM_PMU_SE_CALL_S                            0x0114             /*!< Call to secure function, resulting in Security state change */
+#define ARM_PMU_SE_CALL_NS                           0x0115             /*!< Call to non-secure function, resulting in Security state change */
+#define ARM_PMU_DWT_CMPMATCH0                        0x0118             /*!< DWT comparator 0 match */
+#define ARM_PMU_DWT_CMPMATCH1                        0x0119             /*!< DWT comparator 1 match */
+#define ARM_PMU_DWT_CMPMATCH2                        0x011A             /*!< DWT comparator 2 match */
+#define ARM_PMU_DWT_CMPMATCH3                        0x011B             /*!< DWT comparator 3 match */
+#define ARM_PMU_MVE_INST_RETIRED                     0x0200             /*!< MVE instruction architecturally executed */
+#define ARM_PMU_MVE_INST_SPEC                        0x0201             /*!< MVE instruction speculatively executed */
+#define ARM_PMU_MVE_FP_RETIRED                       0x0204             /*!< MVE floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SPEC                          0x0205             /*!< MVE floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_HP_RETIRED                    0x0208             /*!< MVE half-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_HP_SPEC                       0x0209             /*!< MVE half-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_SP_RETIRED                    0x020C             /*!< MVE single-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SP_SPEC                       0x020D             /*!< MVE single-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_MAC_RETIRED                   0x0214             /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_FP_MAC_SPEC                      0x0215             /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_INT_RETIRED                      0x0224             /*!< MVE integer instruction architecturally executed */
+#define ARM_PMU_MVE_INT_SPEC                         0x0225             /*!< MVE integer instruction speculatively executed */
+#define ARM_PMU_MVE_INT_MAC_RETIRED                  0x0228             /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_INT_MAC_SPEC                     0x0229             /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_RETIRED                     0x0238             /*!< MVE load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_SPEC                        0x0239             /*!< MVE load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_RETIRED                       0x023C             /*!< MVE load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_SPEC                          0x023D             /*!< MVE load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_RETIRED                       0x0240             /*!< MVE store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_SPEC                          0x0241             /*!< MVE store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_CONTIG_RETIRED              0x0244             /*!< MVE contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_CONTIG_SPEC                 0x0245             /*!< MVE contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_CONTIG_RETIRED                0x0248             /*!< MVE contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_CONTIG_SPEC                   0x0249             /*!< MVE contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_CONTIG_RETIRED                0x024C             /*!< MVE contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_CONTIG_SPEC                   0x024D             /*!< MVE contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED           0x0250             /*!< MVE non-contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC              0x0251             /*!< MVE non-contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED             0x0254             /*!< MVE non-contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_SPEC                0x0255             /*!< MVE non-contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED             0x0258             /*!< MVE non-contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_SPEC                0x0259             /*!< MVE non-contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_MULTI_RETIRED               0x025C             /*!< MVE memory instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LDST_MULTI_SPEC                  0x025D             /*!< MVE memory instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LD_MULTI_RETIRED                 0x0260             /*!< MVE memory load instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LD_MULTI_SPEC                    0x0261             /*!< MVE memory load instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_ST_MULTI_RETIRED                 0x0261             /*!< MVE memory store instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_ST_MULTI_SPEC                    0x0265             /*!< MVE memory store instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED           0x028C             /*!< MVE unaligned memory load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC              0x028D             /*!< MVE unaligned memory load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED             0x0290             /*!< MVE unaligned load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_SPEC                0x0291             /*!< MVE unaligned load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED             0x0294             /*!< MVE unaligned store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_SPEC                0x0295             /*!< MVE unaligned store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298             /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC    0x0299             /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_RETIRED                  0x02A0             /*!< MVE vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_SPEC                     0x02A1             /*!< MVE vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_FP_RETIRED               0x02A4             /*!< MVE floating-point vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_FP_SPEC                  0x02A5             /*!< MVE floating-point vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_INT_RETIRED              0x02A8             /*!< MVE integer vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_INT_SPEC                 0x02A9             /*!< MVE integer vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_PRED                             0x02B8             /*!< Cycles where one or more predicated beats architecturally executed */
+#define ARM_PMU_MVE_STALL                            0x02CC             /*!< Stall cycles caused by an MVE instruction */
+#define ARM_PMU_MVE_STALL_RESOURCE                   0x02CD             /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_MEM               0x02CE             /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_FP                0x02CF             /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_INT               0x02D0             /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
+#define ARM_PMU_MVE_STALL_BREAK                      0x02D3             /*!< Stall cycles caused by an MVE chain break */
+#define ARM_PMU_MVE_STALL_DEPENDENCY                 0x02D4             /*!< Stall cycles caused by MVE register dependency */
+#define ARM_PMU_ITCM_ACCESS                          0x4007             /*!< Instruction TCM access */
+#define ARM_PMU_DTCM_ACCESS                          0x4008             /*!< Data TCM access */
+#define ARM_PMU_TRCEXTOUT0                           0x4010             /*!< ETM external output 0 */
+#define ARM_PMU_TRCEXTOUT1                           0x4011             /*!< ETM external output 1 */
+#define ARM_PMU_TRCEXTOUT2                           0x4012             /*!< ETM external output 2 */
+#define ARM_PMU_TRCEXTOUT3                           0x4013             /*!< ETM external output 3 */
+#define ARM_PMU_CTI_TRIGOUT4                         0x4018             /*!< Cross-trigger Interface output trigger 4 */
+#define ARM_PMU_CTI_TRIGOUT5                         0x4019             /*!< Cross-trigger Interface output trigger 5 */
+#define ARM_PMU_CTI_TRIGOUT6                         0x401A             /*!< Cross-trigger Interface output trigger 6 */
+#define ARM_PMU_CTI_TRIGOUT7                         0x401B             /*!< Cross-trigger Interface output trigger 7 */
+
+/** \brief PMU Functions */
+
+__STATIC_INLINE void ARM_PMU_Enable(void);
+__STATIC_INLINE void ARM_PMU_Disable(void);
+
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
+
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
+
+/** 
+  \brief   Enable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Enable(void) 
+{
+  PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
+}
+
+/** 
+  \brief   Disable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Disable(void) 
+{
+  PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
+}
+
+/** 
+  \brief   Set event to count for PMU eventer counter
+  \param [in]    num     Event counter (0-30) to configure
+  \param [in]    type    Event to count
+*/
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
+{
+  PMU->EVTYPER[num] = type;
+}
+
+/** 
+  \brief  Reset cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
+{
+  PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
+}
+
+/** 
+  \brief  Reset all event counters
+*/
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
+{
+  PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
+}
+
+/** 
+  \brief  Enable counters 
+  \param [in]     mask    Counters to enable
+  \note   Enables one or more of the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
+{
+  PMU->CNTENSET = mask;
+}
+
+/** 
+  \brief  Disable counters
+  \param [in]     mask    Counters to enable
+  \note   Disables one or more of the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
+{
+  PMU->CNTENCLR = mask;
+}
+
+/** 
+  \brief  Read cycle counter
+  \return                 Cycle count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
+{
+  return PMU->CCNTR;
+}
+
+/** 
+  \brief   Read event counter
+  \param [in]     num     Event counter (0-30) to read
+  \return                 Event count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
+{
+  return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
+}
+
+/** 
+  \brief   Read counter overflow status
+  \return  Counter overflow status bits for the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
+{
+  return PMU->OVSSET;	
+}
+
+/** 
+  \brief   Clear counter overflow status
+  \param [in]     mask    Counter overflow status bits to clear
+  \note    Clears overflow status bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
+{
+  PMU->OVSCLR = mask;
+}
+
+/** 
+  \brief   Enable counter overflow interrupt request 
+  \param [in]     mask    Counter overflow interrupt request bits to set
+  \note    Sets overflow interrupt request bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
+{
+  PMU->INTENSET = mask;
+}
+
+/** 
+  \brief   Disable counter overflow interrupt request 
+  \param [in]     mask    Counter overflow interrupt request bits to clear
+  \note    Clears overflow interrupt request bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
+{
+  PMU->INTENCLR = mask;
+}
+
+/** 
+  \brief   Software increment event counter 
+  \param [in]     mask    Counters to increment
+  \note    Software increment bits for one or more event counters (0-30)
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
+{
+  PMU->SWINC = mask;
+}
+
+#endif

external/CMSIS_5/CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/main_s.c

@@ -0,0 +1,58 @@
+/******************************************************************************
+ * @file     main_s.c
+ * @brief    Code template for secure main function
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Use CMSE intrinsics */
+#include <arm_cmse.h>
+ 
+#include "RTE_Components.h"
+#include CMSIS_device_header
+ 
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x200000U)
+#endif
+ 
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+ 
+/* Secure main() */
+int main(void) {
+  funcptr_void NonSecure_ResetHandler;
+ 
+  /* Add user setup code for secure part here*/
+ 
+  /* Set non-secure main stack (MSP_NS) */
+  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+ 
+  /* Get non-secure reset handler */
+  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+ 
+  /* Start non-secure state software application */
+  NonSecure_ResetHandler();
+ 
+  /* Non-secure software does not return, this code is not executed */
+  while (1) {
+    __NOP();
+  }
+}

external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/tz_context.c

@@ -0,0 +1,200 @@
+/******************************************************************************
+ * @file     tz_context.c
+ * @brief    Context Management for Armv8-M TrustZone - Sample implementation
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS     8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE      256U
+#endif
+
+typedef struct {
+  uint32_t sp_top;      // stack space top
+  uint32_t sp_limit;    // stack space limit
+  uint32_t sp;          // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];
+static uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+  uint32_t n;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+    ProcessStackInfo[n].sp = 0U;
+    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+  }
+  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+  ProcessStackFreeSlot = 0U;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  // Privileged Thread Mode using PSP
+  __set_CONTROL(0x02U);
+
+  return 1U;    // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+  uint32_t slot;
+
+  (void)module; // Ignore (fixed Stack size)
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+    return 0U;  // No slot available
+  }
+
+  slot = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+  return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+  ProcessStackInfo[slot].sp = 0U;
+
+  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = slot;
+
+  return 1U;    // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  // Setup process stack pointer and stack limit
+  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+  __set_PSP   (ProcessStackInfo[slot].sp);
+
+  return 1U;    // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+  uint32_t sp;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  sp = __get_PSP();
+  if ((sp < ProcessStackInfo[slot].sp_limit) ||
+      (sp > ProcessStackInfo[slot].sp_top)) {
+    return 0U;  // SP out of range
+  }
+  ProcessStackInfo[slot].sp = sp;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  return 1U;    // Success
+}

external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Framework.h

@@ -0,0 +1,44 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Framework.h 
+ *      Purpose:      Framework header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __FRAMEWORK_H__
+#define __FRAMEWORK_H__
+
+#include "CV_Typedefs.h"
+#include "CV_Report.h"
+
+/*-----------------------------------------------------------------------------
+ * Test framework global definitions
+ *----------------------------------------------------------------------------*/
+
+/* Test case definition macro                                                 */
+#define TCD(x, y) {x, #x, y}
+
+/* Test case description structure                                            */
+typedef struct __TestCase {
+  void (*TestFunc)(void);             /* Test function                        */
+  const char *TFName;                 /* Test function name string            */
+  BOOL en;                            /* Test function enabled                */
+} TEST_CASE;
+
+/* Test suite description structure                                           */
+typedef struct __TestSuite {
+  const char *FileName;               /* Test module file name                */
+  const char *Date;                   /* Compilation date                     */
+  const char *Time;                   /* Compilation time                     */
+  const char *ReportTitle;            /* Title or name of module under test   */
+  void (*Init)(void);                 /* Init function callback               */
+  
+  uint32_t TCBaseNum;                 /* Base number for test case numbering  */
+  TEST_CASE *TC;                      /* Array of test cases                  */
+  uint32_t NumOfTC;                   /* Number of test cases (sz of TC array)*/
+
+} TEST_SUITE;
+
+/* Defined in user test module                                                */
+extern TEST_SUITE ts;
+
+#endif /* __FRAMEWORK_H__ */

external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Report.h

@@ -0,0 +1,89 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Report.h 
+ *      Purpose:      Report statistics and layout header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __REPORT_H__
+#define __REPORT_H__
+
+#include "CV_Config.h"
+#include "CV_Typedefs.h"
+
+/*-----------------------------------------------------------------------------
+ * Test report global definitions
+ *----------------------------------------------------------------------------*/
+ 
+#define REP_TC_FAIL 0
+#define REP_TC_WARN 1
+#define REP_TC_PASS 2
+#define REP_TC_NOEX 3
+
+/* Test case result definition */
+typedef enum {
+  PASSED = 0,
+  WARNING,
+  FAILED,
+  NOT_EXECUTED
+} TC_RES;
+
+/* Assertion result info */
+typedef struct {
+  const char    *module;                  /* Module name                        */
+  uint32_t       line;                    /* Assertion line                     */
+} AS_INFO;
+
+/* Test case callback interface definition */
+typedef struct {
+  BOOL (* Result) (TC_RES res);
+  BOOL (* Dbgi)   (TC_RES res, const char *fn, uint32_t ln, char *desc);
+} TC_ITF;
+
+/* Assert interface to the report */
+extern TC_ITF tcitf;
+
+/* Assertion result buffer */
+typedef struct {
+AS_INFO passed[BUFFER_ASSERTIONS];  
+AS_INFO failed[BUFFER_ASSERTIONS];  
+AS_INFO warnings[BUFFER_ASSERTIONS];  
+} AS_T_INFO;
+
+/* Assertion statistics */
+typedef struct {
+  uint32_t passed;           /* Total assertions passed                  */
+  uint32_t failed;           /* Total assertions failed                  */
+  uint32_t warnings;         /* Total assertions warnings                */
+  AS_T_INFO info;            /* Detailed assertion info                  */
+} AS_STAT;
+
+/* Test global statistics */
+typedef struct {
+  uint32_t  tests;           /* Total test cases count                   */
+  uint32_t  executed;        /* Total test cases executed                */
+  uint32_t  passed;          /* Total test cases passed                  */
+  uint32_t  failed;          /* Total test cases failed                  */
+  uint32_t  warnings;        /* Total test cases warnings                */
+  AS_STAT   assertions;      /* Total assertions statistics              */
+} TEST_REPORT;
+
+/* Test report interface */
+typedef struct {
+  BOOL (* Init)     (void);
+  BOOL (* Open)     (const char *title, const char *date, const char *time, const char *fn);
+  BOOL (* Close)    (void);  
+  BOOL (* Open_TC)  (uint32_t num, const char *fn);
+  BOOL (* Close_TC) (void);
+} REPORT_ITF;
+
+/* Test report statistics */
+extern TEST_REPORT  test_report;
+
+/* Test report interface */
+extern REPORT_ITF   ritf;
+
+/* Assertions and test results */
+extern TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc);
+extern TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond);
+
+#endif /* __REPORT_H__ */

external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Typedefs.h

@@ -0,0 +1,58 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Typedefs.h
+ *      Purpose:      Test framework filetypes and structures description
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+#include <stdint.h>
+#include <stdarg.h>
+#include <string.h>
+#include <stdio.h>
+
+typedef unsigned int    BOOL;
+
+#ifndef __TRUE
+ #define __TRUE         1
+#endif
+#ifndef __FALSE
+ #define __FALSE        0
+#endif
+
+#ifndef ENABLED
+ #define ENABLED        1
+#endif
+#ifndef DISABLED
+ #define DISABLED       0
+#endif
+
+#ifndef NULL
+ #ifdef __cplusplus              // EC++
+  #define NULL          0
+ #else
+  #define NULL          ((void *) 0)
+ #endif
+#endif
+
+#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0]))
+
+#if defined( __GNUC__ ) || defined ( __clang__ )
+static const int PATH_DELIMITER = '/';
+#else
+static const int PATH_DELIMITER = '\\';
+#endif
+
+//lint -emacro(9016,__FILENAME__) allow pointer arithmetic for truncating filename
+//lint -emacro(613,__FILENAME__) null pointer is checked
+#define __FILENAME__ ((strrchr(__FILE__, PATH_DELIMITER) != NULL) ? (strrchr(__FILE__, PATH_DELIMITER) + 1) : __FILE__)
+
+/* Assertions and test results */
+#define SET_RESULT(res, desc) (void)__set_result(__FILENAME__, __LINE__, (res), (desc));
+
+//lint -emacro(9031,ASSERT_TRUE) allow boolean condition as parameter
+//lint -emacro(613,ASSERT_TRUE) null pointer is checked
+#define ASSERT_TRUE(cond) (void)__assert_true (__FILENAME__, __LINE__, (cond) ? 1U : 0U)
+
+#endif /* __TYPEDEFS_H__ */

external/CMSIS_5/CMSIS/CoreValidation/Include/cmsis_cv.h

@@ -0,0 +1,135 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         cmsis_cv.h
+ *      Purpose:      cmsis_cv header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 - 2021 Arm Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CMSIS_CV_H
+#define __CMSIS_CV_H
+
+#include <stdint.h>
+#include "CV_Config.h"
+
+/* Expansion macro used to create CMSIS Driver references */
+#define EXPAND_SYMBOL(name, port) name##port
+#define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
+
+// Simulator counter
+#ifndef HW_PRESENT
+extern uint32_t SIM_CYCCNT;
+#endif
+
+// SVC interrupt callback
+extern void (*TST_IRQHandler)(void);
+
+// Test main function
+extern void cmsis_cv (void);
+extern void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc);
+
+// Test cases
+extern void TC_CoreInstr_NOP (void);
+extern void TC_CoreInstr_SEV (void);
+extern void TC_CoreInstr_BKPT (void);
+extern void TC_CoreInstr_ISB (void);
+extern void TC_CoreInstr_DSB (void);
+extern void TC_CoreInstr_DMB (void);
+extern void TC_CoreInstr_WFI (void);
+extern void TC_CoreInstr_WFE (void);
+extern void TC_CoreInstr_REV (void);
+extern void TC_CoreInstr_REV16 (void);
+extern void TC_CoreInstr_REVSH (void);
+extern void TC_CoreInstr_ROR (void);
+extern void TC_CoreInstr_RBIT (void);
+extern void TC_CoreInstr_CLZ (void);
+extern void TC_CoreInstr_SSAT (void);
+extern void TC_CoreInstr_USAT (void);
+extern void TC_CoreInstr_RRX (void);
+extern void TC_CoreInstr_LoadStoreExclusive (void);
+extern void TC_CoreInstr_LoadStoreUnpriv (void);
+extern void TC_CoreInstr_LoadStoreAcquire (void);
+extern void TC_CoreInstr_LoadStoreAcquireExclusive (void);
+extern void TC_CoreInstr_UnalignedUint16 (void);
+extern void TC_CoreInstr_UnalignedUint32 (void);
+
+extern void TC_CoreSimd_SatAddSub (void);
+extern void TC_CoreSimd_ParSat16 (void);
+extern void TC_CoreSimd_PackUnpack (void);
+extern void TC_CoreSimd_ParSel (void);
+extern void TC_CoreSimd_ParAddSub8 (void);
+extern void TC_CoreSimd_AbsDif8 (void);
+extern void TC_CoreSimd_ParAddSub16 (void);
+extern void TC_CoreSimd_ParMul16 (void);
+extern void TC_CoreSimd_Pack16 (void);
+extern void TC_CoreSimd_MulAcc32 (void);
+
+#if defined(__CORTEX_M)
+  extern void TC_CoreFunc_EnDisIRQ (void);
+  extern void TC_CoreFunc_IRQPrio (void);
+  extern void TC_CoreFunc_EncDecIRQPrio (void);
+  extern void TC_CoreFunc_IRQVect (void);
+  extern void TC_CoreFunc_Control (void);
+  extern void TC_CoreFunc_IPSR (void);
+  extern void TC_CoreFunc_APSR (void);
+  extern void TC_CoreFunc_PSP (void);
+  extern void TC_CoreFunc_MSP (void);
+  extern void TC_CoreFunc_PSPLIM (void);
+  extern void TC_CoreFunc_PSPLIM_NS (void);
+  extern void TC_CoreFunc_MSPLIM (void);
+  extern void TC_CoreFunc_MSPLIM_NS (void);
+  extern void TC_CoreFunc_PRIMASK (void);
+  extern void TC_CoreFunc_FAULTMASK (void);
+  extern void TC_CoreFunc_BASEPRI (void);
+  extern void TC_CoreFunc_FPUType (void);
+  extern void TC_CoreFunc_FPSCR (void);
+#elif defined(__CORTEX_A)
+  extern void TC_CoreAFunc_IRQ (void);
+  extern void TC_CoreAFunc_FaultIRQ (void);
+  extern void TC_CoreAFunc_FPSCR (void);
+  extern void TC_CoreAFunc_CPSR (void);
+  extern void TC_CoreAFunc_Mode (void);
+  extern void TC_CoreAFunc_SP (void);
+  extern void TC_CoreAFunc_SP_usr (void);
+  extern void TC_CoreAFunc_FPEXC (void);
+  extern void TC_CoreAFunc_ACTLR (void);
+  extern void TC_CoreAFunc_CPACR (void);
+  extern void TC_CoreAFunc_DFSR (void);
+  extern void TC_CoreAFunc_IFSR (void);
+  extern void TC_CoreAFunc_ISR (void);
+  extern void TC_CoreAFunc_CBAR (void);
+  extern void TC_CoreAFunc_TTBR0 (void);
+  extern void TC_CoreAFunc_DACR (void);
+  extern void TC_CoreAFunc_SCTLR (void);
+  extern void TC_CoreAFunc_ACTRL (void);
+  extern void TC_CoreAFunc_MPIDR (void);
+  extern void TC_CoreAFunc_VBAR (void);
+  extern void TC_CoreAFunc_MVBAR (void);
+  extern void TC_CoreAFunc_FPU_Enable (void);
+#endif
+
+#if defined(__CORTEX_M)
+extern void TC_MPU_SetClear (void);
+extern void TC_MPU_Load (void);
+#endif
+
+#if defined(__CORTEX_A)
+extern void TC_GenTimer_CNTFRQ (void);
+extern void TC_GenTimer_CNTP_TVAL (void);
+extern void TC_GenTimer_CNTP_CTL (void);
+extern void TC_GenTimer_CNTPCT(void);
+extern void TC_GenTimer_CNTP_CVAL(void);
+#endif
+
+#if defined(__CORTEX_M)
+extern void TC_CML1Cache_EnDisableICache(void);
+extern void TC_CML1Cache_EnDisableDCache(void);
+extern void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void);
+#elif defined(__CORTEX_A)
+extern void TC_CAL1Cache_EnDisable(void);
+extern void TC_CAL1Cache_EnDisableBTAC(void);
+extern void TC_CAL1Cache_log2_up(void);
+extern void TC_CAL1Cache_InvalidateDCacheAll(void);
+extern void TC_CAL1Cache_CleanDCacheAll(void);
+extern void TC_CAL1Cache_CleanInvalidateDCacheAll(void);
+#endif
+
+#endif /* __CMSIS_CV_H */

external/CMSIS_5/CMSIS/CoreValidation/LICENSE.txt

@@ -0,0 +1,201 @@
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+
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+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.

external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml

@@ -0,0 +1,14 @@
+# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json
+
+layer:
+  # type: App
+  # name: CMSIS-Core_Validation (Bootloader)
+  description: Validation of CMSIS-Core implementation (Bootloader part)
+
+  # packs:
+  #   - pack: ARM::CMSIS
+
+  groups:
+    - group: Source Files
+      files:
+        - file: ./bootloader.c

external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        15. October 2016
+ * $Revision:    1.1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Code template for secure main function
+ *
+ *---------------------------------------------------------------------------*/
+ 
+#include <stdio.h>
+#include <stdlib.h>
+
+/* Use CMSE intrinsics */
+#include <arm_cmse.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+ 
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x200000U)
+#endif
+
+#if 1
+/* Dummy Non-secure callable (entry) function */
+__attribute__((cmse_nonsecure_entry)) int validationDummy(int x) { 
+  return x; 
+}
+#endif
+ 
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+
+/* Secure main() */
+int main(void) {
+  funcptr_void NonSecure_ResetHandler;
+ 
+  /* Add user setup code for secure part here*/
+ 
+  /* Set non-secure main stack (MSP_NS) */
+  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+ 
+  /* Get non-secure reset handler */
+  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+ 
+  /* Start non-secure state software application */
+  NonSecure_ResetHandler();
+ 
+  /* Non-secure software does not return, this code is not executed */
+  while (1) {
+    __NOP();
+  }
+}
+
+#if defined(__CORTEX_M)
+__NO_RETURN
+extern void HardFault_Handler(void);
+void HardFault_Handler(void) {
+  printf("Bootloader HardFault!\n");
+  #ifdef __MICROLIB
+  for(;;) {}
+  #else
+  exit(1);
+  #endif
+}
+#endif

external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/App.clayer.yml

@@ -0,0 +1,48 @@
+# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json
+
+layer:
+  # type: App
+  # name: CMSIS-Core_Validation
+  description: Validation of CMSIS-Core implementation
+
+  # packs:
+  #   - pack: ARM::CMSIS
+
+  define:
+    - PRINT_XML_REPORT: 1
+
+  add-path:
+    - ../../../Include
+    - ../../../Source/ConfigA
+
+  misc:
+    - for-compiler: AC6
+      C-CPP:
+      - -Wno-declaration-after-statement
+      - -Wno-covered-switch-default
+    - for-compiler: GCC
+      C-CPP:
+      - -Wno-declaration-after-statement
+      - -Wno-covered-switch-default
+
+  groups:
+    - group: Documentation
+      files:
+        - file: ../../../README.md
+
+    - group: Source Files
+      files:
+        - file: ./main.c
+
+    - group: CMSIS-Core_Validation
+      files:
+        - file: ../../../Source/cmsis_cv.c
+        - file: ../../../Source/CV_CoreAFunc.c
+        - file: ../../../Source/CV_CoreInstr.c
+        - file: ../../../Source/CV_CAL1Cache.c
+#        - file: ../../../Source/ConfigA/mmu.c
+
+    - group: Validation Framework
+      files:
+        - file: ../../../Source/CV_Framework.c
+        - file: ../../../Source/CV_Report.c

external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/main.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+#include "CV_Report.h"
+
+//lint -e970 allow using int for main
+
+int main (void)
+{
+
+  // System Initialization
+  SystemCoreClockUpdate();
+
+#ifdef RTE_Compiler_EventRecorder
+  // Initialize and start Event Recorder
+  (void)EventRecorderInitialize(EventRecordError, 1U);
+  (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+  cmsis_cv();
+
+  #ifdef __MICROLIB
+  for(;;) {}
+  #else
+  exit(0);
+  #endif
+}
+
+#if defined(__CORTEX_A)
+#include "irq_ctrl.h"
+
+#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
+    (defined ( __GNUC__ ))
+  #define __IRQ __attribute__((interrupt("IRQ")))
+#elif defined ( __CC_ARM )
+  #define __IRQ __irq
+#elif defined ( __ICCARM__ )
+  #define __IRQ __irq __arm
+#else
+  #error "Unsupported compiler!"
+#endif
+
+
+__IRQ
+void IRQ_Handler(void);
+__IRQ
+void IRQ_Handler(void) {
+  const IRQn_ID_t irqn = IRQ_GetActiveIRQ();
+  IRQHandler_t const handler = IRQ_GetHandler(irqn);
+  if (handler != NULL) {
+    __enable_irq();
+    handler();
+    __disable_irq();
+  }
+  IRQ_EndOfInterrupt(irqn);
+}
+
+__IRQ __NO_RETURN
+void Undef_Handler (void);
+__IRQ __NO_RETURN
+void Undef_Handler (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!");
+  exit(0);
+}
+
+__IRQ
+void SVC_Handler   (void);
+__IRQ
+void SVC_Handler   (void) {
+}
+
+__IRQ __NO_RETURN
+void PAbt_Handler  (void);
+__IRQ __NO_RETURN
+void PAbt_Handler  (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!");
+  exit(0);
+}
+
+__IRQ __NO_RETURN
+void DAbt_Handler  (void);
+__IRQ __NO_RETURN
+void DAbt_Handler  (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!");
+  exit(0);
+}
+
+__IRQ
+void FIQ_Handler   (void);
+__IRQ
+void FIQ_Handler   (void) {
+}
+#endif
+
+#if defined(__CORTEX_M)
+__NO_RETURN
+void HardFault_Handler(void);
+__NO_RETURN
+void HardFault_Handler(void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!");
+  #ifdef __MICROLIB
+  for(;;) {}
+  #else
+  exit(0);
+  #endif
+}
+#endif

external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml

@@ -0,0 +1,73 @@
+# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json
+
+layer:
+  # type: App
+  # name: CMSIS-Core_Validation
+  description: Validation of CMSIS-Core implementation
+
+  # packs:
+  #   - pack: ARM::CMSIS
+
+  define:
+    - PRINT_XML_REPORT: 1
+
+  add-path:
+    - ../../../Include
+    - ../../../Source/Config
+
+  misc:
+    - for-compiler: AC6
+      C-CPP:
+      - -Wno-declaration-after-statement
+      - -Wno-covered-switch-default
+    - for-compiler: GCC
+      C-CPP:
+      - -Wno-declaration-after-statement
+      - -Wno-covered-switch-default
+
+  groups:
+    - group: Documentation
+      files:
+        - file: ../../../README.md
+
+    - group: Source Files
+      files:
+        - file: ./main.c
+
+    - group: CMSIS-Core_Validation
+      files:
+        - file: ../../../Source/cmsis_cv.c
+        - file: ../../../Source/CV_CoreFunc.c
+        - file: ../../../Source/CV_CoreInstr.c
+        - file: ../../../Source/CV_CoreSimd.c
+        - file: ../../../Source/CV_CML1Cache.c
+        - file: ../../../Source/CV_MPU_ARMv7.c
+          for-context:
+            - +CM0
+            - +CM0plus
+            - +CM3
+            - +CM4
+            - +CM4FP
+            - +CM7
+            - +CM7SP
+            - +CM7DP
+        - file: ../../../Source/CV_MPU_ARMv8.c
+          for-context:
+            - +CM23
+            - +CM23S
+            - +CM23NS
+            - +CM33
+            - +CM33S
+            - +CM33NS
+            - +CM35P
+            - +CM35PS
+            - +CM35PNS
+            - +CM55S
+            - +CM55NS
+            - +CM85S
+            - +CM85NS
+
+    - group: Validation Framework
+      files:
+        - file: ../../../Source/CV_Framework.c
+        - file: ../../../Source/CV_Report.c

external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/main.c

@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+#include "CV_Report.h"
+
+//lint -e970 allow using int for main
+
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+  #include <arm_cmse.h>
+
+  /* Dummy Non-secure callable (entry) function */
+  __attribute__((cmse_nonsecure_entry)) int validationDummy(int x) {
+    return x;
+  }
+#endif
+
+int main (void)
+{
+
+  // System Initialization
+  SystemCoreClockUpdate();
+
+#ifdef RTE_Compiler_EventRecorder
+  // Initialize and start Event Recorder
+  (void)EventRecorderInitialize(EventRecordError, 1U);
+  (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+  cmsis_cv();
+
+  #ifdef __MICROLIB
+  for(;;) {}
+  #else
+  exit(0);
+  #endif
+}
+
+#if defined(__CORTEX_A)
+#include "irq_ctrl.h"
+
+#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
+    (defined ( __GNUC__ ))
+  #define __IRQ __attribute__((interrupt("IRQ")))
+#elif defined ( __CC_ARM )
+  #define __IRQ __irq
+#elif defined ( __ICCARM__ )
+  #define __IRQ __irq __arm
+#else
+  #error "Unsupported compiler!"
+#endif
+
+
+__IRQ
+void IRQ_Handler(void);
+__IRQ
+void IRQ_Handler(void) {
+  const IRQn_ID_t irqn = IRQ_GetActiveIRQ();
+  IRQHandler_t const handler = IRQ_GetHandler(irqn);
+  if (handler != NULL) {
+    __enable_irq();
+    handler();
+    __disable_irq();
+  }
+  IRQ_EndOfInterrupt(irqn);
+}
+
+__IRQ __NO_RETURN
+void Undef_Handler (void);
+__IRQ __NO_RETURN
+void Undef_Handler (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!");
+  exit(0);
+}
+
+__IRQ
+void SVC_Handler   (void);
+__IRQ
+void SVC_Handler   (void) {
+}
+
+__IRQ __NO_RETURN
+void PAbt_Handler  (void);
+__IRQ __NO_RETURN
+void PAbt_Handler  (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!");
+  exit(0);
+}
+
+__IRQ __NO_RETURN
+void DAbt_Handler  (void);
+__IRQ __NO_RETURN
+void DAbt_Handler  (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!");
+  exit(0);
+}
+
+__IRQ
+void FIQ_Handler   (void);
+__IRQ
+void FIQ_Handler   (void) {
+}
+#endif
+
+#if defined(__CORTEX_M)
+__NO_RETURN
+void HardFault_Handler(void);
+__NO_RETURN
+void HardFault_Handler(void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!");
+  #ifdef __MICROLIB
+  for(;;) {}
+  #else
+  exit(0);
+  #endif
+}
+#endif

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf

@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+define symbol __ICFEDIT_region_TTB_start__   = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x1000;
+define symbol __ICFEDIT_size_irqstack__      = 0x100;
+define symbol __ICFEDIT_size_fiqstack__      = 0x100;
+define symbol __ICFEDIT_size_svcstack__      = 0x100;
+define symbol __ICFEDIT_size_abtstack__      = 0x100;
+define symbol __ICFEDIT_size_undstack__      = 0x100;
+define symbol __ICFEDIT_size_heap__          = 0x8000;
+define symbol __ICFEDIT_size_ttb__           = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];
+
+define block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };
+define block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };
+define block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };
+define block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };
+define block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };
+define block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };
+define block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };
+define block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };
+
+do not initialize  { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region  { readonly };
+place in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region   { block TTB };

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0

@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+define symbol __ICFEDIT_region_TTB_start__   = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x1000;
+define symbol __ICFEDIT_size_irqstack__      = 0x100;
+define symbol __ICFEDIT_size_fiqstack__      = 0x100;
+define symbol __ICFEDIT_size_svcstack__      = 0x100;
+define symbol __ICFEDIT_size_abtstack__      = 0x100;
+define symbol __ICFEDIT_size_undstack__      = 0x100;
+define symbol __ICFEDIT_size_heap__          = 0x8000;
+define symbol __ICFEDIT_size_ttb__           = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];
+
+define block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };
+define block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };
+define block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };
+define block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };
+define block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };
+define block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };
+define block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };
+define block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };
+
+do not initialize  { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region  { readonly };
+place in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region   { block TTB };

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld

@@ -0,0 +1,181 @@
+#include "mem_ARMCA5.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data :
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM AT > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.sct

@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mem_ARMCA5.h

@@ -0,0 +1,100 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00005000
+
+#endif /* __MEM_ARMCA5_H */

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c

@@ -0,0 +1,232 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA5.c
+ * @brief    MMU Configuration for ARM Cortex-A5 Device Series
+ * @version  V1.2.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xfffff000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xfff00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |          Stack           |                Normal
+           |--------------------------|             ------------
+           |          Heap            |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2c002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2c000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA5.h"
+#include "mem_ARMCA5.h"
+
+// TTB base address
+#define TTB_BASE ((uint32_t*)__TTB_BASE)
+
+// L2 table pointers
+//----------------------------------------
+#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core
+                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
+                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
+
+#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC     0xFFFFF000
+#define F_SYNC_BASE   0xFFF00000  //1M aligned
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
+
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Define Image
+    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
+    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections
+
+    //--------------------- PERIPHERALS -------------------
+    MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR
+    MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR
+    MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM
+    MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM
+    MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+    MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE      , 16, Sect_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define private address space entry.
+    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+    // Define L2CC entry.  Uncomment if PL310 is present
+    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define synchronization space entry.
+    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x1  (Inner WB WA)
+    ; 5     - NOS     0x0  (Non-shared)
+    ; 4:3   - RGN     0x01 (Outer WB WA)
+    ; 2     - IMP     0x0  (Implementation Defined)
+    ; 1     - S       0x0  (Non-shared)
+    ; 0     - IRGN[1] 0x0  (Inner WB WA) */
+    __set_TTBR0(__TTB_BASE | 0x48);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c

@@ -0,0 +1,148 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.0.1
+ * @date     10. January 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors        (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler  (void) __attribute__ ((naked));
+void Default_Handler(void) __attribute__ ((noreturn));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+#elif defined ( __GNUC__ )
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+#else
+  #error Unknown compiler.
+#endif
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  "BL     __main                                   \n"
+#elif defined ( __GNUC__ )
+  "BL     _start                                   \n"
+#else
+  #error Unknown compiler.
+#endif
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1

@@ -0,0 +1,136 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.0.1
+ * @date     10. January 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors        (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler  (void) __attribute__ ((naked));
+void Default_Handler(void) __attribute__ ((noreturn));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s

@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file     startup_ARMCA9.s
+ * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+  MODULE  ?startup_ARMCA5
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+  PUBLIC  Reset_Handler
+  PUBWEAK Undef_Handler
+  PUBWEAK SVC_Handler
+  PUBWEAK PAbt_Handler
+  PUBWEAK DAbt_Handler
+  PUBWEAK IRQ_Handler
+  PUBWEAK FIQ_Handler
+
+  SECTION SVC_STACK:DATA:NOROOT(3)
+  SECTION IRQ_STACK:DATA:NOROOT(3)
+  SECTION FIQ_STACK:DATA:NOROOT(3)
+  SECTION ABT_STACK:DATA:NOROOT(3)
+  SECTION UND_STACK:DATA:NOROOT(3)
+  SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+  section RESET:CODE:NOROOT(2)
+  PUBLIC  Vectors
+
+Vectors:  
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+
+
+  section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+  *----------------------------------------------------------------------------*/
+  EXTERN  SystemInit
+  EXTERN  __iar_program_start
+
+Reset_Handler:  
+
+  // Mask interrupts
+  CPSID   if
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5
+  ANDS    R0, R0, #3
+goToSleep:
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exception mode
+  CPS    #0x11
+  LDR    SP, =SFE(FIQ_STACK)
+  CPS    #0x12
+  LDR    SP, =SFE(IRQ_STACK)
+  CPS    #0x13
+  LDR    SP, =SFE(SVC_STACK)
+  CPS    #0x17
+  LDR    SP, =SFE(ABT_STACK)
+  CPS    #0x1B
+  LDR    SP, =SFE(UND_STACK)
+  CPS    #0x1F
+  LDR    SP, =SFE(USR_STACK)
+
+  // Call SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __iar_program_start
+  BL     __iar_program_start
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+  B .
+
+  END

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0

@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file     startup_ARMCA9.s
+ * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+  MODULE  ?startup_ARMCA5
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+  PUBLIC  Reset_Handler
+  PUBWEAK Undef_Handler
+  PUBWEAK SVC_Handler
+  PUBWEAK PAbt_Handler
+  PUBWEAK DAbt_Handler
+  PUBWEAK IRQ_Handler
+  PUBWEAK FIQ_Handler
+
+  SECTION SVC_STACK:DATA:NOROOT(3)
+  SECTION IRQ_STACK:DATA:NOROOT(3)
+  SECTION FIQ_STACK:DATA:NOROOT(3)
+  SECTION ABT_STACK:DATA:NOROOT(3)
+  SECTION UND_STACK:DATA:NOROOT(3)
+  SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+  section RESET:CODE:NOROOT(2)
+  PUBLIC  Vectors
+
+Vectors:  
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+
+
+  section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+  *----------------------------------------------------------------------------*/
+  EXTERN  SystemInit
+  EXTERN  __iar_program_start
+
+Reset_Handler:  
+
+  // Mask interrupts
+  CPSID   if
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5
+  ANDS    R0, R0, #3
+goToSleep:
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exception mode
+  CPS    #0x11
+  LDR    SP, =SFE(FIQ_STACK)
+  CPS    #0x12
+  LDR    SP, =SFE(IRQ_STACK)
+  CPS    #0x13
+  LDR    SP, =SFE(SVC_STACK)
+  CPS    #0x17
+  LDR    SP, =SFE(ABT_STACK)
+  CPS    #0x1B
+  LDR    SP, =SFE(UND_STACK)
+  CPS    #0x1F
+  LDR    SP, =SFE(USR_STACK)
+
+  // Call SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __iar_program_start
+  BL     __iar_program_start
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+  B .
+
+  END

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.0.1
+ * @date     13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.0.1
+ * @date     13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml

@@ -0,0 +1,23 @@
+# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json
+
+layer:
+  # type: Target
+  description: Target setup
+
+  # packs:
+  #   - pack: ARM::CMSIS
+
+  components:
+    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
+    - component: ARM::CMSIS:CORE
+    - component: Device:Startup
+    - component: Device:IRQ Controller:GIC
+
+  misc:
+    - for-compiler: IAR
+      Link: [--config generic_cortex.icf]
+
+  groups:
+    - group: VHT/FVP
+      files:
+        - file: ./model_config.txt

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/model_config.txt

@@ -0,0 +1,21 @@
+# Parameters:
+# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+motherboard.vis.disable_visualisation=1               # (bool  , init-time) default = '0'      : Enable/disable visualisation
+cluster.cpu0.vfp-present=1                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support 
+cluster.cpu0.ase-present=0                            # (bool  , init-time) default = '1'      : Set whether model has NEON support
+cluster.cpu0.semihosting-enable=1                     # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
+cluster.cpu0.semihosting-hlt-enable=0                 # (bool  , init-time) default = '0'      : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
+cluster.cpu0.semihosting-ARM_SVC=0x123456             # (int   , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]
+cluster.cpu0.semihosting-Thumb_SVC=0xAB               # (int   , init-time) default = '0xAB'   : Thumb SVC number for semihosting : [0x0..0xFF]
+cluster.cpu0.semihosting-ARM_HLT=0xF000               # (int   , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]
+cluster.cpu0.semihosting-Thumb_HLT=0x3C               # (int   , init-time) default = '0x3C'   : Thumb HLT number for semihosting : [0x0..0x3F]
+cluster.cpu0.semihosting-cmd_line=""                  # (string, init-time) default = ''       : Command line available to semihosting SVC calls
+cluster.cpu0.semihosting-heap_base=0x0                # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-heap_limit=0x0               # (int   , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-stack_base=0x0               # (int   , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-stack_limit=0x0              # (int   , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-cwd=""                       # (string, init-time) default = ''       : Base directory for semihosting file access.
+cluster.dcache-state_modelled=1                       # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation
+cluster.icache-state_modelled=1                       # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation
+#----------------------------------------------------------------------------------------------

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf

@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+define symbol __ICFEDIT_region_TTB_start__   = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x1000;
+define symbol __ICFEDIT_size_irqstack__      = 0x100;
+define symbol __ICFEDIT_size_fiqstack__      = 0x100;
+define symbol __ICFEDIT_size_svcstack__      = 0x100;
+define symbol __ICFEDIT_size_abtstack__      = 0x100;
+define symbol __ICFEDIT_size_undstack__      = 0x100;
+define symbol __ICFEDIT_size_heap__          = 0x8000;
+define symbol __ICFEDIT_size_ttb__           = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];
+
+define block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };
+define block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };
+define block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };
+define block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };
+define block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };
+define block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };
+define block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };
+define block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };
+
+do not initialize  { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region  { readonly };
+place in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region   { block TTB };

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0

@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+define symbol __ICFEDIT_region_TTB_start__   = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x1000;
+define symbol __ICFEDIT_size_irqstack__      = 0x100;
+define symbol __ICFEDIT_size_fiqstack__      = 0x100;
+define symbol __ICFEDIT_size_svcstack__      = 0x100;
+define symbol __ICFEDIT_size_abtstack__      = 0x100;
+define symbol __ICFEDIT_size_undstack__      = 0x100;
+define symbol __ICFEDIT_size_heap__          = 0x8000;
+define symbol __ICFEDIT_size_ttb__           = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];
+
+define block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };
+define block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };
+define block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };
+define block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };
+define block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };
+define block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };
+define block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };
+define block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };
+
+do not initialize  { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region  { readonly };
+place in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region   { block TTB };

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.ld

@@ -0,0 +1,181 @@
+#include "mem_ARMCA7.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data :
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM AT > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.sct

@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA7.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mem_ARMCA7.h

@@ -0,0 +1,100 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA7.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA7_H
+#define __MEM_ARMCA7_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00005000
+
+#endif /* __MEM_ARMCA7_H */

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c

@@ -0,0 +1,232 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA7.c
+ * @brief    MMU Configuration for Arm Cortex-A7 Device Series
+ * @version  V1.2.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xfffff000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xfff00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |          Stack           |                Normal
+           |--------------------------|             ------------
+           |          Heap            |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2c002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2c000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA7.h"
+#include "mem_ARMCA7.h"
+
+// TTB base address
+#define TTB_BASE ((uint32_t*)__TTB_BASE)
+
+// L2 table pointers
+//----------------------------------------
+#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core
+                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
+                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
+
+#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC     0xFFFFF000
+#define F_SYNC_BASE   0xFFF00000  //1M aligned
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
+
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Define Image
+    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
+    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections
+
+    //--------------------- PERIPHERALS -------------------
+    MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR
+    MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR
+    MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM
+    MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM
+    MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+    MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE      , 16, Sect_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define private address space entry.
+    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+    // Define L2CC entry.  Uncomment if PL310 is present
+    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define synchronization space entry.
+    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x1  (Inner WB WA)
+    ; 5     - NOS     0x0  (Non-shared)
+    ; 4:3   - RGN     0x01 (Outer WB WA)
+    ; 2     - IMP     0x0  (Implementation Defined)
+    ; 1     - S       0x0  (Non-shared)
+    ; 0     - IRGN[1] 0x0  (Inner WB WA) */
+    __set_TTBR0(__TTB_BASE | 0x48);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c

@@ -0,0 +1,148 @@
+/******************************************************************************
+ * @file     startup_ARMCA7.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series
+ * @version  V1.0.1
+ * @date     10. January 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors        (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler  (void) __attribute__ ((naked));
+void Default_Handler(void) __attribute__ ((noreturn));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+#elif defined ( __GNUC__ )
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+#else
+  #error Unknown compiler.
+#endif
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  "BL     __main                                   \n"
+#elif defined ( __GNUC__ )
+  "BL     _start                                   \n"
+#else
+  #error Unknown compiler.
+#endif
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1

@@ -0,0 +1,136 @@
+/******************************************************************************
+ * @file     startup_ARMCA7.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series
+ * @version  V1.0.1
+ * @date     10. January 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors        (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler  (void) __attribute__ ((naked));
+void Default_Handler(void) __attribute__ ((noreturn));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s

@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file     startup_ARMCA7.s
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+  MODULE  ?startup_ARMCA7
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+  PUBLIC  Reset_Handler
+  PUBWEAK Undef_Handler
+  PUBWEAK SVC_Handler
+  PUBWEAK PAbt_Handler
+  PUBWEAK DAbt_Handler
+  PUBWEAK IRQ_Handler
+  PUBWEAK FIQ_Handler
+
+  SECTION SVC_STACK:DATA:NOROOT(3)
+  SECTION IRQ_STACK:DATA:NOROOT(3)
+  SECTION FIQ_STACK:DATA:NOROOT(3)
+  SECTION ABT_STACK:DATA:NOROOT(3)
+  SECTION UND_STACK:DATA:NOROOT(3)
+  SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+  section RESET:CODE:NOROOT(2)
+  PUBLIC  Vectors
+
+Vectors:
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+
+
+  section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+  *----------------------------------------------------------------------------*/
+  EXTERN  SystemInit
+  EXTERN  __iar_program_start
+
+Reset_Handler:  
+
+  // Mask interrupts
+  CPSID   if
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5
+  ANDS    R0, R0, #3
+goToSleep:
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exception mode
+  CPS    #0x11
+  LDR    SP, =SFE(FIQ_STACK)
+  CPS    #0x12
+  LDR    SP, =SFE(IRQ_STACK)
+  CPS    #0x13
+  LDR    SP, =SFE(SVC_STACK)
+  CPS    #0x17
+  LDR    SP, =SFE(ABT_STACK)
+  CPS    #0x1B
+  LDR    SP, =SFE(UND_STACK)
+  CPS    #0x1F
+  LDR    SP, =SFE(USR_STACK)
+
+  // Call SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __iar_program_start
+  BL     __iar_program_start
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+  B .
+
+  END

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0

@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file     startup_ARMCA7.s
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+  MODULE  ?startup_ARMCA7
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+  PUBLIC  Reset_Handler
+  PUBWEAK Undef_Handler
+  PUBWEAK SVC_Handler
+  PUBWEAK PAbt_Handler
+  PUBWEAK DAbt_Handler
+  PUBWEAK IRQ_Handler
+  PUBWEAK FIQ_Handler
+
+  SECTION SVC_STACK:DATA:NOROOT(3)
+  SECTION IRQ_STACK:DATA:NOROOT(3)
+  SECTION FIQ_STACK:DATA:NOROOT(3)
+  SECTION ABT_STACK:DATA:NOROOT(3)
+  SECTION UND_STACK:DATA:NOROOT(3)
+  SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+  section RESET:CODE:NOROOT(2)
+  PUBLIC  Vectors
+
+Vectors:
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+
+
+  section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+  *----------------------------------------------------------------------------*/
+  EXTERN  SystemInit
+  EXTERN  __iar_program_start
+
+Reset_Handler:  
+
+  // Mask interrupts
+  CPSID   if
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5
+  ANDS    R0, R0, #3
+goToSleep:
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exception mode
+  CPS    #0x11
+  LDR    SP, =SFE(FIQ_STACK)
+  CPS    #0x12
+  LDR    SP, =SFE(IRQ_STACK)
+  CPS    #0x13
+  LDR    SP, =SFE(SVC_STACK)
+  CPS    #0x17
+  LDR    SP, =SFE(ABT_STACK)
+  CPS    #0x1B
+  LDR    SP, =SFE(UND_STACK)
+  CPS    #0x1F
+  LDR    SP, =SFE(USR_STACK)
+
+  // Call SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __iar_program_start
+  BL     __iar_program_start
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+  B .
+
+  END

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA7.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series
+ * @version  V1.0.1
+ * @date     13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA7.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series
+ * @version  V1.0.1
+ * @date     13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA7.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A7 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA7_H
+#define __SYSTEM_ARMCA7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA7_H */

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA7.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A7 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA7_H
+#define __SYSTEM_ARMCA7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA7_H */

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml

@@ -0,0 +1,23 @@
+# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json
+
+layer:
+  # type: Target
+  description: Target setup
+
+  # packs:
+  #   - pack: ARM::CMSIS
+
+  components:
+    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
+    - component: ARM::CMSIS:CORE
+    - component: Device:Startup
+    - component: Device:IRQ Controller:GIC
+
+  misc:
+    - for-compiler: IAR
+      Link: [--config generic_cortex.icf]
+
+  groups:
+    - group: VHT/FVP
+      files:
+        - file: ./model_config.txt

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/model_config.txt

@@ -0,0 +1,22 @@
+# Parameters:
+# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+motherboard.vis.disable_visualisation=1               # (bool  , init-time) default = '0'      : Enable/disable visualisation
+cluster.cpu0.vfp-present=1                            # (bool  , init-time) default = '1'      : Set whether CT model has been built with VFP support
+cluster.cpu0.ase-present=0                            # (bool  , init-time) default = '1'      : Set whether CT model has been built with NEON support
+cluster.cpu0.semihosting-enable=1                     # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
+cluster.cpu0.semihosting-hlt-enable=0                 # (bool  , init-time) default = '0'      : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
+cluster.cpu0.semihosting-ARM_SVC=0x123456             # (int   , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]
+cluster.cpu0.semihosting-Thumb_SVC=0xAB               # (int   , init-time) default = '0xAB'   : Thumb SVC number for semihosting : [0x0..0xFF]
+cluster.cpu0.semihosting-ARM_HLT=0xF000               # (int   , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]
+cluster.cpu0.semihosting-Thumb_HLT=0x3C               # (int   , init-time) default = '0x3C'   : Thumb HLT number for semihosting : [0x0..0x3F]
+cluster.cpu0.semihosting-cmd_line=""                  # (string, init-time) default = ''       : Command line available to semihosting SVC calls
+cluster.cpu0.semihosting-heap_base=0x0                # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-heap_limit=0x0               # (int   , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-stack_base=0x0               # (int   , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-stack_limit=0x0              # (int   , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
+cluster.cpu0.semihosting-cwd=""                       # (string, init-time) default = ''       : Base directory for semihosting file access.
+cluster.l1_icache-state_modelled=1                    # (bool  , run-time ) default = '0'      : Set whether L1 I-cache has stateful implementation
+cluster.l1_dcache-state_modelled=1                    # (bool  , run-time ) default = '0'      : Set whether L1 D-cache has stateful implementation
+cluster.l2_cache-state_modelled=1                     # (bool  , run-time ) default = '0'      : Set whether L2 cache has stateful implementation
+#----------------------------------------------------------------------------------------------

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf

@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+define symbol __ICFEDIT_region_TTB_start__   = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x1000;
+define symbol __ICFEDIT_size_irqstack__      = 0x100;
+define symbol __ICFEDIT_size_fiqstack__      = 0x100;
+define symbol __ICFEDIT_size_svcstack__      = 0x100;
+define symbol __ICFEDIT_size_abtstack__      = 0x100;
+define symbol __ICFEDIT_size_undstack__      = 0x100;
+define symbol __ICFEDIT_size_heap__          = 0x8000;
+define symbol __ICFEDIT_size_ttb__           = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];
+
+define block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };
+define block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };
+define block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };
+define block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };
+define block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };
+define block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };
+define block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };
+define block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };
+
+do not initialize  { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region  { readonly };
+place in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region   { block TTB };

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0

@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+define symbol __ICFEDIT_region_TTB_start__   = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x1000;
+define symbol __ICFEDIT_size_irqstack__      = 0x100;
+define symbol __ICFEDIT_size_fiqstack__      = 0x100;
+define symbol __ICFEDIT_size_svcstack__      = 0x100;
+define symbol __ICFEDIT_size_abtstack__      = 0x100;
+define symbol __ICFEDIT_size_undstack__      = 0x100;
+define symbol __ICFEDIT_size_heap__          = 0x8000;
+define symbol __ICFEDIT_size_ttb__           = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];
+
+define block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };
+define block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };
+define block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };
+define block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };
+define block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };
+define block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };
+define block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };
+define block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };
+
+do not initialize  { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region  { readonly };
+place in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region   { block TTB };

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.ld

@@ -0,0 +1,181 @@
+#include "mem_ARMCA9.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data :
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM AT > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.sct

@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA9.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mem_ARMCA9.h

@@ -0,0 +1,100 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA9.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA9_H
+#define __MEM_ARMCA9_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00005000
+
+#endif /* __MEM_ARMCA9_H */

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c

@@ -0,0 +1,232 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA9.c
+ * @brief    MMU Configuration for Arm Cortex-A9 Device Series
+ * @version  V1.2.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xfffff000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xfff00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |          Stack           |                Normal
+           |--------------------------|             ------------
+           |          Heap            |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2c002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2c000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA9.h"
+#include "mem_ARMCA9.h"
+
+// TTB base address
+#define TTB_BASE ((uint32_t*)__TTB_BASE)
+
+// L2 table pointers
+//----------------------------------------
+#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core
+                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
+                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
+
+#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC     0xFFFFF000
+#define F_SYNC_BASE   0xFFF00000  //1M aligned
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
+
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Define Image
+    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
+    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections
+
+    //--------------------- PERIPHERALS -------------------
+    MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR
+    MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR
+    MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM
+    MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM
+    MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+    MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE      , 16, Sect_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define private address space entry.
+    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  2,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+    // Define L2CC entry.  Uncomment if PL310 is present
+    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define synchronization space entry.
+    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x1  (Inner WB WA)
+    ; 5     - NOS     0x0  (Non-shared)
+    ; 4:3   - RGN     0x01 (Outer WB WA)
+    ; 2     - IMP     0x0  (Implementation Defined)
+    ; 1     - S       0x0  (Non-shared)
+    ; 0     - IRGN[1] 0x0  (Inner WB WA) */
+    __set_TTBR0(__TTB_BASE | 0x48);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.c

@@ -0,0 +1,148 @@
+/******************************************************************************
+ * @file     startup_ARMCA9.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series
+ * @version  V1.0.1
+ * @date     10. January 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA9.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors        (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler  (void) __attribute__ ((naked));
+void Default_Handler(void) __attribute__ ((noreturn));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+#elif defined ( __GNUC__ )
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+#else
+  #error Unknown compiler.
+#endif
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  "BL     __main                                   \n"
+#elif defined ( __GNUC__ )
+  "BL     _start                                   \n"
+#else
+  #error Unknown compiler.
+#endif
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s

@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file     startup_ARMCA9.s
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+  MODULE  ?startup_ARMCA9
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+  PUBLIC  Reset_Handler
+  PUBWEAK Undef_Handler
+  PUBWEAK SVC_Handler
+  PUBWEAK PAbt_Handler
+  PUBWEAK DAbt_Handler
+  PUBWEAK IRQ_Handler
+  PUBWEAK FIQ_Handler
+
+  SECTION SVC_STACK:DATA:NOROOT(3)
+  SECTION IRQ_STACK:DATA:NOROOT(3)
+  SECTION FIQ_STACK:DATA:NOROOT(3)
+  SECTION ABT_STACK:DATA:NOROOT(3)
+  SECTION UND_STACK:DATA:NOROOT(3)
+  SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+  section RESET:CODE:NOROOT(2)
+  PUBLIC  Vectors
+
+Vectors:
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+
+
+  section .text:CODE:NOROOT(2)
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+  *----------------------------------------------------------------------------*/
+  EXTERN  SystemInit
+  EXTERN  __iar_program_start
+
+Reset_Handler:  
+
+  // Mask interrupts
+  CPSID   if
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5
+  ANDS    R0, R0, #3
+goToSleep:
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exception mode
+  CPS    #0x11
+  LDR    SP, =SFE(FIQ_STACK)
+  CPS    #0x12
+  LDR    SP, =SFE(IRQ_STACK)
+  CPS    #0x13
+  LDR    SP, =SFE(SVC_STACK)
+  CPS    #0x17
+  LDR    SP, =SFE(ABT_STACK)
+  CPS    #0x1B
+  LDR    SP, =SFE(UND_STACK)
+  CPS    #0x1F
+  LDR    SP, =SFE(USR_STACK)
+
+  // Call SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __iar_program_start
+  BL     __iar_program_start
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+  B .
+
+  END

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0

@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file     startup_ARMCA9.s
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+  MODULE  ?startup_ARMCA9
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+  PUBLIC  Reset_Handler
+  PUBWEAK Undef_Handler
+  PUBWEAK SVC_Handler
+  PUBWEAK PAbt_Handler
+  PUBWEAK DAbt_Handler
+  PUBWEAK IRQ_Handler
+  PUBWEAK FIQ_Handler
+
+  SECTION SVC_STACK:DATA:NOROOT(3)
+  SECTION IRQ_STACK:DATA:NOROOT(3)
+  SECTION FIQ_STACK:DATA:NOROOT(3)
+  SECTION ABT_STACK:DATA:NOROOT(3)
+  SECTION UND_STACK:DATA:NOROOT(3)
+  SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+  section RESET:CODE:NOROOT(2)
+  PUBLIC  Vectors
+
+Vectors:
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+
+
+  section .text:CODE:NOROOT(2)
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+  *----------------------------------------------------------------------------*/
+  EXTERN  SystemInit
+  EXTERN  __iar_program_start
+
+Reset_Handler:  
+
+  // Mask interrupts
+  CPSID   if
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5
+  ANDS    R0, R0, #3
+goToSleep:
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exception mode
+  CPS    #0x11
+  LDR    SP, =SFE(FIQ_STACK)
+  CPS    #0x12
+  LDR    SP, =SFE(IRQ_STACK)
+  CPS    #0x13
+  LDR    SP, =SFE(SVC_STACK)
+  CPS    #0x17
+  LDR    SP, =SFE(ABT_STACK)
+  CPS    #0x1B
+  LDR    SP, =SFE(UND_STACK)
+  CPS    #0x1F
+  LDR    SP, =SFE(USR_STACK)
+
+  // Call SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __iar_program_start
+  BL     __iar_program_start
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+  B .
+
+  END

external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.c

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA9.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series
+ * @version  V1.0.1
+ * @date     13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}