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external/CMSIS_5/CMSIS/DAP/Firmware/Config/DAP_config.h vendored Normal file
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/*
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 16. June 2021
* $Revision: V2.1.0
*
* Project: CMSIS-DAP Configuration
* Title: DAP_config.h CMSIS-DAP Configuration File (Template)
*
*---------------------------------------------------------------------------*/
#ifndef __DAP_CONFIG_H__
#define __DAP_CONFIG_H__
//**************************************************************************************************
/**
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
\ingroup DAP_ConfigIO_gr
@{
Provides definitions about the hardware and configuration of the Debug Unit.
This information includes:
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
- Debug Unit Identification strings (Vendor, Product, Serial Number).
- Debug Unit communication packet size.
- Debug Access Port supported modes and settings (JTAG/SWD and SWO).
- Optional information about a connected Target Device (for Evaluation Boards).
*/
#ifdef _RTE_
#include "RTE_Components.h"
#include CMSIS_device_header
#else
#include "device.h" // Debug Unit Cortex-M Processor Header File
#endif
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
/// This value is used to calculate the SWD/JTAG clock speed.
#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz.
/// Number of processor cycles for I/O Port write operations.
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
/// required.
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
/// Indicate that JTAG communication mode is available at the Debug Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
/// Default communication mode on the Debug Access Port.
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
/// Used to initialize the default SWD/JTAG clock frequency.
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
/// Maximum Package Size for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes.
/// Maximum Package Buffers for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
/// setting can be reduced (valid range is 1 .. 255).
#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered.
/// Indicate that UART Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART SWO.
#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#).
/// Maximum SWO UART Baudrate.
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz.
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
/// SWO Trace Buffer Size.
#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n).
/// SWO Streaming Trace.
#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
#define TIMESTAMP_CLOCK 100000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
/// Indicate that UART Communication Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART Communication Port.
#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#).
/// UART Receive Buffer Size.
#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n).
/// UART Transmit Buffer Size.
#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n).
/// Indicate that UART Communication via USB COM Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available.
/// Debug Unit is connected to fixed Target Device.
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings
/// are stored and may be used by the debugger or IDE to configure device parameters.
#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown;
#define TARGET_DEVICE_VENDOR "Arm" ///< String indicating the Silicon Vendor
#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device
#define TARGET_BOARD_VENDOR "Arm" ///< String indicating the Board Vendor
#define TARGET_BOARD_NAME "Arm board" ///< String indicating the Board Name
#if TARGET_FIXED != 0
#include <string.h>
static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;
static const char TargetDeviceName [] = TARGET_DEVICE_NAME;
static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR;
static const char TargetBoardName [] = TARGET_BOARD_NAME;
#endif
/** Get Vendor Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
(void)str;
return (0U);
}
/** Get Product Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
(void)str;
return (0U);
}
/** Get Serial Number string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
(void)str;
return (0U);
}
/** Get Target Device Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceVendor);
len = (uint8_t)(strlen(TargetDeviceVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Device Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceName);
len = (uint8_t)(strlen(TargetDeviceName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardVendor);
len = (uint8_t)(strlen(TargetBoardVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardName);
len = (uint8_t)(strlen(TargetBoardName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Product Firmware Version string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
(void)str;
return (0U);
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
\ingroup DAP_ConfigIO_gr
@{
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
interface of a device. The following I/O Pins are provided:
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
---------------------------- | -------------------- | ---------------------------------------------
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
TDI: Test Data Input | | Output Push/Pull
TDO: Test Data Output | | Input
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
DAP Hardware I/O Pin Access Functions
-------------------------------------
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
these I/O Pins.
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
peripherals that can independently write/read a single I/O pin without affecting any other pins
of the same I/O port. The following SWDIO I/O Pin functions are provided:
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
*/
// Configure DAP I/O pins ------------------------------
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Configures the DAP Hardware I/O pins for JTAG mode:
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
- TDO to input mode.
*/
__STATIC_INLINE void PORT_JTAG_SETUP (void) {
;
}
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
*/
__STATIC_INLINE void PORT_SWD_SETUP (void) {
;
}
/** Disable JTAG/SWD I/O Pins.
Disables the DAP Hardware I/O pins which configures:
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
*/
__STATIC_INLINE void PORT_OFF (void) {
;
}
// SWCLK/TCK I/O pin -------------------------------------
/** SWCLK/TCK I/O pin: Get Input.
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
return (0U);
}
/** SWCLK/TCK I/O pin: Set Output to High.
Set the SWCLK/TCK DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
;
}
/** SWCLK/TCK I/O pin: Set Output to Low.
Set the SWCLK/TCK DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
;
}
// SWDIO/TMS Pin I/O --------------------------------------
/** SWDIO/TMS I/O pin: Get Input.
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
return (0U);
}
/** SWDIO/TMS I/O pin: Set Output to High.
Set the SWDIO/TMS DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
;
}
/** SWDIO/TMS I/O pin: Set Output to Low.
Set the SWDIO/TMS DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
;
}
/** SWDIO I/O pin: Get Input (used in SWD mode only).
\return Current status of the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
return (0U);
}
/** SWDIO I/O pin: Set Output (used in SWD mode only).
\param bit Output value for the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) {
;
}
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
called prior \ref PIN_SWDIO_OUT function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
;
}
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
called prior \ref PIN_SWDIO_IN function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
;
}
// TDI Pin I/O ---------------------------------------------
/** TDI I/O pin: Get Input.
\return Current status of the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
return (0U);
}
/** TDI I/O pin: Set Output.
\param bit Output value for the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
;
}
// TDO Pin I/O ---------------------------------------------
/** TDO I/O pin: Get Input.
\return Current status of the TDO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
return (0U);
}
// nTRST Pin I/O -------------------------------------------
/** nTRST I/O pin: Get Input.
\return Current status of the nTRST DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
return (0U);
}
/** nTRST I/O pin: Set Output.
\param bit JTAG TRST Test Reset pin status:
- 0: issue a JTAG TRST Test Reset.
- 1: release JTAG TRST Test Reset.
*/
__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
;
}
// nRESET Pin I/O------------------------------------------
/** nRESET I/O pin: Get Input.
\return Current status of the nRESET DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
return (0U);
}
/** nRESET I/O pin: Set Output.
\param bit target device hardware reset pin status:
- 0: issue a device hardware reset.
- 1: release device hardware reset.
*/
__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
;
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
It is recommended to provide the following LEDs for status indication:
- Connect LED: is active when the DAP hardware is connected to a debugger.
- Running LED: is active when the debugger has put the target device into running state.
*/
/** Debug Unit: Set status of Connected LED.
\param bit status of the Connect LED.
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
*/
__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {}
/** Debug Unit: Set status Target Running LED.
\param bit status of the Target Running LED.
- 1: Target Running LED ON: program execution in target started.
- 0: Target Running LED OFF: program execution in target stopped.
*/
__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
\ingroup DAP_ConfigIO_gr
@{
Access function for Test Domain Timer.
The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
*/
/** Get timestamp of Test Domain Timer.
\return Current timestamp value.
*/
__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
return (DWT->CYCCNT);
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
*/
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
- I/O clock system enabled.
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
- for nTRST, nRESET a weak pull-up (if available) is enabled.
- LED output pins are enabled and LEDs are turned off.
*/
__STATIC_INLINE void DAP_SETUP (void) {
;
}
/** Reset Target Device with custom specific I/O pin or command sequence.
This function allows the optional implementation of a device specific reset sequence.
It is called when the command \ref DAP_ResetTarget and is for example required
when a device needs a time-critical unlock sequence that enables the debug port.
\return 0 = no device specific reset sequence is implemented.\n
1 = a device specific reset sequence is implemented.
*/
__STATIC_INLINE uint8_t RESET_TARGET (void) {
return (0U); // change to '1' when a device reset sequence is implemented
}
///@}
#endif /* __DAP_CONFIG_H__ */

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
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<lExt>*.lib</lExt>
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/*
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 16. June 2021
* $Revision: V2.1.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: DAP_config.h CMSIS-DAP Configuration File for LPC-Link2
*
*---------------------------------------------------------------------------*/
#ifndef __DAP_CONFIG_H__
#define __DAP_CONFIG_H__
//**************************************************************************************************
/**
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
\ingroup DAP_ConfigIO_gr
@{
Provides definitions about the hardware and configuration of the Debug Unit.
This information includes:
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
- Debug Unit Identification strings (Vendor, Product, Serial Number).
- Debug Unit communication packet size.
- Debug Access Port supported modes and settings (JTAG/SWD and SWO).
- Optional information about a connected Target Device (for Evaluation Boards).
*/
#ifdef _RTE_
#include "RTE_Components.h"
#include CMSIS_device_header
#else
#include "device.h" // Debug Unit Cortex-M Processor Header File
#endif
#ifdef LPC_LINK2_ONBOARD
#include <string.h>
#include "ser_num.h"
#endif
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
/// This value is used to calculate the SWD/JTAG clock speed.
#define CPU_CLOCK 180000000U ///< Specifies the CPU Clock in Hz.
/// Number of processor cycles for I/O Port write operations.
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
/// required.
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
/// Indicate that JTAG communication mode is available at the Debug Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
/// Default communication mode on the Debug Access Port.
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
/// Used to initialize the default SWD/JTAG clock frequency.
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
/// Maximum Package Size for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes.
/// Maximum Package Buffers for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
/// setting can be reduced (valid range is 1 .. 255).
#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered.
/// Indicate that UART Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART SWO.
#define SWO_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#).
/// Maximum SWO UART Baudrate.
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz.
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
/// SWO Trace Buffer Size.
#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n).
/// SWO Streaming Trace.
#define SWO_STREAM 1 ///< SWO Streaming Trace: 1 = available, 0 = not available.
/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
#define TIMESTAMP_CLOCK 180000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
/// Indicate that UART Communication Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART Communication Port.
#define DAP_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#).
/// UART Receive Buffer Size.
#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n).
/// UART Transmit Buffer Size.
#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n).
/// Indicate that UART Communication via USB COM Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available.
/// Debug Unit is connected to fixed Target Device.
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings
/// are stored and may be used by the debugger or IDE to configure device parameters.
#ifdef LPC_LINK2_ONBOARD
#define TARGET_FIXED 1 ///< Target: 1 = known, 0 = unknown;
#else
#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown;
#endif
#define TARGET_DEVICE_VENDOR "NXP" ///< String indicating the Silicon Vendor
#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device
#define TARGET_BOARD_VENDOR "NXP" ///< String indicating the Board Vendor
#define TARGET_BOARD_NAME "NXP board" ///< String indicating the Board Name
#if TARGET_FIXED != 0
extern const char TargetDeviceVendor [];
extern const char TargetDeviceName [];
extern const char TargetBoardVendor [];
extern const char TargetBoardName [];
#endif
/** Get Vendor Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
(void)str;
return (0U);
}
/** Get Product Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
(void)str;
return (0U);
}
/** Get Serial Number string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
#ifdef LPC_LINK2_ONBOARD
uint8_t len = 0U;
char *ser_num;
ser_num = GetSerialNum();
if (ser_num != NULL) {
strcpy(str, ser_num);
len = (uint8_t)(strlen(ser_num) + 1U);
}
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Device Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceVendor);
len = (uint8_t)(strlen(TargetDeviceVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Device Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceName);
len = (uint8_t)(strlen(TargetDeviceName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardVendor);
len = (uint8_t)(strlen(TargetBoardVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardName);
len = (uint8_t)(strlen(TargetBoardName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Product Firmware Version string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
(void)str;
return (0U);
}
///@}
// LPC43xx peripheral register bit masks (used by macros)
#define CCU_CLK_CFG_RUN (1U << 0)
#define CCU_CLK_CFG_AUTO (1U << 1)
#define CCU_CLK_STAT_RUN (1U << 0)
#define SCU_SFS_EPD (1U << 3)
#define SCU_SFS_EPUN (1U << 4)
#define SCU_SFS_EHS (1U << 5)
#define SCU_SFS_EZI (1U << 6)
#define SCU_SFS_ZIF (1U << 7)
// Debug Port I/O Pins
// SWCLK/TCK Pin P1_17: GPIO0[12]
#define PIN_SWCLK_TCK_PORT 0
#define PIN_SWCLK_TCK_BIT 12
// SWDIO/TMS Pin P1_6: GPIO1[9]
#define PIN_SWDIO_TMS_PORT 1
#define PIN_SWDIO_TMS_BIT 9
// SWDIO Output Enable Pin P1_5: GPIO1[8]
#define PIN_SWDIO_OE_PORT 1
#define PIN_SWDIO_OE_BIT 8
// TDI Pin P1_18: GPIO0[13]
#define PIN_TDI_PORT 0
#define PIN_TDI_BIT 13
// TDO Pin P1_14: GPIO1[7]
#define PIN_TDO_PORT 1
#define PIN_TDO_BIT 7
// nTRST Pin Not available
#define PIN_nTRST_PORT
#define PIN_nTRST_BIT
// nRESET Pin P2_5: GPIO5[5]
#define PIN_nRESET_PORT 5
#define PIN_nRESET_BIT 5
// nRESET Output Enable Pin P2_6: GPIO5[6]
#define PIN_nRESET_OE_PORT 5
#define PIN_nRESET_OE_BIT 6
// Debug Unit LEDs
// Connected LED P1_1: GPIO0[8]
#define LED_CONNECTED_PORT 0
#define LED_CONNECTED_BIT 8
// Target Running LED Not available
//**************************************************************************************************
/**
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
\ingroup DAP_ConfigIO_gr
@{
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
interface of a device. The following I/O Pins are provided:
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
---------------------------- | -------------------- | ---------------------------------------------
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
TDI: Test Data Input | | Output Push/Pull
TDO: Test Data Output | | Input
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
DAP Hardware I/O Pin Access Functions
-------------------------------------
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
these I/O Pins.
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
peripherals that can independently write/read a single I/O pin without affecting any other pins
of the same I/O port. The following SWDIO I/O Pin functions are provided:
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
*/
// Configure DAP I/O pins ------------------------------
// LPC-Link2 HW uses buffers for debug port pins. Therefore it is not
// possible to disable outputs SWCLK/TCK, TDI and they are left active.
// Only SWDIO/TMS output can be disabled but it is also left active.
// nRESET is configured for open drain mode.
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Configures the DAP Hardware I/O pins for JTAG mode:
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
- TDO to input mode.
*/
__STATIC_INLINE void PORT_JTAG_SETUP (void) {
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U;
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT);
}
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
*/
__STATIC_INLINE void PORT_SWD_SETUP (void) {
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U;
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT);
}
/** Disable JTAG/SWD I/O Pins.
Disables the DAP Hardware I/O pins which configures:
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
*/
__STATIC_INLINE void PORT_OFF (void) {
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
}
// SWCLK/TCK I/O pin -------------------------------------
/** SWCLK/TCK I/O pin: Get Input.
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1U);
}
/** SWCLK/TCK I/O pin: Set Output to High.
Set the SWCLK/TCK DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
}
/** SWCLK/TCK I/O pin: Set Output to Low.
Set the SWCLK/TCK DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
LPC_GPIO_PORT->CLR[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
}
// SWDIO/TMS Pin I/O --------------------------------------
/** SWDIO/TMS I/O pin: Get Input.
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1U);
}
/** SWDIO/TMS I/O pin: Set Output to High.
Set the SWDIO/TMS DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
}
/** SWDIO/TMS I/O pin: Set Output to Low.
Set the SWDIO/TMS DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
LPC_GPIO_PORT->CLR[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
}
/** SWDIO I/O pin: Get Input (used in SWD mode only).
\return Current status of the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
return (LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT);
}
/** SWDIO I/O pin: Set Output (used in SWD mode only).
\param bit Output value for the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) {
LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] = bit << PIN_SWDIO_TMS_BIT;
}
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
called prior \ref PIN_SWDIO_OUT function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
}
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
called prior \ref PIN_SWDIO_IN function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
LPC_GPIO_PORT->CLR[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
}
// TDI Pin I/O ---------------------------------------------
/** TDI I/O pin: Get Input.
\return Current status of the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
return ((LPC_GPIO_PORT->PIN [PIN_TDI_PORT] >> PIN_TDI_BIT) & 1U);
}
/** TDI I/O pin: Set Output.
\param bit Output value for the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
LPC_GPIO_PORT->MPIN[PIN_TDI_PORT] = bit << PIN_TDI_BIT;
}
// TDO Pin I/O ---------------------------------------------
/** TDO I/O pin: Get Input.
\return Current status of the TDO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_TDO_PORT] >> PIN_TDO_BIT) & 1U);
}
// nTRST Pin I/O -------------------------------------------
/** nTRST I/O pin: Get Input.
\return Current status of the nTRST DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
return (0U); // Not available
}
/** nTRST I/O pin: Set Output.
\param bit JTAG TRST Test Reset pin status:
- 0: issue a JTAG TRST Test Reset.
- 1: release JTAG TRST Test Reset.
*/
__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
(void) bit;
// Not available
}
// nRESET Pin I/O------------------------------------------
/** nRESET I/O pin: Get Input.
\return Current status of the nRESET DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_nRESET_PORT] >> PIN_nRESET_BIT) & 1U);
}
/** nRESET I/O pin: Set Output.
\param bit target device hardware reset pin status:
- 0: issue a device hardware reset.
- 1: release device hardware reset.
*/
__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
if (bit) {
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
} else {
LPC_GPIO_PORT->SET[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] |= (1U << PIN_nRESET_BIT);
}
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
It is recommended to provide the following LEDs for status indication:
- Connect LED: is active when the DAP hardware is connected to a debugger.
- Running LED: is active when the debugger has put the target device into running state.
*/
/** Debug Unit: Set status of Connected LED.
\param bit status of the Connect LED.
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
*/
__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
LPC_GPIO_PORT->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = (uint8_t)bit;
}
/** Debug Unit: Set status Target Running LED.
\param bit status of the Target Running LED.
- 1: Target Running LED ON: program execution in target started.
- 0: Target Running LED OFF: program execution in target stopped.
*/
__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
(void) bit;
// Not available
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
\ingroup DAP_ConfigIO_gr
@{
Access function for Test Domain Timer.
The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
*/
/** Get timestamp of Test Domain Timer.
\return Current timestamp value.
*/
__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
return (DWT->CYCCNT);
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
*/
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
- I/O clock system enabled.
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
- for nTRST, nRESET a weak pull-up (if available) is enabled.
- LED output pins are enabled and LEDs are turned off.
*/
__STATIC_INLINE void DAP_SETUP (void) {
/* Enable clock and init GPIO outputs */
LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
/* Configure I/O pins: function number, input buffer enabled, */
/* no pull-up/down except nRESET (pull-up) */
LPC_SCU->SFSP1_17 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWCLK/TCK: GPIO0[12] */
LPC_SCU->SFSP1_6 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO/TMS: GPIO1[9] */
LPC_SCU->SFSP1_5 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO_OE: GPIO1[8] */
LPC_SCU->SFSP1_18 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDI: GPIO0[13] */
LPC_SCU->SFSP1_14 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDO: GPIO1[7] */
LPC_SCU->SFSP2_5 = 4U | SCU_SFS_EZI; /* nRESET: GPIO5[5] */
LPC_SCU->SFSP2_6 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* nRESET_OE: GPIO5[6] */
LPC_SCU->SFSP1_1 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* LED: GPIO0[8] */
#ifdef TARGET_POWER_EN
LPC_SCU->SFSP3_1 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* Target Power enable P3_1 GPIO5[8] */
#endif
/* Configure: SWCLK/TCK, SWDIO/TMS, SWDIO_OE, TDI as outputs (high level) */
/* TDO as input */
/* nRESET as input with output latch set to low level */
/* nRESET_OE as output (low level) */
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_PORT] = (1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
LPC_GPIO_PORT->DIR[PIN_SWCLK_TCK_PORT] |= (1U << PIN_SWCLK_TCK_BIT);
LPC_GPIO_PORT->DIR[PIN_SWDIO_TMS_PORT] |= (1U << PIN_SWDIO_TMS_BIT);
LPC_GPIO_PORT->DIR[PIN_SWDIO_OE_PORT] |= (1U << PIN_SWDIO_OE_BIT);
LPC_GPIO_PORT->DIR[PIN_TDI_PORT] |= (1U << PIN_TDI_BIT);
LPC_GPIO_PORT->DIR[PIN_TDO_PORT] &= ~(1U << PIN_TDO_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_OE_PORT] |= (1U << PIN_nRESET_OE_BIT);
#ifdef TARGET_POWER_EN
/* Target Power enable as output (turned on) */
LPC_GPIO_PORT->SET[5] = (1U << 8);
LPC_GPIO_PORT->DIR[5] |= (1U << 8);
#endif
/* Configure: LED as output (turned off) */
LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1U << LED_CONNECTED_BIT);
LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1U << LED_CONNECTED_BIT);
/* Configure Peripheral Interrupt Priorities */
NVIC_SetPriority(USB0_IRQn, 1U);
}
/** Reset Target Device with custom specific I/O pin or command sequence.
This function allows the optional implementation of a device specific reset sequence.
It is called when the command \ref DAP_ResetTarget and is for example required
when a device needs a time-critical unlock sequence that enables the debug port.
\return 0 = no device specific reset sequence is implemented.\n
1 = a device specific reset sequence is implemented.
*/
__STATIC_INLINE uint8_t RESET_TARGET (void) {
return (0U); // change to '1' when a device reset sequence is implemented
}
///@}
#endif /* __DAP_CONFIG_H__ */

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf vendored Normal file
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// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug Setup
// <o> Release M0 On Connect
// <0=> No
// <1=> Yes
// <i> Debugger releases the M0 Application processor from reset when connecting to it.
ReleaseM0OnConnect = 1;
// <o> Release M0 Sub-System On Connect
// <0=> No
// <1=> Yes
// <i> Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only).
ReleaseM0SubOnConnect = 1;
// <o> Vector Reset
// <0=> Processor Only
// <1=> Processor and Peripherals
// <i> Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset
VecResetWithPeriph = 1;
// </h>
// <h> TPIU Pin Routing (TRACECLK fixed on PF_4)
// <i> Configure the TPIU pin routing as used on your target platform.
// <o.1> TRACEDATA0
// <0=> Pin PF_5
// <1=> Pin P7_4
// <o.2> TRACEDATA1
// <0=> Pin PF_6
// <1=> Pin P7_5
// <o.3> TRACEDATA2
// <0=> Pin PF_7
// <1=> Pin P7_6
// <o.4> TRACEDATA3
// <0=> Pin PF_8
// <1=> Pin P7_7
RoutingTPIU = 0x00000000;
// </h>
// <<< end of configuration section >>>

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// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug Setup
// <o> Release M0 On Connect
// <0=> No
// <1=> Yes
// <i> Debugger releases the M0 Application processor from reset when connecting to it.
ReleaseM0OnConnect = 1;
// <o> Release M0 Sub-System On Connect
// <0=> No
// <1=> Yes
// <i> Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only).
ReleaseM0SubOnConnect = 1;
// <o> Vector Reset
// <0=> Processor Only
// <1=> Processor and Peripherals
// <i> Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset
VecResetWithPeriph = 1;
// </h>
// <h> TPIU Pin Routing (TRACECLK fixed on PF_4)
// <i> Configure the TPIU pin routing as used on your target platform.
// <o.1> TRACEDATA0
// <0=> Pin PF_5
// <1=> Pin P7_4
// <o.2> TRACEDATA1
// <0=> Pin PF_6
// <1=> Pin P7_5
// <o.3> TRACEDATA2
// <0=> Pin PF_7
// <1=> Pin P7_6
// <o.4> TRACEDATA3
// <0=> Pin PF_8
// <1=> Pin P7_7
RoutingTPIU = 0x00000000;
// </h>
// <<< end of configuration section >>>

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CMSIS-DAP v2 firmware for NXP LPC-Link2 debug probe.
CMSIS-DAP v2 uses USB bulk endpoints for the communication with the host PC and is therefore faster.
Optionally, support for streaming SWO trace is provided via an additional USB endpoint.
Following targets are available:
- LPC-Link2: stand-alone debug probe
- LPC-Link2 on-board: on-board debug probe (LPC55S69-EVK, MIMXRT1064-EVK, ...)

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
break;
}
for (;;) {}
//return 0U;
}

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/*
* Copyright (c) 2013-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.5.1
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 32
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 512
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <h>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x01U
#endif
// <h>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x01U
#endif
// <h>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x05U
#endif
// <h>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x01U
#endif
// <h>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x01U
#endif
// <h>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x01U
#endif
// <h>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x01U
#endif
// <h>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x01U
#endif
// <h>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x01U
#endif
// <h>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x01U
#endif
// <h>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x01U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

2483
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/RTE_Device.h vendored Normal file
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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/startup_LPC43xx.s vendored Normal file
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;/**************************************************************************//**
; * @file LPC43xx.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * NXP LPC43xxDevice Series
; * @version V1.00
; * @date 03. September 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; * <<< Use Configuration Wizard in Context Menu >>>
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External LPC43xx/M4 Interrupts
DCD DAC_IRQHandler ; 0 DAC interrupt
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
DCD DMA_IRQHandler ; 2 DMA interrupt
DCD 0 ; 3 Reserved
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
DCD LCD_IRQHandler ; 7 LCD interrupt
DCD USB0_IRQHandler ; 8 OTG interrupt
DCD USB1_IRQHandler ; 9 USB1 interrupt
DCD SCT_IRQHandler ; 10 SCT combined interrupt
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
DCD SPI_IRQHandler ; 20 SPI interrupt
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
DCD USART0_IRQHandler ; 24 USART0 interrupt
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
DCD USART2_IRQHandler ; 26 USART2 interrupt
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
DCD 0 ; 44 Reserved
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
DCD RTC_IRQHandler ; 47 RTC interrupt
DCD 0 ; 48 Reserved
DCD WWDT_IRQHandler ; 49 WWDT interrupt
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
DCD QEI_IRQHandler ; 52 QEI interrupt
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0APP_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASHEEPROM_IRQHandler [WEAK]
EXPORT ETHERNET_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RITIMER_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT C_CAN1_IRQHandler [WEAK]
EXPORT ADCHS_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT M0SUB_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0APP_IRQHandler
DMA_IRQHandler
FLASHEEPROM_IRQHandler
ETHERNET_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ADCHS_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
M0SUB_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

938
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/system_LPC43xx.c vendored Normal file
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@ -0,0 +1,938 @@
/* -----------------------------------------------------------------------------
* Copyright (c) 2013 - 2017 ARM Ltd.
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising from
* the use of this software. Permission is granted to anyone to use this
* software for any purpose, including commercial applications, and to alter
* it and redistribute it freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software in
* a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
*
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
*
* 3. This notice may not be removed or altered from any source distribution.
*
* $Date: 10. September 2018
* $Revision: V1.0.3
*
* Project: NXP LPC43xx System initialization
* -------------------------------------------------------------------------- */
#include "LPC43xx.h"
/*----------------------------------------------------------------------------
This file configures the clocks as follows:
-----------------------------------------------------------------------------
Clock Unit | Output clock | Source clock | Note
-----------------------------------------------------------------------------
PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
-----------------------------------------------------------------------------
IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
-----------------------------------------------------------------------------
IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
-----------------------------------------------------------------------------
IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV E | 5.3 MHz | PLL1 | To the LCD controller
-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock source selection definitions (do not change)
*----------------------------------------------------------------------------*/
#define CLK_SRC_32KHZ 0x00
#define CLK_SRC_IRC 0x01
#define CLK_SRC_ENET_RX 0x02
#define CLK_SRC_ENET_TX 0x03
#define CLK_SRC_GP_CLKIN 0x04
#define CLK_SRC_XTAL 0x06
#define CLK_SRC_PLL0U 0x07
#define CLK_SRC_PLL0A 0x08
#define CLK_SRC_PLL1 0x09
#define CLK_SRC_IDIVA 0x0C
#define CLK_SRC_IDIVB 0x0D
#define CLK_SRC_IDIVC 0x0E
#define CLK_SRC_IDIVD 0x0F
#define CLK_SRC_IDIVE 0x10
/*----------------------------------------------------------------------------
Define external input frequency values
*----------------------------------------------------------------------------*/
#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
#define CLK_IRC 12000000UL /* Internal oscillator frequency */
#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
/*----------------------------------------------------------------------------
Define clock sources
*----------------------------------------------------------------------------*/
#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
/*----------------------------------------------------------------------------
Configure integer divider values
*----------------------------------------------------------------------------*/
#define IDIVA_IDIV 2 /* Divide input clock by 3 */
#define IDIVB_IDIV 1 /* Divide input clock by 2 */
#define IDIVC_IDIV 0 /* Divide input clock by 1 */
#define IDIVD_IDIV 0 /* Divide input clock by 1 */
#define IDIVE_IDIV 33 /* Divide input clock by 34 */
/*----------------------------------------------------------------------------
Define CPU clock input
*----------------------------------------------------------------------------*/
#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
/*----------------------------------------------------------------------------
Configure external memory controller options
*----------------------------------------------------------------------------*/
#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
/*----------------------------------------------------------------------------
* Configure PLL1
*----------------------------------------------------------------------------
* Integer mode:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT * 2 * P
*
* Non-integer:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M / (2 * P)
* FCCO = FCLKOUT * 2 * P
*
* Direct mode:
* - PLL1_DIRECT = 1 (Post divider disabled)
* - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT
*
*----------------------------------------------------------------------------
* PLL1 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 1MHz | 50MHz | |
* | FCCO | 156MHz | 320MHz | |
* | FCLKOUT | 9.75MHz | 320MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
* | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
* | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
* | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
* | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
* | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
* | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
* | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
*----------------------------------------------------------------------------
* Relations beetwen PLL dividers and definitions:
* N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
*----------------------------------------------------------------------------*/
/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
/* 1: FCLKOUT is used as PLL feedback */
/*----------------------------------------------------------------------------
* Configure Flash Accelerator
*----------------------------------------------------------------------------
* Flash acces time:
* | CPU clock | FLASHTIM |
* | up to 21MHz | 0 |
* | up to 43MHz | 1 |
* | up to 64MHz | 2 |
* | up to 86MHz | 3 |
* | up to 107MHz | 4 |
* | up to 129MHz | 5 |
* | up to 150MHz | 6 |
* | up to 172MHz | 7 |
* | up to 193MHz | 8 |
* | up to 204MHz | 9 |
*----------------------------------------------------------------------------*/
#define FLASHCFG_FLASHTIM 9
/*----------------------------------------------------------------------------
* Configure PLL0USB
*----------------------------------------------------------------------------
*
* Normal operating mode without post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M
* FCCO = FOUT
*
* Normal operating mode with post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * (M / P)
* FCCO = FOUT * 2 * P
*
* Normal operating mode without post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M / N
* FCCO = FOUT
*
* Normal operating mode with post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * M / (P * N)
* FCCO = FOUT * 2 * P
*----------------------------------------------------------------------------
* PLL0 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 14kHz | 150MHz | |
* | FCCO | 275MHz | 550MHz | |
* | FCLKOUT | 4.3MHz | 550MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
* | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
* | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
*----------------------------------------------------------------------------*/
/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
/*----------------------------------------------------------------------------
End of configuration
*----------------------------------------------------------------------------*/
/* PLL0 Setting Check */
#if (PLL0USB_BYPASS == 0)
#if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
#define PLL0USB_CLKIN CLK_XTAL
#else
#define PLL0USB_CLKIN CLK_IRC
#endif
#if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#else /* Mode 1d */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#endif
#if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
#error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
#endif
#if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
#error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
#endif
#endif
/* PLL1 Setting Check */
#if (PLL1_BYPASS == 0)
#if (PLL1_CLK_SEL == CLK_SRC_XTAL)
#define PLL1_CLKIN CLK_XTAL
#else
#define PLL1_CLKIN CLK_IRC
#endif
#if (PLL1_DIRECT == 1) /* Direct Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#elif (PLL1_FBSEL == 1) /* Integer Mode */
#define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#else /* Noninteger Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
#endif
#if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
#error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
#endif
#if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
#error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
#endif
#endif
/*----------------------------------------------------------------------------
System Core Clock variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */
/******************************************************************************
* SetClock
******************************************************************************/
void SetClock (void) {
uint32_t x, i;
uint32_t selp, seli;
/* Set flash accelerator configuration for bank A and B to reset value */
LPC_CREG->FLASHCFGA |= (0xF << 12);
LPC_CREG->FLASHCFGB |= (0xF << 12);
/* Set flash wait states to maximum */
LPC_EMC->STATICWAITRD0 = 0x1F;
/* Switch BASE_M4_CLOCK to IRC */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Set clock source */
/* Configure input to crystal oscilator */
LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
(0 << 1) | /* Operation with crystal connected */
(0 << 2) ; /* Low-frequency mode */
/* Wait ~250us @ 12MHz */
for (i = 1500; i; i--);
#if (USE_SPIFI)
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Clock source */
LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IDIVA << 24) ; /* Clock source */
#endif
/*----------------------------------------------------------------------------
PLL1 Setup
*----------------------------------------------------------------------------*/
/* Power down PLL */
LPC_CGU->PLL1_CTRL |= 1;
#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
/* To run at full speed, CPU must first run at an intermediate speed */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(0 << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(0 << 11)| /* Autoblock Disabled */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* CPU base clock is in the mid frequency range before final clock set */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(0x09 << 24) ; /* Clock source: PLL1 */
/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
#endif
/* Configure PLL1 */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(PLL1_DIRECT << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(1 << 11)| /* Autoblock En */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* Set CPU base clock source */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CPU_CLK_SEL << 24) ; /* Set clock source */
/* Set flash accelerator configuration for internal flash bank A and B */
LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
/*----------------------------------------------------------------------------
PLL0USB Setup
*----------------------------------------------------------------------------*/
/* Power down PLL0USB */
LPC_CGU->PLL0USB_CTRL |= 1;
/* M divider */
x = 0x00004000;
switch (PLL0USB_M) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00018003;
break;
case 2: x = 0x00010003;
break;
default:
for (i = PLL0USB_M; i <= 0x8000; i++) {
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
}
}
if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
else selp = 31;
if (PLL0USB_M > 16384) seli = 1;
else if (PLL0USB_M > 8192) seli = 2;
else if (PLL0USB_M > 2048) seli = 4;
else if (PLL0USB_M >= 501) seli = 8;
else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
else seli = (PLL0USB_M & 0x3C) + 4;
LPC_CGU->PLL0USB_MDIV = (selp << 17) |
(seli << 22) |
(x << 0);
/* N divider */
x = 0x80;
switch (PLL0USB_N) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000302;
break;
case 2: x = 0x00000202;
break;
default:
for (i = PLL0USB_N; i <= 0x0100; i++) {
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
}
}
LPC_CGU->PLL0USB_NP_DIV = (x << 12);
/* P divider */
x = 0x10;
switch (PLL0USB_P) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000062;
break;
case 2: x = 0x00000042;
break;
default:
for (i = PLL0USB_P; i <= 0x200; i++) {
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
}
}
LPC_CGU->PLL0USB_NP_DIV |= x;
LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
(1 << 11) | /* Autoblock En */
(1 << 4 ) | /* PLL0USB clock en */
(PLL0USB_DIRECTO << 3 ) | /* Direct output */
(PLL0USB_DIRECTI << 2 ) | /* Direct input */
(PLL0USB_BYPASS << 1 ) | /* PLL bypass */
(0 << 0 ) ; /* PLL0USB Enabled */
while (!(LPC_CGU->PLL0USB_STAT & 1));
/*----------------------------------------------------------------------------
Integer divider Setup
*----------------------------------------------------------------------------*/
/* Configure integer dividers */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVA_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVA_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVB_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVB_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVC_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVC_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVD_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVD_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVE_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVE_CLK_SEL << 24) ; /* Clock source */
}
/*----------------------------------------------------------------------------
Approximate delay function (must be used after SystemCoreClockUpdate() call)
*----------------------------------------------------------------------------*/
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
static void WaitUs (uint32_t us) {
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
while(cyc--);
}
/*----------------------------------------------------------------------------
External Memory Controller Definitions
*----------------------------------------------------------------------------*/
#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
/* Write Mode register macro */
#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
const uint16_t emcdivby2_opc[] = {
0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
0xD0FC, /* BEQ loop ; Jump if 0 */
0x4770, /* BX LR ; Exit */
0,
};
#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
#define emcdivby2_ram 0x10000000
/*----------------------------------------------------------------------------
Initialize external memory controller
*----------------------------------------------------------------------------*/
void SystemInit_ExtMemCtl (void) {
uint32_t emcdivby2_buf[emcdivby2_szw];
uint32_t div, n;
/* Select and enable EMC branch clock */
LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
/* Set EMC clock output delay */
if (SystemCoreClock < 80000000UL) {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
}
else {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
}
/* Configure EMC port pins */
LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
div = 0;
if (SystemCoreClock > 120000000UL) {
/* Use EMC clock divider and EMC clock output delay */
div = 1;
/* Following code must be executed in RAM to ensure stable operation */
/* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
/* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
/* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
/* This code configures EMC clock divider and is executed in RAM */
for (n = 0; n < emcdivby2_szw; n++) {
emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
*((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
}
__ISB();
((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
for (n = 0; n < emcdivby2_szw; n++) {
*((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
}
}
/* Configure EMC clock-out pins */
LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
/* Static memory configuration (chip select 0) */
#if (USE_EXT_STAT_MEM_CS0)
LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
(2 << 0) | /* Memory width 32-bit */
(1 << 3); /* Async page mode enable */
LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
LPC_EMC->STATICWAITPAGE0 = 2;
/* Set Static Memory Read Delay for 90ns External NOR Flash */
LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
#endif
/* Dynamic memory configuration (chip select 0) */
#if (USE_EXT_DYN_MEM_CS0)
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
(0 << 12) | /* AM[12] = 0 */
(2 << 9) | /* AM[11:9] = 2 */
(2 << 7) ; /* AM[8:7] = 2 */
LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
WaitUs (100);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
WaitUs (1);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (1);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
WR_MODE(((3 << 4) | 2) << 12);
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
#endif
}
/*----------------------------------------------------------------------------
Measure frequency using frequency monitor
*----------------------------------------------------------------------------*/
uint32_t MeasureFreq (uint32_t clk_sel) {
uint32_t fcnt, rcnt, fout;
/* Set register values */
LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
while (LPC_CGU->FREQ_MON & (1 << 23)) {
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
if (fcnt == 0 && rcnt == 0) {
return (0); /* No input clock present */
}
}
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
return (fout);
}
/*----------------------------------------------------------------------------
Get PLL1 (divider and multiplier) parameters
*----------------------------------------------------------------------------*/
static __inline uint32_t GetPLL1Param (void) {
uint32_t ctrl;
uint32_t p;
uint32_t div, mul;
ctrl = LPC_CGU->PLL1_CTRL;
div = ((ctrl >> 12) & 0x03) + 1;
mul = ((ctrl >> 16) & 0xFF) + 1;
p = 1 << ((ctrl >> 8) & 0x03);
if (ctrl & (1 << 1)) {
/* Bypass = 1, PLL1 input clock sent to post-dividers */
if (ctrl & (1 << 7)) {
div *= (2*p);
}
}
else {
/* Direct and integer mode */
if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
/* Non-integer mode */
div *= (2*p);
}
}
return ((div << 8) | (mul));
}
/*----------------------------------------------------------------------------
Get input clock source for specified clock generation block
*----------------------------------------------------------------------------*/
int32_t GetClkSel (uint32_t clk_src) {
uint32_t reg;
int32_t clk_sel = -1;
switch (clk_src) {
case CLK_SRC_IRC:
case CLK_SRC_ENET_RX:
case CLK_SRC_ENET_TX:
case CLK_SRC_GP_CLKIN:
return (clk_src);
case CLK_SRC_32KHZ:
return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
case CLK_SRC_XTAL:
return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
default:
return (clk_sel);
}
if (!(reg & 1)) {
clk_sel = (reg >> 24) & 0x1F;
}
return (clk_sel);
}
/*----------------------------------------------------------------------------
Get clock frequency for specified clock source
*----------------------------------------------------------------------------*/
uint32_t GetClockFreq (uint32_t clk_src) {
uint32_t tmp;
uint32_t mul = 1;
uint32_t div = 1;
uint32_t main_freq = 0;
int32_t clk_sel = clk_src;
do {
switch (clk_sel) {
case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
case CLK_SRC_IRC: main_freq = CLK_IRC; break;
case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
case CLK_SRC_PLL0U: /* Not implemented */ break;
case CLK_SRC_PLL0A: /* Not implemented */ break;
case CLK_SRC_PLL1:
tmp = GetPLL1Param ();
mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
break;
default:
return (0); /* Clock not running or not supported */
}
if (main_freq == 0) {
clk_sel = GetClkSel (clk_sel);
}
}
while (main_freq == 0);
return ((main_freq * mul) / div);
}
/*----------------------------------------------------------------------------
System Core Clock update
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) {
/* Check BASE_M4_CLK connection */
uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
/* Update core clock frequency */
SystemCoreClock = GetClockFreq (base_src);
}
extern uint32_t __Vectors; /* see startup_LPC43xx.s */
/*----------------------------------------------------------------------------
Initialize the system
*----------------------------------------------------------------------------*/
void SystemInit (void) {
#if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Stop CM0 core */
LPC_RGU->RESET_CTRL1 = (1 << 24);
/* Disable SysTick timer */
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
/* Set vector table pointer */
SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
SetClock();
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
/* Configure External Memory Controller */
//SystemInit_ExtMemCtl ();
}

2483
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h vendored Normal file
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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s vendored Normal file
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;/**************************************************************************//**
; * @file LPC43xx.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * NXP LPC43xxDevice Series
; * @version V1.00
; * @date 03. September 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; * <<< Use Configuration Wizard in Context Menu >>>
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External LPC43xx/M4 Interrupts
DCD DAC_IRQHandler ; 0 DAC interrupt
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
DCD DMA_IRQHandler ; 2 DMA interrupt
DCD 0 ; 3 Reserved
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
DCD LCD_IRQHandler ; 7 LCD interrupt
DCD USB0_IRQHandler ; 8 OTG interrupt
DCD USB1_IRQHandler ; 9 USB1 interrupt
DCD SCT_IRQHandler ; 10 SCT combined interrupt
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
DCD SPI_IRQHandler ; 20 SPI interrupt
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
DCD USART0_IRQHandler ; 24 USART0 interrupt
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
DCD USART2_IRQHandler ; 26 USART2 interrupt
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
DCD 0 ; 44 Reserved
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
DCD RTC_IRQHandler ; 47 RTC interrupt
DCD 0 ; 48 Reserved
DCD WWDT_IRQHandler ; 49 WWDT interrupt
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
DCD QEI_IRQHandler ; 52 QEI interrupt
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0APP_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASHEEPROM_IRQHandler [WEAK]
EXPORT ETHERNET_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RITIMER_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT C_CAN1_IRQHandler [WEAK]
EXPORT ADCHS_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT M0SUB_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0APP_IRQHandler
DMA_IRQHandler
FLASHEEPROM_IRQHandler
ETHERNET_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ADCHS_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
M0SUB_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

938
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c vendored Normal file
View File

@ -0,0 +1,938 @@
/* -----------------------------------------------------------------------------
* Copyright (c) 2013 - 2017 ARM Ltd.
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising from
* the use of this software. Permission is granted to anyone to use this
* software for any purpose, including commercial applications, and to alter
* it and redistribute it freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software in
* a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
*
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
*
* 3. This notice may not be removed or altered from any source distribution.
*
* $Date: 10. September 2018
* $Revision: V1.0.3
*
* Project: NXP LPC43xx System initialization
* -------------------------------------------------------------------------- */
#include "LPC43xx.h"
/*----------------------------------------------------------------------------
This file configures the clocks as follows:
-----------------------------------------------------------------------------
Clock Unit | Output clock | Source clock | Note
-----------------------------------------------------------------------------
PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
-----------------------------------------------------------------------------
IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
-----------------------------------------------------------------------------
IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
-----------------------------------------------------------------------------
IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV E | 5.3 MHz | PLL1 | To the LCD controller
-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock source selection definitions (do not change)
*----------------------------------------------------------------------------*/
#define CLK_SRC_32KHZ 0x00
#define CLK_SRC_IRC 0x01
#define CLK_SRC_ENET_RX 0x02
#define CLK_SRC_ENET_TX 0x03
#define CLK_SRC_GP_CLKIN 0x04
#define CLK_SRC_XTAL 0x06
#define CLK_SRC_PLL0U 0x07
#define CLK_SRC_PLL0A 0x08
#define CLK_SRC_PLL1 0x09
#define CLK_SRC_IDIVA 0x0C
#define CLK_SRC_IDIVB 0x0D
#define CLK_SRC_IDIVC 0x0E
#define CLK_SRC_IDIVD 0x0F
#define CLK_SRC_IDIVE 0x10
/*----------------------------------------------------------------------------
Define external input frequency values
*----------------------------------------------------------------------------*/
#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
#define CLK_IRC 12000000UL /* Internal oscillator frequency */
#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
/*----------------------------------------------------------------------------
Define clock sources
*----------------------------------------------------------------------------*/
#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
/*----------------------------------------------------------------------------
Configure integer divider values
*----------------------------------------------------------------------------*/
#define IDIVA_IDIV 2 /* Divide input clock by 3 */
#define IDIVB_IDIV 1 /* Divide input clock by 2 */
#define IDIVC_IDIV 0 /* Divide input clock by 1 */
#define IDIVD_IDIV 0 /* Divide input clock by 1 */
#define IDIVE_IDIV 33 /* Divide input clock by 34 */
/*----------------------------------------------------------------------------
Define CPU clock input
*----------------------------------------------------------------------------*/
#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
/*----------------------------------------------------------------------------
Configure external memory controller options
*----------------------------------------------------------------------------*/
#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
/*----------------------------------------------------------------------------
* Configure PLL1
*----------------------------------------------------------------------------
* Integer mode:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT * 2 * P
*
* Non-integer:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M / (2 * P)
* FCCO = FCLKOUT * 2 * P
*
* Direct mode:
* - PLL1_DIRECT = 1 (Post divider disabled)
* - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT
*
*----------------------------------------------------------------------------
* PLL1 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 1MHz | 50MHz | |
* | FCCO | 156MHz | 320MHz | |
* | FCLKOUT | 9.75MHz | 320MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
* | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
* | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
* | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
* | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
* | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
* | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
* | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
*----------------------------------------------------------------------------
* Relations beetwen PLL dividers and definitions:
* N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
*----------------------------------------------------------------------------*/
/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
/* 1: FCLKOUT is used as PLL feedback */
/*----------------------------------------------------------------------------
* Configure Flash Accelerator
*----------------------------------------------------------------------------
* Flash acces time:
* | CPU clock | FLASHTIM |
* | up to 21MHz | 0 |
* | up to 43MHz | 1 |
* | up to 64MHz | 2 |
* | up to 86MHz | 3 |
* | up to 107MHz | 4 |
* | up to 129MHz | 5 |
* | up to 150MHz | 6 |
* | up to 172MHz | 7 |
* | up to 193MHz | 8 |
* | up to 204MHz | 9 |
*----------------------------------------------------------------------------*/
#define FLASHCFG_FLASHTIM 9
/*----------------------------------------------------------------------------
* Configure PLL0USB
*----------------------------------------------------------------------------
*
* Normal operating mode without post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M
* FCCO = FOUT
*
* Normal operating mode with post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * (M / P)
* FCCO = FOUT * 2 * P
*
* Normal operating mode without post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M / N
* FCCO = FOUT
*
* Normal operating mode with post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * M / (P * N)
* FCCO = FOUT * 2 * P
*----------------------------------------------------------------------------
* PLL0 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 14kHz | 150MHz | |
* | FCCO | 275MHz | 550MHz | |
* | FCLKOUT | 4.3MHz | 550MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
* | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
* | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
*----------------------------------------------------------------------------*/
/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
/*----------------------------------------------------------------------------
End of configuration
*----------------------------------------------------------------------------*/
/* PLL0 Setting Check */
#if (PLL0USB_BYPASS == 0)
#if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
#define PLL0USB_CLKIN CLK_XTAL
#else
#define PLL0USB_CLKIN CLK_IRC
#endif
#if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#else /* Mode 1d */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#endif
#if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
#error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
#endif
#if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
#error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
#endif
#endif
/* PLL1 Setting Check */
#if (PLL1_BYPASS == 0)
#if (PLL1_CLK_SEL == CLK_SRC_XTAL)
#define PLL1_CLKIN CLK_XTAL
#else
#define PLL1_CLKIN CLK_IRC
#endif
#if (PLL1_DIRECT == 1) /* Direct Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#elif (PLL1_FBSEL == 1) /* Integer Mode */
#define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#else /* Noninteger Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
#endif
#if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
#error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
#endif
#if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
#error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
#endif
#endif
/*----------------------------------------------------------------------------
System Core Clock variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */
/******************************************************************************
* SetClock
******************************************************************************/
void SetClock (void) {
uint32_t x, i;
uint32_t selp, seli;
/* Set flash accelerator configuration for bank A and B to reset value */
LPC_CREG->FLASHCFGA |= (0xF << 12);
LPC_CREG->FLASHCFGB |= (0xF << 12);
/* Set flash wait states to maximum */
LPC_EMC->STATICWAITRD0 = 0x1F;
/* Switch BASE_M4_CLOCK to IRC */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Set clock source */
/* Configure input to crystal oscilator */
LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
(0 << 1) | /* Operation with crystal connected */
(0 << 2) ; /* Low-frequency mode */
/* Wait ~250us @ 12MHz */
for (i = 1500; i; i--);
#if (USE_SPIFI)
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Clock source */
LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IDIVA << 24) ; /* Clock source */
#endif
/*----------------------------------------------------------------------------
PLL1 Setup
*----------------------------------------------------------------------------*/
/* Power down PLL */
LPC_CGU->PLL1_CTRL |= 1;
#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
/* To run at full speed, CPU must first run at an intermediate speed */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(0 << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(0 << 11)| /* Autoblock Disabled */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* CPU base clock is in the mid frequency range before final clock set */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(0x09 << 24) ; /* Clock source: PLL1 */
/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
#endif
/* Configure PLL1 */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(PLL1_DIRECT << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(1 << 11)| /* Autoblock En */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* Set CPU base clock source */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CPU_CLK_SEL << 24) ; /* Set clock source */
/* Set flash accelerator configuration for internal flash bank A and B */
LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
/*----------------------------------------------------------------------------
PLL0USB Setup
*----------------------------------------------------------------------------*/
/* Power down PLL0USB */
LPC_CGU->PLL0USB_CTRL |= 1;
/* M divider */
x = 0x00004000;
switch (PLL0USB_M) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00018003;
break;
case 2: x = 0x00010003;
break;
default:
for (i = PLL0USB_M; i <= 0x8000; i++) {
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
}
}
if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
else selp = 31;
if (PLL0USB_M > 16384) seli = 1;
else if (PLL0USB_M > 8192) seli = 2;
else if (PLL0USB_M > 2048) seli = 4;
else if (PLL0USB_M >= 501) seli = 8;
else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
else seli = (PLL0USB_M & 0x3C) + 4;
LPC_CGU->PLL0USB_MDIV = (selp << 17) |
(seli << 22) |
(x << 0);
/* N divider */
x = 0x80;
switch (PLL0USB_N) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000302;
break;
case 2: x = 0x00000202;
break;
default:
for (i = PLL0USB_N; i <= 0x0100; i++) {
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
}
}
LPC_CGU->PLL0USB_NP_DIV = (x << 12);
/* P divider */
x = 0x10;
switch (PLL0USB_P) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000062;
break;
case 2: x = 0x00000042;
break;
default:
for (i = PLL0USB_P; i <= 0x200; i++) {
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
}
}
LPC_CGU->PLL0USB_NP_DIV |= x;
LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
(1 << 11) | /* Autoblock En */
(1 << 4 ) | /* PLL0USB clock en */
(PLL0USB_DIRECTO << 3 ) | /* Direct output */
(PLL0USB_DIRECTI << 2 ) | /* Direct input */
(PLL0USB_BYPASS << 1 ) | /* PLL bypass */
(0 << 0 ) ; /* PLL0USB Enabled */
while (!(LPC_CGU->PLL0USB_STAT & 1));
/*----------------------------------------------------------------------------
Integer divider Setup
*----------------------------------------------------------------------------*/
/* Configure integer dividers */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVA_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVA_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVB_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVB_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVC_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVC_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVD_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVD_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVE_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVE_CLK_SEL << 24) ; /* Clock source */
}
/*----------------------------------------------------------------------------
Approximate delay function (must be used after SystemCoreClockUpdate() call)
*----------------------------------------------------------------------------*/
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
static void WaitUs (uint32_t us) {
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
while(cyc--);
}
/*----------------------------------------------------------------------------
External Memory Controller Definitions
*----------------------------------------------------------------------------*/
#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
/* Write Mode register macro */
#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
const uint16_t emcdivby2_opc[] = {
0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
0xD0FC, /* BEQ loop ; Jump if 0 */
0x4770, /* BX LR ; Exit */
0,
};
#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
#define emcdivby2_ram 0x10000000
/*----------------------------------------------------------------------------
Initialize external memory controller
*----------------------------------------------------------------------------*/
void SystemInit_ExtMemCtl (void) {
uint32_t emcdivby2_buf[emcdivby2_szw];
uint32_t div, n;
/* Select and enable EMC branch clock */
LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
/* Set EMC clock output delay */
if (SystemCoreClock < 80000000UL) {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
}
else {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
}
/* Configure EMC port pins */
LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
div = 0;
if (SystemCoreClock > 120000000UL) {
/* Use EMC clock divider and EMC clock output delay */
div = 1;
/* Following code must be executed in RAM to ensure stable operation */
/* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
/* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
/* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
/* This code configures EMC clock divider and is executed in RAM */
for (n = 0; n < emcdivby2_szw; n++) {
emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
*((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
}
__ISB();
((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
for (n = 0; n < emcdivby2_szw; n++) {
*((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
}
}
/* Configure EMC clock-out pins */
LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
/* Static memory configuration (chip select 0) */
#if (USE_EXT_STAT_MEM_CS0)
LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
(2 << 0) | /* Memory width 32-bit */
(1 << 3); /* Async page mode enable */
LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
LPC_EMC->STATICWAITPAGE0 = 2;
/* Set Static Memory Read Delay for 90ns External NOR Flash */
LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
#endif
/* Dynamic memory configuration (chip select 0) */
#if (USE_EXT_DYN_MEM_CS0)
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
(0 << 12) | /* AM[12] = 0 */
(2 << 9) | /* AM[11:9] = 2 */
(2 << 7) ; /* AM[8:7] = 2 */
LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
WaitUs (100);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
WaitUs (1);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (1);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
WR_MODE(((3 << 4) | 2) << 12);
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
#endif
}
/*----------------------------------------------------------------------------
Measure frequency using frequency monitor
*----------------------------------------------------------------------------*/
uint32_t MeasureFreq (uint32_t clk_sel) {
uint32_t fcnt, rcnt, fout;
/* Set register values */
LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
while (LPC_CGU->FREQ_MON & (1 << 23)) {
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
if (fcnt == 0 && rcnt == 0) {
return (0); /* No input clock present */
}
}
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
return (fout);
}
/*----------------------------------------------------------------------------
Get PLL1 (divider and multiplier) parameters
*----------------------------------------------------------------------------*/
static __inline uint32_t GetPLL1Param (void) {
uint32_t ctrl;
uint32_t p;
uint32_t div, mul;
ctrl = LPC_CGU->PLL1_CTRL;
div = ((ctrl >> 12) & 0x03) + 1;
mul = ((ctrl >> 16) & 0xFF) + 1;
p = 1 << ((ctrl >> 8) & 0x03);
if (ctrl & (1 << 1)) {
/* Bypass = 1, PLL1 input clock sent to post-dividers */
if (ctrl & (1 << 7)) {
div *= (2*p);
}
}
else {
/* Direct and integer mode */
if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
/* Non-integer mode */
div *= (2*p);
}
}
return ((div << 8) | (mul));
}
/*----------------------------------------------------------------------------
Get input clock source for specified clock generation block
*----------------------------------------------------------------------------*/
int32_t GetClkSel (uint32_t clk_src) {
uint32_t reg;
int32_t clk_sel = -1;
switch (clk_src) {
case CLK_SRC_IRC:
case CLK_SRC_ENET_RX:
case CLK_SRC_ENET_TX:
case CLK_SRC_GP_CLKIN:
return (clk_src);
case CLK_SRC_32KHZ:
return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
case CLK_SRC_XTAL:
return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
default:
return (clk_sel);
}
if (!(reg & 1)) {
clk_sel = (reg >> 24) & 0x1F;
}
return (clk_sel);
}
/*----------------------------------------------------------------------------
Get clock frequency for specified clock source
*----------------------------------------------------------------------------*/
uint32_t GetClockFreq (uint32_t clk_src) {
uint32_t tmp;
uint32_t mul = 1;
uint32_t div = 1;
uint32_t main_freq = 0;
int32_t clk_sel = clk_src;
do {
switch (clk_sel) {
case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
case CLK_SRC_IRC: main_freq = CLK_IRC; break;
case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
case CLK_SRC_PLL0U: /* Not implemented */ break;
case CLK_SRC_PLL0A: /* Not implemented */ break;
case CLK_SRC_PLL1:
tmp = GetPLL1Param ();
mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
break;
default:
return (0); /* Clock not running or not supported */
}
if (main_freq == 0) {
clk_sel = GetClkSel (clk_sel);
}
}
while (main_freq == 0);
return ((main_freq * mul) / div);
}
/*----------------------------------------------------------------------------
System Core Clock update
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) {
/* Check BASE_M4_CLK connection */
uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
/* Update core clock frequency */
SystemCoreClock = GetClockFreq (base_src);
}
extern uint32_t __Vectors; /* see startup_LPC43xx.s */
/*----------------------------------------------------------------------------
Initialize the system
*----------------------------------------------------------------------------*/
void SystemInit (void) {
#if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Stop CM0 core */
LPC_RGU->RESET_CTRL1 = (1 << 24);
/* Disable SysTick timer */
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
/* Set vector table pointer */
SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
SetClock();
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
/* Configure External Memory Controller */
//SystemInit_ExtMemCtl ();
}

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_0.c vendored Normal file
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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_0.c
* Purpose: USB Device Configuration
* Rev.: V5.2.0
*------------------------------------------------------------------------------
* Use the following configuration settings in the Device Class configuration
* files to assign a Device Class to this USB Device 0.
*
* Configuration Setting Value
* --------------------- -----
* Assign Device Class to USB Device # = 0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device 0
// <o>Connect to hardware via Driver_USBD# <0-255>
// <i>Select driver control block for hardware interface.
#define USBD0_PORT 0
// <o.0>High-speed
// <i>Enable High-speed functionality (if device supports it).
#define USBD0_HS 1
// <h>Device Settings
// <i>These settings are used to create the Device Descriptor
// <o>Max Endpoint 0 Packet Size
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
#define USBD0_MAX_PACKET0 64
// <o.0..15>Vendor ID <0x0000-0xFFFF>
// <i>Vendor ID assigned by USB-IF (idVendor).
#define USBD0_DEV_DESC_IDVENDOR 0xC251
// <o.0..15>Product ID <0x0000-0xFFFF>
// <i>Product ID assigned by manufacturer (idProduct).
#define USBD0_DEV_DESC_IDPRODUCT 0xF00A
// <o.0..15>Device Release Number <0x0000-0xFFFF>
// <i>Device Release Number in binary-coded decimal (bcdDevice)
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
// </h>
// <h>Configuration Settings
// <i>These settings are used to create the Configuration Descriptor.
// <o.6>Power
// <i>Default Power Setting (D6: of bmAttributes).
// <0=>Bus-powered
// <1=>Self-powered
// <o.5>Remote Wakeup
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
// <i>Maximum Power Consumption of USB Device from bus in this
// <i>specific configuration when device is fully operational (bMaxPower).
#define USBD0_CFG_DESC_BMAXPOWER 250
// </h>
// <h>String Settings
// <i>These settings are used to create the String Descriptor.
// <o.0..15>Language ID <0x0000-0xFCFF>
// <i>English (United States) = 0x0409.
#define USBD0_STR_DESC_LANGID 0x0409
// <s.126>Manufacturer String
// <i>String Descriptor describing Manufacturer.
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
// <s.126>Product String
// <i>String Descriptor describing Product.
#define USBD0_STR_DESC_PROD L"LPC-Link2"
// <e.0>Serial Number String
// <i>Enable Serial Number String.
// <i>If disabled Serial Number String will not be assigned to USB Device.
#define USBD0_STR_DESC_SER_EN 1
// <s.126>Default value
// <i>Default device's Serial Number String.
#define USBD0_STR_DESC_SER L"0001A0000000"
// <o.0..7>Maximum Length (in characters) <0-126>
// <i>Specifies the maximum number of Serial Number String characters that can be set at run-time.
// <i>Maximum value is 126. Use value 0 to disable RAM allocation for string.
#define USBD0_STR_DESC_SER_MAX_LEN 16
// </e>
// </h>
// <h>Microsoft OS Descriptors Settings
// <i>These settings are used to create the Microsoft OS Descriptors.
// <e.0>OS String
// <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
#define USBD0_OS_DESC_EN 1
// <o.0..7>Vendor Code <0x01-0xFF>
// <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
#define USBD0_OS_DESC_VENDOR_CODE 0x01
// </e>
// </h>
// <o>Control Transfer Buffer Size <64-65536:64>
// <i>Specifies size of buffer used for Control Transfers.
// <i>It should be at least as big as maximum packet size for Endpoint 0.
#define USBD0_EP0_BUF_SIZE 128
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Core Thread Stack Size <64-65536>
#define USBD0_CORE_THREAD_STACK_SIZE 1024
// Core Thread Priority
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
#include "RTE_Components.h"
#ifdef RTE_USB_Device_CustomClass_0
#include "USBD_Config_CustomClass_0.h"
#endif
#ifdef RTE_USB_Device_CustomClass_1
#include "USBD_Config_CustomClass_1.h"
#endif
#ifdef RTE_USB_Device_CustomClass_2
#include "USBD_Config_CustomClass_2.h"
#endif
#ifdef RTE_USB_Device_CustomClass_3
#include "USBD_Config_CustomClass_3.h"
#endif
#ifdef RTE_USB_Device_HID_0
#include "USBD_Config_HID_0.h"
#endif
#ifdef RTE_USB_Device_HID_1
#include "USBD_Config_HID_1.h"
#endif
#ifdef RTE_USB_Device_HID_2
#include "USBD_Config_HID_2.h"
#endif
#ifdef RTE_USB_Device_HID_3
#include "USBD_Config_HID_3.h"
#endif
#ifdef RTE_USB_Device_MSC_0
#include "USBD_Config_MSC_0.h"
#endif
#ifdef RTE_USB_Device_MSC_1
#include "USBD_Config_MSC_1.h"
#endif
#ifdef RTE_USB_Device_MSC_2
#include "USBD_Config_MSC_2.h"
#endif
#ifdef RTE_USB_Device_MSC_3
#include "USBD_Config_MSC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_0
#include "USBD_Config_CDC_0.h"
#endif
#ifdef RTE_USB_Device_CDC_1
#include "USBD_Config_CDC_1.h"
#endif
#ifdef RTE_USB_Device_CDC_2
#include "USBD_Config_CDC_2.h"
#endif
#ifdef RTE_USB_Device_CDC_3
#include "USBD_Config_CDC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_4
#include "USBD_Config_CDC_4.h"
#endif
#ifdef RTE_USB_Device_CDC_5
#include "USBD_Config_CDC_5.h"
#endif
#ifdef RTE_USB_Device_CDC_6
#include "USBD_Config_CDC_6.h"
#endif
#ifdef RTE_USB_Device_CDC_7
#include "USBD_Config_CDC_7.h"
#endif
#ifdef RTE_USB_Device_ADC_0
#include "USBD_Config_ADC_0.h"
#endif
#ifdef RTE_USB_Device_ADC_1
#include "USBD_Config_ADC_1.h"
#endif
#ifdef RTE_USB_Device_ADC_2
#include "USBD_Config_ADC_2.h"
#endif
#ifdef RTE_USB_Device_ADC_3
#include "USBD_Config_ADC_3.h"
#endif
#include "usbd_config.h"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_CDC_0.h
* Purpose: USB Device Communication Device Class (CDC) Configuration
* Rev.: V5.2.0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device: Communication Device Class (CDC) 0
// <o>Assign Device Class to USB Device # <0-3>
// <i>Select USB Device that is used for this Device Class instance
#define USBD_CDC0_DEV 0
// <o>Communication Class Subclass
// <i>Specifies the model used by the CDC class.
// <2=>Abstract Control Model (ACM)
// <13=>Network Control Model (NCM)
#define USBD_CDC0_SUBCLASS 2
// <o>Communication Class Protocol
// <i>Specifies the protocol used by the CDC class.
// <0=>No protocol (Virtual COM)
// <255=>Vendor-specific (RNDIS)
#define USBD_CDC0_PROTOCOL 0
// <h>Interrupt Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Interrupt IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_INT_IN 3
// <h>Endpoint Settings
// <i>Parameters are used to create Endpoint Descriptors
// <i>and for memory allocation in the USB component.
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE 16
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
#define USBD_CDC0_BINTERVAL 2
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 1024.
// <o.11..12>Additional transactions per microframe
// <i>Additional transactions improve communication performance.
// <0=>None <1=>1 additional <2=>2 additional
#define USBD_CDC0_HS_WMAXPACKETSIZE 16
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
#define USBD_CDC0_HS_BINTERVAL 2
// </h>
// </h>
// </h>
// <h>Bulk Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Bulk IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_IN 4
// <o.0..3>Bulk OUT Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_OUT 4
// <h>Endpoint Settings
// <i>Parameters are used to create USB Descriptors and for memory
// <i>allocation in the USB component.
//
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE1 64
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..9>Maximum Endpoint Packet Size (in bytes) <512=>512
// <i>Specifies the physical packet size used for information exchange.
// <i>Only available value is 512.
#define USBD_CDC0_HS_WMAXPACKETSIZE1 512
// <o.0..7>Maximum NAK Rate <0-255>
// <i>Specifies the interval in which Bulk Endpoint can NAK.
// <i>Value of 0 indicates that Bulk Endpoint never NAKs.
#define USBD_CDC0_HS_BINTERVAL1 0
// </h>
// </h>
// </h>
// <h>Communication Device Class Settings
// <i>Parameters are used to create USB Descriptors and for memory allocation
// <i>in the USB component.
//
// <s.126>Communication Class Interface String
#define USBD_CDC0_CIF_STR_DESC L"USB_CDC0_0"
// <s.126>Data Class Interface String
#define USBD_CDC0_DIF_STR_DESC L"USB_CDC0_1"
// <h>Abstract Control Model Settings
// <h>Call Management Capabilities
// <i>Specifies which call management functionality is supported.
// <o.1>Call Management channel
// <0=>Communication Class Interface only
// <1=>Communication and Data Class Interface
// <o.0>Device Call Management handling
// <0=>None
// <1=>All
// </h>
#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03
// <h>Abstract Control Management Capabilities
// <i>Specifies which abstract control management functionality is supported.
// <o.3>D3 bit
// <i>Enabled = Supports the notification Network_Connection
// <o.2>D2 bit
// <i>Enabled = Supports the request Send_Break
// <o.1>D1 bit
// <i>Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding,
// <i> Set_Control_Line_State, and notification Serial_State
// <o.0>D0 bit
// <i>Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature
// </h>
#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06
// <o>Maximum Communication Device Send Buffer Size
// <i>Specifies size of buffer used for sending of data to USB Host.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_SEND_BUF_SIZE 1024
// <o>Maximum Communication Device Receive Buffer Size
// <i>Specifies size of buffer used for receiving of data from USB Host.
// <i>Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint.
// <i>Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE 2048
// </h>
// <h>Network Control Model Settings
// <s.12>MAC Address String
// <i>Specifies 48-bit Ethernet MAC address.
#define USBD_CDC0_NCM_MAC_ADDRESS L"1E306CA2455E"
// <h>Ethernet Statistics
// <i>Specifies Ethernet statistic functions supported.
// <o.0>XMIT_OK
// <i>Frames transmitted without errors
// <o.1>RVC_OK
// <i>Frames received without errors
// <o.2>XMIT_ERROR
// <i>Frames not transmitted, or transmitted with errors
// <o.3>RCV_ERROR
// <i>Frames received with errors that are not delivered to the USB host.
// <o.4>RCV_NO_BUFFER
// <i>Frame missed, no buffers
// <o.5>DIRECTED_BYTES_XMIT
// <i>Directed bytes transmitted without errors
// <o.6>DIRECTED_FRAMES_XMIT
// <i>Directed frames transmitted without errors
// <o.7>MULTICAST_BYTES_XMIT
// <i>Multicast bytes transmitted without errors
// <o.8>MULTICAST_FRAMES_XMIT
// <i>Multicast frames transmitted without errors
// <o.9>BROADCAST_BYTES_XMIT
// <i>Broadcast bytes transmitted without errors
// <o.10>BROADCAST_FRAMES_XMIT
// <i>Broadcast frames transmitted without errors
// <o.11>DIRECTED_BYTES_RCV
// <i>Directed bytes received without errors
// <o.12>DIRECTED_FRAMES_RCV
// <i>Directed frames received without errors
// <o.13>MULTICAST_BYTES_RCV
// <i>Multicast bytes received without errors
// <o.14>MULTICAST_FRAMES_RCV
// <i>Multicast frames received without errors
// <o.15>BROADCAST_BYTES_RCV
// <i>Broadcast bytes received without errors
// <o.16>BROADCAST_FRAMES_RCV
// <i>Broadcast frames received without errors
// <o.17>RCV_CRC_ERROR
// <i>Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error
// <o.18>TRANSMIT_QUEUE_LENGTH
// <i>Length of transmit queue
// <o.19>RCV_ERROR_ALIGNMENT
// <i>Frames received with alignment error
// <o.20>XMIT_ONE_COLLISION
// <i>Frames transmitted with one collision
// <o.21>XMIT_MORE_COLLISIONS
// <i>Frames transmitted with more than one collision
// <o.22>XMIT_DEFERRED
// <i>Frames transmitted after deferral
// <o.23>XMIT_MAX_COLLISIONS
// <i>Frames not transmitted due to collisions
// <o.24>RCV_OVERRUN
// <i>Frames not received due to overrun
// <o.25>XMIT_UNDERRUN
// <i>Frames not transmitted due to underrun
// <o.26>XMIT_HEARTBEAT_FAILURE
// <i>Frames transmitted with heartbeat failure
// <o.27>XMIT_TIMES_CRS_LOST
// <i>Times carrier sense signal lost during transmission
// <o.28>XMIT_LATE_COLLISIONS
// <i>Late collisions detected
// </h>
#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS 0x00000003
// <o>Maximum Segment Size
// <i>Specifies maximum segment size that Ethernet device is capable of supporting.
// <i>Typically 1514 bytes.
#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE 1514
// <o.15>Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing)
// <i>Specifies multicast filtering type.
// <o.0..14>Number of Multicast Filters
// <i>Specifies number of multicast filters that can be configured by the USB Host.
#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS 1
// <o.0..7>Number of Power Filters
// <i>Specifies number of pattern filters that are available for causing wake-up of the USB Host.
#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS 0
// <h>Network Capabilities
// <i>Specifies which functions are supported.
// <o.4>SetCrcMode/GetCrcMode
// <o.3>SetMaxDatagramSize/GetMaxDatagramSize
// <o.1>SetNetAddress/GetNetAddress
// <o.0>SetEthernetPacketFilter
// </h>
#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES 0x1B
// <h>NTB Parameters
// <i>Specifies NTB parameters reported by GetNtbParameters function.
// <h>NTB Formats Supported (bmNtbFormatsSupported)
// <i>Specifies NTB formats supported.
// <o.0>16-bit NTB (always supported)
// <o.1>32-bit NTB
// </h>
#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED 0x0001
// <h>IN Data Pipe
//
// <o>Maximum NTB Size (dwNtbInMaxSize)
// <i>Specifies maximum IN NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpInDivisor)
// <i>Specifies divisor used for IN NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder)
// <i>Specifies remainder used to align input datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpInAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT 4
// </h>
// <h>OUT Data Pipe
//
// <o>Maximum NTB Size (dwNtbOutMaxSize)
// <i>Specifies maximum OUT NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpOutDivisor)
// <i>Specifies divisor used for OUT NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder)
// <i>Specifies remainder used to align output datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpOutAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT 4
// </h>
// </h>
// <o.0>Raw Data Access API
// <i>Enables or disables Raw Data Access API.
#define USBD_CDC0_NCM_RAW_ENABLE 0
// <o>IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for sending data to USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_IN_BUF_CNT 1
// <o>OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for receiving data from USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT 1
// </h>
// </h>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536>
#define USBD_CDC0_INT_THREAD_STACK_SIZE 512
// Communication Device Class Interrupt Endpoint Thread Priority
#define USBD_CDC0_INT_THREAD_PRIORITY osPriorityAboveNormal
// <o>Communication Device Class Bulk Endpoints Thread Stack Size <64-65536>
#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512
// Communication Device Class Bulk Endpoints Thread Priority
#define USBD_CDC0_BULK_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device:CDC
* Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_User_CDC_ACM_UART_0.c
* Purpose: USB Device Communication Device Class (CDC)
* Abstract Control Model (ACM) USB <-> UART Bridge User module
* Rev.: V1.0.8
*----------------------------------------------------------------------------*/
/**
* \addtogroup usbd_cdcFunctions
*
* USBD_User_CDC_ACM_UART_0.c implements the application specific
* functionality of the CDC ACM class and is used to demonstrate a USB <-> UART
* bridge. All data received on USB is transmitted on UART and all data
* received on UART is transmitted on USB.
*
* Details of operation:
* UART -> USB:
* Initial reception on UART is started after the USB Host sets line coding
* with SetLineCoding command. Having received a full UART buffer, any
* new reception is restarted on the same buffer. Any data received on
* the UART is sent over USB using the CDC0_ACM_UART_to_USB_Thread thread.
* USB -> UART:
* While the UART transmit is not busy, data transmission on the UART is
* started in the USBD_CDC0_ACM_DataReceived callback as soon as data is
* received on the USB. Further data received on USB is transmitted on
* UART in the UART callback routine until there is no more data available.
* In this case, the next UART transmit is restarted from the
* USBD_CDC0_ACM_DataReceived callback as soon as new data is received
* on the USB.
*
* The following constants in this module affect the module functionality:
*
* - UART_PORT: specifies UART Port
* default value: 0 (=UART0)
* - UART_BUFFER_SIZE: specifies UART data Buffer Size
* default value: 512
*
* Notes:
* If the USB is slower than the UART, data can get lost. This may happen
* when USB is pausing during data reception because of the USB Host being
* too loaded with other tasks and not polling the Bulk IN Endpoint often
* enough (up to 2 seconds of gap in polling Bulk IN Endpoint may occur).
* This problem can be solved by using a large enough UART buffer to
* compensate up to a few seconds of received UART data or by using UART
* flow control.
* If the device that receives the UART data (usually a PC) is too loaded
* with other tasks it can also loose UART data. This problem can only be
* solved by using UART flow control.
*
* This file has to be adapted in case of UART flow control usage.
*/
//! [code_USBD_User_CDC_ACM]
#include <stdio.h>
#include <string.h>
#include "rl_usb.h"
#include "Driver_USART.h"
#include "DAP_config.h"
#include "DAP.h"
// UART Configuration ----------------------------------------------------------
#define UART_BUFFER_SIZE (512) // UART Buffer Size
//------------------------------------------------------------------------------
#define _UART_Driver_(n) Driver_USART##n
#define UART_Driver_(n) _UART_Driver_(n)
extern ARM_DRIVER_USART UART_Driver_(DAP_UART_DRIVER);
#define ptrUART (&UART_Driver_(DAP_UART_DRIVER))
// Local Variables
static uint8_t uart_rx_buf[UART_BUFFER_SIZE];
static uint8_t uart_tx_buf[UART_BUFFER_SIZE];
static volatile int32_t uart_rx_cnt = 0;
static volatile int32_t usb_tx_cnt = 0;
static void *cdc_acm_bridge_tid = 0U;
static CDC_LINE_CODING cdc_acm_line_coding = { 0U, 0U, 0U, 0U };
static uint8_t cdc_acm_active = 1U;
static osMutexId_t cdc_acm_mutex_id = NULL;
// Acquire mutex
__STATIC_INLINE void CDC_ACM_Lock (void) {
if (cdc_acm_mutex_id == NULL) {
cdc_acm_mutex_id = osMutexNew(NULL);
}
osMutexAcquire(cdc_acm_mutex_id, osWaitForever);
}
// Release mutex
__STATIC_INLINE void CDC_ACM_Unlock (void) {
osMutexRelease(cdc_acm_mutex_id);
}
// Change communication settings.
// \param[in] line_coding pointer to CDC_LINE_CODING structure.
// \return true set line coding request processed.
// \return false set line coding request not supported or not processed.
static bool CDC_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
uint32_t data_bits = 0U, parity = 0U, stop_bits = 0U;
int32_t status;
(void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U);
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
(void)ptrUART->Control (ARM_USART_CONTROL_TX, 0U);
(void)ptrUART->Control (ARM_USART_CONTROL_RX, 0U);
switch (line_coding->bCharFormat) {
case 0: // 1 Stop bit
stop_bits = ARM_USART_STOP_BITS_1;
break;
case 1: // 1.5 Stop bits
stop_bits = ARM_USART_STOP_BITS_1_5;
break;
case 2: // 2 Stop bits
stop_bits = ARM_USART_STOP_BITS_2;
break;
default:
return false;
}
switch (line_coding->bParityType) {
case 0: // None
parity = ARM_USART_PARITY_NONE;
break;
case 1: // Odd
parity = ARM_USART_PARITY_ODD;
break;
case 2: // Even
parity = ARM_USART_PARITY_EVEN;
break;
default:
return false;
}
switch (line_coding->bDataBits) {
case 5:
data_bits = ARM_USART_DATA_BITS_5;
break;
case 6:
data_bits = ARM_USART_DATA_BITS_6;
break;
case 7:
data_bits = ARM_USART_DATA_BITS_7;
break;
case 8:
data_bits = ARM_USART_DATA_BITS_8;
break;
default:
return false;
}
status = ptrUART->Control(ARM_USART_MODE_ASYNCHRONOUS |
data_bits |
parity |
stop_bits ,
line_coding->dwDTERate );
if (status != ARM_DRIVER_OK) {
return false;
}
// Store requested settings to local variable
memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
uart_rx_cnt = 0;
usb_tx_cnt = 0;
(void)ptrUART->Control (ARM_USART_CONTROL_TX, 1U);
(void)ptrUART->Control (ARM_USART_CONTROL_RX, 1U);
(void)ptrUART->Receive (uart_rx_buf, UART_BUFFER_SIZE);
return true;
}
// Activate or Deactivate USBD COM PORT
// \param[in] cmd 0=deactivate, 1=activate
// \return 0=Ok, 0xFF=Error
uint8_t USB_COM_PORT_Activate (uint32_t cmd) {
switch (cmd) {
case 0U:
cdc_acm_active = 0U;
USBD_CDC0_ACM_Uninitialize();
break;
case 1U:
USBD_CDC0_ACM_Initialize();
CDC_ACM_Lock();
CDC_ACM_SetLineCoding(&cdc_acm_line_coding);
cdc_acm_active = 1U;
CDC_ACM_Unlock();
break;
}
return 0U;
}
// Called when UART has transmitted or received requested number of bytes.
// \param[in] event UART event
// - ARM_USART_EVENT_SEND_COMPLETE: all requested data was sent
// - ARM_USART_EVENT_RECEIVE_COMPLETE: all requested data was received
static void UART_Callback (uint32_t event) {
int32_t cnt;
if (cdc_acm_active == 0U) {
return;
}
if (event & ARM_USART_EVENT_SEND_COMPLETE) {
// USB -> UART
cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
if (cnt > 0) {
(void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
}
}
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
// UART data received, restart new reception
uart_rx_cnt += UART_BUFFER_SIZE;
(void)ptrUART->Receive(uart_rx_buf, UART_BUFFER_SIZE);
}
}
// Thread: Sends data received on UART to USB
// \param[in] arg not used.
__NO_RETURN static void CDC0_ACM_UART_to_USB_Thread (void *arg) {
int32_t cnt, cnt_to_wrap;
(void)(arg);
for (;;) {
// UART - > USB
if (ptrUART->GetStatus().rx_busy != 0U) {
cnt = uart_rx_cnt;
cnt += (int32_t)ptrUART->GetRxCount();
cnt -= usb_tx_cnt;
if (cnt >= (UART_BUFFER_SIZE - 32)) {
// Dump old data in UART receive buffer if USB is not consuming fast enough
cnt = (UART_BUFFER_SIZE - 32);
usb_tx_cnt = uart_rx_cnt - (UART_BUFFER_SIZE - 32);
}
if (cnt > 0) {
cnt_to_wrap = (int32_t)(UART_BUFFER_SIZE - ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1)));
if (cnt > cnt_to_wrap) {
cnt = cnt_to_wrap;
}
cnt = USBD_CDC_ACM_WriteData(0U, (uart_rx_buf + ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))), cnt);
if (cnt > 0) {
usb_tx_cnt += cnt;
}
}
}
(void)osDelay(10U);
}
}
static osRtxThread_t cdc0_acm_uart_to_usb_thread_cb_mem __SECTION(.bss.os.thread.cb);
static uint64_t cdc0_acm_uart_to_usb_thread_stack_mem[512U / 8U] __SECTION(.bss.os.thread.cdc.stack);
static const osThreadAttr_t cdc0_acm_uart_to_usb_thread_attr = {
"CDC0_ACM_UART_to_USB_Thread",
0U,
&cdc0_acm_uart_to_usb_thread_cb_mem,
sizeof(osRtxThread_t),
&cdc0_acm_uart_to_usb_thread_stack_mem[0],
sizeof(cdc0_acm_uart_to_usb_thread_stack_mem),
osPriorityNormal,
0U,
0U
};
// CDC ACM Callbacks -----------------------------------------------------------
// Called when new data was received from the USB Host.
// \param[in] len number of bytes available to read.
void USBD_CDC0_ACM_DataReceived (uint32_t len) {
int32_t cnt;
(void)(len);
if (cdc_acm_active == 0U) {
return;
}
if (ptrUART->GetStatus().tx_busy == 0U) {
// Start USB -> UART
cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
if (cnt > 0) {
(void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
}
}
}
// Called during USBD_Initialize to initialize the USB CDC class instance (ACM).
void USBD_CDC0_ACM_Initialize (void) {
(void)ptrUART->Initialize (UART_Callback);
(void)ptrUART->PowerControl (ARM_POWER_FULL);
cdc_acm_bridge_tid = osThreadNew (CDC0_ACM_UART_to_USB_Thread, NULL, &cdc0_acm_uart_to_usb_thread_attr);
}
// Called during USBD_Uninitialize to de-initialize the USB CDC class instance (ACM).
void USBD_CDC0_ACM_Uninitialize (void) {
if (osThreadTerminate (cdc_acm_bridge_tid) == osOK) {
cdc_acm_bridge_tid = NULL;
}
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
(void)ptrUART->PowerControl (ARM_POWER_OFF);
(void)ptrUART->Uninitialize ();
}
// Called upon USB Bus Reset Event.
void USBD_CDC0_ACM_Reset (void) {
if (cdc_acm_active == 0U ) {
return;
}
(void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U);
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
}
// Called upon USB Host request to change communication settings.
// \param[in] line_coding pointer to CDC_LINE_CODING structure.
// \return true set line coding request processed.
// \return false set line coding request not supported or not processed.
bool USBD_CDC0_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
bool ret = false;
CDC_ACM_Lock();
if (cdc_acm_active == 0U) {
// Store requested settings to local variable
memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
ret = true;
} else {
ret = CDC_ACM_SetLineCoding(line_coding);
}
CDC_ACM_Unlock();
return ret;
}
// Called upon USB Host request to retrieve communication settings.
// \param[out] line_coding pointer to CDC_LINE_CODING structure.
// \return true get line coding request processed.
// \return false get line coding request not supported or not processed.
bool USBD_CDC0_ACM_GetLineCoding (CDC_LINE_CODING *line_coding) {
// Load settings from ones stored on USBD_CDC0_ACM_SetLineCoding callback
*line_coding = cdc_acm_line_coding;
return true;
}
// Called upon USB Host request to set control line states.
// \param [in] state control line settings bitmap.
// - bit 0: DTR state
// - bit 1: RTS state
// \return true set control line state request processed.
// \return false set control line state request not supported or not processed.
bool USBD_CDC0_ACM_SetControlLineState (uint16_t state) {
// Add code for set control line state
(void)(state);
return true;
}
//! [code_USBD_User_CDC_ACM]

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2016 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_User_CustomClass_0.c
* Purpose: USB Device Custom Class User module
* Rev.: V6.7.3
*----------------------------------------------------------------------------*/
/*
* USBD_User_CustomClass_0.c is a code template for the Custom Class 0
* class request handling. It allows user to handle all Custom Class class
* requests.
*
* Uncomment "Example code" lines to see example that receives data on
* Endpoint 1 OUT and echoes it back on Endpoint 1 IN.
* To try the example you also have to enable Bulk Endpoint 1 IN/OUT in Custom
* Class configuration in USBD_Config_CustomClass_0.h file.
*/
/**
* \addtogroup usbd_custom_classFunctions
*
*/
//! [code_USBD_User_CustomClass]
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "cmsis_os2.h"
#define osObjectsExternal
#include "osObjects.h"
#include "rl_usb.h"
#include "Driver_USBD.h"
#include "DAP_config.h"
#include "DAP.h"
static volatile uint16_t USB_RequestIndexI; // Request Index In
static volatile uint16_t USB_RequestIndexO; // Request Index Out
static volatile uint16_t USB_RequestCountI; // Request Count In
static volatile uint16_t USB_RequestCountO; // Request Count Out
static volatile uint8_t USB_RequestIdle; // Request Idle Flag
static volatile uint16_t USB_ResponseIndexI; // Response Index In
static volatile uint16_t USB_ResponseIndexO; // Response Index Out
static volatile uint16_t USB_ResponseCountI; // Response Count In
static volatile uint16_t USB_ResponseCountO; // Response Count Out
static volatile uint8_t USB_ResponseIdle; // Response Idle Flag
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Request Buffer
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Response Buffer
static uint16_t USB_RespSize[DAP_PACKET_COUNT]; // Response Size
// \brief Callback function called during USBD_Initialize to initialize the USB Custom class instance
void USBD_CustomClass0_Initialize (void) {
// Handle Custom Class Initialization
// Initialize variables
USB_RequestIndexI = 0U;
USB_RequestIndexO = 0U;
USB_RequestCountI = 0U;
USB_RequestCountO = 0U;
USB_RequestIdle = 1U;
USB_ResponseIndexI = 0U;
USB_ResponseIndexO = 0U;
USB_ResponseCountI = 0U;
USB_ResponseCountO = 0U;
USB_ResponseIdle = 1U;
}
// \brief Callback function called during USBD_Uninitialize to de-initialize the USB Custom class instance
void USBD_CustomClass0_Uninitialize (void) {
// Handle Custom Class De-initialization
}
// \brief Callback function called upon USB Bus Reset signaling
void USBD_CustomClass0_Reset (void) {
// Handle USB Bus Reset Event
}
// \brief Callback function called when Endpoint Start was requested (by activating interface or configuration)
// \param[in] ep_addr endpoint address.
void USBD_CustomClass0_EndpointStart (uint8_t ep_addr) {
// Start communication on Endpoint
if (ep_addr == USB_ENDPOINT_OUT(1U)) {
USB_RequestIdle = 0U;
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[0], DAP_PACKET_SIZE);
}
}
// \brief Callback function called when Endpoint Stop was requested (by de-activating interface or activating configuration 0)
// \param[in] ep_addr endpoint address.
void USBD_CustomClass0_EndpointStop (uint8_t ep_addr) {
// Handle Endpoint communication stopped
(void)ep_addr;
}
// \brief Callback function called when Custom Class 0 received SETUP PACKET on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] setup_packet pointer to received setup packet.
// \param[out] buf pointer to data buffer used for data stage requested by setup packet.
// \param[out] len pointer to number of data bytes in data stage requested by setup packet.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet if no data stage)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
usbdRequestStatus USBD_CustomClass0_Endpoint0_SetupPacketReceived (const USB_SETUP_PACKET *setup_packet, uint8_t **buf, uint32_t *len) {
(void)setup_packet;
(void)buf;
(void)len;
switch (setup_packet->bmRequestType.Recipient) {
case USB_REQUEST_TO_DEVICE:
break;
case USB_REQUEST_TO_INTERFACE:
break;
case USB_REQUEST_TO_ENDPOINT:
break;
default:
break;
}
return usbdRequestNotProcessed;
}
// \brief Callback function called when SETUP PACKET was processed by USB library
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback nor by Custom Class callback)
// \param[in] setup_packet pointer to processed setup packet.
void USBD_CustomClass0_Endpoint0_SetupPacketProcessed (const USB_SETUP_PACKET *setup_packet) {
(void)setup_packet;
switch (setup_packet->bmRequestType.Recipient) {
case USB_REQUEST_TO_DEVICE:
break;
case USB_REQUEST_TO_INTERFACE:
break;
case USB_REQUEST_TO_ENDPOINT:
break;
default:
break;
}
}
// \brief Callback function called when Custom Class 0 received OUT DATA on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] len number of received data bytes.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
// \return usbdRequestNAK: request was processed but the device is busy (return NAK)
usbdRequestStatus USBD_CustomClass0_Endpoint0_OutDataReceived (uint32_t len) {
(void)len;
return usbdRequestNotProcessed;
}
// \brief Callback function called when Custom Class 0 sent IN DATA on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] len number of sent data bytes.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (return ACK)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
// \return usbdRequestNAK: request was processed but the device is busy (return NAK)
usbdRequestStatus USBD_CustomClass0_Endpoint0_InDataSent (uint32_t len) {
(void)len;
return usbdRequestNotProcessed;
}
// \brief Callback function called when DATA was sent or received on Endpoint n
// \param[in] event event on Endpoint:
// - ARM_USBD_EVENT_OUT = data OUT received
// - ARM_USBD_EVENT_IN = data IN sent
void USBD_CustomClass0_Endpoint1_Event (uint32_t event) {
// Handle Endpoint 1 events
uint32_t n;
if (event & ARM_USBD_EVENT_OUT) {
n = USBD_EndpointReadGetResult(0U, USB_ENDPOINT_OUT(1U));
if (n != 0U) {
if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) {
DAP_TransferAbort = 1U;
} else {
USB_RequestIndexI++;
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
USB_RequestIndexI = 0U;
}
USB_RequestCountI++;
osThreadFlagsSet(DAP_ThreadId, 0x01);
}
}
// Start reception of next request packet
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
} else {
USB_RequestIdle = 1U;
}
}
if (event & ARM_USBD_EVENT_IN) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]);
USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
} else {
USB_ResponseIdle = 1U;
}
}
}
void USBD_CustomClass0_Endpoint2_Event (uint32_t event) {
// Handle Endpoint 2 events
if (event & ARM_USBD_EVENT_IN) {
SWO_TransferComplete();
}
}
void USBD_CustomClass0_Endpoint3_Event (uint32_t event) {
// Handle Endpoint 3 events
(void)event;
}
void USBD_CustomClass0_Endpoint4_Event (uint32_t event) {
// Handle Endpoint 4 events
(void)event;
}
void USBD_CustomClass0_Endpoint5_Event (uint32_t event) {
// Handle Endpoint 5 events
(void)event;
}
void USBD_CustomClass0_Endpoint6_Event (uint32_t event) {
// Handle Endpoint 6 events
(void)event;
}
void USBD_CustomClass0_Endpoint7_Event (uint32_t event) {
// Handle Endpoint 7 events
(void)event;
}
void USBD_CustomClass0_Endpoint8_Event (uint32_t event) {
// Handle Endpoint 8 events
(void)event;
}
void USBD_CustomClass0_Endpoint9_Event (uint32_t event) {
// Handle Endpoint 9 events
(void)event;
}
void USBD_CustomClass0_Endpoint10_Event (uint32_t event) {
// Handle Endpoint 10 events
(void)event;
}
void USBD_CustomClass0_Endpoint11_Event (uint32_t event) {
// Handle Endpoint 11 events
(void)event;
}
void USBD_CustomClass0_Endpoint12_Event (uint32_t event) {
// Handle Endpoint 12 events
(void)event;
}
void USBD_CustomClass0_Endpoint13_Event (uint32_t event) {
// Handle Endpoint 13 events
(void)event;
}
void USBD_CustomClass0_Endpoint14_Event (uint32_t event) {
// Handle Endpoint 14 events
(void)event;
}
void USBD_CustomClass0_Endpoint15_Event (uint32_t event) {
// Handle Endpoint 15 events
(void)event;
}
// DAP Thread.
__NO_RETURN void DAP_Thread (void *argument) {
uint32_t flags;
uint32_t n;
(void) argument;
for (;;) {
osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
// Process pending requests
while (USB_RequestCountI != USB_RequestCountO) {
// Handle Queue Commands
n = USB_RequestIndexO;
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
USB_Request[n][0] = ID_DAP_ExecuteCommands;
n++;
if (n == DAP_PACKET_COUNT) {
n = 0U;
}
if (n == USB_RequestIndexI) {
flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
if (flags & 0x80U) {
break;
}
}
}
// Execute DAP Command (process request and prepare response)
USB_RespSize[USB_ResponseIndexI] =
(uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
// Update Request Index and Count
USB_RequestIndexO++;
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
USB_RequestIndexO = 0U;
}
USB_RequestCountO++;
if (USB_RequestIdle) {
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
USB_RequestIdle = 0U;
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
}
}
// Update Response Index and Count
USB_ResponseIndexI++;
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
USB_ResponseIndexI = 0U;
}
USB_ResponseCountI++;
if (USB_ResponseIdle) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
n = USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
USB_ResponseIdle = 0U;
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[n], USB_RespSize[n]);
}
}
}
}
}
// SWO Data Queue Transfer
// buf: pointer to buffer with data
// num: number of bytes to transfer
void SWO_QueueTransfer (uint8_t *buf, uint32_t num) {
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(2U), buf, num);
}
// SWO Data Abort Transfer
void SWO_AbortTransfer (void) {
USBD_EndpointAbort(0U, USB_ENDPOINT_IN(2U));
}
//! [code_USBD_User_CustomClass]

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/*
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 21. May 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: main.c CMSIS-DAP Main module for LPC-Link2
*
*---------------------------------------------------------------------------*/
#include "cmsis_os2.h"
#include "osObjects.h"
#include "rl_usb.h"
#include "DAP_config.h"
#include "DAP.h"
// Application Main program
__NO_RETURN void app_main (void *argument) {
(void)argument;
DAP_Setup(); // DAP Setup
USBD_Initialize(0U); // USB Device Initialization
#ifdef LPC_LINK2_ONBOARD
char *ser_num;
ser_num = GetSerialNum();
if (ser_num != NULL) {
USBD_SetSerialNumber(0U, ser_num); // Update Serial Number
}
#endif
USBD_Connect(0U); // USB Device Connect
while (!USBD_Configured(0U)); // Wait for USB Device to configure
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
LED_RUNNING_OUT(1U); // Turn on Target Running LED
Delayms(500U); // Wait for 500ms
LED_RUNNING_OUT(0U); // Turn off Target Running LED
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
// Create DAP Thread
DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr);
// Create SWO Thread
SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr);
osDelay(osWaitForever);
for (;;) {}
}
int main (void) {
SystemCoreClockUpdate();
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
if (osKernelGetState() == osKernelReady) {
osKernelStart(); // Start thread execution
}
for (;;) {}
}

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 11. June 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: osObjects.h CMSIS-DAP RTOS2 Objects for LPC-Link2
*
*---------------------------------------------------------------------------*/
#ifndef __osObjects_h__
#define __osObjects_h__
#include "cmsis_os2.h"
#ifdef osObjectsExternal
extern osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
#else
static const osThreadAttr_t DAP_ThreadAttr = {
.priority = osPriorityNormal
};
static const osThreadAttr_t SWO_ThreadAttr = {
.priority = osPriorityAboveNormal
};
extern osThreadId_t DAP_ThreadId;
osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
osThreadId_t SWO_ThreadId;
#endif
extern void DAP_Thread (void *argument);
extern void SWO_Thread (void *argument);
extern void app_main (void *argument);
#endif /* __osObjects_h__ */

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/*
* Copyright (c) 2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 27. May 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: ser_num.c CMSIS-DAP Serial Number module for LPC-Link2
*
*---------------------------------------------------------------------------*/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "ser_num.h"
// Serial Number
#define SER_NUM_PREFIX "00A1"
static char SerialNum[32];
#define IAP_LOCATION *(volatile unsigned int *)(0x10400100)
#define IAP_READ_DEVICE_SERIAL_NUMBER 58U
typedef void (*IAP)(unsigned int [],unsigned int[]);
/**
\brief Calculate 32-bit CRC (polynom: 0x04C11DB7, init value: 0xFFFFFFFF)
\param[in] data pointer to data
\param[in] len data length (in bytes)
\return CRC32 value
*/
static uint32_t crc32 (const uint8_t *data, uint32_t len) {
uint32_t crc32;
uint32_t n;
crc32 = 0xFFFFFFFFU;
while (len != 0U) {
crc32 ^= ((uint32_t)*data++) << 24U;
for (n = 8U; n; n--) {
if (crc32 & 0x80000000U) {
crc32 <<= 1U;
crc32 ^= 0x04C11DB7U;
} else {
crc32 <<= 1U;
}
}
len--;
}
return (crc32);
}
/**
\brief Get serial number string. First characters are fixed. Last eight
characters are Unique (calculated from devices's unique ID)
\return Serial number string or NULL (callculation of unique ID failed)
*/
char *GetSerialNum (void) {
uint32_t command_param[5];
uint32_t status_result[5];
uint32_t uid;
char *str;
IAP iap_entry;
memset(command_param, 0, sizeof(command_param));
memset(status_result, 0, sizeof(status_result));
iap_entry = (IAP)IAP_LOCATION;
command_param[0] = IAP_READ_DEVICE_SERIAL_NUMBER;
iap_entry(command_param, status_result);
str = NULL;
if (status_result[0] == 0U) {
uid = crc32 ((uint8_t *)&status_result[1], 16U);
snprintf(SerialNum, sizeof(SerialNum), "%s%08X", SER_NUM_PREFIX, uid);
str = SerialNum;
}
return (str);
}

33
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.h vendored Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (c) 2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 27. May 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: ser_num.h CMSIS-DAP Serial Number module for LPC-Link2
*
*---------------------------------------------------------------------------*/
#ifndef __SER_NUM_H__
#define __SER_NUM_H__
char *GetSerialNum (void);
#endif /* __SER_NUM_H__ */

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/target.c vendored Normal file
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@ -0,0 +1,35 @@
/*
* Copyright (c) 2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 16. June 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: target.c CMSIS-DAP Target Device/Board information (patchable)
*
*---------------------------------------------------------------------------*/
#include "DAP_config.h"
#if TARGET_FIXED != 0
const char TargetDeviceVendor [64] = TARGET_DEVICE_VENDOR;
const char TargetDeviceName [64] = TARGET_DEVICE_NAME;
const char TargetBoardVendor [64] = TARGET_BOARD_VENDOR;
const char TargetBoardName [64] = TARGET_BOARD_NAME;
#endif

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvguix vendored Normal file
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480
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvoptx vendored Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>MCU-LINK</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>8</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI_V8M</Key>
<Name>-X"ULINKplus CMSIS-DAP" -UL68410450A -O206 -S9 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>EVENTREC_CNF</Key>
<Name>-l0 -a1 -s0 -f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ULPL2CM3</Key>
<Name>-UL68410450A -O718 -S9 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(6010=75,104,552,700,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>-UAny -O206 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<ScvdPack>
<Filename>C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.13.0\USB\USB.scvd</Filename>
<Type>Keil.MDK-Middleware.7.13.0</Type>
<SubType>1</SubType>
</ScvdPack>
<ScvdPack>
<Filename>C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.8.0\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
<Type>ARM.CMSIS.5.8.0</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>1</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>5000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>Source</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
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<bDave2>0</bDave2>
<PathWithFileName>.\ser_num.c</PathWithFileName>
<FilenameWithoutPath>ser_num.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\USBD_User_CustomClass_0.c</PathWithFileName>
<FilenameWithoutPath>USBD_User_CustomClass_0.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
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<bDave2>0</bDave2>
<PathWithFileName>.\USBD_User_CDC_ACM_UART_0.c</PathWithFileName>
<FilenameWithoutPath>USBD_User_CDC_ACM_UART_0.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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<PathWithFileName>.\USBD1_LPC55xxx.c</PathWithFileName>
<FilenameWithoutPath>USBD1_LPC55xxx.c</FilenameWithoutPath>
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</File>
<File>
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<bDave2>0</bDave2>
<PathWithFileName>.\fsl_usart.c</PathWithFileName>
<FilenameWithoutPath>fsl_usart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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</File>
</Group>
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<PathWithFileName>.\README.md</PathWithFileName>
<FilenameWithoutPath>README.md</FilenameWithoutPath>
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</File>
</Group>
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</File>
<File>
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<PathWithFileName>.\board\peripherals.c</PathWithFileName>
<FilenameWithoutPath>peripherals.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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</File>
<File>
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<PathWithFileName>.\board\pin_mux.c</PathWithFileName>
<FilenameWithoutPath>pin_mux.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>CMSIS DAP</GroupName>
<tvExp>1</tvExp>
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<File>
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<FileNumber>11</FileNumber>
<FileType>5</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\DAP_config.h</PathWithFileName>
<FilenameWithoutPath>DAP_config.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\DAP.c</PathWithFileName>
<FilenameWithoutPath>DAP.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\JTAG_DP.c</PathWithFileName>
<FilenameWithoutPath>JTAG_DP.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\SW_DP.c</PathWithFileName>
<FilenameWithoutPath>SW_DP.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\SWO.c</PathWithFileName>
<FilenameWithoutPath>SWO.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\UART.c</PathWithFileName>
<FilenameWithoutPath>UART.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
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<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::CMSIS Driver</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::USB</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvprojx vendored Normal file
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@ -0,0 +1,955 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>MCU-LINK</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>LPC55S69JBD64:cm33_core0</Device>
<Vendor>NXP</Vendor>
<PackID>NXP.LPC55S69_DFP.13.1.0</PackID>
<PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
<Cpu>IRAM(0x20000000,0x040000) IRAM2(0x20040000,0x4000) IROM(0x00000000,0x098000) XRAM(0x04000000,0x8000) XRAM2(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:LPC55S69JBD64$fsl_device_registers.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:LPC55S69JBD64$LPC55S69_cm33_core0.xml</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>CMSIS_DAP</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName></SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll></SimDlgDll>
<SimDlgDllArguments></SimDlgDllArguments>
<TargetDllName>SARMV8M.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4102</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2V8M.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M33"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>1</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>1</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>2</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x40000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x98000</Size>
</IROM>
<XRAM>
<Type>1</Type>
<StartAddress>0x4000000</StartAddress>
<Size>0x8000</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x98000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x4000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x40100000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x20040000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>3</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>.;.\board;..\..\Include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x10000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash.scf</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--diag_suppress=L6314</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
<File>
<FileName>ser_num.c</FileName>
<FileType>1</FileType>
<FilePath>.\ser_num.c</FilePath>
</File>
<File>
<FileName>USBD_User_CustomClass_0.c</FileName>
<FileType>1</FileType>
<FilePath>.\USBD_User_CustomClass_0.c</FilePath>
</File>
<File>
<FileName>USBD_User_CDC_ACM_UART_0.c</FileName>
<FileType>1</FileType>
<FilePath>.\USBD_User_CDC_ACM_UART_0.c</FilePath>
</File>
<File>
<FileName>USBD1_LPC55xxx.c</FileName>
<FileType>1</FileType>
<FilePath>.\USBD1_LPC55xxx.c</FilePath>
</File>
<File>
<FileName>fsl_usart.c</FileName>
<FileType>1</FileType>
<FilePath>.\fsl_usart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Documentation</GroupName>
<Files>
<File>
<FileName>README.md</FileName>
<FileType>5</FileType>
<FilePath>.\README.md</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Board</GroupName>
<Files>
<File>
<FileName>clock_config.c</FileName>
<FileType>1</FileType>
<FilePath>.\board\clock_config.c</FilePath>
</File>
<File>
<FileName>peripherals.c</FileName>
<FileType>1</FileType>
<FilePath>.\board\peripherals.c</FilePath>
</File>
<File>
<FileName>pin_mux.c</FileName>
<FileType>1</FileType>
<FilePath>.\board\pin_mux.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CMSIS DAP</GroupName>
<Files>
<File>
<FileName>DAP_config.h</FileName>
<FileType>5</FileType>
<FilePath>.\DAP_config.h</FilePath>
</File>
<File>
<FileName>DAP.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\DAP.c</FilePath>
</File>
<File>
<FileName>JTAG_DP.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\JTAG_DP.c</FilePath>
</File>
<File>
<FileName>SW_DP.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\SW_DP.c</FilePath>
</File>
<File>
<FileName>SWO.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\SWO.c</FilePath>
</File>
<File>
<FileName>UART.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\UART.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::CMSIS Driver</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<ClangAsOpt>0</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
</Group>
<Group>
<GroupName>::Device</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<ClangAsOpt>0</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
</Group>
<Group>
<GroupName>::USB</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<packages>
<filter>
<targetInfos/>
</filter>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0">
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</package>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0">
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</package>
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0">
<targetInfos>
<targetInfo name="MCU-LINK" versionMatchMode="fixed"/>
</targetInfos>
</package>
</packages>
<apis>
<api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" exclusive="0">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</api>
<api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" exclusive="0">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</api>
<api Capiversion="2.1.2" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</api>
</apis>
<components>
<component Capiversion="2.4.0" Cclass="CMSIS Driver" Cgroup="USART" Csub="Custom" Cvendor="ARM" Cversion="1.0.0" custom="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Capiversion="2.3.0" Cclass="CMSIS Driver" Cgroup="USB Device" Csub="Custom" Cvendor="ARM" Cversion="1.0.0" custom="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.5.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.3" condition="RTOS2 RTX5">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cbundle="MDK-Plus" Cclass="USB" Cgroup="CORE" Cvariant="Release" Cvendor="Keil" Cversion="6.15.0" condition="USB Core">
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="CDC" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="8">
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="Custom Class" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Capiversion="2.3.0" Cclass="CMSIS Driver" Cgroup="USART" Csub="flexcomm_usart_cmsis" Cvendor="NXP" Cversion="2.2.0" condition="device.LPC55S69_AND_CMSIS_Driver_Include.USART_AND_RTE_Device_AND_driver.flexcomm_usart_dma">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="CMSIS" Csub="LPC55S69_system" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_device.LPC55S69_CMSIS">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="clock" Cvendor="NXP" Cversion="2.3.3" condition="device.LPC55S69_AND__driver.power_OR_driver.power_s__AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="common" Cvendor="NXP" Cversion="2.3.0" condition="device.LPC55S69_AND_device.LPC55S69_CMSIS_AND_driver.clock_AND_driver.reset">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="dma" Cvendor="NXP" Cversion="2.4.2" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="flexcomm" Cvendor="NXP" Cversion="2.0.2" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="gpio" Cvendor="NXP" Cversion="2.1.7" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="iap1" Cvendor="NXP" Cversion="2.1.3" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="iocon" Cvendor="NXP" Cversion="2.2.0" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="lists" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="power" Cvendor="NXP" Cversion="2.0.0" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="reset" Cvendor="NXP" Cversion="2.0.1" condition="device.LPC55S69_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="usart" Cvendor="NXP" Cversion="2.6.0" condition="device.LPC55S69_AND_driver.flexcomm">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo excluded="1" name="MCU-LINK" versionMatchMode=""/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="usart_adapter" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.common_AND_driver.flexcomm_AND_driver.flexcomm_usart">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Drivers" Csub="usart_dma" Cvendor="NXP" Cversion="2.6.0" condition="device.LPC55S69_AND_driver.flexcomm_AND_driver.flexcomm_usart_AND_driver.lpc_dma">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Project Template" Csub="RTE_Device" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.lpc_dma">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Utilities" Csub="assert" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_utility.debug_console">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Utilities" Csub="debug_console" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_component.serial_manager_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Utilities" Csub="serial_manager" Cvendor="NXP" Cversion="1.0.1" condition="device.LPC55S69_AND__component.serial_manager_swo_OR_component.serial_manager_uart_OR_component.serial_manager_virtual__AND_component.lists_AND_driver.common">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="SDK Utilities" Csub="serial_manager_uart" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_component.serial_manager_AND_component.usart_adapter_AND_driver.flexcomm_usart">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system">
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.1">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.3" condition="RTOS2 RTX5"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.2">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.3" condition="RTOS2 RTX5"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_flash.scf" version="1.1.0">
<instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash.scf</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_flash_ns.scf" version="1.1.0">
<instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash_ns.scf</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_flash_s.scf" version="1.1.0">
<instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash_s.scf</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_ram.scf" version="1.1.0">
<instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_ram.scf</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="header" name="template\RTE_Device.h" version="1.0.0">
<instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\RTE_Device.h</instance>
<component Cclass="Device" Cgroup="SDK Project Template" Csub="RTE_Device" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.lpc_dma"/>
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="sourceAsm" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\startup_LPC55S69_cm33_core0.S" version="1.1.0">
<instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\startup_LPC55S69_cm33_core0.S</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
<package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="source" name="USB\Config\USBD_Config.c" version="5.2.0">
<instance index="0">RTE\USB\USBD_Config_0.c</instance>
<component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="header" name="USB\Config\USBD_Config_CDC.h" version="5.2.0">
<instance index="0">RTE\USB\USBD_Config_CDC_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="CDC" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="8"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
<file attr="config" category="header" name="USB\Config\USBD_Config_CustomClass.h" version="5.2.0">
<instance index="0">RTE\USB\USBD_Config_CustomClass_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="Custom Class" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
<targetInfos>
<targetInfo name="MCU-LINK"/>
</targetInfos>
</file>
</files>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>CMSIS_DAP</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DAP_config.h vendored Normal file
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@ -0,0 +1,651 @@
/*
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. September 2021
* $Revision: V2.1.0
*
* Project: CMSIS-DAP Examples MCU-LINK
* Title: DAP_config.h CMSIS-DAP Configuration File for MCU-LINK
*
*---------------------------------------------------------------------------*/
#ifndef __DAP_CONFIG_H__
#define __DAP_CONFIG_H__
//**************************************************************************************************
/**
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
\ingroup DAP_ConfigIO_gr
@{
Provides definitions about the hardware and configuration of the Debug Unit.
This information includes:
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
- Debug Unit Identification strings (Vendor, Product, Serial Number).
- Debug Unit communication packet size.
- Debug Access Port supported modes and settings (JTAG/SWD and SWO).
- Optional information about a connected Target Device (for Evaluation Boards).
*/
#ifdef _RTE_
#include "RTE_Components.h"
#include CMSIS_device_header
#else
#include "device.h" // Debug Unit Cortex-M Processor Header File
#endif
#include "pin_mux.h"
#include "fsl_gpio.h"
#include "ser_num.h"
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
/// This value is used to calculate the SWD/JTAG clock speed.
#define CPU_CLOCK 150000000U ///< Specifies the CPU Clock in Hz.
/// Number of processor cycles for I/O Port write operations.
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
/// required.
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
/// Indicate that JTAG communication mode is available at the Debug Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
/// Default communication mode on the Debug Access Port.
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
/// Used to initialize the default SWD/JTAG clock frequency.
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
/// Maximum Package Size for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes.
/// Maximum Package Buffers for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
/// setting can be reduced (valid range is 1 .. 255).
#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered.
/// Indicate that UART Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART SWO.
#define SWO_UART_DRIVER 3 ///< USART Driver instance number (Driver_USART#).
/// Maximum SWO UART Baudrate.
#define SWO_UART_MAX_BAUDRATE 9000000U ///< SWO UART Maximum Baudrate in Hz.
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
/// SWO Trace Buffer Size.
#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n).
/// SWO Streaming Trace.
#define SWO_STREAM 1 ///< SWO Streaming Trace: 1 = available, 0 = not available.
/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
#define TIMESTAMP_CLOCK 150000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
/// Indicate that UART Communication Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART Communication Port.
#define DAP_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#).
/// UART Receive Buffer Size.
#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n).
/// UART Transmit Buffer Size.
#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n).
/// Indicate that UART Communication via USB COM Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available.
/// Debug Unit is connected to fixed Target Device.
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings
/// are stored and may be used by the debugger or IDE to configure device parameters.
#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown;
#define TARGET_DEVICE_VENDOR "NXP" ///< String indicating the Silicon Vendor
#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device
#define TARGET_BOARD_VENDOR "NXP" ///< String indicating the Board Vendor
#define TARGET_BOARD_NAME "NXP board" ///< String indicating the Board Name
#if TARGET_FIXED != 0
#include <string.h>
static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;
static const char TargetDeviceName [] = TARGET_DEVICE_NAME;
static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR;
static const char TargetBoardName [] = TARGET_BOARD_NAME;
#endif
/** Get Vendor Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
(void)str;
return (0U);
}
/** Get Product Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
(void)str;
return (0U);
}
/** Get Serial Number string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
uint8_t len = 0U;
char *ser_num;
ser_num = GetSerialNum();
if (ser_num != NULL) {
strcpy(str, ser_num);
len = (uint8_t)(strlen(ser_num) + 1U);
}
return (len);
}
/** Get Target Device Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceVendor);
len = (uint8_t)(strlen(TargetDeviceVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Device Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceName);
len = (uint8_t)(strlen(TargetDeviceName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardVendor);
len = (uint8_t)(strlen(TargetBoardVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardName);
len = (uint8_t)(strlen(TargetBoardName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Product Firmware Version string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
(void)str;
return (0U);
}
///@}
// Debug Port I/O Pins
//SWO/TDO
#define PIN_SWO_TDO_PORT (0U)
#define PIN_SWO_TDO_PIN (3U)
//**************************************************************************************************
/**
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
\ingroup DAP_ConfigIO_gr
@{
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
interface of a device. The following I/O Pins are provided:
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
---------------------------- | -------------------- | ---------------------------------------------
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
TDI: Test Data Input | | Output Push/Pull
TDO: Test Data Output | | Input
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
DAP Hardware I/O Pin Access Functions
-------------------------------------
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
these I/O Pins.
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
peripherals that can independently write/read a single I/O pin without affecting any other pins
of the same I/O port. The following SWDIO I/O Pin functions are provided:
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
*/
// Configure DAP I/O pins ------------------------------
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Configures the DAP Hardware I/O pins for JTAG mode:
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
- TDO to input mode.
*/
__STATIC_INLINE void PORT_JTAG_SETUP (void) {
// TCK
DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
DBGIF_TCK_SWCLK_GPIO->DIRSET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
// TDI
DBGIF_TDI_GPIO->SET[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN);
DBGIF_TDI_GPIO->DIRSET[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN);
// TMS
DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
// nRESET
DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
// TDO
GPIO->DIRCLR[PIN_SWO_TDO_PORT] = (1U << PIN_SWO_TDO_PIN);
}
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
*/
__STATIC_INLINE void PORT_SWD_SETUP (void) {
// SWCLK
DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
DBGIF_TCK_SWCLK_GPIO->DIRSET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
// SWDIO
DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
// nRESET
DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
// TDI
DBGIF_TDI_GPIO->DIRCLR[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN);
}
/** Disable JTAG/SWD I/O Pins.
Disables the DAP Hardware I/O pins which configures:
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
*/
__STATIC_INLINE void PORT_OFF (void) {
// TCK/SWCLK
DBGIF_TCK_SWCLK_GPIO->DIRCLR[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
// TMS/SWDIO
DBGIF_TMS_SWDIO_TXEN_GPIO->CLR[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
DBGIF_TMS_SWDIO_GPIO->DIRCLR[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
// nRESET
DBGIF_RESET_TXEN_GPIO->CLR[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
DBGIF_RESET_GPIO->DIRCLR[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
// TDI
DBGIF_TDI_GPIO->DIRCLR[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN);
// TDO
GPIO->DIRCLR[PIN_SWO_TDO_PORT] = (1U << PIN_SWO_TDO_PIN);
}
// SWCLK/TCK I/O pin -------------------------------------
/** SWCLK/TCK I/O pin: Get Input.
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
return ((DBGIF_TCK_SWCLK_GPIO->PIN[DBGIF_TCK_SWCLK_PORT] >> DBGIF_TCK_SWCLK_PIN) & 1U);
}
/** SWCLK/TCK I/O pin: Set Output to High.
Set the SWCLK/TCK DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
}
/** SWCLK/TCK I/O pin: Set Output to Low.
Set the SWCLK/TCK DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
DBGIF_TCK_SWCLK_GPIO->CLR[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
}
// SWDIO/TMS Pin I/O --------------------------------------
/** SWDIO/TMS I/O pin: Get Input.
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
return ((DBGIF_TMS_SWDIO_GPIO->PIN[DBGIF_TMS_SWDIO_PORT] >> DBGIF_TMS_SWDIO_PIN) & 1U);
}
/** SWDIO/TMS I/O pin: Set Output to High.
Set the SWDIO/TMS DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
}
/** SWDIO/TMS I/O pin: Set Output to Low.
Set the SWDIO/TMS DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
DBGIF_TMS_SWDIO_GPIO->CLR[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
}
/** SWDIO I/O pin: Get Input (used in SWD mode only).
\return Current status of the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
return (DBGIF_TMS_SWDIO_GPIO->B[DBGIF_TMS_SWDIO_PORT][DBGIF_TMS_SWDIO_PIN]);
}
/** SWDIO I/O pin: Set Output (used in SWD mode only).
\param bit Output value for the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) {
DBGIF_TMS_SWDIO_GPIO->B[DBGIF_TMS_SWDIO_PORT][DBGIF_TMS_SWDIO_PIN] = bit;
}
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
called prior \ref PIN_SWDIO_OUT function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
}
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
called prior \ref PIN_SWDIO_IN function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
DBGIF_TMS_SWDIO_TXEN_GPIO->CLR[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
DBGIF_TMS_SWDIO_GPIO->DIRCLR[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
}
// TDI Pin I/O ---------------------------------------------
/** TDI I/O pin: Get Input.
\return Current status of the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
return (DBGIF_TDI_GPIO->B[DBGIF_TDI_PORT][DBGIF_TDI_PIN]);
}
/** TDI I/O pin: Set Output.
\param bit Output value for the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
DBGIF_TDI_GPIO->B[DBGIF_TDI_PORT][DBGIF_TDI_PIN] = bit;
}
// TDO Pin I/O ---------------------------------------------
/** TDO I/O pin: Get Input.
\return Current status of the TDO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
return (GPIO->B[PIN_SWO_TDO_PORT][PIN_SWO_TDO_PIN]);
}
// nTRST Pin I/O -------------------------------------------
/** nTRST I/O pin: Get Input.
\return Current status of the nTRST DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
return (0U); // Not available
}
/** nTRST I/O pin: Set Output.
\param bit JTAG TRST Test Reset pin status:
- 0: issue a JTAG TRST Test Reset.
- 1: release JTAG TRST Test Reset.
*/
__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
(void) bit;
// Not available
}
// nRESET Pin I/O------------------------------------------
/** nRESET I/O pin: Get Input.
\return Current status of the nRESET DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
return ((DBGIF_RESET_GPIO->PIN[DBGIF_RESET_PORT] >> DBGIF_RESET_PIN) & 1U);
}
/** nRESET I/O pin: Set Output.
\param bit target device hardware reset pin status:
- 0: issue a device hardware reset.
- 1: release device hardware reset.
*/
__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
if (bit) {
DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
DBGIF_RESET_TXEN_GPIO->CLR[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
DBGIF_RESET_GPIO->DIRCLR[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
} else {
DBGIF_RESET_GPIO->CLR[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN);
DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
}
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
It is recommended to provide the following LEDs for status indication:
- Connect LED: is active when the DAP hardware is connected to a debugger.
- Running LED: is active when the debugger has put the target device into running state.
*/
/** Debug Unit: Set status of Connected LED.
\param bit status of the Connect LED.
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
*/
__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
if (bit) {
LED1_GPIO->CLR[LED1_PORT] = (1U << LED1_PIN);
} else {
LED1_GPIO->SET[LED1_PORT] = (1U << LED1_PIN);
}
}
/** Debug Unit: Set status Target Running LED.
\param bit status of the Target Running LED.
- 1: Target Running LED ON: program execution in target started.
- 0: Target Running LED OFF: program execution in target stopped.
*/
__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
(void) bit;
// Not available
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
\ingroup DAP_ConfigIO_gr
@{
Access function for Test Domain Timer.
The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
*/
/** Get timestamp of Test Domain Timer.
\return Current timestamp value.
*/
__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
return (DWT->CYCCNT);
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
*/
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
- I/O clock system enabled.
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
- for nTRST, nRESET a weak pull-up (if available) is enabled.
- LED output pins are enabled and LEDs are turned off.
*/
__STATIC_INLINE void DAP_SETUP (void) {
BOARD_InitBootPins();
}
/** Reset Target Device with custom specific I/O pin or command sequence.
This function allows the optional implementation of a device specific reset sequence.
It is called when the command \ref DAP_ResetTarget and is for example required
when a device needs a time-critical unlock sequence that enables the debug port.
\return 0 = no device specific reset sequence is implemented.\n
1 = a device specific reset sequence is implemented.
*/
__STATIC_INLINE uint8_t RESET_TARGET (void) {
return (0U); // change to '1' when a device reset sequence is implemented
}
///@}
#endif /* __DAP_CONFIG_H__ */

18
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DebugConfig/MCU-Link_LPC55S69JBD64_cm33_core0.dbgconf vendored Normal file
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@ -0,0 +1,18 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <o0> SWO pin
// <i> The SWO (Serial Wire Output) pin optionally provides data from the ITM
// <i> for an external debug tool to evaluate.
// <0=> PIO0_10
// <1=> PIO0_8
SWO_Pin = 0;
//
// <h>Debug Configuration
// <o.0> StopAfterBootloader <i> Stop after Bootloader
// </h>
Dbg_CR = 0x00000001;
//
// <<< end of configuration section >>>

743
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/MCU-Link.mex vendored Normal file
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@ -0,0 +1,743 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MCU-LINK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.9 http://mcuxpresso.nxp.com/XSD/mex_configuration_1.9.xsd" uuid="ec487fd8-754b-47b3-bbcd-ee484cc22247" version="1.9" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.9" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>LPC55S69</processor>
<package>LPC55S69JBD64</package>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="cm33_core0">
<core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/>
<core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
</preferences>
<tools>
<pins name="Pins" version="9.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>9.0.3</processor_version>
<pin_labels>
<pin_label pin_num="36" pin_signal="PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A" label="_DBGIF_TCK_SWCLK" identifier="DBGIF_TCK_SWCLK"/>
<pin_label pin_num="2" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="_DBGIF_TDI" identifier="DBGIF_TDI"/>
<pin_label pin_num="52" pin_signal="PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2" label="_DBGIF_TMS_SWDIO" identifier="DBGIF_TMS_SWDIO"/>
<pin_label pin_num="44" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28" label="_DBGIF_TMS_SWDIO_TXEN" identifier="DBGIF_TMS_SWDIO_TXEN"/>
<pin_label pin_num="58" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19" label="_DBGIF_RESET" identifier="DBG_IF_RESET;DBGIF_RESET"/>
<pin_label pin_num="46" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13" label="_DBGIF_RESET_TXEN" identifier="DBG_IF_RESET_TXEN;DBGIF_RESET_TXEN"/>
<pin_label pin_num="53" pin_signal="PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3" label="_DBGIF_TDO_SWO" identifier="DBG_IF_TDO_SWO;DBGIF_TDO_SWO"/>
<pin_label pin_num="45" pin_signal="PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24" label="_FC0_TARGET_RXD" identifier="FC0_TARGET_RXD"/>
<pin_label pin_num="51" pin_signal="PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25" label="_FC0_TARGET_TXD" identifier="FC0_TARGET_TXD"/>
<pin_label pin_num="56" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5" label="_LED1" identifier="LED1"/>
</pin_labels>
</pins_profile>
<functions_list>
<function name="MCU_LINK_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<prefix></prefix>
<coreID>cm33_core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="FLEXCOMM3" description="Peripheral FLEXCOMM3 is not initialized" problem_level="1" source="Pins:MCU_LINK_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 is not initialized" problem_level="1" source="Pins:MCU_LINK_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH is not initialized" problem_level="1" source="Pins:MCU_LINK_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:MCU_LINK_InitPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core1">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:MCU_LINK_InitPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core1">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO" signal="PIO0, 0" pin_num="36" pin_signal="PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="GPIO" signal="PIO0, 1" pin_num="2" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="GPIO" signal="PIO0, 2" pin_num="52" pin_signal="PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="mode" value="inactive"/>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="GPIO" signal="PIO0, 28" pin_num="44" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="gpio_init_state" value="false"/>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="GPIO" signal="PIO0, 19" pin_num="58" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19">
<pin_features>
<pin_feature name="identifier" value="DBGIF_RESET"/>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="GPIO" signal="PIO0, 13" pin_num="46" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13">
<pin_features>
<pin_feature name="identifier" value="DBGIF_RESET_TXEN"/>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="gpio_init_state" value="false"/>
</pin_features>
</pin>
<pin peripheral="FLEXCOMM3" signal="RXD_SDA_MOSI_DATA" pin_num="53" pin_signal="PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3">
<pin_features>
<pin_feature name="identifier" value="DBGIF_TDO_SWO"/>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="45" pin_signal="PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="51" pin_signal="PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
</pin_features>
</pin>
<pin peripheral="USBHSH" signal="USB_DP" pin_num="23" pin_signal="USB1_DP"/>
<pin peripheral="USBHSH" signal="USB_DM" pin_num="24" pin_signal="USB1_DM"/>
<pin peripheral="USBHSH" signal="USB_VBUS" pin_num="25" pin_signal="USB1_VBUS"/>
<pin peripheral="USBHSH" signal="USB_VSS" pin_num="22" pin_signal="USB1_VSS22"/>
<pin peripheral="USBHSH" signal="USB_VSS" pin_num="26" pin_signal="USB1_VSS26"/>
<pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="41" pin_signal="PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5"/>
<pin peripheral="GPIO" signal="PIO0, 5" pin_num="56" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="gpio_init_state" value="true"/>
<pin_feature name="mode" value="pullUp"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="7.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>9.0.3</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="cm33_core1">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="cm33_core1">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="cm33_core1">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/>
<clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FXCOM3_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="System_clock.outFreq" value="150 MHz" locked="true" accuracy="0.001"/>
<clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="PLL0_Mode" value="Normal" locked="false"/>
<setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/>
<setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
<setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/>
<setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
<setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.FROHFDIV" locked="false"/>
<setting id="SYSCON.FCCLKSEL3.sel" value="SYSCON.FROHFDIV" locked="false"/>
<setting id="SYSCON.FRGCTRL3_DIV.scale" value="256" locked="true"/>
<setting id="SYSCON.FROHFDIV.scale" value="2" locked="true"/>
<setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/>
<setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
<setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/>
<setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/>
<setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>0.0.0</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcdx>
<periphs name="Peripherals" version="9.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/peripherals.c" update_enabled="true"/>
<file path="board/peripherals.h" update_enabled="true"/>
</generated_project_files>
<peripherals_profile>
<processor_version>9.0.3</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="85f4cd0c-3b58-4e23-a413-239f6952f139" called_from_default_init="true" id_prefix="" core="cm33_core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="NVIC" uuid="96d19cd9-5329-408b-ab68-cd8a2e493850" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
<instance name="FLEXCOMM3" uuid="878079cb-696c-4271-a7b1-8f9fbc96ca99" type="flexcomm_usart_cmsis" type_id="flexcomm_usart_cmsis_adab49614496eb4b6311b98863269f48" mode="interrupt" peripheral="FLEXCOMM3" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="general" quick_selection="default">
<struct name="main_config">
<setting name="operationMode" value="ARM_USART_MODE_ASYNCHRONOUS"/>
<setting name="clockSource" value="FXCOMFunctionClock"/>
<setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
<setting name="power_state" value="ARM_POWER_FULL"/>
<setting name="baudRate_Bps" value="500000"/>
<setting name="dataBits" value="ARM_USART_DATA_BITS_8"/>
<setting name="parityBit" value="ARM_USART_PARITY_NONE"/>
<setting name="stopBit" value="ARM_USART_STOP_BITS_1"/>
<setting name="enableRX" value="false"/>
<setting name="enableTX" value="false"/>
<setting name="signalEventFunctionId" value="USART_SignalEvent"/>
<setting name="enableGetFreqFnCustomName" value="false"/>
<setting name="getFreqFunctionCustomID" value="USART_GetFreq"/>
<setting name="enableInitPinsFnCustomName" value="false"/>
<setting name="initPinFunctionCustomID" value="USART_InitPins"/>
<setting name="enableDeinitPinsFnCustomName" value="false"/>
<setting name="deinitPinFunctionCustomID" value="USART_DeinitPins"/>
</struct>
</config_set>
<config_set name="fsl_cmsis_uart">
<struct name="interrupt">
<setting name="IRQn" value="FLEXCOMM3_IRQn"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
</struct>
</config_set>
</instance>
<instance name="FLEXCOMM0" uuid="700bce49-bf21-46fe-8618-062c52fe30f6" type="flexcomm_usart_cmsis" type_id="flexcomm_usart_cmsis_adab49614496eb4b6311b98863269f48" mode="interrupt" peripheral="FLEXCOMM0" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="general" quick_selection="default">
<struct name="main_config">
<setting name="operationMode" value="ARM_USART_MODE_ASYNCHRONOUS"/>
<setting name="clockSource" value="FXCOMFunctionClock"/>
<setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
<setting name="power_state" value="ARM_POWER_FULL"/>
<setting name="baudRate_Bps" value="500000"/>
<setting name="dataBits" value="ARM_USART_DATA_BITS_8"/>
<setting name="parityBit" value="ARM_USART_PARITY_NONE"/>
<setting name="stopBit" value="ARM_USART_STOP_BITS_1"/>
<setting name="enableRX" value="false"/>
<setting name="enableTX" value="false"/>
<setting name="signalEventFunctionId" value="USART_SignalEvent"/>
<setting name="enableGetFreqFnCustomName" value="false"/>
<setting name="getFreqFunctionCustomID" value="USART_GetFreq"/>
<setting name="enableInitPinsFnCustomName" value="false"/>
<setting name="initPinFunctionCustomID" value="USART_InitPins"/>
<setting name="enableDeinitPinsFnCustomName" value="false"/>
<setting name="deinitPinFunctionCustomID" value="USART_DeinitPins"/>
</struct>
</config_set>
<config_set name="fsl_cmsis_uart">
<struct name="interrupt">
<setting name="IRQn" value="FLEXCOMM0_IRQn"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
</struct>
</config_set>
</instance>
<instance name="USBHSH" uuid="953a3f80-8155-4308-af14-b0c8598e9b55" type="usb" type_id="usb_49b3e4c7d25fbcd298641994d1b911e9" mode="host" peripheral="USBHSH" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="hostSettings" quick_selection="QS_HOST_DEFAULT">
<setting name="max_power" value="500"/>
<setting name="hub_support" value="true"/>
<array name="interfaces"/>
</config_set>
</instance>
<instance name="DMA0" uuid="883b2846-ab3c-4241-941c-366bc6b8da44" type="lpc_dma" type_id="lpc_dma_c13ca997a68f2ca6c666916ba13db7d7" mode="basic" peripheral="DMA0" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="fsl_dma">
<array name="dma_table"/>
<array name="dma_channels">
<struct name="0">
<setting name="apiMode" value="trans"/>
<struct name="dma_channel">
<setting name="channel_prefix_id" value="CH0"/>
<setting name="DMA_source" value="kDma0RequestFlexcomm3Rx"/>
<setting name="init_channel_priority" value="true"/>
<setting name="dma_priority" value="kDMA_ChannelPriority0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
<setting name="peripheral_request" value="true"/>
<setting name="init_trigger_config" value="false"/>
<struct name="trigger_config">
<setting name="type" value="kDMA_NoTrigger"/>
<setting name="burst" value="kDMA_SingleTransfer"/>
<setting name="wrap" value="kDMA_NoWrap"/>
</struct>
<struct name="trans_config">
<setting name="init_callback" value="false"/>
<setting name="callback_function" value=""/>
<setting name="callback_user_data" value=""/>
</struct>
<array name="tcd_config"/>
<setting name="allocateTCD" value="noncache"/>
<setting name="initTCD" value="noTCDInit"/>
</struct>
</array>
<struct name="dma_interrupt_trans">
<setting name="IRQn" value="DMA0_IRQn"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
</struct>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="9cbd66be-7ac1-4104-b28d-2bebba2e4e11" type_id="system_54b53072540eeeb8f8e9343e71f28176">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="617d74e2-0b6d-4083-802c-350abaf71755" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
<config_set_global name="global_messages"/>
</component>
<component name="generic_uart" uuid="7f9addee-5c8c-4ce3-8089-19751347aba2" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="1282bde3-0821-45b7-8df8-cde69f421f03" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
</components>
</periphs>
<tee name="TEE" version="2.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>0.0.0</processor_version>
</tee_profile>
<ahb>
<relative_region start="0" size="655360" security="ns_user" memory="PROGRAM_FLASH"/>
<relative_region start="0" size="131072" security="ns_user" memory="BootROM"/>
<relative_region start="0" size="32768" security="ns_user" memory="SRAMX"/>
<relative_region start="0" size="65536" security="ns_user" memory="SRAM0"/>
<relative_region start="0" size="65536" security="ns_user" memory="SRAM1"/>
<relative_region start="0" size="65536" security="ns_user" memory="SRAM2"/>
<relative_region start="0" size="65536" security="ns_user" memory="SRAM3"/>
<relative_region start="0" size="16384" security="ns_user" memory="SRAM4"/>
<relative_region start="0" size="16384" security="ns_user" memory="USB_RAM"/>
<masters>
<master id="HASH" security="ns_user"/>
<master id="MCM33C" security="ns_user"/>
<master id="MCM33S" security="ns_user"/>
<master id="PQ" security="ns_user"/>
<master id="SDIO" security="ns_user"/>
<master id="SDMA0" security="ns_user"/>
<master id="SDMA1" security="ns_user"/>
<master id="USBFSD" security="ns_user"/>
<master id="USBFSH" security="ns_user"/>
</masters>
<peripherals>
<peripheral id="ADC0" security="ns_user"/>
<peripheral id="AHB_SECURE_CTRL" security="ns_user"/>
<peripheral id="ANACTRL" security="ns_user"/>
<peripheral id="CASPER" security="ns_user"/>
<peripheral id="CRC_ENGINE" security="ns_user"/>
<peripheral id="CTIMER0" security="ns_user"/>
<peripheral id="CTIMER1" security="ns_user"/>
<peripheral id="CTIMER2" security="ns_user"/>
<peripheral id="CTIMER3" security="ns_user"/>
<peripheral id="CTIMER4" security="ns_user"/>
<peripheral id="DBGMAILBOX" security="ns_user"/>
<peripheral id="DMA0" security="ns_user"/>
<peripheral id="DMA1" security="ns_user"/>
<peripheral id="FLASH" security="ns_user"/>
<peripheral id="FLEXCOMM0" security="ns_user"/>
<peripheral id="FLEXCOMM1" security="ns_user"/>
<peripheral id="FLEXCOMM2" security="ns_user"/>
<peripheral id="FLEXCOMM3" security="ns_user"/>
<peripheral id="FLEXCOMM4" security="ns_user"/>
<peripheral id="FLEXCOMM5" security="ns_user"/>
<peripheral id="FLEXCOMM6" security="ns_user"/>
<peripheral id="FLEXCOMM7" security="ns_user"/>
<peripheral id="GINT0" security="ns_user"/>
<peripheral id="GINT1" security="ns_user"/>
<peripheral id="GPIO" security="ns_user"/>
<peripheral id="HASHCRYPT" security="ns_user"/>
<peripheral id="INPUTMUX" security="ns_user"/>
<peripheral id="IOCON" security="ns_user"/>
<peripheral id="MAILBOX" security="ns_user"/>
<peripheral id="MRT0" security="ns_user"/>
<peripheral id="OSTIMER" security="ns_user"/>
<peripheral id="PINT" security="ns_user"/>
<peripheral id="PLU" security="ns_user"/>
<peripheral id="PMC" security="ns_user"/>
<peripheral id="POWERQUAD" security="ns_user"/>
<peripheral id="PRINCE" security="ns_user"/>
<peripheral id="PUF" security="ns_user"/>
<peripheral id="RNG" security="ns_user"/>
<peripheral id="RTC" security="ns_user"/>
<peripheral id="SCT0" security="ns_user"/>
<peripheral id="SDIF" security="ns_user"/>
<peripheral id="SECGPIO" security="ns_user"/>
<peripheral id="SECPINT" security="ns_user"/>
<peripheral id="SPI8" security="ns_user"/>
<peripheral id="SYSCON" security="ns_user"/>
<peripheral id="SYSCTL" security="ns_user"/>
<peripheral id="USB0" security="ns_user"/>
<peripheral id="USBFSH" security="ns_user"/>
<peripheral id="USBHSD" security="ns_user"/>
<peripheral id="USBHSH" security="ns_user"/>
<peripheral id="USBPHY" security="ns_user"/>
<peripheral id="UTICK0" security="ns_user"/>
<peripheral id="WWDT" security="ns_user"/>
</peripherals>
<interrupts>
<masking>
<interrupt id="acmp_capt_irq" masked="Non-masked"/>
<interrupt id="adc_irq" masked="Non-masked"/>
<interrupt id="casper_irq" masked="Non-masked"/>
<interrupt id="ctimer0_irq" masked="Non-masked"/>
<interrupt id="ctimer1_irq" masked="Non-masked"/>
<interrupt id="ctimer2_irq" masked="Non-masked"/>
<interrupt id="ctimer3_irq" masked="Non-masked"/>
<interrupt id="ctimer4_irq" masked="Non-masked"/>
<interrupt id="flexcomm0_irq" masked="Non-masked"/>
<interrupt id="flexcomm1_irq" masked="Non-masked"/>
<interrupt id="flexcomm2_irq" masked="Non-masked"/>
<interrupt id="flexcomm3_irq" masked="Non-masked"/>
<interrupt id="flexcomm4_irq" masked="Non-masked"/>
<interrupt id="flexcomm5_irq" masked="Non-masked"/>
<interrupt id="flexcomm6_irq" masked="Non-masked"/>
<interrupt id="flexcomm7_irq" masked="Non-masked"/>
<interrupt id="global_irq0" masked="Non-masked"/>
<interrupt id="global_irq1" masked="Non-masked"/>
<interrupt id="lspi_hs_irq" masked="Non-masked"/>
<interrupt id="mailbox_irq" masked="Non-masked"/>
<interrupt id="mrt_irq" masked="Non-masked"/>
<interrupt id="os_event_irq" masked="Non-masked"/>
<interrupt id="pin_int4" masked="Non-masked"/>
<interrupt id="pin_int5" masked="Non-masked"/>
<interrupt id="pin_int6" masked="Non-masked"/>
<interrupt id="pin_int7" masked="Non-masked"/>
<interrupt id="pin_irq0" masked="Non-masked"/>
<interrupt id="pin_irq1" masked="Non-masked"/>
<interrupt id="pin_irq2" masked="Non-masked"/>
<interrupt id="pin_irq3" masked="Non-masked"/>
<interrupt id="plu_irq" masked="Non-masked"/>
<interrupt id="pq_irq" masked="Non-masked"/>
<interrupt id="qddkey_irq" masked="Non-masked"/>
<interrupt id="rtc_irq" masked="Non-masked"/>
<interrupt id="sct_irq" masked="Non-masked"/>
<interrupt id="sdio_irq" masked="Non-masked"/>
<interrupt id="sdma0_irq" masked="Non-masked"/>
<interrupt id="sdma1_irq" masked="Non-masked"/>
<interrupt id="sec_hypervisor_call_irq" masked="Non-masked"/>
<interrupt id="sec_int0" masked="Non-masked"/>
<interrupt id="sec_int1" masked="Non-masked"/>
<interrupt id="sec_vio_irq" masked="Non-masked"/>
<interrupt id="sha_irq" masked="Non-masked"/>
<interrupt id="sys_irq" masked="Non-masked"/>
<interrupt id="usb0_irq" masked="Non-masked"/>
<interrupt id="usb0_needclk_irq" masked="Non-masked"/>
<interrupt id="usb1_irq" masked="Non-masked"/>
<interrupt id="usb1_needclk_irq" masked="Non-masked"/>
<interrupt id="usb1_utmi_irq" masked="Non-masked"/>
<interrupt id="utick_irq" masked="Non-masked"/>
</masking>
<security>
<interrupt id="acmp_capt_irq" secure="Secure"/>
<interrupt id="adc_irq" secure="Secure"/>
<interrupt id="casper_irq" secure="Secure"/>
<interrupt id="ctimer0_irq" secure="Secure"/>
<interrupt id="ctimer1_irq" secure="Secure"/>
<interrupt id="ctimer2_irq" secure="Secure"/>
<interrupt id="ctimer3_irq" secure="Secure"/>
<interrupt id="ctimer4_irq" secure="Secure"/>
<interrupt id="flexcomm0_irq" secure="Secure"/>
<interrupt id="flexcomm1_irq" secure="Secure"/>
<interrupt id="flexcomm2_irq" secure="Secure"/>
<interrupt id="flexcomm3_irq" secure="Secure"/>
<interrupt id="flexcomm4_irq" secure="Secure"/>
<interrupt id="flexcomm5_irq" secure="Secure"/>
<interrupt id="flexcomm6_irq" secure="Secure"/>
<interrupt id="flexcomm7_irq" secure="Secure"/>
<interrupt id="global_irq0" secure="Secure"/>
<interrupt id="global_irq1" secure="Secure"/>
<interrupt id="lspi_hs_irq" secure="Secure"/>
<interrupt id="mailbox_irq" secure="Secure"/>
<interrupt id="mrt_irq" secure="Secure"/>
<interrupt id="os_event_irq" secure="Secure"/>
<interrupt id="pin_int4" secure="Secure"/>
<interrupt id="pin_int5" secure="Secure"/>
<interrupt id="pin_int6" secure="Secure"/>
<interrupt id="pin_int7" secure="Secure"/>
<interrupt id="pin_irq0" secure="Secure"/>
<interrupt id="pin_irq1" secure="Secure"/>
<interrupt id="pin_irq2" secure="Secure"/>
<interrupt id="pin_irq3" secure="Secure"/>
<interrupt id="plu_irq" secure="Secure"/>
<interrupt id="pq_irq" secure="Secure"/>
<interrupt id="qddkey_irq" secure="Secure"/>
<interrupt id="rtc_irq" secure="Secure"/>
<interrupt id="sct_irq" secure="Secure"/>
<interrupt id="sdio_irq" secure="Secure"/>
<interrupt id="sdma0_irq" secure="Secure"/>
<interrupt id="sdma1_irq" secure="Secure"/>
<interrupt id="sec_hypervisor_call_irq" secure="Secure"/>
<interrupt id="sec_int0" secure="Secure"/>
<interrupt id="sec_int1" secure="Secure"/>
<interrupt id="sec_vio_irq" secure="Secure"/>
<interrupt id="sha_irq" secure="Secure"/>
<interrupt id="sys_irq" secure="Secure"/>
<interrupt id="usb0_irq" secure="Secure"/>
<interrupt id="usb0_needclk_irq" secure="Secure"/>
<interrupt id="usb1_irq" secure="Secure"/>
<interrupt id="usb1_needclk_irq" secure="Secure"/>
<interrupt id="usb1_utmi_irq" secure="Secure"/>
<interrupt id="utick_irq" secure="Secure"/>
</security>
</interrupts>
<pins_masks>
<port id="pio0">
<pin_mask id="0" masked="Non-masked"/>
<pin_mask id="1" masked="Non-masked"/>
<pin_mask id="10" masked="Non-masked"/>
<pin_mask id="11" masked="Non-masked"/>
<pin_mask id="12" masked="Non-masked"/>
<pin_mask id="13" masked="Non-masked"/>
<pin_mask id="14" masked="Non-masked"/>
<pin_mask id="15" masked="Non-masked"/>
<pin_mask id="16" masked="Non-masked"/>
<pin_mask id="17" masked="Non-masked"/>
<pin_mask id="18" masked="Non-masked"/>
<pin_mask id="19" masked="Non-masked"/>
<pin_mask id="2" masked="Non-masked"/>
<pin_mask id="20" masked="Non-masked"/>
<pin_mask id="21" masked="Non-masked"/>
<pin_mask id="22" masked="Non-masked"/>
<pin_mask id="23" masked="Non-masked"/>
<pin_mask id="24" masked="Non-masked"/>
<pin_mask id="25" masked="Non-masked"/>
<pin_mask id="26" masked="Non-masked"/>
<pin_mask id="27" masked="Non-masked"/>
<pin_mask id="28" masked="Non-masked"/>
<pin_mask id="29" masked="Non-masked"/>
<pin_mask id="3" masked="Non-masked"/>
<pin_mask id="30" masked="Non-masked"/>
<pin_mask id="31" masked="Non-masked"/>
<pin_mask id="4" masked="Non-masked"/>
<pin_mask id="5" masked="Non-masked"/>
<pin_mask id="6" masked="Non-masked"/>
<pin_mask id="7" masked="Non-masked"/>
<pin_mask id="8" masked="Non-masked"/>
<pin_mask id="9" masked="Non-masked"/>
</port>
<port id="pio1">
<pin_mask id="0" masked="Non-masked"/>
<pin_mask id="1" masked="Non-masked"/>
<pin_mask id="10" masked="Non-masked"/>
<pin_mask id="11" masked="Non-masked"/>
<pin_mask id="12" masked="Non-masked"/>
<pin_mask id="13" masked="Non-masked"/>
<pin_mask id="14" masked="Non-masked"/>
<pin_mask id="15" masked="Non-masked"/>
<pin_mask id="16" masked="Non-masked"/>
<pin_mask id="17" masked="Non-masked"/>
<pin_mask id="18" masked="Non-masked"/>
<pin_mask id="19" masked="Non-masked"/>
<pin_mask id="2" masked="Non-masked"/>
<pin_mask id="20" masked="Non-masked"/>
<pin_mask id="21" masked="Non-masked"/>
<pin_mask id="22" masked="Non-masked"/>
<pin_mask id="23" masked="Non-masked"/>
<pin_mask id="24" masked="Non-masked"/>
<pin_mask id="25" masked="Non-masked"/>
<pin_mask id="26" masked="Non-masked"/>
<pin_mask id="27" masked="Non-masked"/>
<pin_mask id="28" masked="Non-masked"/>
<pin_mask id="29" masked="Non-masked"/>
<pin_mask id="3" masked="Non-masked"/>
<pin_mask id="30" masked="Non-masked"/>
<pin_mask id="31" masked="Non-masked"/>
<pin_mask id="4" masked="Non-masked"/>
<pin_mask id="5" masked="Non-masked"/>
<pin_mask id="6" masked="Non-masked"/>
<pin_mask id="7" masked="Non-masked"/>
<pin_mask id="8" masked="Non-masked"/>
<pin_mask id="9" masked="Non-masked"/>
</port>
</pins_masks>
</ahb>
<sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false">
<region start="0" size="268435456" security="ns" enabled="true" index="0"/>
<region start="536870912" size="3489660928" security="ns" enabled="true" index="1"/>
<region start="0" size="32" security="ns" enabled="false" index="2"/>
<region start="0" size="32" security="ns" enabled="false" index="3"/>
<region start="0" size="32" security="ns" enabled="false" index="4"/>
<region start="0" size="32" security="ns" enabled="false" index="5"/>
<region start="0" size="32" security="ns" enabled="false" index="6"/>
<region start="0" size="32" security="ns" enabled="false" index="7"/>
</sau>
<global_options>
<option id="AIRCR_PRIS" value="no"/>
<option id="AIRCR_BFHFNMINS" value="no"/>
<option id="AIRCR_SYSRESETREQS" value="no"/>
<option id="SCR_SLEEPDEEPS" value="no"/>
<option id="SHCSR_SECUREFAULTENA" value="no"/>
<option id="NSACR_CP0" value="yes"/>
<option id="NSACR_CP1" value="yes"/>
<option id="NSACR_CP2" value="no"/>
<option id="NSACR_CP3" value="no"/>
<option id="NSACR_CP4" value="no"/>
<option id="NSACR_CP5" value="no"/>
<option id="NSACR_CP6" value="no"/>
<option id="NSACR_CP7" value="no"/>
<option id="NSACR_CP10" value="yes"/>
<option id="NSACR_CP11" value="yes"/>
<option id="CPPWR_SU0" value="no"/>
<option id="CPPWR_SUS0" value="no"/>
<option id="CPPWR_SU1" value="no"/>
<option id="CPPWR_SUS1" value="no"/>
<option id="CPPWR_SU2" value="no"/>
<option id="CPPWR_SUS2" value="no"/>
<option id="CPPWR_SU3" value="no"/>
<option id="CPPWR_SUS3" value="no"/>
<option id="CPPWR_SU4" value="no"/>
<option id="CPPWR_SUS4" value="no"/>
<option id="CPPWR_SU5" value="no"/>
<option id="CPPWR_SUS5" value="no"/>
<option id="CPPWR_SU6" value="no"/>
<option id="CPPWR_SUS6" value="no"/>
<option id="CPPWR_SU7" value="no"/>
<option id="CPPWR_SUS7" value="no"/>
<option id="CPPWR_SU10" value="no"/>
<option id="CPPWR_SUS10" value="no"/>
<option id="CPPWR_SU11" value="no"/>
<option id="CPPWR_SUS11" value="no"/>
<option id="SEC_GPIO_MASK0_LOCK" value="no"/>
<option id="SEC_GPIO_MASK1_LOCK" value="no"/>
<option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/>
<option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/>
<option id="MASTER_SEC_LEVEL_LOCK" value="no"/>
<option id="CPU0_LOCK_NS_VTOR" value="no"/>
<option id="CPU0_LOCK_NS_MPU" value="no"/>
<option id="CPU0_LOCK_S_VTAIRCR" value="no"/>
<option id="CPU0_LOCK_S_MPU" value="no"/>
<option id="CPU0_LOCK_SAU" value="no"/>
<option id="CPU0_LOCK_REG_LOCK" value="no"/>
<option id="CPU1_LOCK_NS_VTOR" value="no"/>
<option id="CPU1_LOCK_NS_MPU" value="no"/>
<option id="CPU1_LOCK_REG_LOCK" value="no"/>
<option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/>
<option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="no"/>
<option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="no"/>
<option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/>
<option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/>
<option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/>
<option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/>
<option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/>
</global_options>
<user_memory_regions/>
<mpus>
<mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false">
<attributes>
<group index="0" id="Code" memory_type="normal" device="nGnRE"/>
<group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
<group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
</attributes>
<regions/>
</mpu>
<mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false">
<attributes>
<group index="0" id="Code" memory_type="normal" device="nGnRE"/>
<group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
<group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
</attributes>
<regions/>
</mpu>
</mpus>
</tee>
</tools>
</configuration>

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/Objects/CMSIS_DAP.hex vendored Normal file
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CMSIS-DAP v2 firmware for NXP MCU-LINK debug probe.
CMSIS-DAP v2 uses USB bulk endpoints for the communication with the host PC and is therefore faster.
Optionally, support for streaming SWO trace is provided via an additional USB endpoint.
Instructions for programing CMSIS_DAP firmware on MCU-LINK:
- download and install MCU-LINK_installer from https://www.nxp.com/design/microcontrollers-developer-resources/mcu-link-debug-probe:MCU-LINK
- disconnect MCU-LINK from USB (J1), set "firmware update" jumper (J3), connect MCU-LINK to USB (J1)
- open a Command Window
- navigate to the MCU-LINK_installer installation (default C:\nxp\MCU-LINK_installer\) and go to the scripts sub-directory
- copy pre-built firmware hex file ..\CMSIS\DAP\Firmware\Examples\MCU-LINK\Objects\CMSIS_DAP.hex to scripts directory
- run the command: programm_CMSIS.cmd CMSIS_DAP.hex
- follow the instructions in command window

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/*
* Copyright (c) 2013-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.1
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackOverflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
}

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/*
* Copyright (c) 2013-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.5.2
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 32
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch (requires RTX source variant).
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 0
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 512
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x81U
#endif
// <e.7>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x81U
#endif
// <e.7>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x85U
#endif
// <e.7>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x81U
#endif
// <e.7>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x81U
#endif
// <e.7>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x81U
#endif
// <e.7>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x81U
#endif
// <e.7>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x81U
#endif
// <e.7>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x81U
#endif
// <e.7>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x81U
#endif
// <e.7>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

105
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash.scf vendored Normal file
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#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b200722
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* USB BDT size */
#define usb_bdt_size 0x0
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000200
#define m_text_start 0x00000200
#define m_text_size 0x00071E00
#define m_core1_image_start 0x00072000
#define m_core1_image_size 0x00026000
#if (defined(__use_shmem__))
#define m_data_start 0x20000000
#define m_data_size 0x00031800
#define m_rpmsg_sh_mem_start 0x20031800
#define m_rpmsg_sh_mem_size 0x00001800
#else
#define m_data_start 0x20000000
#define m_data_size 0x00033000
#endif
#define m_usb_sram_start 0x40100000
#define m_usb_sram_size 0x00004000
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__use_shmem__))
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
* (rpmsg_sh_mem_section)
}
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
* (.core1_code)
}
}

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_ns.scf vendored Normal file
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#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b190923
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* USB BDT size */
#define usb_bdt_size 0x0
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
/* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */
#define m_interrupts_start 0x00010000
#define m_interrupts_size 0x00000200
#define m_text_start 0x00010200
#define m_text_size 0x00061E00
#define m_core1_image_start 0x00072000
#define m_core1_image_size 0x00026000
/* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */
#if (defined(__use_shmem__))
#define m_data_start 0x20008000
#define m_data_size 0x00029000
#define m_rpmsg_sh_mem_start 0x20031800
#define m_rpmsg_sh_mem_size 0x00001800
#else
#define m_data_start 0x20008000
#define m_data_size 0x0002B000
#endif
#define m_usb_sram_start 0x40100000
#define m_usb_sram_size 0x00004000
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__use_shmem__))
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
* (rpmsg_sh_mem_section)
}
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
* (.core1_code)
}
}

116
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_s.scf vendored Normal file
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#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b190923
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* USB BDT size */
#define usb_bdt_size 0x0
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
/* Only the first 64kB of flash is used as secure memory. */
#define m_interrupts_start 0x10000000
#define m_interrupts_size 0x00000200
#define m_text_start 0x10000200
#define m_text_size 0x0000FC00
#define m_core1_image_start 0x10072000
#define m_core1_image_size 0x00026000
/* Only first 32kB of data RAM is used as secure memory. */
#if (defined(__use_shmem__))
#define m_data_start 0x30000000
#define m_data_size 0x00008000
#define m_rpmsg_sh_mem_start 0x30031800
#define m_rpmsg_sh_mem_size 0x00001800
#else
#define m_data_start 0x30000000
#define m_data_size 0x00008000
#endif
/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */
#define m_veneer_table_start 0x1000FE00
#define m_veneer_table_size 0x200
#define m_usb_sram_start 0x50100000
#define m_usb_sram_size 0x00004000
LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__use_shmem__))
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
* (rpmsg_sh_mem_section)
}
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
*(Veneer$$CMSE)
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
* (.core1_code)
}
}

105
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_ram.scf vendored Normal file
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#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b200722
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* USB BDT size */
#define usb_bdt_size 0x0
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#define m_interrupts_start 0x04000000
#define m_interrupts_size 0x00000200
#define m_text_start 0x04000200
#define m_text_size 0x00007E00
#define m_core1_image_start 0x20033000
#define m_core1_image_size 0x0000C800
#if (defined(__use_shmem__))
#define m_data_start 0x20000000
#define m_data_size 0x00031800
#define m_rpmsg_sh_mem_start 0x20031800
#define m_rpmsg_sh_mem_size 0x00001800
#else
#define m_data_start 0x20000000
#define m_data_size 0x00033000
#endif
#define m_usb_sram_start 0x40100000
#define m_usb_sram_size 0x00004000
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__use_shmem__))
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
* (rpmsg_sh_mem_section)
}
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
* (.core1_code)
}
}

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _RTE_DEVICE_H
#define _RTE_DEVICE_H
#include "pin_mux.h"
/* UART Select, UART0-UART7. */
/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART
* instance. */
#define RTE_USART0 1
#define RTE_USART0_DMA_EN 1
#define RTE_USART1 0
#define RTE_USART1_DMA_EN 0
#define RTE_USART2 0
#define RTE_USART2_DMA_EN 0
#define RTE_USART3 1
#define RTE_USART3_DMA_EN 1
#define RTE_USART4 0
#define RTE_USART4_DMA_EN 0
#define RTE_USART5 0
#define RTE_USART5_DMA_EN 0
#define RTE_USART6 0
#define RTE_USART6_DMA_EN 0
#define RTE_USART7 0
#define RTE_USART7_DMA_EN 0
/* USART configuration. */
#define USART_RX_BUFFER_LEN 64
#define USART0_RX_BUFFER_ENABLE 1
#define USART1_RX_BUFFER_ENABLE 0
#define USART2_RX_BUFFER_ENABLE 0
#define USART3_RX_BUFFER_ENABLE 1
#define USART4_RX_BUFFER_ENABLE 0
#define USART5_RX_BUFFER_ENABLE 0
#define USART6_RX_BUFFER_ENABLE 0
#define USART7_RX_BUFFER_ENABLE 0
#define RTE_USART0_DMA_TX_CH 5
#define RTE_USART0_DMA_TX_DMA_BASE DMA0
#define RTE_USART0_DMA_RX_CH 4
#define RTE_USART0_DMA_RX_DMA_BASE DMA0
#define RTE_USART1_DMA_TX_CH 7
#define RTE_USART1_DMA_TX_DMA_BASE DMA0
#define RTE_USART1_DMA_RX_CH 6
#define RTE_USART1_DMA_RX_DMA_BASE DMA0
#define RTE_USART2_DMA_TX_CH 8
#define RTE_USART2_DMA_TX_DMA_BASE DMA0
#define RTE_USART2_DMA_RX_CH 9
#define RTE_USART2_DMA_RX_DMA_BASE DMA0
#define RTE_USART3_DMA_TX_CH 9
#define RTE_USART3_DMA_TX_DMA_BASE DMA0
#define RTE_USART3_DMA_RX_CH 8
#define RTE_USART3_DMA_RX_DMA_BASE DMA0
#define RTE_USART4_DMA_TX_CH 13
#define RTE_USART4_DMA_TX_DMA_BASE DMA0
#define RTE_USART4_DMA_RX_CH 12
#define RTE_USART4_DMA_RX_DMA_BASE DMA0
#define RTE_USART5_DMA_TX_CH 15
#define RTE_USART5_DMA_TX_DMA_BASE DMA0
#define RTE_USART5_DMA_RX_CH 14
#define RTE_USART5_DMA_RX_DMA_BASE DMA0
#define RTE_USART6_DMA_TX_CH 17
#define RTE_USART6_DMA_TX_DMA_BASE DMA0
#define RTE_USART6_DMA_RX_CH 16
#define RTE_USART6_DMA_RX_DMA_BASE DMA0
#define RTE_USART7_DMA_TX_CH 19
#define RTE_USART7_DMA_TX_DMA_BASE DMA0
#define RTE_USART7_DMA_RX_CH 18
#define RTE_USART7_DMA_RX_DMA_BASE DMA0
/* I2C Select, I2C0 -I2C7*/
/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance.
*/
#define RTE_I2C0 0
#define RTE_I2C0_DMA_EN 0
#define RTE_I2C1 0
#define RTE_I2C1_DMA_EN 0
#define RTE_I2C2 0
#define RTE_I2C2_DMA_EN 0
#define RTE_I2C3 0
#define RTE_I2C3_DMA_EN 0
#define RTE_I2C4 0
#define RTE_I2C4_DMA_EN 0
#define RTE_I2C5 0
#define RTE_I2C5_DMA_EN 0
#define RTE_I2C6 0
#define RTE_I2C6_DMA_EN 0
#define RTE_I2C7 0
#define RTE_I2C7_DMA_EN 0
/*I2C configuration*/
#define RTE_I2C0_Master_DMA_BASE DMA0
#define RTE_I2C0_Master_DMA_CH 1
#define RTE_I2C1_Master_DMA_BASE DMA0
#define RTE_I2C1_Master_DMA_CH 3
#define RTE_I2C2_Master_DMA_BASE DMA0
#define RTE_I2C2_Master_DMA_CH 5
#define RTE_I2C3_Master_DMA_BASE DMA0
#define RTE_I2C3_Master_DMA_CH 7
#define RTE_I2C4_Master_DMA_BASE DMA0
#define RTE_I2C4_Master_DMA_CH 9
#define RTE_I2C5_Master_DMA_BASE DMA0
#define RTE_I2C5_Master_DMA_CH 11
#define RTE_I2C6_Master_DMA_BASE DMA0
#define RTE_I2C6_Master_DMA_CH 13
#define RTE_I2C7_Master_DMA_BASE DMA0
#define RTE_I2C7_Master_DMA_CH 15
/* SPI select, SPI0 - SPI7.*/
/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance.
*/
#define RTE_SPI0 0
#define RTE_SPI0_DMA_EN 0
#define RTE_SPI1 0
#define RTE_SPI1_DMA_EN 0
#define RTE_SPI2 0
#define RTE_SPI2_DMA_EN 0
#define RTE_SPI3 0
#define RTE_SPI3_DMA_EN 0
#define RTE_SPI4 0
#define RTE_SPI4_DMA_EN 0
#define RTE_SPI5 0
#define RTE_SPI5_DMA_EN 0
#define RTE_SPI6 0
#define RTE_SPI6_DMA_EN 0
#define RTE_SPI7 0
#define RTE_SPI7_DMA_EN 0
/* SPI configuration. */
#define RTE_SPI0_SSEL_NUM kSPI_Ssel0
#define RTE_SPI0_PIN_INIT SPI0_InitPins
#define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins
#define RTE_SPI0_DMA_TX_CH 1
#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
#define RTE_SPI0_DMA_RX_CH 0
#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
#define RTE_SPI1_SSEL_NUM kSPI_Ssel0
#define RTE_SPI1_PIN_INIT SPI1_InitPins
#define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins
#define RTE_SPI1_DMA_TX_CH 3
#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
#define RTE_SPI1_DMA_RX_CH 2
#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
#define RTE_SPI2_SSEL_NUM kSPI_Ssel0
#define RTE_SPI2_PIN_INIT SPI2_InitPins
#define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins
#define RTE_SPI2_DMA_TX_CH 5
#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
#define RTE_SPI2_DMA_RX_CH 4
#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
#define RTE_SPI3_SSEL_NUM kSPI_Ssel0
#define RTE_SPI3_PIN_INIT SPI3_InitPins
#define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins
#define RTE_SPI3_DMA_TX_CH 7
#define RTE_SPI3_DMA_TX_DMA_BASE DMA0
#define RTE_SPI3_DMA_RX_CH 6
#define RTE_SPI3_DMA_RX_DMA_BASE DMA0
#define RTE_SPI4_SSEL_NUM kSPI_Ssel0
#define RTE_SPI4_PIN_INIT SPI4_InitPins
#define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins
#define RTE_SPI4_DMA_TX_CH 9
#define RTE_SPI4_DMA_TX_DMA_BASE DMA0
#define RTE_SPI4_DMA_RX_CH 8
#define RTE_SPI4_DMA_RX_DMA_BASE DMA0
#define RTE_SPI5_SSEL_NUM kSPI_Ssel0
#define RTE_SPI5_PIN_INIT SPI5_InitPins
#define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins
#define RTE_SPI5_DMA_TX_CH 11
#define RTE_SPI5_DMA_TX_DMA_BASE DMA0
#define RTE_SPI5_DMA_RX_CH 10
#define RTE_SPI5_DMA_RX_DMA_BASE DMA0
#define RTE_SPI6_SSEL_NUM kSPI_Ssel0
#define RTE_SPI6_PIN_INIT SPI6_InitPins
#define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins
#define RTE_SPI6_DMA_TX_CH 13
#define RTE_SPI6_DMA_TX_DMA_BASE DMA0
#define RTE_SPI6_DMA_RX_CH 12
#define RTE_SPI6_DMA_RX_DMA_BASE DMA0
#define RTE_SPI7_SSEL_NUM kSPI_Ssel0
#define RTE_SPI7_PIN_INIT SPI7_InitPins
#define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins
#define RTE_SPI7_DMA_TX_CH 15
#define RTE_SPI7_DMA_TX_DMA_BASE DMA0
#define RTE_SPI7_DMA_RX_CH 14
#define RTE_SPI7_DMA_RX_DMA_BASE DMA0
#endif /* _RTE_DEVICE_H */

801
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/startup_LPC55S69_cm33_core0.S vendored Normal file
View File

@ -0,0 +1,801 @@
/* ---------------------------------------------------------------------------------------
* @file: startup_LPC55S69_cm33_core0.s
* @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0
* @version: 1.1
* @date: 2019-5-16
* ---------------------------------------------------------------------------------------*/
/*
* Copyright 1997-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv8-m.main
.eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
.section .isr_vector, "a"
.align 2
.globl __Vectors
__Vectors:
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long SecureFault_Handler /* Secure Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
.long DMA0_IRQHandler /* DMA0 controller */
.long GINT0_IRQHandler /* GPIO group 0 */
.long GINT1_IRQHandler /* GPIO group 1 */
.long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
.long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
.long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
.long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
.long UTICK0_IRQHandler /* Micro-tick Timer */
.long MRT0_IRQHandler /* Multi-rate timer */
.long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */
.long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */
.long SCT0_IRQHandler /* SCTimer/PWM */
.long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */
.long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long ADC0_IRQHandler /* ADC0 */
.long Reserved39_IRQHandler /* Reserved interrupt */
.long ACMP_IRQHandler /* ACMP interrupts */
.long Reserved41_IRQHandler /* Reserved interrupt */
.long Reserved42_IRQHandler /* Reserved interrupt */
.long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */
.long USB0_IRQHandler /* USB device */
.long RTC_IRQHandler /* RTC alarm and wake-up interrupts */
.long Reserved46_IRQHandler /* Reserved interrupt */
.long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
.long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
.long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
.long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
.long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
.long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */
.long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */
.long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
.long Reserved55_IRQHandler /* Reserved interrupt */
.long Reserved56_IRQHandler /* Reserved interrupt */
.long Reserved57_IRQHandler /* Reserved interrupt */
.long SDIO_IRQHandler /* SD/MMC */
.long Reserved59_IRQHandler /* Reserved interrupt */
.long Reserved60_IRQHandler /* Reserved interrupt */
.long Reserved61_IRQHandler /* Reserved interrupt */
.long USB1_PHY_IRQHandler /* USB1_PHY */
.long USB1_IRQHandler /* USB1 interrupt */
.long USB1_NEEDCLK_IRQHandler /* USB1 activity */
.long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */
.long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
.long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
.long PLU_IRQHandler /* PLU interrupt */
.long SEC_VIO_IRQHandler /* SEC_VIO interrupt */
.long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */
.long CASER_IRQHandler /* CASPER interrupt */
.long PUF_IRQHandler /* PUF interrupt */
.long PQ_IRQHandler /* PQ interrupt */
.long DMA1_IRQHandler /* DMA1 interrupt */
.long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
.size __Vectors, . - __Vectors
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__Vectors
str r1, [r0]
ldr r2, [r1]
msr msp, r2
ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base
msr msplim, R0
ldr r0,=SystemInit
blx r0
cpsie i /* Unmask interrupts */
ldr r0,=__main
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak WDT_BOD_IRQHandler
.type WDT_BOD_IRQHandler, %function
WDT_BOD_IRQHandler:
ldr r0,=WDT_BOD_DriverIRQHandler
bx r0
.size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
.align 1
.thumb_func
.weak DMA0_IRQHandler
.type DMA0_IRQHandler, %function
DMA0_IRQHandler:
ldr r0,=DMA0_DriverIRQHandler
bx r0
.size DMA0_IRQHandler, . - DMA0_IRQHandler
.align 1
.thumb_func
.weak GINT0_IRQHandler
.type GINT0_IRQHandler, %function
GINT0_IRQHandler:
ldr r0,=GINT0_DriverIRQHandler
bx r0
.size GINT0_IRQHandler, . - GINT0_IRQHandler
.align 1
.thumb_func
.weak GINT1_IRQHandler
.type GINT1_IRQHandler, %function
GINT1_IRQHandler:
ldr r0,=GINT1_DriverIRQHandler
bx r0
.size GINT1_IRQHandler, . - GINT1_IRQHandler
.align 1
.thumb_func
.weak PIN_INT0_IRQHandler
.type PIN_INT0_IRQHandler, %function
PIN_INT0_IRQHandler:
ldr r0,=PIN_INT0_DriverIRQHandler
bx r0
.size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
.align 1
.thumb_func
.weak PIN_INT1_IRQHandler
.type PIN_INT1_IRQHandler, %function
PIN_INT1_IRQHandler:
ldr r0,=PIN_INT1_DriverIRQHandler
bx r0
.size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
.align 1
.thumb_func
.weak PIN_INT2_IRQHandler
.type PIN_INT2_IRQHandler, %function
PIN_INT2_IRQHandler:
ldr r0,=PIN_INT2_DriverIRQHandler
bx r0
.size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
.align 1
.thumb_func
.weak PIN_INT3_IRQHandler
.type PIN_INT3_IRQHandler, %function
PIN_INT3_IRQHandler:
ldr r0,=PIN_INT3_DriverIRQHandler
bx r0
.size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
.align 1
.thumb_func
.weak UTICK0_IRQHandler
.type UTICK0_IRQHandler, %function
UTICK0_IRQHandler:
ldr r0,=UTICK0_DriverIRQHandler
bx r0
.size UTICK0_IRQHandler, . - UTICK0_IRQHandler
.align 1
.thumb_func
.weak MRT0_IRQHandler
.type MRT0_IRQHandler, %function
MRT0_IRQHandler:
ldr r0,=MRT0_DriverIRQHandler
bx r0
.size MRT0_IRQHandler, . - MRT0_IRQHandler
.align 1
.thumb_func
.weak CTIMER0_IRQHandler
.type CTIMER0_IRQHandler, %function
CTIMER0_IRQHandler:
ldr r0,=CTIMER0_DriverIRQHandler
bx r0
.size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
.align 1
.thumb_func
.weak CTIMER1_IRQHandler
.type CTIMER1_IRQHandler, %function
CTIMER1_IRQHandler:
ldr r0,=CTIMER1_DriverIRQHandler
bx r0
.size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
.align 1
.thumb_func
.weak SCT0_IRQHandler
.type SCT0_IRQHandler, %function
SCT0_IRQHandler:
ldr r0,=SCT0_DriverIRQHandler
bx r0
.size SCT0_IRQHandler, . - SCT0_IRQHandler
.align 1
.thumb_func
.weak CTIMER3_IRQHandler
.type CTIMER3_IRQHandler, %function
CTIMER3_IRQHandler:
ldr r0,=CTIMER3_DriverIRQHandler
bx r0
.size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM0_IRQHandler
.type FLEXCOMM0_IRQHandler, %function
FLEXCOMM0_IRQHandler:
ldr r0,=FLEXCOMM0_DriverIRQHandler
bx r0
.size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM1_IRQHandler
.type FLEXCOMM1_IRQHandler, %function
FLEXCOMM1_IRQHandler:
ldr r0,=FLEXCOMM1_DriverIRQHandler
bx r0
.size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM2_IRQHandler
.type FLEXCOMM2_IRQHandler, %function
FLEXCOMM2_IRQHandler:
ldr r0,=FLEXCOMM2_DriverIRQHandler
bx r0
.size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM3_IRQHandler
.type FLEXCOMM3_IRQHandler, %function
FLEXCOMM3_IRQHandler:
ldr r0,=FLEXCOMM3_DriverIRQHandler
bx r0
.size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM4_IRQHandler
.type FLEXCOMM4_IRQHandler, %function
FLEXCOMM4_IRQHandler:
ldr r0,=FLEXCOMM4_DriverIRQHandler
bx r0
.size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM5_IRQHandler
.type FLEXCOMM5_IRQHandler, %function
FLEXCOMM5_IRQHandler:
ldr r0,=FLEXCOMM5_DriverIRQHandler
bx r0
.size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM6_IRQHandler
.type FLEXCOMM6_IRQHandler, %function
FLEXCOMM6_IRQHandler:
ldr r0,=FLEXCOMM6_DriverIRQHandler
bx r0
.size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM7_IRQHandler
.type FLEXCOMM7_IRQHandler, %function
FLEXCOMM7_IRQHandler:
ldr r0,=FLEXCOMM7_DriverIRQHandler
bx r0
.size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
.align 1
.thumb_func
.weak ADC0_IRQHandler
.type ADC0_IRQHandler, %function
ADC0_IRQHandler:
ldr r0,=ADC0_DriverIRQHandler
bx r0
.size ADC0_IRQHandler, . - ADC0_IRQHandler
.align 1
.thumb_func
.weak Reserved39_IRQHandler
.type Reserved39_IRQHandler, %function
Reserved39_IRQHandler:
ldr r0,=Reserved39_DriverIRQHandler
bx r0
.size Reserved39_IRQHandler, . - Reserved39_IRQHandler
.align 1
.thumb_func
.weak ACMP_IRQHandler
.type ACMP_IRQHandler, %function
ACMP_IRQHandler:
ldr r0,=ACMP_DriverIRQHandler
bx r0
.size ACMP_IRQHandler, . - ACMP_IRQHandler
.align 1
.thumb_func
.weak Reserved41_IRQHandler
.type Reserved41_IRQHandler, %function
Reserved41_IRQHandler:
ldr r0,=Reserved41_DriverIRQHandler
bx r0
.size Reserved41_IRQHandler, . - Reserved41_IRQHandler
.align 1
.thumb_func
.weak Reserved42_IRQHandler
.type Reserved42_IRQHandler, %function
Reserved42_IRQHandler:
ldr r0,=Reserved42_DriverIRQHandler
bx r0
.size Reserved42_IRQHandler, . - Reserved42_IRQHandler
.align 1
.thumb_func
.weak USB0_NEEDCLK_IRQHandler
.type USB0_NEEDCLK_IRQHandler, %function
USB0_NEEDCLK_IRQHandler:
ldr r0,=USB0_NEEDCLK_DriverIRQHandler
bx r0
.size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
.align 1
.thumb_func
.weak USB0_IRQHandler
.type USB0_IRQHandler, %function
USB0_IRQHandler:
ldr r0,=USB0_DriverIRQHandler
bx r0
.size USB0_IRQHandler, . - USB0_IRQHandler
.align 1
.thumb_func
.weak RTC_IRQHandler
.type RTC_IRQHandler, %function
RTC_IRQHandler:
ldr r0,=RTC_DriverIRQHandler
bx r0
.size RTC_IRQHandler, . - RTC_IRQHandler
.align 1
.thumb_func
.weak Reserved46_IRQHandler
.type Reserved46_IRQHandler, %function
Reserved46_IRQHandler:
ldr r0,=Reserved46_DriverIRQHandler
bx r0
.size Reserved46_IRQHandler, . - Reserved46_IRQHandler
.align 1
.thumb_func
.weak MAILBOX_IRQHandler
.type MAILBOX_IRQHandler, %function
MAILBOX_IRQHandler:
ldr r0,=MAILBOX_DriverIRQHandler
bx r0
.size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
.align 1
.thumb_func
.weak PIN_INT4_IRQHandler
.type PIN_INT4_IRQHandler, %function
PIN_INT4_IRQHandler:
ldr r0,=PIN_INT4_DriverIRQHandler
bx r0
.size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
.align 1
.thumb_func
.weak PIN_INT5_IRQHandler
.type PIN_INT5_IRQHandler, %function
PIN_INT5_IRQHandler:
ldr r0,=PIN_INT5_DriverIRQHandler
bx r0
.size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
.align 1
.thumb_func
.weak PIN_INT6_IRQHandler
.type PIN_INT6_IRQHandler, %function
PIN_INT6_IRQHandler:
ldr r0,=PIN_INT6_DriverIRQHandler
bx r0
.size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
.align 1
.thumb_func
.weak PIN_INT7_IRQHandler
.type PIN_INT7_IRQHandler, %function
PIN_INT7_IRQHandler:
ldr r0,=PIN_INT7_DriverIRQHandler
bx r0
.size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
.align 1
.thumb_func
.weak CTIMER2_IRQHandler
.type CTIMER2_IRQHandler, %function
CTIMER2_IRQHandler:
ldr r0,=CTIMER2_DriverIRQHandler
bx r0
.size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
.align 1
.thumb_func
.weak CTIMER4_IRQHandler
.type CTIMER4_IRQHandler, %function
CTIMER4_IRQHandler:
ldr r0,=CTIMER4_DriverIRQHandler
bx r0
.size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
.align 1
.thumb_func
.weak OS_EVENT_IRQHandler
.type OS_EVENT_IRQHandler, %function
OS_EVENT_IRQHandler:
ldr r0,=OS_EVENT_DriverIRQHandler
bx r0
.size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
.align 1
.thumb_func
.weak Reserved55_IRQHandler
.type Reserved55_IRQHandler, %function
Reserved55_IRQHandler:
ldr r0,=Reserved55_DriverIRQHandler
bx r0
.size Reserved55_IRQHandler, . - Reserved55_IRQHandler
.align 1
.thumb_func
.weak Reserved56_IRQHandler
.type Reserved56_IRQHandler, %function
Reserved56_IRQHandler:
ldr r0,=Reserved56_DriverIRQHandler
bx r0
.size Reserved56_IRQHandler, . - Reserved56_IRQHandler
.align 1
.thumb_func
.weak Reserved57_IRQHandler
.type Reserved57_IRQHandler, %function
Reserved57_IRQHandler:
ldr r0,=Reserved57_DriverIRQHandler
bx r0
.size Reserved57_IRQHandler, . - Reserved57_IRQHandler
.align 1
.thumb_func
.weak SDIO_IRQHandler
.type SDIO_IRQHandler, %function
SDIO_IRQHandler:
ldr r0,=SDIO_DriverIRQHandler
bx r0
.size SDIO_IRQHandler, . - SDIO_IRQHandler
.align 1
.thumb_func
.weak Reserved59_IRQHandler
.type Reserved59_IRQHandler, %function
Reserved59_IRQHandler:
ldr r0,=Reserved59_DriverIRQHandler
bx r0
.size Reserved59_IRQHandler, . - Reserved59_IRQHandler
.align 1
.thumb_func
.weak Reserved60_IRQHandler
.type Reserved60_IRQHandler, %function
Reserved60_IRQHandler:
ldr r0,=Reserved60_DriverIRQHandler
bx r0
.size Reserved60_IRQHandler, . - Reserved60_IRQHandler
.align 1
.thumb_func
.weak Reserved61_IRQHandler
.type Reserved61_IRQHandler, %function
Reserved61_IRQHandler:
ldr r0,=Reserved61_DriverIRQHandler
bx r0
.size Reserved61_IRQHandler, . - Reserved61_IRQHandler
.align 1
.thumb_func
.weak USB1_PHY_IRQHandler
.type USB1_PHY_IRQHandler, %function
USB1_PHY_IRQHandler:
ldr r0,=USB1_PHY_DriverIRQHandler
bx r0
.size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler
.align 1
.thumb_func
.weak USB1_IRQHandler
.type USB1_IRQHandler, %function
USB1_IRQHandler:
ldr r0,=USB1_DriverIRQHandler
bx r0
.size USB1_IRQHandler, . - USB1_IRQHandler
.align 1
.thumb_func
.weak USB1_NEEDCLK_IRQHandler
.type USB1_NEEDCLK_IRQHandler, %function
USB1_NEEDCLK_IRQHandler:
ldr r0,=USB1_NEEDCLK_DriverIRQHandler
bx r0
.size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
.align 1
.thumb_func
.weak SEC_HYPERVISOR_CALL_IRQHandler
.type SEC_HYPERVISOR_CALL_IRQHandler, %function
SEC_HYPERVISOR_CALL_IRQHandler:
ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
bx r0
.size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
.align 1
.thumb_func
.weak SEC_GPIO_INT0_IRQ0_IRQHandler
.type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
SEC_GPIO_INT0_IRQ0_IRQHandler:
ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
bx r0
.size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
.align 1
.thumb_func
.weak SEC_GPIO_INT0_IRQ1_IRQHandler
.type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
SEC_GPIO_INT0_IRQ1_IRQHandler:
ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
bx r0
.size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
.align 1
.thumb_func
.weak PLU_IRQHandler
.type PLU_IRQHandler, %function
PLU_IRQHandler:
ldr r0,=PLU_DriverIRQHandler
bx r0
.size PLU_IRQHandler, . - PLU_IRQHandler
.align 1
.thumb_func
.weak SEC_VIO_IRQHandler
.type SEC_VIO_IRQHandler, %function
SEC_VIO_IRQHandler:
ldr r0,=SEC_VIO_DriverIRQHandler
bx r0
.size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
.align 1
.thumb_func
.weak HASHCRYPT_IRQHandler
.type HASHCRYPT_IRQHandler, %function
HASHCRYPT_IRQHandler:
ldr r0,=HASHCRYPT_DriverIRQHandler
bx r0
.size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
.align 1
.thumb_func
.weak CASER_IRQHandler
.type CASER_IRQHandler, %function
CASER_IRQHandler:
ldr r0,=CASER_DriverIRQHandler
bx r0
.size CASER_IRQHandler, . - CASER_IRQHandler
.align 1
.thumb_func
.weak PUF_IRQHandler
.type PUF_IRQHandler, %function
PUF_IRQHandler:
ldr r0,=PUF_DriverIRQHandler
bx r0
.size PUF_IRQHandler, . - PUF_IRQHandler
.align 1
.thumb_func
.weak PQ_IRQHandler
.type PQ_IRQHandler, %function
PQ_IRQHandler:
ldr r0,=PQ_DriverIRQHandler
bx r0
.size PQ_IRQHandler, . - PQ_IRQHandler
.align 1
.thumb_func
.weak DMA1_IRQHandler
.type DMA1_IRQHandler, %function
DMA1_IRQHandler:
ldr r0,=DMA1_DriverIRQHandler
bx r0
.size DMA1_IRQHandler, . - DMA1_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM8_IRQHandler
.type FLEXCOMM8_IRQHandler, %function
FLEXCOMM8_IRQHandler:
ldr r0,=FLEXCOMM8_DriverIRQHandler
bx r0
.size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SecureFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */
def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */
def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */
def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */
def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */
def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */
def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */
def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */
def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */
def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler ADC0_DriverIRQHandler /* ADC0 */
def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */
def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */
def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */
def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */
def_irq_handler USB0_DriverIRQHandler /* USB device */
def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */
def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */
def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */
def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */
def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */
def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */
def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */
def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */
def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */
def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */
def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */
def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */
def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */
def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */
def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */
def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */
def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */
def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */
def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
.end

206
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c vendored Normal file
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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_0.c
* Purpose: USB Device Configuration
* Rev.: V5.2.0
*------------------------------------------------------------------------------
* Use the following configuration settings in the Device Class configuration
* files to assign a Device Class to this USB Device 0.
*
* Configuration Setting Value
* --------------------- -----
* Assign Device Class to USB Device # = 0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device 0
// <o>Connect to hardware via Driver_USBD# <0-255>
// <i>Select driver control block for hardware interface.
#define USBD0_PORT 1
// <o.0>High-speed
// <i>Enable High-speed functionality (if device supports it).
#define USBD0_HS 1
// <h>Device Settings
// <i>These settings are used to create the Device Descriptor
// <o>Max Endpoint 0 Packet Size
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
#define USBD0_MAX_PACKET0 64
// <o.0..15>Vendor ID <0x0000-0xFFFF>
// <i>Vendor ID assigned by USB-IF (idVendor).
#define USBD0_DEV_DESC_IDVENDOR 0xC251
// <o.0..15>Product ID <0x0000-0xFFFF>
// <i>Product ID assigned by manufacturer (idProduct).
#define USBD0_DEV_DESC_IDPRODUCT 0xF00B
// <o.0..15>Device Release Number <0x0000-0xFFFF>
// <i>Device Release Number in binary-coded decimal (bcdDevice)
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
// </h>
// <h>Configuration Settings
// <i>These settings are used to create the Configuration Descriptor.
// <o.6>Power
// <i>Default Power Setting (D6: of bmAttributes).
// <0=>Bus-powered
// <1=>Self-powered
// <o.5>Remote Wakeup
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
// <i>Maximum Power Consumption of USB Device from bus in this
// <i>specific configuration when device is fully operational (bMaxPower).
#define USBD0_CFG_DESC_BMAXPOWER 250
// </h>
// <h>String Settings
// <i>These settings are used to create the String Descriptor.
// <o.0..15>Language ID <0x0000-0xFCFF>
// <i>English (United States) = 0x0409.
#define USBD0_STR_DESC_LANGID 0x0409
// <s.126>Manufacturer String
// <i>String Descriptor describing Manufacturer.
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
// <s.126>Product String
// <i>String Descriptor describing Product.
#define USBD0_STR_DESC_PROD L"MCU-LINK"
// <e.0>Serial Number String
// <i>Enable Serial Number String.
// <i>If disabled Serial Number String will not be assigned to USB Device.
#define USBD0_STR_DESC_SER_EN 1
// <s.126>Default value
// <i>Default device's Serial Number String.
#define USBD0_STR_DESC_SER L"0001A0000000"
// <o.0..7>Maximum Length (in characters) <0-126>
// <i>Specifies the maximum number of Serial Number String characters that can be set at run-time.
// <i>Maximum value is 126. Use value 0 to disable RAM allocation for string.
#define USBD0_STR_DESC_SER_MAX_LEN 16
// </e>
// </h>
// <h>Microsoft OS Descriptors Settings
// <i>These settings are used to create the Microsoft OS Descriptors.
// <e.0>OS String
// <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
#define USBD0_OS_DESC_EN 1
// <o.0..7>Vendor Code <0x01-0xFF>
// <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
#define USBD0_OS_DESC_VENDOR_CODE 0x01
// </e>
// </h>
// <o>Control Transfer Buffer Size <64-65536:64>
// <i>Specifies size of buffer used for Control Transfers.
// <i>It should be at least as big as maximum packet size for Endpoint 0.
#define USBD0_EP0_BUF_SIZE 128
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Core Thread Stack Size <64-65536>
#define USBD0_CORE_THREAD_STACK_SIZE 1024
// Core Thread Priority
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
#include "RTE_Components.h"
#ifdef RTE_USB_Device_CustomClass_0
#include "USBD_Config_CustomClass_0.h"
#endif
#ifdef RTE_USB_Device_CustomClass_1
#include "USBD_Config_CustomClass_1.h"
#endif
#ifdef RTE_USB_Device_CustomClass_2
#include "USBD_Config_CustomClass_2.h"
#endif
#ifdef RTE_USB_Device_CustomClass_3
#include "USBD_Config_CustomClass_3.h"
#endif
#ifdef RTE_USB_Device_HID_0
#include "USBD_Config_HID_0.h"
#endif
#ifdef RTE_USB_Device_HID_1
#include "USBD_Config_HID_1.h"
#endif
#ifdef RTE_USB_Device_HID_2
#include "USBD_Config_HID_2.h"
#endif
#ifdef RTE_USB_Device_HID_3
#include "USBD_Config_HID_3.h"
#endif
#ifdef RTE_USB_Device_MSC_0
#include "USBD_Config_MSC_0.h"
#endif
#ifdef RTE_USB_Device_MSC_1
#include "USBD_Config_MSC_1.h"
#endif
#ifdef RTE_USB_Device_MSC_2
#include "USBD_Config_MSC_2.h"
#endif
#ifdef RTE_USB_Device_MSC_3
#include "USBD_Config_MSC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_0
#include "USBD_Config_CDC_0.h"
#endif
#ifdef RTE_USB_Device_CDC_1
#include "USBD_Config_CDC_1.h"
#endif
#ifdef RTE_USB_Device_CDC_2
#include "USBD_Config_CDC_2.h"
#endif
#ifdef RTE_USB_Device_CDC_3
#include "USBD_Config_CDC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_4
#include "USBD_Config_CDC_4.h"
#endif
#ifdef RTE_USB_Device_CDC_5
#include "USBD_Config_CDC_5.h"
#endif
#ifdef RTE_USB_Device_CDC_6
#include "USBD_Config_CDC_6.h"
#endif
#ifdef RTE_USB_Device_CDC_7
#include "USBD_Config_CDC_7.h"
#endif
#ifdef RTE_USB_Device_ADC_0
#include "USBD_Config_ADC_0.h"
#endif
#ifdef RTE_USB_Device_ADC_1
#include "USBD_Config_ADC_1.h"
#endif
#ifdef RTE_USB_Device_ADC_2
#include "USBD_Config_ADC_2.h"
#endif
#ifdef RTE_USB_Device_ADC_3
#include "USBD_Config_ADC_3.h"
#endif
#include "usbd_config.h"

364
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h vendored Normal file
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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_CDC_0.h
* Purpose: USB Device Communication Device Class (CDC) Configuration
* Rev.: V5.2.0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device: Communication Device Class (CDC) 0
// <o>Assign Device Class to USB Device # <0-3>
// <i>Select USB Device that is used for this Device Class instance
#define USBD_CDC0_DEV 0
// <o>Communication Class Subclass
// <i>Specifies the model used by the CDC class.
// <2=>Abstract Control Model (ACM)
// <13=>Network Control Model (NCM)
#define USBD_CDC0_SUBCLASS 2
// <o>Communication Class Protocol
// <i>Specifies the protocol used by the CDC class.
// <0=>No protocol (Virtual COM)
// <255=>Vendor-specific (RNDIS)
#define USBD_CDC0_PROTOCOL 0
// <h>Interrupt Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Interrupt IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_INT_IN 3
// <h>Endpoint Settings
// <i>Parameters are used to create Endpoint Descriptors
// <i>and for memory allocation in the USB component.
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE 16
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
#define USBD_CDC0_BINTERVAL 2
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 1024.
// <o.11..12>Additional transactions per microframe
// <i>Additional transactions improve communication performance.
// <0=>None <1=>1 additional <2=>2 additional
#define USBD_CDC0_HS_WMAXPACKETSIZE 16
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
#define USBD_CDC0_HS_BINTERVAL 2
// </h>
// </h>
// </h>
// <h>Bulk Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Bulk IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_IN 4
// <o.0..3>Bulk OUT Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_OUT 4
// <h>Endpoint Settings
// <i>Parameters are used to create USB Descriptors and for memory
// <i>allocation in the USB component.
//
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE1 64
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..9>Maximum Endpoint Packet Size (in bytes) <512=>512
// <i>Specifies the physical packet size used for information exchange.
// <i>Only available value is 512.
#define USBD_CDC0_HS_WMAXPACKETSIZE1 512
// <o.0..7>Maximum NAK Rate <0-255>
// <i>Specifies the interval in which Bulk Endpoint can NAK.
// <i>Value of 0 indicates that Bulk Endpoint never NAKs.
#define USBD_CDC0_HS_BINTERVAL1 0
// </h>
// </h>
// </h>
// <h>Communication Device Class Settings
// <i>Parameters are used to create USB Descriptors and for memory allocation
// <i>in the USB component.
//
// <s.126>Communication Class Interface String
#define USBD_CDC0_CIF_STR_DESC L"USB_CDC0_0"
// <s.126>Data Class Interface String
#define USBD_CDC0_DIF_STR_DESC L"USB_CDC0_1"
// <h>Abstract Control Model Settings
// <h>Call Management Capabilities
// <i>Specifies which call management functionality is supported.
// <o.1>Call Management channel
// <0=>Communication Class Interface only
// <1=>Communication and Data Class Interface
// <o.0>Device Call Management handling
// <0=>None
// <1=>All
// </h>
#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03
// <h>Abstract Control Management Capabilities
// <i>Specifies which abstract control management functionality is supported.
// <o.3>D3 bit
// <i>Enabled = Supports the notification Network_Connection
// <o.2>D2 bit
// <i>Enabled = Supports the request Send_Break
// <o.1>D1 bit
// <i>Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding,
// <i> Set_Control_Line_State, and notification Serial_State
// <o.0>D0 bit
// <i>Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature
// </h>
#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06
// <o>Maximum Communication Device Send Buffer Size
// <i>Specifies size of buffer used for sending of data to USB Host.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_SEND_BUF_SIZE 1024
// <o>Maximum Communication Device Receive Buffer Size
// <i>Specifies size of buffer used for receiving of data from USB Host.
// <i>Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint.
// <i>Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE 2048
// </h>
// <h>Network Control Model Settings
// <s.12>MAC Address String
// <i>Specifies 48-bit Ethernet MAC address.
#define USBD_CDC0_NCM_MAC_ADDRESS L"1E306CA2455E"
// <h>Ethernet Statistics
// <i>Specifies Ethernet statistic functions supported.
// <o.0>XMIT_OK
// <i>Frames transmitted without errors
// <o.1>RVC_OK
// <i>Frames received without errors
// <o.2>XMIT_ERROR
// <i>Frames not transmitted, or transmitted with errors
// <o.3>RCV_ERROR
// <i>Frames received with errors that are not delivered to the USB host.
// <o.4>RCV_NO_BUFFER
// <i>Frame missed, no buffers
// <o.5>DIRECTED_BYTES_XMIT
// <i>Directed bytes transmitted without errors
// <o.6>DIRECTED_FRAMES_XMIT
// <i>Directed frames transmitted without errors
// <o.7>MULTICAST_BYTES_XMIT
// <i>Multicast bytes transmitted without errors
// <o.8>MULTICAST_FRAMES_XMIT
// <i>Multicast frames transmitted without errors
// <o.9>BROADCAST_BYTES_XMIT
// <i>Broadcast bytes transmitted without errors
// <o.10>BROADCAST_FRAMES_XMIT
// <i>Broadcast frames transmitted without errors
// <o.11>DIRECTED_BYTES_RCV
// <i>Directed bytes received without errors
// <o.12>DIRECTED_FRAMES_RCV
// <i>Directed frames received without errors
// <o.13>MULTICAST_BYTES_RCV
// <i>Multicast bytes received without errors
// <o.14>MULTICAST_FRAMES_RCV
// <i>Multicast frames received without errors
// <o.15>BROADCAST_BYTES_RCV
// <i>Broadcast bytes received without errors
// <o.16>BROADCAST_FRAMES_RCV
// <i>Broadcast frames received without errors
// <o.17>RCV_CRC_ERROR
// <i>Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error
// <o.18>TRANSMIT_QUEUE_LENGTH
// <i>Length of transmit queue
// <o.19>RCV_ERROR_ALIGNMENT
// <i>Frames received with alignment error
// <o.20>XMIT_ONE_COLLISION
// <i>Frames transmitted with one collision
// <o.21>XMIT_MORE_COLLISIONS
// <i>Frames transmitted with more than one collision
// <o.22>XMIT_DEFERRED
// <i>Frames transmitted after deferral
// <o.23>XMIT_MAX_COLLISIONS
// <i>Frames not transmitted due to collisions
// <o.24>RCV_OVERRUN
// <i>Frames not received due to overrun
// <o.25>XMIT_UNDERRUN
// <i>Frames not transmitted due to underrun
// <o.26>XMIT_HEARTBEAT_FAILURE
// <i>Frames transmitted with heartbeat failure
// <o.27>XMIT_TIMES_CRS_LOST
// <i>Times carrier sense signal lost during transmission
// <o.28>XMIT_LATE_COLLISIONS
// <i>Late collisions detected
// </h>
#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS 0x00000003
// <o>Maximum Segment Size
// <i>Specifies maximum segment size that Ethernet device is capable of supporting.
// <i>Typically 1514 bytes.
#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE 1514
// <o.15>Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing)
// <i>Specifies multicast filtering type.
// <o.0..14>Number of Multicast Filters
// <i>Specifies number of multicast filters that can be configured by the USB Host.
#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS 1
// <o.0..7>Number of Power Filters
// <i>Specifies number of pattern filters that are available for causing wake-up of the USB Host.
#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS 0
// <h>Network Capabilities
// <i>Specifies which functions are supported.
// <o.4>SetCrcMode/GetCrcMode
// <o.3>SetMaxDatagramSize/GetMaxDatagramSize
// <o.1>SetNetAddress/GetNetAddress
// <o.0>SetEthernetPacketFilter
// </h>
#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES 0x1B
// <h>NTB Parameters
// <i>Specifies NTB parameters reported by GetNtbParameters function.
// <h>NTB Formats Supported (bmNtbFormatsSupported)
// <i>Specifies NTB formats supported.
// <o.0>16-bit NTB (always supported)
// <o.1>32-bit NTB
// </h>
#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED 0x0001
// <h>IN Data Pipe
//
// <o>Maximum NTB Size (dwNtbInMaxSize)
// <i>Specifies maximum IN NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpInDivisor)
// <i>Specifies divisor used for IN NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder)
// <i>Specifies remainder used to align input datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpInAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT 4
// </h>
// <h>OUT Data Pipe
//
// <o>Maximum NTB Size (dwNtbOutMaxSize)
// <i>Specifies maximum OUT NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpOutDivisor)
// <i>Specifies divisor used for OUT NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder)
// <i>Specifies remainder used to align output datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpOutAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT 4
// </h>
// </h>
// <o.0>Raw Data Access API
// <i>Enables or disables Raw Data Access API.
#define USBD_CDC0_NCM_RAW_ENABLE 0
// <o>IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for sending data to USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_IN_BUF_CNT 1
// <o>OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for receiving data from USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT 1
// </h>
// </h>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536>
#define USBD_CDC0_INT_THREAD_STACK_SIZE 512
// Communication Device Class Interrupt Endpoint Thread Priority
#define USBD_CDC0_INT_THREAD_PRIORITY osPriorityAboveNormal
// <o>Communication Device Class Bulk Endpoints Thread Stack Size <64-65536>
#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512
// Communication Device Class Bulk Endpoints Thread Priority
#define USBD_CDC0_BULK_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>

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/* -----------------------------------------------------------------------------
* Copyright (c) 2021 ARM Ltd.
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising from
* the use of this software. Permission is granted to anyone to use this
* software for any purpose, including commercial applications, and to alter
* it and redistribute it freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software in
* a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
*
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
*
* 3. This notice may not be removed or altered from any source distribution.
*
*
* $Date: 28. June 2021
* $Revision: V1.0
*
* Driver: Driver_USBD1
* Project: USB1 High-Speed Device Driver for NXP LPC55xxx
* --------------------------------------------------------------------------
* Use the following configuration settings in the middleware component
* to connect to this driver.
*
* Configuration Setting Value
* --------------------- -----
* Connect to hardware via Driver_USBD# = 1
* --------------------------------------------------------------------------
* Defines used for driver configuration (at compile time):
*
* USBD1_MAX_ENDPOINT_NUM: defines maximum number of IN/OUT Endpoint pairs
* that driver will support with Control Endpoint 0
* not included, this value impacts driver memory
* requirements
* - default value: 5
* - maximum value: 5
*
* USBD1_OUT_EP0_BUF_SZ: defines Out Endpoint0 buffer size (in Bytes)
* USBD1_IN_EP0_BUF_SZ: defines In Endpoint0 buffer size (in Bytes)
* USBD1_OUT_EP1_BUF_SZ: defines Out Endpoint1 buffer size (in Bytes)
* USBD1_IN_EP1_BUF_SZ: defines In Endpoint1 buffer size (in Bytes)
* USBD1_OUT_EP2_BUF_SZ: defines Out Endpoint2 buffer size (in Bytes)
* USBD1_IN_EP2_BUF_SZ: defines In Endpoint2 buffer size (in Bytes)
* USBD1_OUT_EP3_BUF_SZ: defines Out Endpoint3 buffer size (in Bytes)
* USBD1_IN_EP3_BUF_SZ: defines In Endpoint3 buffer size (in Bytes)
* USBD1_OUT_EP4_BUF_SZ: defines Out Endpoint4 buffer size (in Bytes)
* USBD1_IN_EP4_BUF_SZ: defines In Endpoint4 buffer size (in Bytes)
* USBD1_OUT_EP5_BUF_SZ: defines Out Endpoint5 buffer size (in Bytes)
* USBD1_IN_EP5_BUF_SZ: defines In Endpoint5 buffer size (in Bytes)
* -------------------------------------------------------------------------- */
/* History:
* Version 1.0
* Initial release
*/
#include <stdint.h>
#include <string.h>
#include "Driver_USBD.h"
#include "RTE_Device.h"
#include "RTE_Components.h"
#include "fsl_common.h"
#include "fsl_power.h"
#include "fsl_clock.h"
#include "fsl_reset.h"
#include "USB_LPC55xxx.h"
// Endpoint buffer must be 64Byte aligned
#define ALIGN_64(n) (n == 0U ? (0U) : (64U * (((n - 1U) / 64U) + 1U)))
#ifndef USBD1_MAX_ENDPOINT_NUM
#define USBD1_MAX_ENDPOINT_NUM (5U)
#endif
#if (USBD1_MAX_ENDPOINT_NUM > 5)
#error Too many Endpoints, maximum IN/OUT Endpoint pairs that this driver supports is 5 !!!
#endif
// Endpoint Bufer size definitions
#ifndef USBD1_OUT_EP0_BUF_SZ
#define USBD1_OUT_EP0_BUF_SZ (64U)
#endif
#ifndef USBD1_IN_EP0_BUF_SZ
#define USBD1_IN_EP0_BUF_SZ (64U)
#endif
#define USBD1_OUT_EP0_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP0_BUF_SZ))
#define USBD1_IN_EP0_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP0_BUF_SZ))
#if (USBD1_MAX_ENDPOINT_NUM > 0)
#ifndef USBD1_OUT_EP1_BUF_SZ
#define USBD1_OUT_EP1_BUF_SZ (1024U)
#endif
#ifndef USBD1_IN_EP1_BUF_SZ
#define USBD1_IN_EP1_BUF_SZ (1024U)
#endif
#else
#define USBD1_OUT_EP1_BUF_SZ (0U)
#define USBD1_IN_EP1_BUF_SZ (0U)
#endif
#define USBD1_OUT_EP1_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP1_BUF_SZ))
#define USBD1_IN_EP1_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP1_BUF_SZ))
#if (USBD1_MAX_ENDPOINT_NUM > 1)
#ifndef USBD1_OUT_EP2_BUF_SZ
#define USBD1_OUT_EP2_BUF_SZ (1024U)
#endif
#ifndef USBD1_IN_EP2_BUF_SZ
#define USBD1_IN_EP2_BUF_SZ (1024U)
#endif
#else
#define USBD1_OUT_EP2_BUF_SZ (0U)
#define USBD1_IN_EP2_BUF_SZ (0U)
#endif
#define USBD1_OUT_EP2_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP2_BUF_SZ))
#define USBD1_IN_EP2_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP2_BUF_SZ))
#if (USBD1_MAX_ENDPOINT_NUM > 2)
#ifndef USBD1_OUT_EP3_BUF_SZ
#define USBD1_OUT_EP3_BUF_SZ (1024U)
#endif
#ifndef USBD1_IN_EP3_BUF_SZ
#define USBD1_IN_EP3_BUF_SZ (1024U)
#endif
#else
#define USBD1_OUT_EP3_BUF_SZ (0U)
#define USBD1_IN_EP3_BUF_SZ (0U)
#endif
#define USBD1_OUT_EP3_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP3_BUF_SZ))
#define USBD1_IN_EP3_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP3_BUF_SZ))
#if (USBD1_MAX_ENDPOINT_NUM > 3)
#ifndef USBD1_OUT_EP4_BUF_SZ
#define USBD1_OUT_EP4_BUF_SZ (1024U)
#endif
#ifndef USBD1_IN_EP4_BUF_SZ
#define USBD1_IN_EP4_BUF_SZ (1024U)
#endif
#else
#define USBD1_OUT_EP4_BUF_SZ (0U)
#define USBD1_IN_EP4_BUF_SZ (0U)
#endif
#define USBD1_OUT_EP4_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP4_BUF_SZ))
#define USBD1_IN_EP4_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP4_BUF_SZ))
#if (USBD1_MAX_ENDPOINT_NUM > 4)
#ifndef USBD1_OUT_EP5_BUF_SZ
#define USBD1_OUT_EP5_BUF_SZ (1024U)
#endif
#ifndef USBD1_IN_EP5_BUF_SZ
#define USBD1_IN_EP5_BUF_SZ (1024U)
#endif
#else
#define USBD1_OUT_EP5_BUF_SZ (0U)
#define USBD1_IN_EP5_BUF_SZ (0U)
#endif
#define USBD1_OUT_EP5_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP5_BUF_SZ))
#define USBD1_IN_EP5_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP5_BUF_SZ))
#define USBD1_OUT_EP0_BUF_OFFSET (0U)
#define USBD1_IN_EP0_BUF_OFFSET (USBD1_OUT_EP0_BUF_SZ_64)
#define USBD1_OUT_EP1_BUF_OFFSET (USBD1_IN_EP0_BUF_OFFSET + USBD1_IN_EP0_BUF_SZ_64)
#define USBD1_IN_EP1_BUF_OFFSET (USBD1_OUT_EP1_BUF_OFFSET + USBD1_OUT_EP1_BUF_SZ_64)
#define USBD1_OUT_EP2_BUF_OFFSET (USBD1_IN_EP1_BUF_OFFSET + USBD1_IN_EP1_BUF_SZ_64)
#define USBD1_IN_EP2_BUF_OFFSET (USBD1_OUT_EP2_BUF_OFFSET + USBD1_OUT_EP2_BUF_SZ_64)
#define USBD1_OUT_EP3_BUF_OFFSET (USBD1_IN_EP2_BUF_OFFSET + USBD1_IN_EP2_BUF_SZ_64)
#define USBD1_IN_EP3_BUF_OFFSET (USBD1_OUT_EP3_BUF_OFFSET + USBD1_OUT_EP3_BUF_SZ_64)
#define USBD1_OUT_EP4_BUF_OFFSET (USBD1_IN_EP3_BUF_OFFSET + USBD1_IN_EP3_BUF_SZ_64)
#define USBD1_IN_EP4_BUF_OFFSET (USBD1_OUT_EP4_BUF_OFFSET + USBD1_OUT_EP4_BUF_SZ_64)
#define USBD1_OUT_EP5_BUF_OFFSET (USBD1_IN_EP4_BUF_OFFSET + USBD1_IN_EP4_BUF_SZ_64)
#define USBD1_IN_EP5_BUF_OFFSET (USBD1_OUT_EP5_BUF_OFFSET + USBD1_OUT_EP5_BUF_SZ_64)
#define USBD_EP_BUFFER_SZ (USBD1_OUT_EP0_BUF_SZ_64 + USBD1_IN_EP0_BUF_SZ_64 + \
USBD1_OUT_EP1_BUF_SZ_64 + USBD1_IN_EP1_BUF_SZ_64 + \
USBD1_OUT_EP2_BUF_SZ_64 + USBD1_IN_EP2_BUF_SZ_64 + \
USBD1_OUT_EP3_BUF_SZ_64 + USBD1_IN_EP3_BUF_SZ_64 + \
USBD1_OUT_EP4_BUF_SZ_64 + USBD1_IN_EP4_BUF_SZ_64 + \
USBD1_OUT_EP5_BUF_SZ_64 + USBD1_IN_EP5_BUF_SZ_64 )
#if (USBD_EP_BUFFER_SZ > 0x3C00U)
#error "Endpoint buffers do not fit into RAMx!"
#endif
#define EP_NUM(ep_addr) (ep_addr & ARM_USB_ENDPOINT_NUMBER_MASK)
#define EP_IDX(ep_addr) ((ep_addr & 0x80U) ? ((EP_NUM(ep_addr)) * 2U + 1U) : (ep_addr * 2U))
#define CMD_IDX(ep_addr) ((ep_addr & 0x80U) ? ((EP_NUM(ep_addr)) * 4U + 2U) : (ep_addr * 4U))
// Resource allocation
static uint8_t ep_buf[USBD_EP_BUFFER_SZ] __attribute__((section(".bss.ARM.__at_0x40100000")));
static EP_CMD ep_cmd[(USBD1_MAX_ENDPOINT_NUM + 1) * 4] __attribute__((section(".bss.ARM.__at_0x40103C00")));
static EP_TRANSFER ep_transfer[(USBD1_MAX_ENDPOINT_NUM + 1) * 2];
// Global variables
static ARM_USBD_STATE usbd_state;
static uint8_t usbd_flags;
static uint8_t setup_packet[8]; // Setup packet data
static volatile uint8_t setup_received; // Setup packet received
static ARM_USBD_SignalDeviceEvent_t SignalDeviceEvent;
static ARM_USBD_SignalEndpointEvent_t SignalEndpointEvent;
static const EP endpoint[] = {
// Endpoint 0
{ &(ep_cmd[0]), &(ep_buf[USBD1_OUT_EP0_BUF_OFFSET]), &(ep_transfer[0]), USBD1_OUT_EP0_BUF_OFFSET, },
{ &(ep_cmd[2]), &(ep_buf[USBD1_IN_EP0_BUF_OFFSET]), &(ep_transfer[1]), USBD1_IN_EP0_BUF_OFFSET, },
#if (USBD1_MAX_ENDPOINT_NUM > 0U)
// Endpoint 1
{ &(ep_cmd[4]), &(ep_buf[USBD1_OUT_EP1_BUF_OFFSET]), &(ep_transfer[2]), USBD1_OUT_EP1_BUF_OFFSET, },
{ &(ep_cmd[6]), &(ep_buf[USBD1_IN_EP1_BUF_OFFSET]), &(ep_transfer[3]), USBD1_IN_EP1_BUF_OFFSET, },
#endif
#if (USBD1_MAX_ENDPOINT_NUM > 1U)
// Endpoint 2
{ &(ep_cmd[8]), &(ep_buf[USBD1_OUT_EP2_BUF_OFFSET]), &(ep_transfer[4]), USBD1_OUT_EP2_BUF_OFFSET, },
{ &(ep_cmd[10]), &(ep_buf[USBD1_IN_EP2_BUF_OFFSET]), &(ep_transfer[5]), USBD1_IN_EP2_BUF_OFFSET, },
#endif
#if (USBD1_MAX_ENDPOINT_NUM > 2U)
// Endpoint 3
{ &(ep_cmd[12]), &(ep_buf[USBD1_OUT_EP3_BUF_OFFSET]), &(ep_transfer[6]), USBD1_OUT_EP3_BUF_OFFSET, },
{ &(ep_cmd[14]), &(ep_buf[USBD1_IN_EP3_BUF_OFFSET]), &(ep_transfer[7]), USBD1_IN_EP3_BUF_OFFSET, },
#endif
#if (USBD1_MAX_ENDPOINT_NUM > 3U)
// Endpoint 4
{ &(ep_cmd[16]), &(ep_buf[USBD1_OUT_EP4_BUF_OFFSET]), &(ep_transfer[8]), USBD1_OUT_EP4_BUF_OFFSET, },
{ &(ep_cmd[18]), &(ep_buf[USBD1_IN_EP4_BUF_OFFSET]), &(ep_transfer[9]), USBD1_IN_EP4_BUF_OFFSET, },
#endif
#if (USBD1_MAX_ENDPOINT_NUM > 4U)
// Endpoint 5
{ &(ep_cmd[16]), &(ep_buf[USBD1_OUT_EP5_BUF_OFFSET]), &(ep_transfer[8]), USBD1_OUT_EP5_BUF_OFFSET, },
{ &(ep_cmd[18]), &(ep_buf[USBD1_IN_EP5_BUF_OFFSET]), &(ep_transfer[9]), USBD1_IN_EP5_BUF_OFFSET, },
#endif
};
// USBD Driver *****************************************************************
#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
// Driver Version
static const ARM_DRIVER_VERSION usbd_driver_version = { ARM_USBD_API_VERSION, ARM_USBD_DRV_VERSION };
// Driver Capabilities
static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
#if (USBD_VBUS_DETECT == 1)
1U, // VBUS Detection
1U, // Event VBUS On
1U, // Event VBUS Off
#else
0U, // VBUS Detection
0U, // Event VBUS On
0U // Event VBUS Off
#endif
};
/**
\fn void USBD_Reset (void)
\brief Reset USB Endpoint settings and variables.
*/
static void USBD_Reset (void) {
// Clear USB Endpoint command/status list
memset((void *)ep_cmd, 0, sizeof(ep_cmd));
memset((void *)&usbd_state, 0, sizeof(usbd_state));
}
// USBD Driver functions
/**
\fn ARM_DRIVER_VERSION USBD_GetVersion (void)
\brief Get driver version.
\return \ref ARM_DRIVER_VERSION
*/
static ARM_DRIVER_VERSION USBD_GetVersion (void) { return usbd_driver_version; }
/**
\fn ARM_USBD_CAPABILITIES USBD_GetCapabilities (void)
\brief Get driver capabilities.
\return \ref ARM_USBD_CAPABILITIES
*/
static ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) { return usbd_driver_capabilities; }
/**
\fn int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event,
ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
\brief Initialize USB Device Interface.
\param[in] cb_device_event Pointer to \ref ARM_USBD_SignalDeviceEvent
\param[in] cb_endpoint_event Pointer to \ref ARM_USBD_SignalEndpointEvent
\return \ref execution_status
*/
static int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event,
ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) {
if ((usbd_flags & USBD_DRIVER_FLAG_INITIALIZED) != 0U) { return ARM_DRIVER_OK; }
SignalDeviceEvent = cb_device_event;
SignalEndpointEvent = cb_endpoint_event;
usbd_flags = USBD_DRIVER_FLAG_INITIALIZED;
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_Uninitialize (void)
\brief De-initialize USB Device Interface.
\return \ref execution_status
*/
static int32_t USBD_Uninitialize (void) {
usbd_flags &= ~USBD_DRIVER_FLAG_INITIALIZED;
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_PowerControl (ARM_POWER_STATE state)
\brief Control USB Device Interface Power.
\param[in] state Power state
\return \ref execution_status
*/
static int32_t USBD_PowerControl (ARM_POWER_STATE state) {
switch (state) {
case ARM_POWER_OFF:
NVIC_DisableIRQ (USB1_IRQn); // Disable interrupt
NVIC_ClearPendingIRQ (USB1_IRQn); // Clear pending interrupt
usbd_flags &= ~USBD_DRIVER_FLAG_POWERED; // Clear powered flag
RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn); // Reset USB1 Device controller
RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn); // Reset USB1 PHY
RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); // Reset USB1 RAM controller
// Disable USB IP clock
SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_RAM(1);
SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_DEV(1);
SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_PHY(1);
// Clear USB Endpoint command/status list
memset((void *)ep_cmd, 0, sizeof(ep_cmd));
// Clear Endpoint transfer structure
memset((void *)ep_transfer, 0, sizeof(ep_transfer));
break;
case ARM_POWER_FULL:
if ((usbd_flags & USBD_DRIVER_FLAG_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) != 0U) { return ARM_DRIVER_OK; }
// Enable USB IP clock
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, 16000000U);
CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
// Enable device operation (through USB1 Host PORTMODE register)
CLOCK_EnableClock(kCLOCK_Usbh1);
USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK;
USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
CLOCK_DisableClock(kCLOCK_Usbh1);
// Setup PHY
USBPHY->PWD = 0U;
USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
// Clear USB RAM
memset((void *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
// Reset variables and endpoint settings
USBD_Reset ();
// Set Endpoint list start address
USBHSD->EPLISTSTART = (uint32_t)ep_cmd;
// Set USB Data buffer start address
USBHSD->DATABUFSTART = (uint32_t)ep_buf;
// Enable device status interrupt
USBHSD->INTEN = USB_INTSTAT_DEV_INT_MASK;
usbd_flags |= USBD_DRIVER_FLAG_POWERED;
// Enable USB interrupt
NVIC_EnableIRQ (USB1_IRQn);
break;
default:
return ARM_DRIVER_ERROR_UNSUPPORTED;
}
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_DeviceConnect (void)
\brief Connect USB Device.
\return \ref execution_status
*/
static int32_t USBD_DeviceConnect (void) {
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
// Attach Device
USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DCON_MASK;
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_DeviceDisconnect (void)
\brief Disconnect USB Device.
\return \ref execution_status
*/
static int32_t USBD_DeviceDisconnect (void) {
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
// Detach Device
USBHSD->DEVCMDSTAT &= ~USB_DEVCMDSTAT_DCON_MASK;
return ARM_DRIVER_OK;
}
/**
\fn ARM_USBD_STATE USBD_DeviceGetState (void)
\brief Get current USB Device State.
\return Device State \ref ARM_USBD_STATE
*/
static ARM_USBD_STATE USBD_DeviceGetState (void) {
ARM_USBD_STATE dev_state = { 0U, 0U, 0U };
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return dev_state; }
return usbd_state;
}
/**
\fn int32_t USBD_DeviceRemoteWakeup (void)
\brief Trigger USB Remote Wakeup.
\return \ref execution_status
*/
static int32_t USBD_DeviceRemoteWakeup (void) {
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
// Force remote wakeup
USBHSD->DEVCMDSTAT &= ~USB_DEVCMDSTAT_DSUS_MASK;
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_DeviceSetAddress (uint8_t dev_addr)
\brief Set USB Device Address.
\param[in] dev_addr Device Address
\return \ref execution_status
*/
static int32_t USBD_DeviceSetAddress (uint8_t dev_addr) {
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_ReadSetupPacket (uint8_t *setup)
\brief Read setup packet received over Control Endpoint.
\param[out] setup Pointer to buffer for setup packet
\return \ref execution_status
*/
static int32_t USBD_ReadSetupPacket (uint8_t *setup) {
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
if (setup_received == 0U) { return ARM_DRIVER_ERROR; }
setup_received = 0U;
memcpy(setup, setup_packet, 8);
if (setup_received != 0U) { // If new setup packet was received while this was being read
return ARM_DRIVER_ERROR;
}
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_EndpointConfigure (uint8_t ep_addr,
uint8_t ep_type,
uint16_t ep_max_packet_size)
\brief Configure USB Endpoint.
\param[in] ep_addr Endpoint Address
- ep_addr.0..3: Address
- ep_addr.7: Direction
\param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx)
\param[in] ep_max_packet_size Endpoint Maximum Packet Size
\return \ref execution_status
*/
static int32_t USBD_EndpointConfigure (uint8_t ep_addr,
uint8_t ep_type,
uint16_t ep_max_packet_size) {
uint8_t ep_num, ep_idx;
EP const * ep;
volatile uint32_t DBG1 = 0;
volatile uint32_t DBG2 = 0;
volatile uint32_t DBG3 = 0;
volatile uint32_t DBG4 = 0;
volatile uint32_t DBG5 = ep_addr;
volatile uint32_t DBG6 = ep_type;
volatile uint32_t DBG7 = ep_max_packet_size;
ep_num = EP_NUM(ep_addr);
ep_idx = EP_IDX(ep_addr);
ep = &endpoint[ep_idx];
if (ep_num > USBD1_MAX_ENDPOINT_NUM) {
DBG1++;
return ARM_DRIVER_ERROR;
}
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) {
DBG2++;
return ARM_DRIVER_ERROR;
}
if (ep->cmd->active == 1U) {
// Endpoint is "owned" by hardware
DBG3++;
return ARM_DRIVER_ERROR_BUSY;
}
if (ep_max_packet_size > ((ep+1)->buf_offset - ep->buf_offset)) {
// Configured Endpoint buffer size is too small
DBG4++;
return ARM_DRIVER_ERROR;
}
// Clear Endpoint command/status
memset((void *)ep->cmd, 0, sizeof(EP_CMD) * 2U);
// Clear Endpoint transfer structure
memset((void *)ep->transfer, 0, sizeof(EP_TRANSFER));
ep_transfer[ep_idx].max_packet_sz = ep_max_packet_size & ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK;
ep->cmd->buff_addr_offset = ep->buf_offset >> 6;
if (ep_num != 0U) {
ep->cmd->ep_disabled = 1U;
// Reset data toggle
ep->cmd->ep_type_periodic = 0U;
ep->cmd->toggle_value = 0U;
ep->cmd->toggle_reset = 1U;
switch (ep_type) {
case ARM_USB_ENDPOINT_CONTROL:
break;
case ARM_USB_ENDPOINT_ISOCHRONOUS:
ep->cmd->toggle_value = 0U;
ep->cmd->ep_type_periodic = 1U;
break;
case ARM_USB_ENDPOINT_BULK:
ep->cmd->toggle_value = 0U;
ep->cmd->ep_type_periodic = 0U;
break;
case ARM_USB_ENDPOINT_INTERRUPT:
ep->cmd->toggle_value = 1U;
ep->cmd->ep_type_periodic = 1U;
break;
default: // Unknown endpoint type
return ARM_DRIVER_ERROR;
}
ep->cmd->ep_disabled = 0U;
/* Double-buffering not configured/used */
ep->cmd[1].buff_addr_offset = ep->buf_offset >> 6;
ep->cmd[1].ep_disabled = 1U;
}
// Clear Endpoint Interrupt
USBHSD->INTSTAT = USB_INT_EP(ep_idx);
// Enable endpoint interrupt
USBHSD->INTEN |= USB_INT_EP(ep_idx);
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_EndpointUnconfigure (uint8_t ep_addr)
\brief Unconfigure USB Endpoint.
\param[in] ep_addr Endpoint Address
- ep_addr.0..3: Address
- ep_addr.7: Direction
\return \ref execution_status
*/
static int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) {
uint8_t ep_num, ep_idx;
EP const * ep;
ep_num = EP_NUM(ep_addr);
ep_idx = EP_IDX(ep_addr);
ep = &endpoint[ep_idx];
if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; }
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
if (ep->cmd->active == 1U) {
// Endpoint is "owned" by hardware
return ARM_DRIVER_ERROR_BUSY;
}
// Disable endpoint interrupt
USBHSD->INTEN &= ~USB_INT_EP(ep_idx);
if (ep->cmd->active) {
USBHSD->EPSKIP |= (1U << ep_idx);
while (USBHSD->EPSKIP & (1U << ep_idx));
}
// Clear Endpoint command/status
memset((void *)ep->cmd, 0, sizeof(EP_CMD) * 2U);
ep->cmd->ep_disabled = 1U;
// Clear Endpoint Interrupt
USBHSD->INTSTAT = USB_INT_EP(ep_idx);
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall)
\brief Set/Clear Stall for USB Endpoint.
\param[in] ep_addr Endpoint Address
- ep_addr.0..3: Address
- ep_addr.7: Direction
\param[in] stall Operation
- \b false Clear
- \b true Set
\return \ref execution_status
*/
static int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) {
uint8_t ep_num;
EP const * ep;
ep_num = EP_NUM(ep_addr);
ep = &endpoint[EP_IDX(ep_addr)];
if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; }
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
if (ep->cmd->active == 1U) {
// Endpoint is "owned" by hardware
return ARM_DRIVER_ERROR_BUSY;
}
if (stall != 0U) {
// Set Endpoint stall
ep->cmd->stall = 1U;
} else {
ep->cmd->toggle_value = 0U;
ep->cmd->toggle_reset = 1U;
// Clear Stall
ep->cmd->stall = 0U;
}
return ARM_DRIVER_OK;
}
/**
\fn int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
\brief Read data from or Write data to USB Endpoint.
\param[in] ep_addr Endpoint Address
- ep_addr.0..3: Address
- ep_addr.7: Direction
\param[out] data Pointer to buffer for data to read or with data to write
\param[in] num Number of data bytes to transfer
\return \ref execution_status
*/
static int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) {
uint8_t ep_num, ep_idx;
EP const * ep;
ep_num = EP_NUM(ep_addr);
ep_idx = EP_IDX(ep_addr);
ep = &endpoint[ep_idx];
if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; }
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
if (ep->cmd->active == 1U) {
// Endpoint is "owned" by hardware
return ARM_DRIVER_ERROR_BUSY;
}
ep->transfer->num = num;
ep->transfer->buf = data;
ep->transfer->num_transferred_total = 0U;
if (num > ep->transfer->max_packet_sz) { num = ep->transfer->max_packet_sz; }
if (ep_addr & ARM_USB_ENDPOINT_DIRECTION_MASK) {
// Copy data into IN Endpoint buffer
memcpy (ep->buf, ep->transfer->buf, num);
}
ep->cmd->buff_addr_offset = ep->buf_offset >> 6;
ep->transfer->num_transferring = num;
// Set number of bytes to send/receive
ep->cmd->NBytes = num;
// Activate endpoint
ep->cmd->active |= 1U;
return ARM_DRIVER_OK;
}
/**
\fn uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr)
\brief Get result of USB Endpoint transfer.
\param[in] ep_addr Endpoint Address
- ep_addr.0..3: Address
- ep_addr.7: Direction
\return number of successfully transferred data bytes
*/
static uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) {
if (EP_NUM(ep_addr) > USBD1_MAX_ENDPOINT_NUM) { return 0U; }
return (ep_transfer[EP_IDX(ep_addr)].num_transferred_total);
}
/**
\fn int32_t USBD_EndpointTransferAbort (uint8_t ep_addr)
\brief Abort current USB Endpoint transfer.
\param[in] ep_addr Endpoint Address
- ep_addr.0..3: Address
- ep_addr.7: Direction
\return \ref execution_status
*/
static int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) {
uint8_t ep_num, ep_idx;
EP const * ep;
ep_num = EP_NUM(ep_addr);
ep_idx = EP_IDX(ep_addr);
ep = &endpoint[ep_idx];
if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; }
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
// Disable endpoint interrupt
USBHSD->INTEN &= ~USB_INT_EP(ep_idx);
if (ep->cmd->active == 1U) {
USBHSD->EPSKIP |= (1U << EP_IDX(ep_addr));
while (USBHSD->EPSKIP & (1U << EP_IDX(ep_addr)));
ep->cmd->active = 0U;
}
// Clear transfer info
ep->transfer->num = 0U;
ep->transfer->num_transferred_total = 0U;
ep->transfer->num_transferring = 0U;
// Clear Endpoint Interrupt
USBHSD->INTSTAT = USB_INT_EP(ep_idx);
// Enable endpoint interrupt
USBHSD->INTEN |= USB_INT_EP(ep_idx);
return ARM_DRIVER_OK;
}
/**
\fn uint16_t USBD_GetFrameNumber (void)
\brief Get current USB Frame Number.
\return Frame Number
*/
static uint16_t USBD_GetFrameNumber (void) {
if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return 0; }
return ((USBHSD->INFO & USB_INFO_FRAME_NR_MASK) >> USB_INFO_FRAME_NR_SHIFT);
}
/**
\fn void USB1_IRQHandler (void)
\brief USB1 Device Interrupt Routine (IRQ).
*/
void USB1_IRQHandler (void) {
uint32_t num, ep_idx, intstat, cmdstat, dev_evt = 0U;
uint16_t val;
EP const * ep;
intstat = USBHSD->INTSTAT & USBHSD->INTEN;
cmdstat = USBHSD->DEVCMDSTAT;
// Clear interrupt flags
USBHSD->INTSTAT = intstat;
// Device Status interrupt
if (intstat & USB_INTSTAT_DEV_INT_MASK) {
// Reset
if (cmdstat & USB_DEVCMDSTAT_DRES_C_MASK) {
USBD_Reset ();
usbd_state.active = 1U;
usbd_state.speed = ARM_USB_SPEED_FULL;
USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DRES_C_MASK | USB_DEVCMDSTAT_DEV_EN_MASK;
SignalDeviceEvent(ARM_USBD_EVENT_RESET);
if (((USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >> USBHSD_DEVCMDSTAT_Speed_SHIFT) == 2U) {
SignalDeviceEvent(ARM_USBD_EVENT_HIGH_SPEED);
}
}
// Suspend
if (cmdstat & USB_DEVCMDSTAT_DSUS_MASK) {
usbd_state.active = 0U;
USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DSUS_MASK;
SignalDeviceEvent(ARM_USBD_EVENT_SUSPEND);
}
#if (USBD_VBUS_DETECT == 1)
// Disconnect
if (cmdstat & USB_DEVCMDSTAT_DCON_C) {
usbd_state.active = 0U;
usbd_state.vbus = 0U;
LPC_USB->DEVCMDSTAT |= USB_DEVCMDSTAT_DCON_C;
SignalDeviceEvent(ARM_USBD_EVENT_VBUS_OFF);
}
// VBUS De-bounced
if (cmdstat & USB_DEVCMDSTAT_VBUS_DEBOUNCED) {
usbd_state.vbus = 1U;
SignalDeviceEvent(ARM_USBD_EVENT_VBUS_ON);
}
#endif
}
// Endpoint interrupt
if (intstat & USB_INT_EP_MSK) {
for (ep_idx = 0; ep_idx <= USBD1_MAX_ENDPOINT_NUM * 2U; ep_idx += 2U) {
if (intstat & (USB_INT_EP(ep_idx))) {
// Clear Interrupt status
USBHSD->INTSTAT = (1 << ep_idx);
// Setup Packet
if ((ep_idx == 0U) && ((cmdstat & USB_DEVCMDSTAT_SETUP_MASK) != 0U)) {
ep_cmd[0].stall = 0U;
ep_cmd[1].stall = 0U;
ep_cmd[2].stall = 0U;
ep_cmd[3].stall = 0U;
USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_SETUP_MASK;
memcpy(setup_packet, ep_buf, 8);
// Analyze Setup packet for SetAddress
val = setup_packet[0] | (setup_packet[1] << 8);
if (val == 0x0500U) {
val = (setup_packet[2] | (setup_packet[3] << 8)) & USB_DEVCMDSTAT_DEV_ADDR_MASK;
// Set device address
USBHSD->DEVCMDSTAT = (USBHSD->DEVCMDSTAT & ~USB_DEVCMDSTAT_DEV_ADDR_MASK) |
USB_DEVCMDSTAT_DEV_ADDR(val) | USB_DEVCMDSTAT_DEV_EN_MASK;
}
setup_received = 1U;
if (SignalEndpointEvent != NULL) {
SignalEndpointEvent(0U, ARM_USBD_EVENT_SETUP);
}
} else {
// OUT Packet
ep = &endpoint[ep_idx];
num = ep->transfer->num_transferring - ep->cmd->NBytes;
// Copy EP data
memcpy (ep->transfer->buf, ep->buf, num);
ep->transfer->buf += num;
ep->transfer->num_transferred_total += num;
// Check if all OUT data received:
// - data terminated with ZLP or short packet or
// - all required data received
if ((ep->transfer->num_transferred_total == ep->transfer->num) ||
(num == 0U) || (num != ep->transfer->max_packet_sz)) {
if (SignalEndpointEvent != NULL) {
SignalEndpointEvent(ep_idx / 2U, ARM_USBD_EVENT_OUT);
}
} else {
// Remaining data to transfer
num = ep->transfer->num - ep->transfer->num_transferred_total;
if (num > ep->transfer->max_packet_sz) { num = ep->transfer->max_packet_sz; }
ep->transfer->num_transferring = num;
ep->cmd->NBytes = num;
ep->cmd->buff_addr_offset = ep->buf_offset >> 6;
// Activate EP to receive next packet
ep->cmd->active = 1U;
}
}
}
}
// IN Packet
for (ep_idx = 1; ep_idx <= USBD1_MAX_ENDPOINT_NUM * 2U; ep_idx += 2U) {
if (intstat & (USB_INT_EP(ep_idx))) {
// Clear Interrupt status
USBHSD->INTSTAT = (1 << ep_idx);
ep = &endpoint[ep_idx];
ep->transfer->buf += ep->transfer->num_transferring;
ep->transfer->num_transferred_total += ep->transfer->num_transferring;
if (ep->transfer->num_transferred_total == ep->transfer->num) {
// All data has been transfered
if (SignalEndpointEvent != NULL) {
SignalEndpointEvent(0x80 | (ep_idx / 2), ARM_USBD_EVENT_IN);
}
} else {
// Still data to transfer
num = ep->transfer->num - ep->transfer->num_transferred_total;
if (num > ep->transfer->max_packet_sz) {
// Remaining data bigger than max packet
num = ep->transfer->max_packet_sz;
}
ep->transfer->num_transferring = num;
// Copy data into IN Endpoint buffer
memcpy (ep->buf, ep->transfer->buf, num);
ep->cmd->buff_addr_offset = ep->buf_offset >> 6;
// Set number of bytes to send
ep->cmd->NBytes = num;
// Activate EP to send next packet
ep->cmd->active = 1U;
}
}
}
}
}
ARM_DRIVER_USBD Driver_USBD1 = {
USBD_GetVersion,
USBD_GetCapabilities,
USBD_Initialize,
USBD_Uninitialize,
USBD_PowerControl,
USBD_DeviceConnect,
USBD_DeviceDisconnect,
USBD_DeviceGetState,
USBD_DeviceRemoteWakeup,
USBD_DeviceSetAddress,
USBD_ReadSetupPacket,
USBD_EndpointConfigure,
USBD_EndpointUnconfigure,
USBD_EndpointStall,
USBD_EndpointTransfer,
USBD_EndpointTransferGetResult,
USBD_EndpointTransferAbort,
USBD_GetFrameNumber
};

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external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CDC_ACM_UART_0.c vendored Normal file
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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device:CDC
* Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_User_CDC_ACM_UART_0.c
* Purpose: USB Device Communication Device Class (CDC)
* Abstract Control Model (ACM) USB <-> UART Bridge User module
* Rev.: V1.0.8
*----------------------------------------------------------------------------*/
/**
* \addtogroup usbd_cdcFunctions
*
* USBD_User_CDC_ACM_UART_0.c implements the application specific
* functionality of the CDC ACM class and is used to demonstrate a USB <-> UART
* bridge. All data received on USB is transmitted on UART and all data
* received on UART is transmitted on USB.
*
* Details of operation:
* UART -> USB:
* Initial reception on UART is started after the USB Host sets line coding
* with SetLineCoding command. Having received a full UART buffer, any
* new reception is restarted on the same buffer. Any data received on
* the UART is sent over USB using the CDC0_ACM_UART_to_USB_Thread thread.
* USB -> UART:
* While the UART transmit is not busy, data transmission on the UART is
* started in the USBD_CDC0_ACM_DataReceived callback as soon as data is
* received on the USB. Further data received on USB is transmitted on
* UART in the UART callback routine until there is no more data available.
* In this case, the next UART transmit is restarted from the
* USBD_CDC0_ACM_DataReceived callback as soon as new data is received
* on the USB.
*
* The following constants in this module affect the module functionality:
*
* - UART_PORT: specifies UART Port
* default value: 0 (=UART0)
* - UART_BUFFER_SIZE: specifies UART data Buffer Size
* default value: 512
*
* Notes:
* If the USB is slower than the UART, data can get lost. This may happen
* when USB is pausing during data reception because of the USB Host being
* too loaded with other tasks and not polling the Bulk IN Endpoint often
* enough (up to 2 seconds of gap in polling Bulk IN Endpoint may occur).
* This problem can be solved by using a large enough UART buffer to
* compensate up to a few seconds of received UART data or by using UART
* flow control.
* If the device that receives the UART data (usually a PC) is too loaded
* with other tasks it can also loose UART data. This problem can only be
* solved by using UART flow control.
*
* This file has to be adapted in case of UART flow control usage.
*/
//! [code_USBD_User_CDC_ACM]
#include <stdio.h>
#include <string.h>
#include "rl_usb.h"
#include "Driver_USART.h"
#include "DAP_config.h"
#include "DAP.h"
// UART Configuration ----------------------------------------------------------
#define UART_BUFFER_SIZE (512) // UART Buffer Size
//------------------------------------------------------------------------------
#define _UART_Driver_(n) Driver_USART##n
#define UART_Driver_(n) _UART_Driver_(n)
extern ARM_DRIVER_USART UART_Driver_(DAP_UART_DRIVER);
#define ptrUART (&UART_Driver_(DAP_UART_DRIVER))
// Local Variables
static uint8_t uart_rx_buf[UART_BUFFER_SIZE];
static uint8_t uart_tx_buf[UART_BUFFER_SIZE];
static volatile int32_t uart_rx_cnt = 0;
static volatile int32_t usb_tx_cnt = 0;
static void *cdc_acm_bridge_tid = 0U;
static CDC_LINE_CODING cdc_acm_line_coding = { 0U, 0U, 0U, 0U };
static uint8_t cdc_acm_active = 1U;
static osMutexId_t cdc_acm_mutex_id = NULL;
// Acquire mutex
__STATIC_INLINE void CDC_ACM_Lock (void) {
if (cdc_acm_mutex_id == NULL) {
cdc_acm_mutex_id = osMutexNew(NULL);
}
osMutexAcquire(cdc_acm_mutex_id, osWaitForever);
}
// Release mutex
__STATIC_INLINE void CDC_ACM_Unlock (void) {
osMutexRelease(cdc_acm_mutex_id);
}
// Change communication settings.
// \param[in] line_coding pointer to CDC_LINE_CODING structure.
// \return true set line coding request processed.
// \return false set line coding request not supported or not processed.
static bool CDC_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
uint32_t data_bits = 0U, parity = 0U, stop_bits = 0U;
int32_t status;
(void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U);
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
(void)ptrUART->Control (ARM_USART_CONTROL_TX, 0U);
(void)ptrUART->Control (ARM_USART_CONTROL_RX, 0U);
switch (line_coding->bCharFormat) {
case 0: // 1 Stop bit
stop_bits = ARM_USART_STOP_BITS_1;
break;
case 1: // 1.5 Stop bits
stop_bits = ARM_USART_STOP_BITS_1_5;
break;
case 2: // 2 Stop bits
stop_bits = ARM_USART_STOP_BITS_2;
break;
default:
return false;
}
switch (line_coding->bParityType) {
case 0: // None
parity = ARM_USART_PARITY_NONE;
break;
case 1: // Odd
parity = ARM_USART_PARITY_ODD;
break;
case 2: // Even
parity = ARM_USART_PARITY_EVEN;
break;
default:
return false;
}
switch (line_coding->bDataBits) {
case 5:
data_bits = ARM_USART_DATA_BITS_5;
break;
case 6:
data_bits = ARM_USART_DATA_BITS_6;
break;
case 7:
data_bits = ARM_USART_DATA_BITS_7;
break;
case 8:
data_bits = ARM_USART_DATA_BITS_8;
break;
default:
return false;
}
status = ptrUART->Control(ARM_USART_MODE_ASYNCHRONOUS |
data_bits |
parity |
stop_bits ,
line_coding->dwDTERate );
if (status != ARM_DRIVER_OK) {
return false;
}
// Store requested settings to local variable
memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
uart_rx_cnt = 0;
usb_tx_cnt = 0;
(void)ptrUART->Control (ARM_USART_CONTROL_TX, 1U);
(void)ptrUART->Control (ARM_USART_CONTROL_RX, 1U);
(void)ptrUART->Receive (uart_rx_buf, UART_BUFFER_SIZE);
return true;
}
// Activate or Deactivate USBD COM PORT
// \param[in] cmd 0=deactivate, 1=activate
// \return 0=Ok, 0xFF=Error
uint8_t USB_COM_PORT_Activate (uint32_t cmd) {
switch (cmd) {
case 0U:
cdc_acm_active = 0U;
USBD_CDC0_ACM_Uninitialize();
break;
case 1U:
USBD_CDC0_ACM_Initialize();
CDC_ACM_Lock();
CDC_ACM_SetLineCoding(&cdc_acm_line_coding);
cdc_acm_active = 1U;
CDC_ACM_Unlock();
break;
}
return 0U;
}
// Called when UART has transmitted or received requested number of bytes.
// \param[in] event UART event
// - ARM_USART_EVENT_SEND_COMPLETE: all requested data was sent
// - ARM_USART_EVENT_RECEIVE_COMPLETE: all requested data was received
static void UART_Callback (uint32_t event) {
int32_t cnt;
if (cdc_acm_active == 0U) {
return;
}
if (event & ARM_USART_EVENT_SEND_COMPLETE) {
// USB -> UART
cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
if (cnt > 0) {
(void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
}
}
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
// UART data received, restart new reception
uart_rx_cnt += UART_BUFFER_SIZE;
(void)ptrUART->Receive(uart_rx_buf, UART_BUFFER_SIZE);
}
}
// Thread: Sends data received on UART to USB
// \param[in] arg not used.
__NO_RETURN static void CDC0_ACM_UART_to_USB_Thread (void *arg) {
int32_t cnt, cnt_to_wrap;
(void)(arg);
for (;;) {
// UART - > USB
if (ptrUART->GetStatus().rx_busy != 0U) {
cnt = uart_rx_cnt;
cnt += (int32_t)ptrUART->GetRxCount();
cnt -= usb_tx_cnt;
if (cnt >= (UART_BUFFER_SIZE - 32)) {
// Dump old data in UART receive buffer if USB is not consuming fast enough
cnt = (UART_BUFFER_SIZE - 32);
usb_tx_cnt = uart_rx_cnt - (UART_BUFFER_SIZE - 32);
}
if (cnt > 0) {
cnt_to_wrap = (int32_t)(UART_BUFFER_SIZE - ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1)));
if (cnt > cnt_to_wrap) {
cnt = cnt_to_wrap;
}
cnt = USBD_CDC_ACM_WriteData(0U, (uart_rx_buf + ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))), cnt);
if (cnt > 0) {
usb_tx_cnt += cnt;
}
}
}
(void)osDelay(10U);
}
}
static osRtxThread_t cdc0_acm_uart_to_usb_thread_cb_mem __SECTION(.bss.os.thread.cb);
static uint64_t cdc0_acm_uart_to_usb_thread_stack_mem[512U / 8U] __SECTION(.bss.os.thread.cdc.stack);
static const osThreadAttr_t cdc0_acm_uart_to_usb_thread_attr = {
"CDC0_ACM_UART_to_USB_Thread",
0U,
&cdc0_acm_uart_to_usb_thread_cb_mem,
sizeof(osRtxThread_t),
&cdc0_acm_uart_to_usb_thread_stack_mem[0],
sizeof(cdc0_acm_uart_to_usb_thread_stack_mem),
osPriorityNormal,
0U,
0U
};
// CDC ACM Callbacks -----------------------------------------------------------
// Called when new data was received from the USB Host.
// \param[in] len number of bytes available to read.
void USBD_CDC0_ACM_DataReceived (uint32_t len) {
int32_t cnt;
(void)(len);
if (cdc_acm_active == 0U) {
return;
}
if (ptrUART->GetStatus().tx_busy == 0U) {
// Start USB -> UART
cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
if (cnt > 0) {
(void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
}
}
}
// Called during USBD_Initialize to initialize the USB CDC class instance (ACM).
void USBD_CDC0_ACM_Initialize (void) {
(void)ptrUART->Initialize (UART_Callback);
(void)ptrUART->PowerControl (ARM_POWER_FULL);
cdc_acm_bridge_tid = osThreadNew (CDC0_ACM_UART_to_USB_Thread, NULL, &cdc0_acm_uart_to_usb_thread_attr);
}
// Called during USBD_Uninitialize to de-initialize the USB CDC class instance (ACM).
void USBD_CDC0_ACM_Uninitialize (void) {
if (osThreadTerminate (cdc_acm_bridge_tid) == osOK) {
cdc_acm_bridge_tid = NULL;
}
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
(void)ptrUART->PowerControl (ARM_POWER_OFF);
(void)ptrUART->Uninitialize ();
}
// Called upon USB Bus Reset Event.
void USBD_CDC0_ACM_Reset (void) {
if (cdc_acm_active == 0U ) {
return;
}
(void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U);
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
}
// Called upon USB Host request to change communication settings.
// \param[in] line_coding pointer to CDC_LINE_CODING structure.
// \return true set line coding request processed.
// \return false set line coding request not supported or not processed.
bool USBD_CDC0_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
bool ret = false;
CDC_ACM_Lock();
if (cdc_acm_active == 0U) {
// Store requested settings to local variable
memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
ret = true;
} else {
ret = CDC_ACM_SetLineCoding(line_coding);
}
CDC_ACM_Unlock();
return ret;
}
// Called upon USB Host request to retrieve communication settings.
// \param[out] line_coding pointer to CDC_LINE_CODING structure.
// \return true get line coding request processed.
// \return false get line coding request not supported or not processed.
bool USBD_CDC0_ACM_GetLineCoding (CDC_LINE_CODING *line_coding) {
// Load settings from ones stored on USBD_CDC0_ACM_SetLineCoding callback
*line_coding = cdc_acm_line_coding;
return true;
}
// Called upon USB Host request to set control line states.
// \param [in] state control line settings bitmap.
// - bit 0: DTR state
// - bit 1: RTS state
// \return true set control line state request processed.
// \return false set control line state request not supported or not processed.
bool USBD_CDC0_ACM_SetControlLineState (uint16_t state) {
// Add code for set control line state
(void)(state);
return true;
}
//! [code_USBD_User_CDC_ACM]

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2016 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_User_CustomClass_0.c
* Purpose: USB Device Custom Class User module
* Rev.: V6.7.3
*----------------------------------------------------------------------------*/
/*
* USBD_User_CustomClass_0.c is a code template for the Custom Class 0
* class request handling. It allows user to handle all Custom Class class
* requests.
*
* Uncomment "Example code" lines to see example that receives data on
* Endpoint 1 OUT and echoes it back on Endpoint 1 IN.
* To try the example you also have to enable Bulk Endpoint 1 IN/OUT in Custom
* Class configuration in USBD_Config_CustomClass_0.h file.
*/
/**
* \addtogroup usbd_custom_classFunctions
*
*/
//! [code_USBD_User_CustomClass]
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "cmsis_os2.h"
#define osObjectsExternal
#include "osObjects.h"
#include "rl_usb.h"
#include "Driver_USBD.h"
#include "DAP_config.h"
#include "DAP.h"
static volatile uint16_t USB_RequestIndexI; // Request Index In
static volatile uint16_t USB_RequestIndexO; // Request Index Out
static volatile uint16_t USB_RequestCountI; // Request Count In
static volatile uint16_t USB_RequestCountO; // Request Count Out
static volatile uint8_t USB_RequestIdle; // Request Idle Flag
static volatile uint16_t USB_ResponseIndexI; // Response Index In
static volatile uint16_t USB_ResponseIndexO; // Response Index Out
static volatile uint16_t USB_ResponseCountI; // Response Count In
static volatile uint16_t USB_ResponseCountO; // Response Count Out
static volatile uint8_t USB_ResponseIdle; // Response Idle Flag
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Request Buffer
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Response Buffer
static uint16_t USB_RespSize[DAP_PACKET_COUNT]; // Response Size
// \brief Callback function called during USBD_Initialize to initialize the USB Custom class instance
void USBD_CustomClass0_Initialize (void) {
// Handle Custom Class Initialization
// Initialize variables
USB_RequestIndexI = 0U;
USB_RequestIndexO = 0U;
USB_RequestCountI = 0U;
USB_RequestCountO = 0U;
USB_RequestIdle = 1U;
USB_ResponseIndexI = 0U;
USB_ResponseIndexO = 0U;
USB_ResponseCountI = 0U;
USB_ResponseCountO = 0U;
USB_ResponseIdle = 1U;
}
// \brief Callback function called during USBD_Uninitialize to de-initialize the USB Custom class instance
void USBD_CustomClass0_Uninitialize (void) {
// Handle Custom Class De-initialization
}
// \brief Callback function called upon USB Bus Reset signaling
void USBD_CustomClass0_Reset (void) {
// Handle USB Bus Reset Event
}
// \brief Callback function called when Endpoint Start was requested (by activating interface or configuration)
// \param[in] ep_addr endpoint address.
void USBD_CustomClass0_EndpointStart (uint8_t ep_addr) {
// Start communication on Endpoint
if (ep_addr == USB_ENDPOINT_OUT(1U)) {
USB_RequestIdle = 0U;
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[0], DAP_PACKET_SIZE);
}
}
// \brief Callback function called when Endpoint Stop was requested (by de-activating interface or activating configuration 0)
// \param[in] ep_addr endpoint address.
void USBD_CustomClass0_EndpointStop (uint8_t ep_addr) {
// Handle Endpoint communication stopped
(void)ep_addr;
}
// \brief Callback function called when Custom Class 0 received SETUP PACKET on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] setup_packet pointer to received setup packet.
// \param[out] buf pointer to data buffer used for data stage requested by setup packet.
// \param[out] len pointer to number of data bytes in data stage requested by setup packet.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet if no data stage)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
usbdRequestStatus USBD_CustomClass0_Endpoint0_SetupPacketReceived (const USB_SETUP_PACKET *setup_packet, uint8_t **buf, uint32_t *len) {
(void)setup_packet;
(void)buf;
(void)len;
switch (setup_packet->bmRequestType.Recipient) {
case USB_REQUEST_TO_DEVICE:
break;
case USB_REQUEST_TO_INTERFACE:
break;
case USB_REQUEST_TO_ENDPOINT:
break;
default:
break;
}
return usbdRequestNotProcessed;
}
// \brief Callback function called when SETUP PACKET was processed by USB library
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback nor by Custom Class callback)
// \param[in] setup_packet pointer to processed setup packet.
void USBD_CustomClass0_Endpoint0_SetupPacketProcessed (const USB_SETUP_PACKET *setup_packet) {
(void)setup_packet;
switch (setup_packet->bmRequestType.Recipient) {
case USB_REQUEST_TO_DEVICE:
break;
case USB_REQUEST_TO_INTERFACE:
break;
case USB_REQUEST_TO_ENDPOINT:
break;
default:
break;
}
}
// \brief Callback function called when Custom Class 0 received OUT DATA on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] len number of received data bytes.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
// \return usbdRequestNAK: request was processed but the device is busy (return NAK)
usbdRequestStatus USBD_CustomClass0_Endpoint0_OutDataReceived (uint32_t len) {
(void)len;
return usbdRequestNotProcessed;
}
// \brief Callback function called when Custom Class 0 sent IN DATA on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] len number of sent data bytes.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (return ACK)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
// \return usbdRequestNAK: request was processed but the device is busy (return NAK)
usbdRequestStatus USBD_CustomClass0_Endpoint0_InDataSent (uint32_t len) {
(void)len;
return usbdRequestNotProcessed;
}
// \brief Callback function called when DATA was sent or received on Endpoint n
// \param[in] event event on Endpoint:
// - ARM_USBD_EVENT_OUT = data OUT received
// - ARM_USBD_EVENT_IN = data IN sent
void USBD_CustomClass0_Endpoint1_Event (uint32_t event) {
// Handle Endpoint 1 events
uint32_t n;
if (event & ARM_USBD_EVENT_OUT) {
n = USBD_EndpointReadGetResult(0U, USB_ENDPOINT_OUT(1U));
if (n != 0U) {
if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) {
DAP_TransferAbort = 1U;
} else {
USB_RequestIndexI++;
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
USB_RequestIndexI = 0U;
}
USB_RequestCountI++;
osThreadFlagsSet(DAP_ThreadId, 0x01);
}
}
// Start reception of next request packet
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
} else {
USB_RequestIdle = 1U;
}
}
if (event & ARM_USBD_EVENT_IN) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]);
USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
} else {
USB_ResponseIdle = 1U;
}
}
}
void USBD_CustomClass0_Endpoint2_Event (uint32_t event) {
// Handle Endpoint 2 events
if (event & ARM_USBD_EVENT_IN) {
SWO_TransferComplete();
}
}
void USBD_CustomClass0_Endpoint3_Event (uint32_t event) {
// Handle Endpoint 3 events
(void)event;
}
void USBD_CustomClass0_Endpoint4_Event (uint32_t event) {
// Handle Endpoint 4 events
(void)event;
}
void USBD_CustomClass0_Endpoint5_Event (uint32_t event) {
// Handle Endpoint 5 events
(void)event;
}
void USBD_CustomClass0_Endpoint6_Event (uint32_t event) {
// Handle Endpoint 6 events
(void)event;
}
void USBD_CustomClass0_Endpoint7_Event (uint32_t event) {
// Handle Endpoint 7 events
(void)event;
}
void USBD_CustomClass0_Endpoint8_Event (uint32_t event) {
// Handle Endpoint 8 events
(void)event;
}
void USBD_CustomClass0_Endpoint9_Event (uint32_t event) {
// Handle Endpoint 9 events
(void)event;
}
void USBD_CustomClass0_Endpoint10_Event (uint32_t event) {
// Handle Endpoint 10 events
(void)event;
}
void USBD_CustomClass0_Endpoint11_Event (uint32_t event) {
// Handle Endpoint 11 events
(void)event;
}
void USBD_CustomClass0_Endpoint12_Event (uint32_t event) {
// Handle Endpoint 12 events
(void)event;
}
void USBD_CustomClass0_Endpoint13_Event (uint32_t event) {
// Handle Endpoint 13 events
(void)event;
}
void USBD_CustomClass0_Endpoint14_Event (uint32_t event) {
// Handle Endpoint 14 events
(void)event;
}
void USBD_CustomClass0_Endpoint15_Event (uint32_t event) {
// Handle Endpoint 15 events
(void)event;
}
// DAP Thread.
__NO_RETURN void DAP_Thread (void *argument) {
uint32_t flags;
uint32_t n;
(void) argument;
for (;;) {
osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
// Process pending requests
while (USB_RequestCountI != USB_RequestCountO) {
// Handle Queue Commands
n = USB_RequestIndexO;
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
USB_Request[n][0] = ID_DAP_ExecuteCommands;
n++;
if (n == DAP_PACKET_COUNT) {
n = 0U;
}
if (n == USB_RequestIndexI) {
flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
if (flags & 0x80U) {
break;
}
}
}
// Execute DAP Command (process request and prepare response)
USB_RespSize[USB_ResponseIndexI] =
(uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
// Update Request Index and Count
USB_RequestIndexO++;
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
USB_RequestIndexO = 0U;
}
USB_RequestCountO++;
if (USB_RequestIdle) {
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
USB_RequestIdle = 0U;
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
}
}
// Update Response Index and Count
USB_ResponseIndexI++;
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
USB_ResponseIndexI = 0U;
}
USB_ResponseCountI++;
if (USB_ResponseIdle) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
n = USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
USB_ResponseIdle = 0U;
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[n], USB_RespSize[n]);
}
}
}
}
}
// SWO Data Queue Transfer
// buf: pointer to buffer with data
// num: number of bytes to transfer
void SWO_QueueTransfer (uint8_t *buf, uint32_t num) {
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(2U), buf, num);
}
// SWO Data Abort Transfer
void SWO_AbortTransfer (void) {
USBD_EndpointAbort(0U, USB_ENDPOINT_IN(2U));
}
//! [code_USBD_User_CustomClass]

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/* -----------------------------------------------------------------------------
* Copyright (c) 2021 ARM Ltd.
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising from
* the use of this software. Permission is granted to anyone to use this
* software for any purpose, including commercial applications, and to alter
* it and redistribute it freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software in
* a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
*
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
*
* 3. This notice may not be removed or altered from any source distribution.
*
*
* $Date: 28. June 2021
* $Revision: V1.0
*
* Project: USB Driver Definitions for NXP LPC55xxx
* -------------------------------------------------------------------------- */
#ifndef __USB_LPC55XXX_H
#define __USB_LPC55XXX_H
#include <stdint.h>
// USB Device Endpoint Interrupt definitions
#define USB_INT_EP_MSK (0x0FFFU)
#define USB_INT_EP(ep_idx) ((1U << (ep_idx)) & USB_INT_EP_MSK)
// USB Driver State Flags
// Device State Flags
#define USBD_DRIVER_FLAG_INITIALIZED (1U )
#define USBD_DRIVER_FLAG_POWERED (1U << 1 )
// Transfer information structure
typedef struct {
uint32_t max_packet_sz;
uint32_t num;
uint32_t num_transferred_total;
uint32_t num_transferring;
uint8_t *buf;
} EP_TRANSFER;
// Endpoint command/status
typedef struct {
uint32_t buff_addr_offset : 11;
uint32_t NBytes : 15;
uint32_t ep_type_periodic : 1;
uint32_t toggle_value : 1;
uint32_t toggle_reset : 1;
uint32_t stall : 1;
uint32_t ep_disabled : 1;
uint32_t active : 1;
} EP_CMD;
// Endpoint structure
typedef struct __EP {
EP_CMD * const cmd;
uint8_t * const buf;
EP_TRANSFER * const transfer;
uint16_t buf_offset;
} EP;
#endif /* __USB_LPC55XXX_H */

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to set up clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v7.0
processor: LPC55S69
package_id: LPC55S69JBD64
mcu_data: ksdk2_0
processor_version: 9.0.3
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_power.h"
#include "fsl_clock.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: FXCOM0_clock.outFreq, value: 48 MHz}
- {id: FXCOM3_clock.outFreq, value: 48 MHz}
- {id: System_clock.outFreq, value: 150 MHz, locked: true, accuracy: '0.001'}
- {id: USB1_PHY_clock.outFreq, value: 16 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
- {id: ENABLE_CLKIN_ENA, value: Enabled}
- {id: ENABLE_PLL_USB_OUT, value: Enabled}
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.FROHFDIV}
- {id: SYSCON.FCCLKSEL3.sel, value: SYSCON.FROHFDIV}
- {id: SYSCON.FRGCTRL3_DIV.scale, value: '256', locked: true}
- {id: SYSCON.FROHFDIV.scale, value: '2', locked: true}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
- {id: SYSCON.PLL0_PDEC.scale, value: '2'}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
#ifndef SDK_SECONDARY_CORE
/*!< Set up the clock sources */
/*!< Configure FRO192M */
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
/*!< Configure XTAL32M */
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */
POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
/*!< Set up PLL */
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
const pll_setup_t pll0Setup = {
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
.pllndec = SYSCON_PLL0NDEC_NDIV(8U),
.pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
.pllRate = 150000000U,
.flags = PLL_SETUPFLAG_WAITLOCK
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
/*!< Set up dividers */
#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 0U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
#else
CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 256U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
#endif
#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 0U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
#else
CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 256U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
#endif
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivFrohfClk, 0U, true); /*!< Reset FROHFDIV divider counter and halt it */
CLOCK_SetClkDiv(kCLOCK_DivFrohfClk, 2U, false); /*!< Set FROHFDIV divider to value 2 */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to FRO_HF_DIV */
/*!< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
#endif
}

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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@ -0,0 +1,77 @@
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Peripherals v9.0
processor: LPC55S69
package_id: LPC55S69JBD64
mcu_data: ksdk2_0
processor_version: 9.0.3
functionalGroups:
- name: BOARD_InitPeripherals
UUID: 85f4cd0c-3b58-4e23-a413-239f6952f139
called_from_default_init: true
selectedCore: cm33_core0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
component:
- type: 'system'
- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
- global_system_definitions:
- user_definitions: ''
- user_includes: ''
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/***********************************************************************************************************************
* Included files
**********************************************************************************************************************/
#include "peripherals.h"
/***********************************************************************************************************************
* BOARD_InitPeripherals functional group
**********************************************************************************************************************/
/***********************************************************************************************************************
* NVIC initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'NVIC'
- type: 'nvic'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'NVIC'
- config_sets:
- nvic:
- interrupt_table: []
- interrupts: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* Empty initialization function (commented out)
static void NVIC_init(void) {
} */
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void)
{
/* Initialize components */
}
/***********************************************************************************************************************
* BOARD_InitBootPeripherals function
**********************************************************************************************************************/
void BOARD_InitBootPeripherals(void)
{
BOARD_InitPeripherals();
}

33
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@ -0,0 +1,33 @@
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PERIPHERALS_H_
#define _PERIPHERALS_H_
/***********************************************************************************************************************
* Included files
**********************************************************************************************************************/
#include "fsl_common.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void);
/***********************************************************************************************************************
* BOARD_InitBootPeripherals function
**********************************************************************************************************************/
void BOARD_InitBootPeripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* _PERIPHERALS_H_ */

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v9.0
processor: LPC55S69
package_id: LPC55S69JBD64
mcu_data: ksdk2_0
processor_version: 9.0.3
pin_labels:
- {pin_num: '36', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A, label: _DBGIF_TCK_SWCLK, identifier: DBGIF_TCK_SWCLK}
- {pin_num: '2', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: _DBGIF_TDI, identifier: DBGIF_TDI}
- {pin_num: '52', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, label: _DBGIF_TMS_SWDIO, identifier: DBGIF_TMS_SWDIO}
- {pin_num: '44', pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, label: _DBGIF_TMS_SWDIO_TXEN, identifier: DBGIF_TMS_SWDIO_TXEN}
- {pin_num: '58', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, label: _DBGIF_RESET, identifier: DBG_IF_RESET;DBGIF_RESET}
- {pin_num: '46', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13, label: _DBGIF_RESET_TXEN, identifier: DBG_IF_RESET_TXEN;DBGIF_RESET_TXEN}
- {pin_num: '53', pin_signal: PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3, label: _DBGIF_TDO_SWO, identifier: DBG_IF_TDO_SWO;DBGIF_TDO_SWO}
- {pin_num: '45', pin_signal: PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24, label: _FC0_TARGET_RXD, identifier: FC0_TARGET_RXD}
- {pin_num: '51', pin_signal: PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25, label: _FC0_TARGET_TXD, identifier: FC0_TARGET_TXD}
- {pin_num: '56', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, label: _LED1, identifier: LED1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
MCU_LINK_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
MCU_LINK_InitPins:
- options: {callFromInitBoot: 'true', prefix: '', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '36', peripheral: GPIO, signal: 'PIO0, 0', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A, direction: INPUT,
slew_rate: fast}
- {pin_num: '2', peripheral: GPIO, signal: 'PIO0, 1', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, direction: INPUT, slew_rate: fast}
- {pin_num: '52', peripheral: GPIO, signal: 'PIO0, 2', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, direction: INPUT, mode: inactive,
slew_rate: fast}
- {pin_num: '44', peripheral: GPIO, signal: 'PIO0, 28', pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, direction: OUTPUT,
gpio_init_state: 'false', slew_rate: fast}
- {pin_num: '58', peripheral: GPIO, signal: 'PIO0, 19', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19,
identifier: DBGIF_RESET, direction: INPUT, slew_rate: fast}
- {pin_num: '46', peripheral: GPIO, signal: 'PIO0, 13', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13,
identifier: DBGIF_RESET_TXEN, direction: OUTPUT, gpio_init_state: 'false'}
- {pin_num: '53', peripheral: FLEXCOMM3, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3, identifier: DBGIF_TDO_SWO,
slew_rate: fast}
- {pin_num: '45', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24, slew_rate: fast}
- {pin_num: '51', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25, slew_rate: fast}
- {pin_num: '23', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP}
- {pin_num: '24', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM}
- {pin_num: '25', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS}
- {pin_num: '22', peripheral: USBHSH, signal: USB_VSS, pin_signal: USB1_VSS22}
- {pin_num: '26', peripheral: USBHSH, signal: USB_VSS, pin_signal: USB1_VSS26}
- {pin_num: '41', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5}
- {pin_num: '56', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: OUTPUT,
gpio_init_state: 'true', mode: pullUp}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : MCU_LINK_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
/* Function assigned for the Cortex-M33 (Core #0) */
void MCU_LINK_InitPins(void)
{
/* Enables the clock for the I/O controller.: Enable Clock. */
CLOCK_EnableClock(kCLOCK_Iocon);
/* Enables the clock for the GPIO0 module */
CLOCK_EnableClock(kCLOCK_Gpio0);
gpio_pin_config_t DBGIF_TCK_SWCLK_config = {
.pinDirection = kGPIO_DigitalInput,
.outputLogic = 0U
};
/* Initialize GPIO functionality on pin PIO0_0 (pin 36) */
GPIO_PinInit(DBGIF_TCK_SWCLK_GPIO, DBGIF_TCK_SWCLK_PORT, DBGIF_TCK_SWCLK_PIN, &DBGIF_TCK_SWCLK_config);
gpio_pin_config_t DBGIF_TDI_config = {
.pinDirection = kGPIO_DigitalInput,
.outputLogic = 0U
};
/* Initialize GPIO functionality on pin PIO0_1 (pin 2) */
GPIO_PinInit(DBGIF_TDI_GPIO, DBGIF_TDI_PORT, DBGIF_TDI_PIN, &DBGIF_TDI_config);
gpio_pin_config_t DBGIF_TMS_SWDIO_config = {
.pinDirection = kGPIO_DigitalInput,
.outputLogic = 0U
};
/* Initialize GPIO functionality on pin PIO0_2 (pin 52) */
GPIO_PinInit(DBGIF_TMS_SWDIO_GPIO, DBGIF_TMS_SWDIO_PORT, DBGIF_TMS_SWDIO_PIN, &DBGIF_TMS_SWDIO_config);
gpio_pin_config_t LED1_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 1U
};
/* Initialize GPIO functionality on pin PIO0_5 (pin 56) */
GPIO_PinInit(LED1_GPIO, LED1_PORT, LED1_PIN, &LED1_config);
gpio_pin_config_t DBGIF_RESET_TXEN_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 0U
};
/* Initialize GPIO functionality on pin PIO0_13 (pin 46) */
GPIO_PinInit(DBGIF_RESET_TXEN_GPIO, DBGIF_RESET_TXEN_PORT, DBGIF_RESET_TXEN_PIN, &DBGIF_RESET_TXEN_config);
gpio_pin_config_t DBGIF_RESET_config = {
.pinDirection = kGPIO_DigitalInput,
.outputLogic = 0U
};
/* Initialize GPIO functionality on pin PIO0_19 (pin 58) */
GPIO_PinInit(DBGIF_RESET_GPIO, DBGIF_RESET_PORT, DBGIF_RESET_PIN, &DBGIF_RESET_config);
gpio_pin_config_t DBGIF_TMS_SWDIO_TXEN_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 0U
};
/* Initialize GPIO functionality on pin PIO0_28 (pin 44) */
GPIO_PinInit(DBGIF_TMS_SWDIO_TXEN_GPIO, DBGIF_TMS_SWDIO_TXEN_PORT, DBGIF_TMS_SWDIO_TXEN_PIN, &DBGIF_TMS_SWDIO_TXEN_config);
IOCON->PIO[0][0] = ((IOCON->PIO[0][0] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT00 (pin 36) is configured as PIO0_0. */
| IOCON_PIO_FUNC(PIO0_0_FUNC_ALT0)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_0_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_0_DIGIMODE_DIGITAL));
IOCON->PIO[0][1] = ((IOCON->PIO[0][1] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT01 (pin 2) is configured as PIO0_1. */
| IOCON_PIO_FUNC(PIO0_1_FUNC_ALT0)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_1_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_1_DIGIMODE_DIGITAL));
IOCON->PIO[0][13] = ((IOCON->PIO[0][13] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT013 (pin 46) is configured as PIO0_13. */
| IOCON_PIO_FUNC(PIO0_13_FUNC_ALT0)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_13_DIGIMODE_DIGITAL));
IOCON->PIO[0][19] = ((IOCON->PIO[0][19] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT019 (pin 58) is configured as PIO0_19. */
| IOCON_PIO_FUNC(PIO0_19_FUNC_ALT0)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_19_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_19_DIGIMODE_DIGITAL));
IOCON->PIO[0][2] = ((IOCON->PIO[0][2] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT02 (pin 52) is configured as PIO0_2. */
| IOCON_PIO_FUNC(PIO0_2_FUNC_ALT0)
/* Selects function mode (on-chip pull-up/pull-down resistor control).
* : Inactive.
* Inactive (no pull-down/pull-up resistor enabled). */
| IOCON_PIO_MODE(PIO0_2_MODE_INACTIVE)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_2_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_2_DIGIMODE_DIGITAL));
IOCON->PIO[0][24] = ((IOCON->PIO[0][24] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT024 (pin 45) is configured as FC0_RXD_SDA_MOSI_DATA. */
| IOCON_PIO_FUNC(PIO0_24_FUNC_ALT1)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_24_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_24_DIGIMODE_DIGITAL));
IOCON->PIO[0][25] = ((IOCON->PIO[0][25] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT025 (pin 51) is configured as FC0_TXD_SCL_MISO_WS. */
| IOCON_PIO_FUNC(PIO0_25_FUNC_ALT1)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_25_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_25_DIGIMODE_DIGITAL));
IOCON->PIO[0][28] = ((IOCON->PIO[0][28] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT028 (pin 44) is configured as PIO0_28. */
| IOCON_PIO_FUNC(PIO0_28_FUNC_ALT0)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_28_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL));
IOCON->PIO[0][3] = ((IOCON->PIO[0][3] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT03 (pin 53) is configured as FC3_RXD_SDA_MOSI_DATA. */
| IOCON_PIO_FUNC(PIO0_3_FUNC_ALT1)
/* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details. */
| IOCON_PIO_SLEW(PIO0_3_SLEW_FAST)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_3_DIGIMODE_DIGITAL));
IOCON->PIO[0][5] = ((IOCON->PIO[0][5] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT05 (pin 56) is configured as PIO0_5. */
| IOCON_PIO_FUNC(PIO0_5_FUNC_ALT0)
/* Selects function mode (on-chip pull-up/pull-down resistor control).
* : Pull-up.
* Pull-up resistor enabled. */
| IOCON_PIO_MODE(PIO0_5_MODE_PULL_UP)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO0_5_DIGIMODE_DIGITAL));
IOCON->PIO[1][2] = ((IOCON->PIO[1][2] &
/* Mask bits to zero which are setting */
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
/* Selects pin function.
* : PORT12 (pin 41) is configured as USB1_PORTPWRN. */
| IOCON_PIO_FUNC(PIO1_2_FUNC_ALT7)
/* Select Digital mode.
* : Enable Digital mode.
* Digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO1_2_DIGIMODE_DIGITAL));
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_0_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 0. */
#define PIO0_0_FUNC_ALT0 0x00u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_0_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_13_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 0. */
#define PIO0_13_FUNC_ALT0 0x00u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_19_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 0. */
#define PIO0_19_FUNC_ALT0 0x00u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_19_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_1_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 0. */
#define PIO0_1_FUNC_ALT0 0x00u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_1_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_24_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 1. */
#define PIO0_24_FUNC_ALT1 0x01u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_24_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_25_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 1. */
#define PIO0_25_FUNC_ALT1 0x01u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_25_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_28_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 0. */
#define PIO0_28_FUNC_ALT0 0x00u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_28_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_2_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 0. */
#define PIO0_2_FUNC_ALT0 0x00u
/*!
* @brief
* Selects function mode (on-chip pull-up/pull-down resistor control).
* : Inactive.
* Inactive (no pull-down/pull-up resistor enabled).
*/
#define PIO0_2_MODE_INACTIVE 0x00u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_2_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_3_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 1. */
#define PIO0_3_FUNC_ALT1 0x01u
/*!
* @brief
* Driver slew rate.
* : Fast-mode, output slew rate is faster.
* Refer to the appropriate specific device data sheet for details.
*/
#define PIO0_3_SLEW_FAST 0x01u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO0_5_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 0. */
#define PIO0_5_FUNC_ALT0 0x00u
/*!
* @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
#define PIO0_5_MODE_PULL_UP 0x02u
/*!
* @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
#define PIO1_2_DIGIMODE_DIGITAL 0x01u
/*!
* @brief Selects pin function.: Alternative connection 7. */
#define PIO1_2_FUNC_ALT7 0x07u
/*! @name PIO0_0 (number 36), _DBGIF_TCK_SWCLK
@{ */
/* Symbols to be used with GPIO driver */
#define DBGIF_TCK_SWCLK_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
#define DBGIF_TCK_SWCLK_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */
#define DBGIF_TCK_SWCLK_PORT 0U /*!<@brief PORT peripheral base pointer */
#define DBGIF_TCK_SWCLK_PIN 0U /*!<@brief PORT pin number */
#define DBGIF_TCK_SWCLK_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_1 (number 2), _DBGIF_TDI
@{ */
/* Symbols to be used with GPIO driver */
#define DBGIF_TDI_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
#define DBGIF_TDI_GPIO_PIN_MASK (1U << 1U) /*!<@brief GPIO pin mask */
#define DBGIF_TDI_PORT 0U /*!<@brief PORT peripheral base pointer */
#define DBGIF_TDI_PIN 1U /*!<@brief PORT pin number */
#define DBGIF_TDI_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_2 (number 52), _DBGIF_TMS_SWDIO
@{ */
/* Symbols to be used with GPIO driver */
#define DBGIF_TMS_SWDIO_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
#define DBGIF_TMS_SWDIO_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */
#define DBGIF_TMS_SWDIO_PORT 0U /*!<@brief PORT peripheral base pointer */
#define DBGIF_TMS_SWDIO_PIN 2U /*!<@brief PORT pin number */
#define DBGIF_TMS_SWDIO_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_28 (number 44), _DBGIF_TMS_SWDIO_TXEN
@{ */
/* Symbols to be used with GPIO driver */
#define DBGIF_TMS_SWDIO_TXEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
#define DBGIF_TMS_SWDIO_TXEN_GPIO_PIN_MASK (1U << 28U) /*!<@brief GPIO pin mask */
#define DBGIF_TMS_SWDIO_TXEN_PORT 0U /*!<@brief PORT peripheral base pointer */
#define DBGIF_TMS_SWDIO_TXEN_PIN 28U /*!<@brief PORT pin number */
#define DBGIF_TMS_SWDIO_TXEN_PIN_MASK (1U << 28U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_19 (number 58), _DBGIF_RESET
@{ */
/* Symbols to be used with GPIO driver */
#define DBGIF_RESET_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
#define DBGIF_RESET_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */
#define DBGIF_RESET_PORT 0U /*!<@brief PORT peripheral base pointer */
#define DBGIF_RESET_PIN 19U /*!<@brief PORT pin number */
#define DBGIF_RESET_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_13 (number 46), _DBGIF_RESET_TXEN
@{ */
/* Symbols to be used with GPIO driver */
#define DBGIF_RESET_TXEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
#define DBGIF_RESET_TXEN_GPIO_PIN_MASK (1U << 13U) /*!<@brief GPIO pin mask */
#define DBGIF_RESET_TXEN_PORT 0U /*!<@brief PORT peripheral base pointer */
#define DBGIF_RESET_TXEN_PIN 13U /*!<@brief PORT pin number */
#define DBGIF_RESET_TXEN_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_3 (number 53), _DBGIF_TDO_SWO
@{ */
#define DBGIF_TDO_SWO_PORT 0U /*!<@brief PORT peripheral base pointer */
#define DBGIF_TDO_SWO_PIN 3U /*!<@brief PORT pin number */
#define DBGIF_TDO_SWO_PIN_MASK (1U << 3U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_24 (number 45), _FC0_TARGET_RXD
@{ */
#define FC0_TARGET_RXD_PORT 0U /*!<@brief PORT peripheral base pointer */
#define FC0_TARGET_RXD_PIN 24U /*!<@brief PORT pin number */
#define FC0_TARGET_RXD_PIN_MASK (1U << 24U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_25 (number 51), _FC0_TARGET_TXD
@{ */
#define FC0_TARGET_TXD_PORT 0U /*!<@brief PORT peripheral base pointer */
#define FC0_TARGET_TXD_PIN 25U /*!<@brief PORT pin number */
#define FC0_TARGET_TXD_PIN_MASK (1U << 25U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PIO0_5 (number 56), _LED1
@{ */
/* Symbols to be used with GPIO driver */
#define LED1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
#define LED1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */
#define LED1_PORT 0U /*!<@brief PORT peripheral base pointer */
#define LED1_PIN 5U /*!<@brief PORT pin number */
#define LED1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void MCU_LINK_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/*
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. September 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Examples MCU-LINK
* Title: main.c CMSIS-DAP Main module for MCU-LINK
*
*---------------------------------------------------------------------------*/
#include "cmsis_os2.h"
#include "osObjects.h"
#include "rl_usb.h"
#include "DAP_config.h"
#include "DAP.h"
#include "clock_config.h"
#include "pin_mux.h"
#include "fsl_dma.h"
// Callbacks for USART0 Driver
uint32_t USART0_GetFreq (void) { return CLOCK_GetFlexCommClkFreq(0); }
void USART0_InitPins (void) { /* Done in BOARD_InitBootPins function */ }
void USART0_DeinitPins (void) { /* Not implemented */ }
// Callbacks for USART3 Driver
uint32_t USART3_GetFreq (void) { return CLOCK_GetFlexCommClkFreq(3); }
void USART3_InitPins (void) { /* Done in BOARD_InitBootPins function */ }
void USART3_DeinitPins (void) { /* Not implemented */ }
// Application Main program
__NO_RETURN void app_main (void *argument) {
(void)argument;
BOARD_InitBootPins();
BOARD_InitBootClocks();
DMA_Init(DMA0);
DAP_Setup(); // DAP Setup
USBD_Initialize(0U); // USB Device Initialization
char *ser_num;
ser_num = GetSerialNum();
if (ser_num != NULL) {
USBD_SetSerialNumber(0U, ser_num); // Update Serial Number
}
USBD_Connect(0U); // USB Device Connect
while (!USBD_Configured(0U)); // Wait for USB Device to configure
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
LED_RUNNING_OUT(1U); // Turn on Target Running LED
Delayms(500U); // Wait for 500ms
LED_RUNNING_OUT(0U); // Turn off Target Running LED
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
// Create DAP Thread
DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr);
// Create SWO Thread
SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr);
osDelay(osWaitForever);
for (;;) {}
}
int main (void) {
SystemCoreClockUpdate();
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
if (osKernelGetState() == osKernelReady) {
osKernelStart(); // Start thread execution
}
for (;;) {}
}

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. September 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Examples MCU-LINK
* Title: osObjects.h CMSIS-DAP RTOS2 Objects for MCU-LINK
*
*---------------------------------------------------------------------------*/
#ifndef __osObjects_h__
#define __osObjects_h__
#include "cmsis_os2.h"
#ifdef osObjectsExternal
extern osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
#else
static const osThreadAttr_t DAP_ThreadAttr = {
.priority = osPriorityNormal
};
static const osThreadAttr_t SWO_ThreadAttr = {
.priority = osPriorityAboveNormal
};
extern osThreadId_t DAP_ThreadId;
osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
osThreadId_t SWO_ThreadId;
#endif
extern void DAP_Thread (void *argument);
extern void SWO_Thread (void *argument);
extern void app_main (void *argument);
#endif /* __osObjects_h__ */

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/*
* Copyright (c) 2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. September 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples MCU-LINK
* Title: ser_num.c CMSIS-DAP Serial Number module for MCU-LINK
*
*---------------------------------------------------------------------------*/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "ser_num.h"
#include "fsl_iap_ffr.h"
// Serial Number
#define SER_NUM_PREFIX "00A1"
static char SerialNum[32];
/**
\brief Calculate 32-bit CRC (polynom: 0x04C11DB7, init value: 0xFFFFFFFF)
\param[in] data pointer to data
\param[in] len data length (in bytes)
\return CRC32 value
*/
static uint32_t crc32 (const uint8_t *data, uint32_t len) {
uint32_t crc32;
uint32_t n;
crc32 = 0xFFFFFFFFU;
while (len != 0U) {
crc32 ^= ((uint32_t)*data++) << 24U;
for (n = 8U; n; n--) {
if (crc32 & 0x80000000U) {
crc32 <<= 1U;
crc32 ^= 0x04C11DB7U;
} else {
crc32 <<= 1U;
}
}
len--;
}
return (crc32);
}
/**
\brief Get serial number string. First characters are fixed. Last eight
characters are Unique (calculated from devices's unique ID)
\return Serial number string or NULL (callculation of unique ID failed)
*/
char *GetSerialNum (void) {
flash_config_t flash_config;
uint8_t uuid_buf[16];
uint32_t uid;
char *str;
str = NULL;
if (FFR_Init(&flash_config) == kStatus_Success) {
if (FFR_GetUUID(&flash_config, uuid_buf) == kStatus_Success) {
uid = crc32(uuid_buf, 16U);
snprintf(SerialNum, sizeof(SerialNum), "%s%08X", SER_NUM_PREFIX, uid);
str = SerialNum;
}
}
return (str);
}

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/*
* Copyright (c) 2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. September 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples MCU-LINK
* Title: ser_num.h CMSIS-DAP Serial Number module for MCU-LINK
*
*---------------------------------------------------------------------------*/
#ifndef __SER_NUM_H__
#define __SER_NUM_H__
char *GetSerialNum (void);
#endif /* __SER_NUM_H__ */

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/*
* Copyright (c) 2013-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 5. December 2022
* $Revision: V2.1.2
*
* Project: CMSIS-DAP Include
* Title: DAP.h Definitions
*
*---------------------------------------------------------------------------*/
#ifndef __DAP_H__
#define __DAP_H__
// DAP Firmware Version
#ifdef DAP_FW_V1
#define DAP_FW_VER "1.3.0"
#else
#define DAP_FW_VER "2.1.2"
#endif
// DAP Command IDs
#define ID_DAP_Info 0x00U
#define ID_DAP_HostStatus 0x01U
#define ID_DAP_Connect 0x02U
#define ID_DAP_Disconnect 0x03U
#define ID_DAP_TransferConfigure 0x04U
#define ID_DAP_Transfer 0x05U
#define ID_DAP_TransferBlock 0x06U
#define ID_DAP_TransferAbort 0x07U
#define ID_DAP_WriteABORT 0x08U
#define ID_DAP_Delay 0x09U
#define ID_DAP_ResetTarget 0x0AU
#define ID_DAP_SWJ_Pins 0x10U
#define ID_DAP_SWJ_Clock 0x11U
#define ID_DAP_SWJ_Sequence 0x12U
#define ID_DAP_SWD_Configure 0x13U
#define ID_DAP_SWD_Sequence 0x1DU
#define ID_DAP_JTAG_Sequence 0x14U
#define ID_DAP_JTAG_Configure 0x15U
#define ID_DAP_JTAG_IDCODE 0x16U
#define ID_DAP_SWO_Transport 0x17U
#define ID_DAP_SWO_Mode 0x18U
#define ID_DAP_SWO_Baudrate 0x19U
#define ID_DAP_SWO_Control 0x1AU
#define ID_DAP_SWO_Status 0x1BU
#define ID_DAP_SWO_ExtendedStatus 0x1EU
#define ID_DAP_SWO_Data 0x1CU
#define ID_DAP_UART_Transport 0x1FU
#define ID_DAP_UART_Configure 0x20U
#define ID_DAP_UART_Control 0x22U
#define ID_DAP_UART_Status 0x23U
#define ID_DAP_UART_Transfer 0x21U
#define ID_DAP_QueueCommands 0x7EU
#define ID_DAP_ExecuteCommands 0x7FU
// DAP Vendor Command IDs
#define ID_DAP_Vendor0 0x80U
#define ID_DAP_Vendor1 0x81U
#define ID_DAP_Vendor2 0x82U
#define ID_DAP_Vendor3 0x83U
#define ID_DAP_Vendor4 0x84U
#define ID_DAP_Vendor5 0x85U
#define ID_DAP_Vendor6 0x86U
#define ID_DAP_Vendor7 0x87U
#define ID_DAP_Vendor8 0x88U
#define ID_DAP_Vendor9 0x89U
#define ID_DAP_Vendor10 0x8AU
#define ID_DAP_Vendor11 0x8BU
#define ID_DAP_Vendor12 0x8CU
#define ID_DAP_Vendor13 0x8DU
#define ID_DAP_Vendor14 0x8EU
#define ID_DAP_Vendor15 0x8FU
#define ID_DAP_Vendor16 0x90U
#define ID_DAP_Vendor17 0x91U
#define ID_DAP_Vendor18 0x92U
#define ID_DAP_Vendor19 0x93U
#define ID_DAP_Vendor20 0x94U
#define ID_DAP_Vendor21 0x95U
#define ID_DAP_Vendor22 0x96U
#define ID_DAP_Vendor23 0x97U
#define ID_DAP_Vendor24 0x98U
#define ID_DAP_Vendor25 0x99U
#define ID_DAP_Vendor26 0x9AU
#define ID_DAP_Vendor27 0x9BU
#define ID_DAP_Vendor28 0x9CU
#define ID_DAP_Vendor29 0x9DU
#define ID_DAP_Vendor30 0x9EU
#define ID_DAP_Vendor31 0x9FU
#define ID_DAP_Invalid 0xFFU
// DAP Status Code
#define DAP_OK 0U
#define DAP_ERROR 0xFFU
// DAP ID
#define DAP_ID_VENDOR 1U
#define DAP_ID_PRODUCT 2U
#define DAP_ID_SER_NUM 3U
#define DAP_ID_DAP_FW_VER 4U
#define DAP_ID_DEVICE_VENDOR 5U
#define DAP_ID_DEVICE_NAME 6U
#define DAP_ID_BOARD_VENDOR 7U
#define DAP_ID_BOARD_NAME 8U
#define DAP_ID_PRODUCT_FW_VER 9U
#define DAP_ID_CAPABILITIES 0xF0U
#define DAP_ID_TIMESTAMP_CLOCK 0xF1U
#define DAP_ID_UART_RX_BUFFER_SIZE 0xFBU
#define DAP_ID_UART_TX_BUFFER_SIZE 0xFCU
#define DAP_ID_SWO_BUFFER_SIZE 0xFDU
#define DAP_ID_PACKET_COUNT 0xFEU
#define DAP_ID_PACKET_SIZE 0xFFU
// DAP Host Status
#define DAP_DEBUGGER_CONNECTED 0U
#define DAP_TARGET_RUNNING 1U
// DAP Port
#define DAP_PORT_AUTODETECT 0U // Autodetect Port
#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z)
#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET
#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET
// DAP SWJ Pins
#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK
#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS
#define DAP_SWJ_TDI 2 // TDI
#define DAP_SWJ_TDO 3 // TDO
#define DAP_SWJ_nTRST 5 // nTRST
#define DAP_SWJ_nRESET 7 // nRESET
// DAP Transfer Request
#define DAP_TRANSFER_APnDP (1U<<0)
#define DAP_TRANSFER_RnW (1U<<1)
#define DAP_TRANSFER_A2 (1U<<2)
#define DAP_TRANSFER_A3 (1U<<3)
#define DAP_TRANSFER_MATCH_VALUE (1U<<4)
#define DAP_TRANSFER_MATCH_MASK (1U<<5)
#define DAP_TRANSFER_TIMESTAMP (1U<<7)
// DAP Transfer Response
#define DAP_TRANSFER_OK (1U<<0)
#define DAP_TRANSFER_WAIT (1U<<1)
#define DAP_TRANSFER_FAULT (1U<<2)
#define DAP_TRANSFER_ERROR (1U<<3)
#define DAP_TRANSFER_MISMATCH (1U<<4)
// DAP SWO Trace Mode
#define DAP_SWO_OFF 0U
#define DAP_SWO_UART 1U
#define DAP_SWO_MANCHESTER 2U
// DAP SWO Trace Status
#define DAP_SWO_CAPTURE_ACTIVE (1U<<0)
#define DAP_SWO_CAPTURE_PAUSED (1U<<1)
#define DAP_SWO_STREAM_ERROR (1U<<6)
#define DAP_SWO_BUFFER_OVERRUN (1U<<7)
// DAP UART Transport
#define DAP_UART_TRANSPORT_NONE 0U
#define DAP_UART_TRANSPORT_USB_COM_PORT 1U
#define DAP_UART_TRANSPORT_DAP_COMMAND 2U
// DAP UART Control
#define DAP_UART_CONTROL_RX_ENABLE (1U<<0)
#define DAP_UART_CONTROL_RX_DISABLE (1U<<1)
#define DAP_UART_CONTROL_RX_BUF_FLUSH (1U<<2)
#define DAP_UART_CONTROL_TX_ENABLE (1U<<4)
#define DAP_UART_CONTROL_TX_DISABLE (1U<<5)
#define DAP_UART_CONTROL_TX_BUF_FLUSH (1U<<6)
// DAP UART Status
#define DAP_UART_STATUS_RX_ENABLED (1U<<0)
#define DAP_UART_STATUS_RX_DATA_LOST (1U<<1)
#define DAP_UART_STATUS_FRAMING_ERROR (1U<<2)
#define DAP_UART_STATUS_PARITY_ERROR (1U<<3)
#define DAP_UART_STATUS_TX_ENABLED (1U<<4)
// DAP UART Configure Error
#define DAP_UART_CFG_ERROR_DATA_BITS (1U<<0)
#define DAP_UART_CFG_ERROR_PARITY (1U<<1)
#define DAP_UART_CFG_ERROR_STOP_BITS (1U<<2)
// Debug Port Register Addresses
#define DP_IDCODE 0x00U // IDCODE Register (SW Read only)
#define DP_ABORT 0x00U // Abort Register (SW Write only)
#define DP_CTRL_STAT 0x04U // Control & Status
#define DP_WCR 0x04U // Wire Control Register (SW Only)
#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W)
#define DP_RESEND 0x08U // Resend (SW Read Only)
#define DP_RDBUFF 0x0CU // Read Buffer (Read Only)
// JTAG IR Codes
#define JTAG_ABORT 0x08U
#define JTAG_DPACC 0x0AU
#define JTAG_APACC 0x0BU
#define JTAG_IDCODE 0x0EU
#define JTAG_BYPASS 0x0FU
// JTAG Sequence Info
#define JTAG_SEQUENCE_TCK 0x3FU // TCK count
#define JTAG_SEQUENCE_TMS 0x40U // TMS value
#define JTAG_SEQUENCE_TDO 0x80U // TDO capture
// SWD Sequence Info
#define SWD_SEQUENCE_CLK 0x3FU // SWCLK count
#define SWD_SEQUENCE_DIN 0x80U // SWDIO capture
#include <stddef.h>
#include <stdint.h>
#include "cmsis_compiler.h"
// DAP Data structure
typedef struct {
uint8_t debug_port; // Debug Port
uint8_t fast_clock; // Fast Clock Flag
uint8_t padding[2];
uint32_t clock_delay; // Clock Delay
uint32_t timestamp; // Last captured Timestamp
struct { // Transfer Configuration
uint8_t idle_cycles; // Idle cycles after transfer
uint8_t padding[3];
uint16_t retry_count; // Number of retries after WAIT response
uint16_t match_retry; // Number of retries if read value does not match
uint32_t match_mask; // Match Mask
} transfer;
#if (DAP_SWD != 0)
struct { // SWD Configuration
uint8_t turnaround; // Turnaround period
uint8_t data_phase; // Always generate Data Phase
} swd_conf;
#endif
#if (DAP_JTAG != 0)
struct { // JTAG Device Chain
uint8_t count; // Number of devices
uint8_t index; // Device index (device at TDO has index 0)
#if (DAP_JTAG_DEV_CNT != 0)
uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits
uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR
uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR
#endif
} jtag_dev;
#endif
} DAP_Data_t;
extern DAP_Data_t DAP_Data; // DAP Data
extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag
#ifdef __cplusplus
extern "C"
{
#endif
// Functions
extern void SWJ_Sequence (uint32_t count, const uint8_t *data);
extern void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi);
extern void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo);
extern void JTAG_IR (uint32_t ir);
extern uint32_t JTAG_ReadIDCode (void);
extern void JTAG_WriteAbort (uint32_t data);
extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data);
extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data);
extern void Delayms (uint32_t delay);
extern uint32_t SWO_Transport (const uint8_t *request, uint8_t *response);
extern uint32_t SWO_Mode (const uint8_t *request, uint8_t *response);
extern uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response);
extern uint32_t SWO_Control (const uint8_t *request, uint8_t *response);
extern uint32_t SWO_Status (uint8_t *response);
extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response);
extern uint32_t SWO_Data (const uint8_t *request, uint8_t *response);
extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num);
extern void SWO_AbortTransfer (void);
extern void SWO_TransferComplete (void);
extern uint32_t SWO_Mode_UART (uint32_t enable);
extern uint32_t SWO_Baudrate_UART (uint32_t baudrate);
extern uint32_t SWO_Control_UART (uint32_t active);
extern void SWO_Capture_UART (uint8_t *buf, uint32_t num);
extern uint32_t SWO_GetCount_UART (void);
extern uint32_t SWO_Mode_Manchester (uint32_t enable);
extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate);
extern uint32_t SWO_Control_Manchester (uint32_t active);
extern void SWO_Capture_Manchester (uint8_t *buf, uint32_t num);
extern uint32_t SWO_GetCount_Manchester (void);
extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response);
extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response);
extern uint32_t UART_Control (const uint8_t *request, uint8_t *response);
extern uint32_t UART_Status (uint8_t *response);
extern uint32_t UART_Transfer (const uint8_t *request, uint8_t *response);
extern uint8_t USB_COM_PORT_Activate (uint32_t cmd);
extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response);
extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response);
extern uint32_t DAP_ExecuteCommand (const uint8_t *request, uint8_t *response);
extern void DAP_Setup (void);
// Configurable delay for clock generation
#ifndef DELAY_SLOW_CYCLES
#define DELAY_SLOW_CYCLES 3U // Number of cycles for one iteration
#endif
#if defined(__CC_ARM)
__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
uint32_t count = delay;
while (--count);
}
#else
__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
__ASM volatile (
".syntax unified\n"
"0:\n\t"
"subs %0,%0,#1\n\t"
"bne 0b\n"
: "+l" (delay) : : "cc"
);
}
#endif
// Fixed delay for fast clock generation
#ifndef DELAY_FAST_CYCLES
#define DELAY_FAST_CYCLES 0U // Number of cycles: 0..3
#endif
__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) {
#if (DELAY_FAST_CYCLES >= 1U)
__NOP();
#endif
#if (DELAY_FAST_CYCLES >= 2U)
__NOP();
#endif
#if (DELAY_FAST_CYCLES >= 3U)
__NOP();
#endif
}
#ifdef __cplusplus
}
#endif
#endif /* __DAP_H__ */

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 1. December 2017
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Source
* Title: DAP_vendor.c CMSIS-DAP Vendor Commands
*
*---------------------------------------------------------------------------*/
#include "DAP_config.h"
#include "DAP.h"
//**************************************************************************************************
/**
\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands
\ingroup DAP_Vendor_gr
@{
The file DAP_vendor.c provides template source code for extension of a Debug Unit with
Vendor Commands. Copy this file to the project folder of the Debug Unit and add the
file to the MDK-ARM project under the file group Configuration.
*/
/** Process DAP Vendor Command and prepare Response Data
\param request pointer to request data
\param response pointer to response data
\return number of bytes in response (lower 16 bits)
number of bytes in request (upper 16 bits)
*/
uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
uint32_t num = (1U << 16) | 1U;
*response++ = *request; // copy Command ID
switch (*request++) { // first byte in request is Command ID
case ID_DAP_Vendor0:
#if 0 // example user command
num += 1U << 16; // increment request count
if (*request == 1U) { // when first command data byte is 1
*response++ = 'X'; // send 'X' as response
num++; // increment response count
}
#endif
break;
case ID_DAP_Vendor1: break;
case ID_DAP_Vendor2: break;
case ID_DAP_Vendor3: break;
case ID_DAP_Vendor4: break;
case ID_DAP_Vendor5: break;
case ID_DAP_Vendor6: break;
case ID_DAP_Vendor7: break;
case ID_DAP_Vendor8: break;
case ID_DAP_Vendor9: break;
case ID_DAP_Vendor10: break;
case ID_DAP_Vendor11: break;
case ID_DAP_Vendor12: break;
case ID_DAP_Vendor13: break;
case ID_DAP_Vendor14: break;
case ID_DAP_Vendor15: break;
case ID_DAP_Vendor16: break;
case ID_DAP_Vendor17: break;
case ID_DAP_Vendor18: break;
case ID_DAP_Vendor19: break;
case ID_DAP_Vendor20: break;
case ID_DAP_Vendor21: break;
case ID_DAP_Vendor22: break;
case ID_DAP_Vendor23: break;
case ID_DAP_Vendor24: break;
case ID_DAP_Vendor25: break;
case ID_DAP_Vendor26: break;
case ID_DAP_Vendor27: break;
case ID_DAP_Vendor28: break;
case ID_DAP_Vendor29: break;
case ID_DAP_Vendor30: break;
case ID_DAP_Vendor31: break;
}
return (num);
}
///@}

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 1. December 2017
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Source
* Title: JTAG_DP.c CMSIS-DAP JTAG DP I/O
*
*---------------------------------------------------------------------------*/
#include "DAP_config.h"
#include "DAP.h"
// JTAG Macros
#define PIN_TCK_SET PIN_SWCLK_TCK_SET
#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR
#define PIN_TMS_SET PIN_SWDIO_TMS_SET
#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR
#define JTAG_CYCLE_TCK() \
PIN_TCK_CLR(); \
PIN_DELAY(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define JTAG_CYCLE_TDI(tdi) \
PIN_TDI_OUT(tdi); \
PIN_TCK_CLR(); \
PIN_DELAY(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define JTAG_CYCLE_TDO(tdo) \
PIN_TCK_CLR(); \
PIN_DELAY(); \
tdo = PIN_TDO_IN(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define JTAG_CYCLE_TDIO(tdi,tdo) \
PIN_TDI_OUT(tdi); \
PIN_TCK_CLR(); \
PIN_DELAY(); \
tdo = PIN_TDO_IN(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
#if (DAP_JTAG != 0)
// Generate JTAG Sequence
// info: sequence information
// tdi: pointer to TDI generated data
// tdo: pointer to TDO captured data
// return: none
void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) {
uint32_t i_val;
uint32_t o_val;
uint32_t bit;
uint32_t n, k;
n = info & JTAG_SEQUENCE_TCK;
if (n == 0U) {
n = 64U;
}
if (info & JTAG_SEQUENCE_TMS) {
PIN_TMS_SET();
} else {
PIN_TMS_CLR();
}
while (n) {
i_val = *tdi++;
o_val = 0U;
for (k = 8U; k && n; k--, n--) {
JTAG_CYCLE_TDIO(i_val, bit);
i_val >>= 1;
o_val >>= 1;
o_val |= bit << 7;
}
o_val >>= k;
if (info & JTAG_SEQUENCE_TDO) {
*tdo++ = (uint8_t)o_val;
}
}
}
// JTAG Set IR
// ir: IR value
// return: none
#define JTAG_IR_Function(speed) /**/ \
static void JTAG_IR_##speed (uint32_t ir) { \
uint32_t n; \
\
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Capture-IR */ \
JTAG_CYCLE_TCK(); /* Shift-IR */ \
\
PIN_TDI_OUT(1U); \
for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass before data */ \
} \
for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \
JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \
ir >>= 1; \
} \
n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \
if (n) { \
JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \
PIN_TDI_OUT(1U); \
for (--n; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass after data */ \
} \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \
} else { \
PIN_TMS_SET(); \
JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \
} \
\
JTAG_CYCLE_TCK(); /* Update-IR */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Idle */ \
PIN_TDI_OUT(1U); \
}
// JTAG Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
#define JTAG_TransferFunction(speed) /**/ \
static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \
uint32_t ack; \
uint32_t bit; \
uint32_t val; \
uint32_t n; \
\
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Capture-DR */ \
JTAG_CYCLE_TCK(); /* Shift-DR */ \
\
for (n = DAP_Data.jtag_dev.index; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass before data */ \
} \
\
JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \
ack = bit << 1; \
JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \
ack |= bit << 0; \
JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \
ack |= bit << 2; \
\
if (ack != DAP_TRANSFER_OK) { \
/* Exit on error */ \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Exit1-DR */ \
goto exit; \
} \
\
if (request & DAP_TRANSFER_RnW) { \
/* Read Transfer */ \
val = 0U; \
for (n = 31U; n; n--) { \
JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \
val |= bit << 31; \
val >>= 1; \
} \
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \
if (n) { \
JTAG_CYCLE_TDO(bit); /* Get D31 */ \
for (--n; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass after data */ \
} \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
} else { \
PIN_TMS_SET(); \
JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \
} \
val |= bit << 31; \
if (data) { *data = val; } \
} else { \
/* Write Transfer */ \
val = *data; \
for (n = 31U; n; n--) { \
JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \
val >>= 1; \
} \
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \
if (n) { \
JTAG_CYCLE_TDI(val); /* Set D31 */ \
for (--n; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass after data */ \
} \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
} else { \
PIN_TMS_SET(); \
JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \
} \
} \
\
exit: \
JTAG_CYCLE_TCK(); /* Update-DR */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Idle */ \
PIN_TDI_OUT(1U); \
\
/* Capture Timestamp */ \
if (request & DAP_TRANSFER_TIMESTAMP) { \
DAP_Data.timestamp = TIMESTAMP_GET(); \
} \
\
/* Idle cycles */ \
n = DAP_Data.transfer.idle_cycles; \
while (n--) { \
JTAG_CYCLE_TCK(); /* Idle */ \
} \
\
return ((uint8_t)ack); \
}
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_FAST()
JTAG_IR_Function(Fast)
JTAG_TransferFunction(Fast)
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
JTAG_IR_Function(Slow)
JTAG_TransferFunction(Slow)
// JTAG Read IDCODE register
// return: value read
uint32_t JTAG_ReadIDCode (void) {
uint32_t bit;
uint32_t val;
uint32_t n;
PIN_TMS_SET();
JTAG_CYCLE_TCK(); /* Select-DR-Scan */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Capture-DR */
JTAG_CYCLE_TCK(); /* Shift-DR */
for (n = DAP_Data.jtag_dev.index; n; n--) {
JTAG_CYCLE_TCK(); /* Bypass before data */
}
val = 0U;
for (n = 31U; n; n--) {
JTAG_CYCLE_TDO(bit); /* Get D0..D30 */
val |= bit << 31;
val >>= 1;
}
PIN_TMS_SET();
JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */
val |= bit << 31;
JTAG_CYCLE_TCK(); /* Update-DR */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Idle */
return (val);
}
// JTAG Write ABORT register
// data: value to write
// return: none
void JTAG_WriteAbort (uint32_t data) {
uint32_t n;
PIN_TMS_SET();
JTAG_CYCLE_TCK(); /* Select-DR-Scan */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Capture-DR */
JTAG_CYCLE_TCK(); /* Shift-DR */
for (n = DAP_Data.jtag_dev.index; n; n--) {
JTAG_CYCLE_TCK(); /* Bypass before data */
}
PIN_TDI_OUT(0U);
JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */
JTAG_CYCLE_TCK(); /* Set A2=0 */
JTAG_CYCLE_TCK(); /* Set A3=0 */
for (n = 31U; n; n--) {
JTAG_CYCLE_TDI(data); /* Set D0..D30 */
data >>= 1;
}
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;
if (n) {
JTAG_CYCLE_TDI(data); /* Set D31 */
for (--n; n; n--) {
JTAG_CYCLE_TCK(); /* Bypass after data */
}
PIN_TMS_SET();
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */
} else {
PIN_TMS_SET();
JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */
}
JTAG_CYCLE_TCK(); /* Update-DR */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Idle */
PIN_TDI_OUT(1U);
}
// JTAG Set IR
// ir: IR value
// return: none
void JTAG_IR (uint32_t ir) {
if (DAP_Data.fast_clock) {
JTAG_IR_Fast(ir);
} else {
JTAG_IR_Slow(ir);
}
}
// JTAG Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) {
if (DAP_Data.fast_clock) {
return JTAG_TransferFast(request, data);
} else {
return JTAG_TransferSlow(request, data);
}
}
#endif /* (DAP_JTAG != 0) */

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@ -0,0 +1,798 @@
/*
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 29. March 2021
* $Revision: V2.0.1
*
* Project: CMSIS-DAP Source
* Title: SWO.c CMSIS-DAP SWO I/O
*
*---------------------------------------------------------------------------*/
#include "DAP_config.h"
#include "DAP.h"
#if (SWO_UART != 0)
#include "Driver_USART.h"
#endif
#if (SWO_STREAM != 0)
#include "cmsis_os2.h"
#define osObjectsExternal
#include "osObjects.h"
#endif
#if (SWO_STREAM != 0)
#ifdef DAP_FW_V1
#error "SWO Streaming Trace not supported in DAP V1!"
#endif
#endif
#if (SWO_UART != 0)
// USART Driver
#define _USART_Driver_(n) Driver_USART##n
#define USART_Driver_(n) _USART_Driver_(n)
extern ARM_DRIVER_USART USART_Driver_(SWO_UART_DRIVER);
#define pUSART (&USART_Driver_(SWO_UART_DRIVER))
static uint8_t USART_Ready = 0U;
#endif /* (SWO_UART != 0) */
#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
#define SWO_STREAM_TIMEOUT 50U /* Stream timeout in ms */
#define USB_BLOCK_SIZE 512U /* USB Block Size */
#define TRACE_BLOCK_SIZE 64U /* Trace Block Size (2^n: 32...512) */
// Trace State
static uint8_t TraceTransport = 0U; /* Trace Transport */
static uint8_t TraceMode = 0U; /* Trace Mode */
static uint8_t TraceStatus = 0U; /* Trace Status without Errors */
static uint8_t TraceError[2] = {0U, 0U}; /* Trace Error flags (banked) */
static uint8_t TraceError_n = 0U; /* Active Trace Error bank */
// Trace Buffer
static uint8_t TraceBuf[SWO_BUFFER_SIZE]; /* Trace Buffer (must be 2^n) */
static volatile uint32_t TraceIndexI = 0U; /* Incoming Trace Index */
static volatile uint32_t TraceIndexO = 0U; /* Outgoing Trace Index */
static volatile uint8_t TraceUpdate; /* Trace Update Flag */
static uint32_t TraceBlockSize; /* Current Trace Block Size */
#if (TIMESTAMP_CLOCK != 0U)
// Trace Timestamp
static volatile struct {
uint32_t index;
uint32_t tick;
} TraceTimestamp;
#endif
// Trace Helper functions
static void ClearTrace (void);
static void ResumeTrace (void);
static uint32_t GetTraceCount (void);
static uint8_t GetTraceStatus (void);
static void SetTraceError (uint8_t flag);
#if (SWO_STREAM != 0)
extern osThreadId_t SWO_ThreadId;
static volatile uint8_t TransferBusy = 0U; /* Transfer Busy Flag */
static uint32_t TransferSize; /* Current Transfer Size */
#endif
#if (SWO_UART != 0)
// USART Driver Callback function
// event: event mask
static void USART_Callback (uint32_t event) {
uint32_t index_i;
uint32_t index_o;
uint32_t count;
uint32_t num;
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
#if (TIMESTAMP_CLOCK != 0U)
TraceTimestamp.tick = TIMESTAMP_GET();
#endif
index_o = TraceIndexO;
index_i = TraceIndexI;
index_i += TraceBlockSize;
TraceIndexI = index_i;
#if (TIMESTAMP_CLOCK != 0U)
TraceTimestamp.index = index_i;
#endif
num = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U));
count = index_i - index_o;
if (count <= (SWO_BUFFER_SIZE - num)) {
index_i &= SWO_BUFFER_SIZE - 1U;
TraceBlockSize = num;
pUSART->Receive(&TraceBuf[index_i], num);
} else {
TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
}
TraceUpdate = 1U;
#if (SWO_STREAM != 0)
if (TraceTransport == 2U) {
if (count >= (USB_BLOCK_SIZE - (index_o & (USB_BLOCK_SIZE - 1U)))) {
osThreadFlagsSet(SWO_ThreadId, 1U);
}
}
#endif
}
if (event & ARM_USART_EVENT_RX_OVERFLOW) {
SetTraceError(DAP_SWO_BUFFER_OVERRUN);
}
if (event & (ARM_USART_EVENT_RX_BREAK |
ARM_USART_EVENT_RX_FRAMING_ERROR |
ARM_USART_EVENT_RX_PARITY_ERROR)) {
SetTraceError(DAP_SWO_STREAM_ERROR);
}
}
// Enable or disable SWO Mode (UART)
// enable: enable flag
// return: 1 - Success, 0 - Error
__WEAK uint32_t SWO_Mode_UART (uint32_t enable) {
int32_t status;
USART_Ready = 0U;
if (enable != 0U) {
status = pUSART->Initialize(USART_Callback);
if (status != ARM_DRIVER_OK) {
return (0U);
}
status = pUSART->PowerControl(ARM_POWER_FULL);
if (status != ARM_DRIVER_OK) {
pUSART->Uninitialize();
return (0U);
}
} else {
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
pUSART->PowerControl(ARM_POWER_OFF);
pUSART->Uninitialize();
}
return (1U);
}
// Configure SWO Baudrate (UART)
// baudrate: requested baudrate
// return: actual baudrate or 0 when not configured
__WEAK uint32_t SWO_Baudrate_UART (uint32_t baudrate) {
int32_t status;
uint32_t index;
uint32_t num;
if (baudrate > SWO_UART_MAX_BAUDRATE) {
baudrate = SWO_UART_MAX_BAUDRATE;
}
if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
if (pUSART->GetStatus().rx_busy) {
TraceIndexI += pUSART->GetRxCount();
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
}
}
status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS |
ARM_USART_DATA_BITS_8 |
ARM_USART_PARITY_NONE |
ARM_USART_STOP_BITS_1,
baudrate);
if (status == ARM_DRIVER_OK) {
USART_Ready = 1U;
} else {
USART_Ready = 0U;
return (0U);
}
if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
if ((TraceStatus & DAP_SWO_CAPTURE_PAUSED) == 0U) {
index = TraceIndexI & (SWO_BUFFER_SIZE - 1U);
num = TRACE_BLOCK_SIZE - (index & (TRACE_BLOCK_SIZE - 1U));
TraceBlockSize = num;
pUSART->Receive(&TraceBuf[index], num);
}
pUSART->Control(ARM_USART_CONTROL_RX, 1U);
}
return (baudrate);
}
// Control SWO Capture (UART)
// active: active flag
// return: 1 - Success, 0 - Error
__WEAK uint32_t SWO_Control_UART (uint32_t active) {
int32_t status;
if (active) {
if (!USART_Ready) {
return (0U);
}
TraceBlockSize = 1U;
status = pUSART->Receive(&TraceBuf[0], 1U);
if (status != ARM_DRIVER_OK) {
return (0U);
}
status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
if (status != ARM_DRIVER_OK) {
return (0U);
}
} else {
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
if (pUSART->GetStatus().rx_busy) {
TraceIndexI += pUSART->GetRxCount();
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
}
}
return (1U);
}
// Start SWO Capture (UART)
// buf: pointer to buffer for capturing
// num: number of bytes to capture
__WEAK void SWO_Capture_UART (uint8_t *buf, uint32_t num) {
TraceBlockSize = num;
pUSART->Receive(buf, num);
}
// Get SWO Pending Trace Count (UART)
// return: number of pending trace data bytes
__WEAK uint32_t SWO_GetCount_UART (void) {
uint32_t count;
if (pUSART->GetStatus().rx_busy) {
count = pUSART->GetRxCount();
} else {
count = 0U;
}
return (count);
}
#endif /* (SWO_UART != 0) */
#if (SWO_MANCHESTER != 0)
// Enable or disable SWO Mode (Manchester)
// enable: enable flag
// return: 1 - Success, 0 - Error
__WEAK uint32_t SWO_Mode_Manchester (uint32_t enable) {
return (0U);
}
// Configure SWO Baudrate (Manchester)
// baudrate: requested baudrate
// return: actual baudrate or 0 when not configured
__WEAK uint32_t SWO_Baudrate_Manchester (uint32_t baudrate) {
return (0U);
}
// Control SWO Capture (Manchester)
// active: active flag
// return: 1 - Success, 0 - Error
__WEAK uint32_t SWO_Control_Manchester (uint32_t active) {
return (0U);
}
// Start SWO Capture (Manchester)
// buf: pointer to buffer for capturing
// num: number of bytes to capture
__WEAK void SWO_Capture_Manchester (uint8_t *buf, uint32_t num) {
}
// Get SWO Pending Trace Count (Manchester)
// return: number of pending trace data bytes
__WEAK uint32_t SWO_GetCount_Manchester (void) {
}
#endif /* (SWO_MANCHESTER != 0) */
// Clear Trace Errors and Data
static void ClearTrace (void) {
#if (SWO_STREAM != 0)
if (TraceTransport == 2U) {
if (TransferBusy != 0U) {
SWO_AbortTransfer();
TransferBusy = 0U;
}
}
#endif
TraceError[0] = 0U;
TraceError[1] = 0U;
TraceError_n = 0U;
TraceIndexI = 0U;
TraceIndexO = 0U;
#if (TIMESTAMP_CLOCK != 0U)
TraceTimestamp.index = 0U;
TraceTimestamp.tick = 0U;
#endif
}
// Resume Trace Capture
static void ResumeTrace (void) {
uint32_t index_i;
uint32_t index_o;
if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) {
index_i = TraceIndexI;
index_o = TraceIndexO;
if ((index_i - index_o) < SWO_BUFFER_SIZE) {
index_i &= SWO_BUFFER_SIZE - 1U;
switch (TraceMode) {
#if (SWO_UART != 0)
case DAP_SWO_UART:
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
SWO_Capture_UART(&TraceBuf[index_i], 1U);
break;
#endif
#if (SWO_MANCHESTER != 0)
case DAP_SWO_MANCHESTER:
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
SWO_Capture_Manchester(&TraceBuf[index_i], 1U);
break;
#endif
default:
break;
}
}
}
}
// Get Trace Count
// return: number of available data bytes in trace buffer
static uint32_t GetTraceCount (void) {
uint32_t count;
if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
do {
TraceUpdate = 0U;
count = TraceIndexI - TraceIndexO;
switch (TraceMode) {
#if (SWO_UART != 0)
case DAP_SWO_UART:
count += SWO_GetCount_UART();
break;
#endif
#if (SWO_MANCHESTER != 0)
case DAP_SWO_MANCHESTER:
count += SWO_GetCount_Manchester();
break;
#endif
default:
break;
}
} while (TraceUpdate != 0U);
} else {
count = TraceIndexI - TraceIndexO;
}
return (count);
}
// Get Trace Status (clear Error flags)
// return: Trace Status (Active flag and Error flags)
static uint8_t GetTraceStatus (void) {
uint8_t status;
uint32_t n;
n = TraceError_n;
TraceError_n ^= 1U;
status = TraceStatus | TraceError[n];
TraceError[n] = 0U;
return (status);
}
// Set Trace Error flag(s)
// flag: error flag(s) to set
static void SetTraceError (uint8_t flag) {
TraceError[TraceError_n] |= flag;
}
// Process SWO Transport command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) {
uint8_t transport;
uint32_t result;
if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) == 0U) {
transport = *request;
switch (transport) {
case 0U:
case 1U:
#if (SWO_STREAM != 0)
case 2U:
#endif
TraceTransport = transport;
result = 1U;
break;
default:
result = 0U;
break;
}
} else {
result = 0U;
}
if (result != 0U) {
*response = DAP_OK;
} else {
*response = DAP_ERROR;
}
return ((1U << 16) | 1U);
}
// Process SWO Mode command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
uint8_t mode;
uint32_t result;
mode = *request;
switch (TraceMode) {
#if (SWO_UART != 0)
case DAP_SWO_UART:
SWO_Mode_UART(0U);
break;
#endif
#if (SWO_MANCHESTER != 0)
case DAP_SWO_MANCHESTER:
SWO_Mode_Manchester(0U);
break;
#endif
default:
break;
}
switch (mode) {
case DAP_SWO_OFF:
result = 1U;
break;
#if (SWO_UART != 0)
case DAP_SWO_UART:
result = SWO_Mode_UART(1U);
break;
#endif
#if (SWO_MANCHESTER != 0)
case DAP_SWO_MANCHESTER:
result = SWO_Mode_Manchester(1U);
break;
#endif
default:
result = 0U;
break;
}
if (result != 0U) {
TraceMode = mode;
} else {
TraceMode = DAP_SWO_OFF;
}
TraceStatus = 0U;
if (result != 0U) {
*response = DAP_OK;
} else {
*response = DAP_ERROR;
}
return ((1U << 16) | 1U);
}
// Process SWO Baudrate command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) {
uint32_t baudrate;
baudrate = (uint32_t)(*(request+0) << 0) |
(uint32_t)(*(request+1) << 8) |
(uint32_t)(*(request+2) << 16) |
(uint32_t)(*(request+3) << 24);
switch (TraceMode) {
#if (SWO_UART != 0)
case DAP_SWO_UART:
baudrate = SWO_Baudrate_UART(baudrate);
break;
#endif
#if (SWO_MANCHESTER != 0)
case DAP_SWO_MANCHESTER:
baudrate = SWO_Baudrate_Manchester(baudrate);
break;
#endif
default:
baudrate = 0U;
break;
}
if (baudrate == 0U) {
TraceStatus = 0U;
}
*response++ = (uint8_t)(baudrate >> 0);
*response++ = (uint8_t)(baudrate >> 8);
*response++ = (uint8_t)(baudrate >> 16);
*response = (uint8_t)(baudrate >> 24);
return ((4U << 16) | 4U);
}
// Process SWO Control command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t SWO_Control (const uint8_t *request, uint8_t *response) {
uint8_t active;
uint32_t result;
active = *request & DAP_SWO_CAPTURE_ACTIVE;
if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
if (active) {
ClearTrace();
}
switch (TraceMode) {
#if (SWO_UART != 0)
case DAP_SWO_UART:
result = SWO_Control_UART(active);
break;
#endif
#if (SWO_MANCHESTER != 0)
case DAP_SWO_MANCHESTER:
result = SWO_Control_Manchester(active);
break;
#endif
default:
result = 0U;
break;
}
if (result != 0U) {
TraceStatus = active;
#if (SWO_STREAM != 0)
if (TraceTransport == 2U) {
osThreadFlagsSet(SWO_ThreadId, 1U);
}
#endif
}
} else {
result = 1U;
}
if (result != 0U) {
*response = DAP_OK;
} else {
*response = DAP_ERROR;
}
return ((1U << 16) | 1U);
}
// Process SWO Status command and prepare response
// response: pointer to response data
// return: number of bytes in response
uint32_t SWO_Status (uint8_t *response) {
uint8_t status;
uint32_t count;
status = GetTraceStatus();
count = GetTraceCount();
*response++ = status;
*response++ = (uint8_t)(count >> 0);
*response++ = (uint8_t)(count >> 8);
*response++ = (uint8_t)(count >> 16);
*response = (uint8_t)(count >> 24);
return (5U);
}
// Process SWO Extended Status command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) {
uint8_t cmd;
uint8_t status;
uint32_t count;
#if (TIMESTAMP_CLOCK != 0U)
uint32_t index;
uint32_t tick;
#endif
uint32_t num;
num = 0U;
cmd = *request;
if (cmd & 0x01U) {
status = GetTraceStatus();
*response++ = status;
num += 1U;
}
if (cmd & 0x02U) {
count = GetTraceCount();
*response++ = (uint8_t)(count >> 0);
*response++ = (uint8_t)(count >> 8);
*response++ = (uint8_t)(count >> 16);
*response++ = (uint8_t)(count >> 24);
num += 4U;
}
#if (TIMESTAMP_CLOCK != 0U)
if (cmd & 0x04U) {
do {
TraceUpdate = 0U;
index = TraceTimestamp.index;
tick = TraceTimestamp.tick;
} while (TraceUpdate != 0U);
*response++ = (uint8_t)(index >> 0);
*response++ = (uint8_t)(index >> 8);
*response++ = (uint8_t)(index >> 16);
*response++ = (uint8_t)(index >> 24);
*response++ = (uint8_t)(tick >> 0);
*response++ = (uint8_t)(tick >> 8);
*response++ = (uint8_t)(tick >> 16);
*response++ = (uint8_t)(tick >> 24);
num += 4U;
}
#endif
return ((1U << 16) | num);
}
// Process SWO Data command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t SWO_Data (const uint8_t *request, uint8_t *response) {
uint8_t status;
uint32_t count;
uint32_t index;
uint32_t n, i;
status = GetTraceStatus();
count = GetTraceCount();
if (TraceTransport == 1U) {
n = (uint32_t)(*(request+0) << 0) |
(uint32_t)(*(request+1) << 8);
if (n > (DAP_PACKET_SIZE - 4U)) {
n = DAP_PACKET_SIZE - 4U;
}
if (count > n) {
count = n;
}
} else {
count = 0U;
}
*response++ = status;
*response++ = (uint8_t)(count >> 0);
*response++ = (uint8_t)(count >> 8);
if (TraceTransport == 1U) {
index = TraceIndexO;
for (i = index, n = count; n; n--) {
i &= SWO_BUFFER_SIZE - 1U;
*response++ = TraceBuf[i++];
}
TraceIndexO = index + count;
ResumeTrace();
}
return ((2U << 16) | (3U + count));
}
#if (SWO_STREAM != 0)
// SWO Data Transfer complete callback
void SWO_TransferComplete (void) {
TraceIndexO += TransferSize;
TransferBusy = 0U;
ResumeTrace();
osThreadFlagsSet(SWO_ThreadId, 1U);
}
// SWO Thread
__NO_RETURN void SWO_Thread (void *argument) {
uint32_t timeout;
uint32_t flags;
uint32_t count;
uint32_t index;
uint32_t i, n;
(void) argument;
timeout = osWaitForever;
for (;;) {
flags = osThreadFlagsWait(1U, osFlagsWaitAny, timeout);
if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
timeout = SWO_STREAM_TIMEOUT;
} else {
timeout = osWaitForever;
flags = osFlagsErrorTimeout;
}
if (TransferBusy == 0U) {
count = GetTraceCount();
if (count != 0U) {
index = TraceIndexO & (SWO_BUFFER_SIZE - 1U);
n = SWO_BUFFER_SIZE - index;
if (count > n) {
count = n;
}
if (flags != osFlagsErrorTimeout) {
i = index & (USB_BLOCK_SIZE - 1U);
if (i == 0U) {
count &= ~(USB_BLOCK_SIZE - 1U);
} else {
n = USB_BLOCK_SIZE - i;
if (count >= n) {
count = n;
} else {
count = 0U;
}
}
}
if (count != 0U) {
TransferSize = count;
TransferBusy = 1U;
SWO_QueueTransfer(&TraceBuf[index], count);
}
}
}
}
}
#endif /* (SWO_STREAM != 0) */
#endif /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 1. December 2017
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Source
* Title: SW_DP.c CMSIS-DAP SW DP I/O
*
*---------------------------------------------------------------------------*/
#include "DAP_config.h"
#include "DAP.h"
// SW Macros
#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET
#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR
#define SW_CLOCK_CYCLE() \
PIN_SWCLK_CLR(); \
PIN_DELAY(); \
PIN_SWCLK_SET(); \
PIN_DELAY()
#define SW_WRITE_BIT(bit) \
PIN_SWDIO_OUT(bit); \
PIN_SWCLK_CLR(); \
PIN_DELAY(); \
PIN_SWCLK_SET(); \
PIN_DELAY()
#define SW_READ_BIT(bit) \
PIN_SWCLK_CLR(); \
PIN_DELAY(); \
bit = PIN_SWDIO_IN(); \
PIN_SWCLK_SET(); \
PIN_DELAY()
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
// Generate SWJ Sequence
// count: sequence bit count
// data: pointer to sequence bit data
// return: none
#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
void SWJ_Sequence (uint32_t count, const uint8_t *data) {
uint32_t val;
uint32_t n;
val = 0U;
n = 0U;
while (count--) {
if (n == 0U) {
val = *data++;
n = 8U;
}
if (val & 1U) {
PIN_SWDIO_TMS_SET();
} else {
PIN_SWDIO_TMS_CLR();
}
SW_CLOCK_CYCLE();
val >>= 1;
n--;
}
}
#endif
// Generate SWD Sequence
// info: sequence information
// swdo: pointer to SWDIO generated data
// swdi: pointer to SWDIO captured data
// return: none
#if (DAP_SWD != 0)
void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) {
uint32_t val;
uint32_t bit;
uint32_t n, k;
n = info & SWD_SEQUENCE_CLK;
if (n == 0U) {
n = 64U;
}
if (info & SWD_SEQUENCE_DIN) {
while (n) {
val = 0U;
for (k = 8U; k && n; k--, n--) {
SW_READ_BIT(bit);
val >>= 1;
val |= bit << 7;
}
val >>= k;
*swdi++ = (uint8_t)val;
}
} else {
while (n) {
val = *swdo++;
for (k = 8U; k && n; k--, n--) {
SW_WRITE_BIT(val);
val >>= 1;
}
}
}
}
#endif
#if (DAP_SWD != 0)
// SWD Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
#define SWD_TransferFunction(speed) /**/ \
static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \
uint32_t ack; \
uint32_t bit; \
uint32_t val; \
uint32_t parity; \
\
uint32_t n; \
\
/* Packet Request */ \
parity = 0U; \
SW_WRITE_BIT(1U); /* Start Bit */ \
bit = request >> 0; \
SW_WRITE_BIT(bit); /* APnDP Bit */ \
parity += bit; \
bit = request >> 1; \
SW_WRITE_BIT(bit); /* RnW Bit */ \
parity += bit; \
bit = request >> 2; \
SW_WRITE_BIT(bit); /* A2 Bit */ \
parity += bit; \
bit = request >> 3; \
SW_WRITE_BIT(bit); /* A3 Bit */ \
parity += bit; \
SW_WRITE_BIT(parity); /* Parity Bit */ \
SW_WRITE_BIT(0U); /* Stop Bit */ \
SW_WRITE_BIT(1U); /* Park Bit */ \
\
/* Turnaround */ \
PIN_SWDIO_OUT_DISABLE(); \
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
SW_CLOCK_CYCLE(); \
} \
\
/* Acknowledge response */ \
SW_READ_BIT(bit); \
ack = bit << 0; \
SW_READ_BIT(bit); \
ack |= bit << 1; \
SW_READ_BIT(bit); \
ack |= bit << 2; \
\
if (ack == DAP_TRANSFER_OK) { /* OK response */ \
/* Data transfer */ \
if (request & DAP_TRANSFER_RnW) { \
/* Read data */ \
val = 0U; \
parity = 0U; \
for (n = 32U; n; n--) { \
SW_READ_BIT(bit); /* Read RDATA[0:31] */ \
parity += bit; \
val >>= 1; \
val |= bit << 31; \
} \
SW_READ_BIT(bit); /* Read Parity */ \
if ((parity ^ bit) & 1U) { \
ack = DAP_TRANSFER_ERROR; \
} \
if (data) { *data = val; } \
/* Turnaround */ \
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
SW_CLOCK_CYCLE(); \
} \
PIN_SWDIO_OUT_ENABLE(); \
} else { \
/* Turnaround */ \
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
SW_CLOCK_CYCLE(); \
} \
PIN_SWDIO_OUT_ENABLE(); \
/* Write data */ \
val = *data; \
parity = 0U; \
for (n = 32U; n; n--) { \
SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \
parity += val; \
val >>= 1; \
} \
SW_WRITE_BIT(parity); /* Write Parity Bit */ \
} \
/* Capture Timestamp */ \
if (request & DAP_TRANSFER_TIMESTAMP) { \
DAP_Data.timestamp = TIMESTAMP_GET(); \
} \
/* Idle cycles */ \
n = DAP_Data.transfer.idle_cycles; \
if (n) { \
PIN_SWDIO_OUT(0U); \
for (; n; n--) { \
SW_CLOCK_CYCLE(); \
} \
} \
PIN_SWDIO_OUT(1U); \
return ((uint8_t)ack); \
} \
\
if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \
/* WAIT or FAULT response */ \
if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \
for (n = 32U+1U; n; n--) { \
SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \
} \
} \
/* Turnaround */ \
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
SW_CLOCK_CYCLE(); \
} \
PIN_SWDIO_OUT_ENABLE(); \
if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \
PIN_SWDIO_OUT(0U); \
for (n = 32U+1U; n; n--) { \
SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \
} \
} \
PIN_SWDIO_OUT(1U); \
return ((uint8_t)ack); \
} \
\
/* Protocol error */ \
for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \
SW_CLOCK_CYCLE(); /* Back off data phase */ \
} \
PIN_SWDIO_OUT_ENABLE(); \
PIN_SWDIO_OUT(1U); \
return ((uint8_t)ack); \
}
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_FAST()
SWD_TransferFunction(Fast)
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
SWD_TransferFunction(Slow)
// SWD Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
uint8_t SWD_Transfer(uint32_t request, uint32_t *data) {
if (DAP_Data.fast_clock) {
return SWD_TransferFast(request, data);
} else {
return SWD_TransferSlow(request, data);
}
}
#endif /* (DAP_SWD != 0) */

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/*
* Copyright (c) 2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 1. March 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Source
* Title: UART.c CMSIS-DAP UART
*
*---------------------------------------------------------------------------*/
#include "DAP_config.h"
#include "DAP.h"
#if (DAP_UART != 0)
#ifdef DAP_FW_V1
#error "UART Communication Port not supported in DAP V1!"
#endif
#include "Driver_USART.h"
#include "cmsis_os2.h"
#include <string.h>
#define UART_RX_BLOCK_SIZE 32U /* Uart Rx Block Size (must be 2^n) */
// USART Driver
#define _USART_Driver_(n) Driver_USART##n
#define USART_Driver_(n) _USART_Driver_(n)
extern ARM_DRIVER_USART USART_Driver_(DAP_UART_DRIVER);
#define pUSART (&USART_Driver_(DAP_UART_DRIVER))
// UART Configuration
#if (DAP_UART_USB_COM_PORT != 0)
static uint8_t UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
#else
static uint8_t UartTransport = DAP_UART_TRANSPORT_NONE;
#endif
// UART Flags
static uint8_t UartConfigured = 0U;
static uint8_t UartReceiveEnabled = 0U;
static uint8_t UartTransmitEnabled = 0U;
static uint8_t UartTransmitActive = 0U;
// UART TX Buffer
static uint8_t UartTxBuf[DAP_UART_TX_BUFFER_SIZE];
static volatile uint32_t UartTxIndexI = 0U;
static volatile uint32_t UartTxIndexO = 0U;
// UART RX Buffer
static uint8_t UartRxBuf[DAP_UART_RX_BUFFER_SIZE];
static volatile uint32_t UartRxIndexI = 0U;
static volatile uint32_t UartRxIndexO = 0U;
// Uart Errors
static volatile uint8_t UartErrorRxDataLost = 0U;
static volatile uint8_t UartErrorFraming = 0U;
static volatile uint8_t UartErrorParity = 0U;
// UART Transmit
static uint32_t UartTxNum = 0U;
// Function prototypes
static uint8_t UART_Init (void);
static void UART_Uninit (void);
static uint8_t UART_Get_Status (void);
static uint8_t UART_Receive_Enable (void);
static uint8_t UART_Transmit_Enable (void);
static void UART_Receive_Disable (void);
static void UART_Transmit_Disable (void);
static void UART_Receive_Flush (void);
static void UART_Transmit_Flush (void);
static void UART_Receive (void);
static void UART_Transmit (void);
// USART Driver Callback function
// event: event mask
static void USART_Callback (uint32_t event) {
if (event & ARM_USART_EVENT_SEND_COMPLETE) {
UartTxIndexO += UartTxNum;
UartTransmitActive = 0U;
UART_Transmit();
}
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
UartRxIndexI += UART_RX_BLOCK_SIZE;
UART_Receive();
}
if (event & ARM_USART_EVENT_RX_OVERFLOW) {
UartErrorRxDataLost = 1U;
}
if (event & ARM_USART_EVENT_RX_FRAMING_ERROR) {
UartErrorFraming = 1U;
}
if (event & ARM_USART_EVENT_RX_PARITY_ERROR) {
UartErrorParity = 1U;
}
}
// Init UART
// return: DAP_OK or DAP_ERROR
static uint8_t UART_Init (void) {
int32_t status;
uint8_t ret = DAP_ERROR;
UartConfigured = 0U;
UartReceiveEnabled = 0U;
UartTransmitEnabled = 0U;
UartTransmitActive = 0U;
UartErrorRxDataLost = 0U;
UartErrorFraming = 0U;
UartErrorParity = 0U;
UartTxIndexI = 0U;
UartTxIndexO = 0U;
UartRxIndexI = 0U;
UartRxIndexO = 0U;
UartTxNum = 0U;
status = pUSART->Initialize(USART_Callback);
if (status == ARM_DRIVER_OK) {
status = pUSART->PowerControl(ARM_POWER_FULL);
}
if (status == ARM_DRIVER_OK) {
ret = DAP_OK;
}
return (ret);
}
// Un-Init UART
static void UART_Uninit (void) {
UartConfigured = 0U;
pUSART->PowerControl(ARM_POWER_OFF);
pUSART->Uninitialize();
}
// Get UART Status
// return: status
static uint8_t UART_Get_Status (void) {
uint8_t status = 0U;
if (UartReceiveEnabled != 0U) {
status |= DAP_UART_STATUS_RX_ENABLED;
}
if (UartErrorRxDataLost != 0U) {
UartErrorRxDataLost = 0U;
status |= DAP_UART_STATUS_RX_DATA_LOST;
}
if (UartErrorFraming != 0U) {
UartErrorFraming = 0U;
status |= DAP_UART_STATUS_FRAMING_ERROR;
}
if (UartErrorParity != 0U) {
UartErrorParity = 0U;
status |= DAP_UART_STATUS_PARITY_ERROR;
}
if (UartTransmitEnabled != 0U) {
status |= DAP_UART_STATUS_TX_ENABLED;
}
return (status);
}
// Enable UART Receive
// return: DAP_OK or DAP_ERROR
static uint8_t UART_Receive_Enable (void) {
int32_t status;
uint8_t ret = DAP_ERROR;
if (UartReceiveEnabled == 0U) {
// Flush Buffers
UartRxIndexI = 0U;
UartRxIndexO = 0U;
UART_Receive();
status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
if (status == ARM_DRIVER_OK) {
UartReceiveEnabled = 1U;
ret = DAP_OK;
}
} else {
ret = DAP_OK;
}
return (ret);
}
// Enable UART Transmit
// return: DAP_OK or DAP_ERROR
static uint8_t UART_Transmit_Enable (void) {
int32_t status;
uint8_t ret = DAP_ERROR;
if (UartTransmitEnabled == 0U) {
// Flush Buffers
UartTransmitActive = 0U;
UartTxIndexI = 0U;
UartTxIndexO = 0U;
UartTxNum = 0U;
status = pUSART->Control(ARM_USART_CONTROL_TX, 1U);
if (status == ARM_DRIVER_OK) {
UartTransmitEnabled = 1U;
ret = DAP_OK;
}
} else {
ret = DAP_OK;
}
return (ret);
}
// Disable UART Receive
static void UART_Receive_Disable (void) {
if (UartReceiveEnabled != 0U) {
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
UartReceiveEnabled = 0U;
}
}
// Disable UART Transmit
static void UART_Transmit_Disable (void) {
if (UartTransmitEnabled != 0U) {
pUSART->Control(ARM_USART_ABORT_SEND, 0U);
pUSART->Control(ARM_USART_CONTROL_TX, 0U);
UartTransmitActive = 0U;
UartTransmitEnabled = 0U;
}
}
// Flush UART Receive buffer
static void UART_Receive_Flush (void) {
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
UartRxIndexI = 0U;
UartRxIndexO = 0U;
if (UartReceiveEnabled != 0U) {
UART_Receive();
}
}
// Flush UART Transmit buffer
static void UART_Transmit_Flush (void) {
pUSART->Control(ARM_USART_ABORT_SEND, 0U);
UartTransmitActive = 0U;
UartTxIndexI = 0U;
UartTxIndexO = 0U;
UartTxNum = 0U;
}
// Receive data from target via UART
static void UART_Receive (void) {
uint32_t index;
index = UartRxIndexI & (DAP_UART_RX_BUFFER_SIZE - 1U);
pUSART->Receive(&UartRxBuf[index], UART_RX_BLOCK_SIZE);
}
// Transmit available data to target via UART
static void UART_Transmit (void) {
uint32_t count;
uint32_t index;
count = UartTxIndexI - UartTxIndexO;
index = UartTxIndexO & (DAP_UART_TX_BUFFER_SIZE - 1U);
if (count != 0U) {
if ((index + count) <= DAP_UART_TX_BUFFER_SIZE) {
UartTxNum = count;
} else {
UartTxNum = DAP_UART_TX_BUFFER_SIZE - index;
}
UartTransmitActive = 1U;
pUSART->Send(&UartTxBuf[index], UartTxNum);
}
}
// Process UART Transport command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t UART_Transport (const uint8_t *request, uint8_t *response) {
uint8_t transport;
uint8_t ret = DAP_ERROR;
transport = *request;
switch (transport) {
case DAP_UART_TRANSPORT_NONE:
switch (UartTransport) {
case DAP_UART_TRANSPORT_NONE:
ret = DAP_OK;
break;
case DAP_UART_TRANSPORT_USB_COM_PORT:
#if (DAP_UART_USB_COM_PORT != 0)
USB_COM_PORT_Activate(0U);
UartTransport = DAP_UART_TRANSPORT_NONE;
ret = DAP_OK;
#endif
break;
case DAP_UART_TRANSPORT_DAP_COMMAND:
UART_Receive_Disable();
UART_Transmit_Disable();
UART_Uninit();
UartTransport = DAP_UART_TRANSPORT_NONE;
ret= DAP_OK;
break;
}
break;
case DAP_UART_TRANSPORT_USB_COM_PORT:
switch (UartTransport) {
case DAP_UART_TRANSPORT_NONE:
#if (DAP_UART_USB_COM_PORT != 0)
if (USB_COM_PORT_Activate(1U) == 0U) {
UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
ret = DAP_OK;
}
#endif
break;
case DAP_UART_TRANSPORT_USB_COM_PORT:
ret = DAP_OK;
break;
case DAP_UART_TRANSPORT_DAP_COMMAND:
UART_Receive_Disable();
UART_Transmit_Disable();
UART_Uninit();
UartTransport = DAP_UART_TRANSPORT_NONE;
#if (DAP_UART_USB_COM_PORT != 0)
if (USB_COM_PORT_Activate(1U) == 0U) {
UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
ret = DAP_OK;
}
#endif
break;
}
break;
case DAP_UART_TRANSPORT_DAP_COMMAND:
switch (UartTransport) {
case DAP_UART_TRANSPORT_NONE:
ret = UART_Init();
if (ret == DAP_OK) {
UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND;
}
break;
case DAP_UART_TRANSPORT_USB_COM_PORT:
#if (DAP_UART_USB_COM_PORT != 0)
USB_COM_PORT_Activate(0U);
UartTransport = DAP_UART_TRANSPORT_NONE;
#endif
ret = UART_Init();
if (ret == DAP_OK) {
UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND;
}
break;
case DAP_UART_TRANSPORT_DAP_COMMAND:
ret = DAP_OK;
break;
}
break;
default:
break;
}
*response = ret;
return ((1U << 16) | 1U);
}
// Process UART Configure command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t UART_Configure (const uint8_t *request, uint8_t *response) {
uint8_t control, status;
uint32_t baudrate;
int32_t result;
if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
status = DAP_UART_CFG_ERROR_DATA_BITS |
DAP_UART_CFG_ERROR_PARITY |
DAP_UART_CFG_ERROR_STOP_BITS;
baudrate = 0U; // baudrate error
} else {
status = 0U;
control = *request;
baudrate = (uint32_t)(*(request+1) << 0) |
(uint32_t)(*(request+2) << 8) |
(uint32_t)(*(request+3) << 16) |
(uint32_t)(*(request+4) << 24);
result = pUSART->Control(control |
ARM_USART_MODE_ASYNCHRONOUS |
ARM_USART_FLOW_CONTROL_NONE,
baudrate);
if (result == ARM_DRIVER_OK) {
UartConfigured = 1U;
} else {
UartConfigured = 0U;
switch (result) {
case ARM_USART_ERROR_BAUDRATE:
status = 0U;
baudrate = 0U;
break;
case ARM_USART_ERROR_DATA_BITS:
status = DAP_UART_CFG_ERROR_DATA_BITS;
break;
case ARM_USART_ERROR_PARITY:
status = DAP_UART_CFG_ERROR_PARITY;
break;
case ARM_USART_ERROR_STOP_BITS:
status = DAP_UART_CFG_ERROR_STOP_BITS;
break;
default:
status = DAP_UART_CFG_ERROR_DATA_BITS |
DAP_UART_CFG_ERROR_PARITY |
DAP_UART_CFG_ERROR_STOP_BITS;
baudrate = 0U;
break;
}
}
}
*response++ = status;
*response++ = (uint8_t)(baudrate >> 0);
*response++ = (uint8_t)(baudrate >> 8);
*response++ = (uint8_t)(baudrate >> 16);
*response = (uint8_t)(baudrate >> 24);
return ((5U << 16) | 5U);
}
// Process UART Control command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t UART_Control (const uint8_t *request, uint8_t *response) {
uint8_t control;
uint8_t result;
uint8_t ret = DAP_OK;
if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
ret = DAP_ERROR;
} else {
control = *request;
if ((control & DAP_UART_CONTROL_RX_DISABLE) != 0U) {
// Receive disable
UART_Receive_Disable();
} else if ((control & DAP_UART_CONTROL_RX_ENABLE) != 0U) {
// Receive enable
if (UartConfigured != 0U) {
result = UART_Receive_Enable();
if (result != DAP_OK) {
ret = DAP_ERROR;
}
} else {
ret = DAP_ERROR;
}
}
if ((control & DAP_UART_CONTROL_RX_BUF_FLUSH) != 0U) {
UART_Receive_Flush();
}
if ((control & DAP_UART_CONTROL_TX_DISABLE) != 0U) {
// Transmit disable
UART_Transmit_Disable();
} else if ((control & DAP_UART_CONTROL_TX_ENABLE) != 0U) {
// Transmit enable
if (UartConfigured != 0U) {
result = UART_Transmit_Enable();
if (result != DAP_OK) {
ret = DAP_ERROR;
}
} else {
ret = DAP_ERROR;
}
}
if ((control & DAP_UART_CONTROL_TX_BUF_FLUSH) != 0U) {
UART_Transmit_Flush();
}
}
*response = ret;
return ((1U << 16) | 1U);
}
// Process UART Status command and prepare response
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t UART_Status (uint8_t *response) {
uint32_t rx_cnt, tx_cnt;
uint32_t cnt;
uint8_t status;
if ((UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) ||
(UartConfigured == 0U)) {
rx_cnt = 0U;
tx_cnt = 0U;
status = 0U;
} else {
rx_cnt = UartRxIndexI - UartRxIndexO;
rx_cnt += pUSART->GetRxCount();
if (rx_cnt > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) {
// Overflow
UartErrorRxDataLost = 1U;
rx_cnt = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2));
UartRxIndexO = UartRxIndexI - rx_cnt;
}
tx_cnt = UartTxIndexI - UartTxIndexO;
cnt = pUSART->GetTxCount();
if (UartTransmitActive != 0U) {
tx_cnt -= cnt;
}
status = UART_Get_Status();
}
*response++ = status;
*response++ = (uint8_t)(rx_cnt >> 0);
*response++ = (uint8_t)(rx_cnt >> 8);
*response++ = (uint8_t)(rx_cnt >> 16);
*response++ = (uint8_t)(rx_cnt >> 24);
*response++ = (uint8_t)(tx_cnt >> 0);
*response++ = (uint8_t)(tx_cnt >> 8);
*response++ = (uint8_t)(tx_cnt >> 16);
*response = (uint8_t)(tx_cnt >> 24);
return ((0U << 16) | 9U);
}
// Process UART Transfer command and prepare response
// request: pointer to request data
// response: pointer to response data
// return: number of bytes in response (lower 16 bits)
// number of bytes in request (upper 16 bits)
uint32_t UART_Transfer (const uint8_t *request, uint8_t *response) {
uint32_t rx_cnt, tx_cnt;
uint32_t rx_num, tx_num;
uint8_t *rx_data;
const
uint8_t *tx_data;
uint32_t num;
uint32_t index;
uint8_t status;
if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
status = 0U;
rx_cnt = 0U;
tx_cnt = 0U;
} else {
// RX Data
rx_cnt = ((uint32_t)(*(request+0) << 0) |
(uint32_t)(*(request+1) << 8));
if (rx_cnt > (DAP_PACKET_SIZE - 6U)) {
rx_cnt = (DAP_PACKET_SIZE - 6U);
}
rx_num = UartRxIndexI - UartRxIndexO;
rx_num += pUSART->GetRxCount();
if (rx_num > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) {
// Overflow
UartErrorRxDataLost = 1U;
rx_num = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2));
UartRxIndexO = UartRxIndexI - rx_num;
}
if (rx_cnt > rx_num) {
rx_cnt = rx_num;
}
rx_data = (response+5);
index = UartRxIndexO & (DAP_UART_RX_BUFFER_SIZE - 1U);
if ((index + rx_cnt) <= DAP_UART_RX_BUFFER_SIZE) {
memcpy( rx_data, &UartRxBuf[index], rx_cnt);
} else {
num = DAP_UART_RX_BUFFER_SIZE - index;
memcpy( rx_data, &UartRxBuf[index], num);
memcpy(&rx_data[num], &UartRxBuf[0], rx_cnt - num);
}
UartRxIndexO += rx_cnt;
// TX Data
tx_cnt = ((uint32_t)(*(request+2) << 0) |
(uint32_t)(*(request+3) << 8));
tx_data = (request+4);
if (tx_cnt > (DAP_PACKET_SIZE - 5U)) {
tx_cnt = (DAP_PACKET_SIZE - 5U);
}
tx_num = UartTxIndexI - UartTxIndexO;
num = pUSART->GetTxCount();
if (UartTransmitActive != 0U) {
tx_num -= num;
}
if (tx_cnt > (DAP_UART_TX_BUFFER_SIZE - tx_num)) {
tx_cnt = (DAP_UART_TX_BUFFER_SIZE - tx_num);
}
index = UartTxIndexI & (DAP_UART_TX_BUFFER_SIZE - 1U);
if ((index + tx_cnt) <= DAP_UART_TX_BUFFER_SIZE) {
memcpy(&UartTxBuf[index], tx_data, tx_cnt);
} else {
num = DAP_UART_TX_BUFFER_SIZE - index;
memcpy(&UartTxBuf[index], tx_data, num);
memcpy(&UartTxBuf[0], &tx_data[num], tx_cnt - num);
}
UartTxIndexI += tx_cnt;
if (UartTransmitActive == 0U) {
UART_Transmit();
}
status = UART_Get_Status();
}
*response++ = status;
*response++ = (uint8_t)(tx_cnt >> 0);
*response++ = (uint8_t)(tx_cnt >> 8);
*response++ = (uint8_t)(rx_cnt >> 0);
*response = (uint8_t)(rx_cnt >> 8);
return (((4U + tx_cnt) << 16) | (5U + rx_cnt));
}
#endif /* DAP_UART */

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@ -0,0 +1,54 @@
[Version]
Signature = "$Windows NT$"
Class = USBDevice
ClassGUID = {88BAE032-5A81-49f0-BC3D-A4FF138216D6}
Provider = %ManufacturerName%
DriverVer = 04/13/2016, 1.0.0.0
CatalogFile.nt = CMSIS_DAP_v2_x86.cat
CatalogFile.ntx86 = CMSIS_DAP_v2_x86.cat
CatalogFile.ntamd64 = CMSIS_DAP_v2_amd64.cat
; ========== Manufacturer/Models sections ===========
[Manufacturer]
%ManufacturerName% = Devices, NTx86, NTamd64
[Devices.NTx86]
%DeviceName% = USB_Install, USB\VID_c251&PID_f000
[Devices.NTamd64]
%DeviceName% = USB_Install, USB\VID_c251&PID_f000
; ========== Class definition ===========
[ClassInstall32]
AddReg = ClassInstall_AddReg
[ClassInstall_AddReg]
HKR,,,,%ClassName%
HKR,,NoInstallClass,,1
HKR,,IconPath,0x10000,"%%SystemRoot%%\System32\setupapi.dll,-20"
HKR,,LowerLogoVersion,,5.2
; =================== Installation ===================
[USB_Install]
Include = winusb.inf
Needs = WINUSB.NT
[USB_Install.Services]
Include = winusb.inf
Needs = WINUSB.NT.Services
[USB_Install.HW]
AddReg = Dev_AddReg
[Dev_AddReg]
HKR,,DeviceInterfaceGUIDs,0x10000,"{CDB3B5AD-293B-4663-AA36-1AAE46463776}"
; =================== Strings ===================
[Strings]
ClassName = "Universal Serial Bus devices"
ManufacturerName = "KEIL - Tools By ARM"
DeviceName = "CMSIS-DAP v2"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device:CDC
* Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_User_CDC_ACM_UART_0.c
* Purpose: USB Device Communication Device Class (CDC)
* Abstract Control Model (ACM) USB <-> UART Bridge User module
* Rev.: V1.0.8
*----------------------------------------------------------------------------*/
/**
* \addtogroup usbd_cdcFunctions
*
* USBD_User_CDC_ACM_UART_0.c implements the application specific
* functionality of the CDC ACM class and is used to demonstrate a USB <-> UART
* bridge. All data received on USB is transmitted on UART and all data
* received on UART is transmitted on USB.
*
* Details of operation:
* UART -> USB:
* Initial reception on UART is started after the USB Host sets line coding
* with SetLineCoding command. Having received a full UART buffer, any
* new reception is restarted on the same buffer. Any data received on
* the UART is sent over USB using the CDC0_ACM_UART_to_USB_Thread thread.
* USB -> UART:
* While the UART transmit is not busy, data transmission on the UART is
* started in the USBD_CDC0_ACM_DataReceived callback as soon as data is
* received on the USB. Further data received on USB is transmitted on
* UART in the UART callback routine until there is no more data available.
* In this case, the next UART transmit is restarted from the
* USBD_CDC0_ACM_DataReceived callback as soon as new data is received
* on the USB.
*
* The following constants in this module affect the module functionality:
*
* - UART_PORT: specifies UART Port
* default value: 0 (=UART0)
* - UART_BUFFER_SIZE: specifies UART data Buffer Size
* default value: 512
*
* Notes:
* If the USB is slower than the UART, data can get lost. This may happen
* when USB is pausing during data reception because of the USB Host being
* too loaded with other tasks and not polling the Bulk IN Endpoint often
* enough (up to 2 seconds of gap in polling Bulk IN Endpoint may occur).
* This problem can be solved by using a large enough UART buffer to
* compensate up to a few seconds of received UART data or by using UART
* flow control.
* If the device that receives the UART data (usually a PC) is too loaded
* with other tasks it can also loose UART data. This problem can only be
* solved by using UART flow control.
*
* This file has to be adapted in case of UART flow control usage.
*/
//! [code_USBD_User_CDC_ACM]
#include <stdio.h>
#include <string.h>
#include "rl_usb.h"
#include "Driver_USART.h"
#include "DAP_config.h"
#include "DAP.h"
// UART Configuration ----------------------------------------------------------
#define UART_BUFFER_SIZE (512) // UART Buffer Size
//------------------------------------------------------------------------------
#define _UART_Driver_(n) Driver_USART##n
#define UART_Driver_(n) _UART_Driver_(n)
extern ARM_DRIVER_USART UART_Driver_(DAP_UART_DRIVER);
#define ptrUART (&UART_Driver_(DAP_UART_DRIVER))
// Local Variables
static uint8_t uart_rx_buf[UART_BUFFER_SIZE];
static uint8_t uart_tx_buf[UART_BUFFER_SIZE];
static volatile int32_t uart_rx_cnt = 0;
static volatile int32_t usb_tx_cnt = 0;
static void *cdc_acm_bridge_tid = 0U;
static CDC_LINE_CODING cdc_acm_line_coding = { 0U, 0U, 0U, 0U };
static uint8_t cdc_acm_active = 1U;
static osMutexId_t cdc_acm_mutex_id = NULL;
// Acquire mutex
__STATIC_INLINE void CDC_ACM_Lock (void) {
if (cdc_acm_mutex_id == NULL) {
cdc_acm_mutex_id = osMutexNew(NULL);
}
osMutexAcquire(cdc_acm_mutex_id, osWaitForever);
}
// Release mutex
__STATIC_INLINE void CDC_ACM_Unlock (void) {
osMutexRelease(cdc_acm_mutex_id);
}
// Change communication settings.
// \param[in] line_coding pointer to CDC_LINE_CODING structure.
// \return true set line coding request processed.
// \return false set line coding request not supported or not processed.
static bool CDC_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
uint32_t data_bits = 0U, parity = 0U, stop_bits = 0U;
int32_t status;
(void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U);
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
(void)ptrUART->Control (ARM_USART_CONTROL_TX, 0U);
(void)ptrUART->Control (ARM_USART_CONTROL_RX, 0U);
switch (line_coding->bCharFormat) {
case 0: // 1 Stop bit
stop_bits = ARM_USART_STOP_BITS_1;
break;
case 1: // 1.5 Stop bits
stop_bits = ARM_USART_STOP_BITS_1_5;
break;
case 2: // 2 Stop bits
stop_bits = ARM_USART_STOP_BITS_2;
break;
default:
return false;
}
switch (line_coding->bParityType) {
case 0: // None
parity = ARM_USART_PARITY_NONE;
break;
case 1: // Odd
parity = ARM_USART_PARITY_ODD;
break;
case 2: // Even
parity = ARM_USART_PARITY_EVEN;
break;
default:
return false;
}
switch (line_coding->bDataBits) {
case 5:
data_bits = ARM_USART_DATA_BITS_5;
break;
case 6:
data_bits = ARM_USART_DATA_BITS_6;
break;
case 7:
data_bits = ARM_USART_DATA_BITS_7;
break;
case 8:
data_bits = ARM_USART_DATA_BITS_8;
break;
default:
return false;
}
status = ptrUART->Control(ARM_USART_MODE_ASYNCHRONOUS |
data_bits |
parity |
stop_bits ,
line_coding->dwDTERate );
if (status != ARM_DRIVER_OK) {
return false;
}
// Store requested settings to local variable
memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
uart_rx_cnt = 0;
usb_tx_cnt = 0;
(void)ptrUART->Control (ARM_USART_CONTROL_TX, 1U);
(void)ptrUART->Control (ARM_USART_CONTROL_RX, 1U);
(void)ptrUART->Receive (uart_rx_buf, UART_BUFFER_SIZE);
return true;
}
// Activate or Deactivate USBD COM PORT
// \param[in] cmd 0=deactivate, 1=activate
// \return 0=Ok, 0xFF=Error
uint8_t USB_COM_PORT_Activate (uint32_t cmd) {
switch (cmd) {
case 0U:
cdc_acm_active = 0U;
USBD_CDC0_ACM_Uninitialize();
break;
case 1U:
USBD_CDC0_ACM_Initialize();
CDC_ACM_Lock();
CDC_ACM_SetLineCoding(&cdc_acm_line_coding);
cdc_acm_active = 1U;
CDC_ACM_Unlock();
break;
}
return 0U;
}
// Called when UART has transmitted or received requested number of bytes.
// \param[in] event UART event
// - ARM_USART_EVENT_SEND_COMPLETE: all requested data was sent
// - ARM_USART_EVENT_RECEIVE_COMPLETE: all requested data was received
static void UART_Callback (uint32_t event) {
int32_t cnt;
if (cdc_acm_active == 0U) {
return;
}
if (event & ARM_USART_EVENT_SEND_COMPLETE) {
// USB -> UART
cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
if (cnt > 0) {
(void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
}
}
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
// UART data received, restart new reception
uart_rx_cnt += UART_BUFFER_SIZE;
(void)ptrUART->Receive(uart_rx_buf, UART_BUFFER_SIZE);
}
}
// Thread: Sends data received on UART to USB
// \param[in] arg not used.
__NO_RETURN static void CDC0_ACM_UART_to_USB_Thread (void *arg) {
int32_t cnt, cnt_to_wrap;
(void)(arg);
for (;;) {
// UART - > USB
if (ptrUART->GetStatus().rx_busy != 0U) {
cnt = uart_rx_cnt;
cnt += (int32_t)ptrUART->GetRxCount();
cnt -= usb_tx_cnt;
if (cnt >= (UART_BUFFER_SIZE - 32)) {
// Dump old data in UART receive buffer if USB is not consuming fast enough
cnt = (UART_BUFFER_SIZE - 32);
usb_tx_cnt = uart_rx_cnt - (UART_BUFFER_SIZE - 32);
}
if (cnt > 0) {
cnt_to_wrap = (int32_t)(UART_BUFFER_SIZE - ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1)));
if (cnt > cnt_to_wrap) {
cnt = cnt_to_wrap;
}
cnt = USBD_CDC_ACM_WriteData(0U, (uart_rx_buf + ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))), cnt);
if (cnt > 0) {
usb_tx_cnt += cnt;
}
}
}
(void)osDelay(10U);
}
}
static osRtxThread_t cdc0_acm_uart_to_usb_thread_cb_mem __SECTION(.bss.os.thread.cb);
static uint64_t cdc0_acm_uart_to_usb_thread_stack_mem[512U / 8U] __SECTION(.bss.os.thread.cdc.stack);
static const osThreadAttr_t cdc0_acm_uart_to_usb_thread_attr = {
"CDC0_ACM_UART_to_USB_Thread",
0U,
&cdc0_acm_uart_to_usb_thread_cb_mem,
sizeof(osRtxThread_t),
&cdc0_acm_uart_to_usb_thread_stack_mem[0],
sizeof(cdc0_acm_uart_to_usb_thread_stack_mem),
osPriorityNormal,
0U,
0U
};
// CDC ACM Callbacks -----------------------------------------------------------
// Called when new data was received from the USB Host.
// \param[in] len number of bytes available to read.
void USBD_CDC0_ACM_DataReceived (uint32_t len) {
int32_t cnt;
(void)(len);
if (cdc_acm_active == 0U) {
return;
}
if (ptrUART->GetStatus().tx_busy == 0U) {
// Start USB -> UART
cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
if (cnt > 0) {
(void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
}
}
}
// Called during USBD_Initialize to initialize the USB CDC class instance (ACM).
void USBD_CDC0_ACM_Initialize (void) {
(void)ptrUART->Initialize (UART_Callback);
(void)ptrUART->PowerControl (ARM_POWER_FULL);
cdc_acm_bridge_tid = osThreadNew (CDC0_ACM_UART_to_USB_Thread, NULL, &cdc0_acm_uart_to_usb_thread_attr);
}
// Called during USBD_Uninitialize to de-initialize the USB CDC class instance (ACM).
void USBD_CDC0_ACM_Uninitialize (void) {
if (osThreadTerminate (cdc_acm_bridge_tid) == osOK) {
cdc_acm_bridge_tid = NULL;
}
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
(void)ptrUART->PowerControl (ARM_POWER_OFF);
(void)ptrUART->Uninitialize ();
}
// Called upon USB Bus Reset Event.
void USBD_CDC0_ACM_Reset (void) {
if (cdc_acm_active == 0U ) {
return;
}
(void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U);
(void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
}
// Called upon USB Host request to change communication settings.
// \param[in] line_coding pointer to CDC_LINE_CODING structure.
// \return true set line coding request processed.
// \return false set line coding request not supported or not processed.
bool USBD_CDC0_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
bool ret = false;
CDC_ACM_Lock();
if (cdc_acm_active == 0U) {
// Store requested settings to local variable
memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
ret = true;
} else {
ret = CDC_ACM_SetLineCoding(line_coding);
}
CDC_ACM_Unlock();
return ret;
}
// Called upon USB Host request to retrieve communication settings.
// \param[out] line_coding pointer to CDC_LINE_CODING structure.
// \return true get line coding request processed.
// \return false get line coding request not supported or not processed.
bool USBD_CDC0_ACM_GetLineCoding (CDC_LINE_CODING *line_coding) {
// Load settings from ones stored on USBD_CDC0_ACM_SetLineCoding callback
*line_coding = cdc_acm_line_coding;
return true;
}
// Called upon USB Host request to set control line states.
// \param [in] state control line settings bitmap.
// - bit 0: DTR state
// - bit 1: RTS state
// \return true set control line state request processed.
// \return false set control line state request not supported or not processed.
bool USBD_CDC0_ACM_SetControlLineState (uint16_t state) {
// Add code for set control line state
(void)(state);
return true;
}
//! [code_USBD_User_CDC_ACM]

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2016 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_User_CustomClass_0.c
* Purpose: USB Device Custom Class User module
* Rev.: V6.7.3
*----------------------------------------------------------------------------*/
/*
* USBD_User_CustomClass_0.c is a code template for the Custom Class 0
* class request handling. It allows user to handle all Custom Class class
* requests.
*
* Uncomment "Example code" lines to see example that receives data on
* Endpoint 1 OUT and echoes it back on Endpoint 1 IN.
* To try the example you also have to enable Bulk Endpoint 1 IN/OUT in Custom
* Class configuration in USBD_Config_CustomClass_0.h file.
*/
/**
* \addtogroup usbd_custom_classFunctions
*
*/
//! [code_USBD_User_CustomClass]
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "cmsis_os2.h"
#define osObjectsExternal
#include "osObjects.h"
#include "rl_usb.h"
#include "Driver_USBD.h"
#include "DAP_config.h"
#include "DAP.h"
static volatile uint16_t USB_RequestIndexI; // Request Index In
static volatile uint16_t USB_RequestIndexO; // Request Index Out
static volatile uint16_t USB_RequestCountI; // Request Count In
static volatile uint16_t USB_RequestCountO; // Request Count Out
static volatile uint8_t USB_RequestIdle; // Request Idle Flag
static volatile uint16_t USB_ResponseIndexI; // Response Index In
static volatile uint16_t USB_ResponseIndexO; // Response Index Out
static volatile uint16_t USB_ResponseCountI; // Response Count In
static volatile uint16_t USB_ResponseCountO; // Response Count Out
static volatile uint8_t USB_ResponseIdle; // Response Idle Flag
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Request Buffer
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Response Buffer
static uint16_t USB_RespSize[DAP_PACKET_COUNT]; // Response Size
// \brief Callback function called during USBD_Initialize to initialize the USB Custom class instance
void USBD_CustomClass0_Initialize (void) {
// Handle Custom Class Initialization
// Initialize variables
USB_RequestIndexI = 0U;
USB_RequestIndexO = 0U;
USB_RequestCountI = 0U;
USB_RequestCountO = 0U;
USB_RequestIdle = 1U;
USB_ResponseIndexI = 0U;
USB_ResponseIndexO = 0U;
USB_ResponseCountI = 0U;
USB_ResponseCountO = 0U;
USB_ResponseIdle = 1U;
}
// \brief Callback function called during USBD_Uninitialize to de-initialize the USB Custom class instance
void USBD_CustomClass0_Uninitialize (void) {
// Handle Custom Class De-initialization
}
// \brief Callback function called upon USB Bus Reset signaling
void USBD_CustomClass0_Reset (void) {
// Handle USB Bus Reset Event
}
// \brief Callback function called when Endpoint Start was requested (by activating interface or configuration)
// \param[in] ep_addr endpoint address.
void USBD_CustomClass0_EndpointStart (uint8_t ep_addr) {
// Start communication on Endpoint
if (ep_addr == USB_ENDPOINT_OUT(1U)) {
USB_RequestIdle = 0U;
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[0], DAP_PACKET_SIZE);
}
}
// \brief Callback function called when Endpoint Stop was requested (by de-activating interface or activating configuration 0)
// \param[in] ep_addr endpoint address.
void USBD_CustomClass0_EndpointStop (uint8_t ep_addr) {
// Handle Endpoint communication stopped
(void)ep_addr;
}
// \brief Callback function called when Custom Class 0 received SETUP PACKET on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] setup_packet pointer to received setup packet.
// \param[out] buf pointer to data buffer used for data stage requested by setup packet.
// \param[out] len pointer to number of data bytes in data stage requested by setup packet.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet if no data stage)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
usbdRequestStatus USBD_CustomClass0_Endpoint0_SetupPacketReceived (const USB_SETUP_PACKET *setup_packet, uint8_t **buf, uint32_t *len) {
(void)setup_packet;
(void)buf;
(void)len;
switch (setup_packet->bmRequestType.Recipient) {
case USB_REQUEST_TO_DEVICE:
break;
case USB_REQUEST_TO_INTERFACE:
break;
case USB_REQUEST_TO_ENDPOINT:
break;
default:
break;
}
return usbdRequestNotProcessed;
}
// \brief Callback function called when SETUP PACKET was processed by USB library
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback nor by Custom Class callback)
// \param[in] setup_packet pointer to processed setup packet.
void USBD_CustomClass0_Endpoint0_SetupPacketProcessed (const USB_SETUP_PACKET *setup_packet) {
(void)setup_packet;
switch (setup_packet->bmRequestType.Recipient) {
case USB_REQUEST_TO_DEVICE:
break;
case USB_REQUEST_TO_INTERFACE:
break;
case USB_REQUEST_TO_ENDPOINT:
break;
default:
break;
}
}
// \brief Callback function called when Custom Class 0 received OUT DATA on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] len number of received data bytes.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
// \return usbdRequestNAK: request was processed but the device is busy (return NAK)
usbdRequestStatus USBD_CustomClass0_Endpoint0_OutDataReceived (uint32_t len) {
(void)len;
return usbdRequestNotProcessed;
}
// \brief Callback function called when Custom Class 0 sent IN DATA on Control Endpoint 0
// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed
// previously by Device callback)
// \param[in] len number of sent data bytes.
// \return usbdRequestStatus enumerator value indicating the function execution status
// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library
// \return usbdRequestOK: request was processed successfully (return ACK)
// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0)
// \return usbdRequestNAK: request was processed but the device is busy (return NAK)
usbdRequestStatus USBD_CustomClass0_Endpoint0_InDataSent (uint32_t len) {
(void)len;
return usbdRequestNotProcessed;
}
// \brief Callback function called when DATA was sent or received on Endpoint n
// \param[in] event event on Endpoint:
// - ARM_USBD_EVENT_OUT = data OUT received
// - ARM_USBD_EVENT_IN = data IN sent
void USBD_CustomClass0_Endpoint1_Event (uint32_t event) {
// Handle Endpoint 1 events
uint32_t n;
if (event & ARM_USBD_EVENT_OUT) {
n = USBD_EndpointReadGetResult(0U, USB_ENDPOINT_OUT(1U));
if (n != 0U) {
if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) {
DAP_TransferAbort = 1U;
} else {
USB_RequestIndexI++;
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
USB_RequestIndexI = 0U;
}
USB_RequestCountI++;
osThreadFlagsSet(DAP_ThreadId, 0x01);
}
}
// Start reception of next request packet
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
} else {
USB_RequestIdle = 1U;
}
}
if (event & ARM_USBD_EVENT_IN) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]);
USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
} else {
USB_ResponseIdle = 1U;
}
}
}
void USBD_CustomClass0_Endpoint2_Event (uint32_t event) {
// Handle Endpoint 2 events
if (event & ARM_USBD_EVENT_IN) {
SWO_TransferComplete();
}
}
void USBD_CustomClass0_Endpoint3_Event (uint32_t event) {
// Handle Endpoint 3 events
(void)event;
}
void USBD_CustomClass0_Endpoint4_Event (uint32_t event) {
// Handle Endpoint 4 events
(void)event;
}
void USBD_CustomClass0_Endpoint5_Event (uint32_t event) {
// Handle Endpoint 5 events
(void)event;
}
void USBD_CustomClass0_Endpoint6_Event (uint32_t event) {
// Handle Endpoint 6 events
(void)event;
}
void USBD_CustomClass0_Endpoint7_Event (uint32_t event) {
// Handle Endpoint 7 events
(void)event;
}
void USBD_CustomClass0_Endpoint8_Event (uint32_t event) {
// Handle Endpoint 8 events
(void)event;
}
void USBD_CustomClass0_Endpoint9_Event (uint32_t event) {
// Handle Endpoint 9 events
(void)event;
}
void USBD_CustomClass0_Endpoint10_Event (uint32_t event) {
// Handle Endpoint 10 events
(void)event;
}
void USBD_CustomClass0_Endpoint11_Event (uint32_t event) {
// Handle Endpoint 11 events
(void)event;
}
void USBD_CustomClass0_Endpoint12_Event (uint32_t event) {
// Handle Endpoint 12 events
(void)event;
}
void USBD_CustomClass0_Endpoint13_Event (uint32_t event) {
// Handle Endpoint 13 events
(void)event;
}
void USBD_CustomClass0_Endpoint14_Event (uint32_t event) {
// Handle Endpoint 14 events
(void)event;
}
void USBD_CustomClass0_Endpoint15_Event (uint32_t event) {
// Handle Endpoint 15 events
(void)event;
}
// DAP Thread.
__NO_RETURN void DAP_Thread (void *argument) {
uint32_t flags;
uint32_t n;
(void) argument;
for (;;) {
osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
// Process pending requests
while (USB_RequestCountI != USB_RequestCountO) {
// Handle Queue Commands
n = USB_RequestIndexO;
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
USB_Request[n][0] = ID_DAP_ExecuteCommands;
n++;
if (n == DAP_PACKET_COUNT) {
n = 0U;
}
if (n == USB_RequestIndexI) {
flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
if (flags & 0x80U) {
break;
}
}
}
// Execute DAP Command (process request and prepare response)
USB_RespSize[USB_ResponseIndexI] =
(uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
// Update Request Index and Count
USB_RequestIndexO++;
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
USB_RequestIndexO = 0U;
}
USB_RequestCountO++;
if (USB_RequestIdle) {
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
USB_RequestIdle = 0U;
USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
}
}
// Update Response Index and Count
USB_ResponseIndexI++;
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
USB_ResponseIndexI = 0U;
}
USB_ResponseCountI++;
if (USB_ResponseIdle) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
n = USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
USB_ResponseIdle = 0U;
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[n], USB_RespSize[n]);
}
}
}
}
}
// SWO Data Queue Transfer
// buf: pointer to buffer with data
// num: number of bytes to transfer
void SWO_QueueTransfer (uint8_t *buf, uint32_t num) {
USBD_EndpointWrite(0U, USB_ENDPOINT_IN(2U), buf, num);
}
// SWO Data Abort Transfer
void SWO_AbortTransfer (void) {
USBD_EndpointAbort(0U, USB_ENDPOINT_IN(2U));
}
//! [code_USBD_User_CustomClass]

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2017 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_User_HID_0.c
* Purpose: USB Device Human Interface Device class (HID) User module
* Rev.: V6.2.3
*----------------------------------------------------------------------------*/
/**
* \addtogroup usbd_hidFunctions
*
* USBD_User_HID_0.c implements the application specific functionality of the
* HID class and is used to receive and send data reports to the USB Host.
*
* The implementation must match the configuration file USBD_Config_HID_0.h.
* The following values in USBD_Config_HID_0.h affect the user code:
*
* - 'Endpoint polling Interval' specifies the frequency of requests
* initiated by USB Host for \ref USBD_HIDn_GetReport.
*
* - 'Number of Output Reports' configures the values for \em rid of
* \ref USBD_HIDn_SetReport.
*
* - 'Number of Input Reports' configures the values for \em rid of
* \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
*
* - 'Maximum Input Report Size' specifies the maximum value for:
* - return of \ref USBD_HIDn_GetReport
* - len of \ref USBD_HID_GetReportTrigger.
*
* - 'Maximum Output Report Size' specifies the maximum value for \em len
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
*
* - 'Maximum Feature Report Size' specifies the maximum value for \em len
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
*
*/
//! [code_USBD_User_HID]
#include <stdint.h>
#include <string.h>
#include "cmsis_os2.h"
#define osObjectsExternal
#include "osObjects.h"
#include "rl_usb.h"
#include "RTE\USB\USBD_Config_HID_0.h"
#include "DAP_config.h"
#include "DAP.h"
#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
#error "USB HID0 Output Report Size must match DAP Packet Size"
#endif
#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
#error "USB HID Input Report Size must match DAP Packet Size"
#endif
static volatile uint16_t USB_RequestIndexI; // Request Index In
static volatile uint16_t USB_RequestIndexO; // Request Index Out
static volatile uint16_t USB_RequestCountI; // Request Count In
static volatile uint16_t USB_RequestCountO; // Request Count Out
static volatile uint16_t USB_ResponseIndexI; // Response Index In
static volatile uint16_t USB_ResponseIndexO; // Response Index Out
static volatile uint16_t USB_ResponseCountI; // Response Count In
static volatile uint16_t USB_ResponseCountO; // Response Count Out
static volatile uint8_t USB_ResponseIdle; // Response Idle Flag
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer
// Called during USBD_Initialize to initialize the USB HID class instance.
void USBD_HID0_Initialize (void) {
// Initialize variables
USB_RequestIndexI = 0U;
USB_RequestIndexO = 0U;
USB_RequestCountI = 0U;
USB_RequestCountO = 0U;
USB_ResponseIndexI = 0U;
USB_ResponseIndexO = 0U;
USB_ResponseCountI = 0U;
USB_ResponseCountO = 0U;
USB_ResponseIdle = 1U;
}
// Called during USBD_Uninitialize to de-initialize the USB HID class instance.
void USBD_HID0_Uninitialize (void) {
}
// \brief Prepare HID Report data to send.
// \param[in] rtype report type:
// - HID_REPORT_INPUT = input report requested
// - HID_REPORT_FEATURE = feature report requested
// \param[in] req request type:
// - USBD_HID_REQ_EP_CTRL = control endpoint request
// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request
// \param[in] rid report ID (0 if only one report exists).
// \param[out] buf buffer containing report data to send.
// \return number of report data bytes prepared to send or invalid report requested.
// - value >= 0: number of report data bytes prepared to send
// - value = -1: invalid report requested
int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
(void)rid;
switch (rtype) {
case HID_REPORT_INPUT:
switch (req) {
case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint
case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint
break;
case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained.
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
return ((int32_t)DAP_PACKET_SIZE);
} else {
USB_ResponseIdle = 1U;
}
break;
}
break;
case HID_REPORT_FEATURE:
break;
}
return (0);
}
// \brief Process received HID Report data.
// \param[in] rtype report type:
// - HID_REPORT_OUTPUT = output report received
// - HID_REPORT_FEATURE = feature report received
// \param[in] req request type:
// - USBD_HID_REQ_EP_CTRL = report received on control endpoint
// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint
// \param[in] rid report ID (0 if only one report exists).
// \param[in] buf buffer that receives report data.
// \param[in] len length of received report data.
// \return true received report data processed.
// \return false received report data not processed or request not supported.
bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
(void)req;
(void)rid;
switch (rtype) {
case HID_REPORT_OUTPUT:
if (len == 0) {
break;
}
if (buf[0] == ID_DAP_TransferAbort) {
DAP_TransferAbort = 1U;
break;
}
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
osThreadFlagsSet(DAP_ThreadId, 0x80U);
break; // Discard packet when buffer is full
}
// Store received data into request buffer
memcpy(USB_Request[USB_RequestIndexI], buf, (uint32_t)len);
USB_RequestIndexI++;
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
USB_RequestIndexI = 0U;
}
USB_RequestCountI++;
osThreadFlagsSet(DAP_ThreadId, 0x01U);
break;
case HID_REPORT_FEATURE:
break;
}
return true;
}
// DAP Thread.
__NO_RETURN void DAP_Thread (void *argument) {
uint32_t flags;
uint32_t n;
(void) argument;
for (;;) {
osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
// Process pending requests
while (USB_RequestCountI != USB_RequestCountO) {
// Handle Queue Commands
n = USB_RequestIndexO;
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
USB_Request[n][0] = ID_DAP_ExecuteCommands;
n++;
if (n == DAP_PACKET_COUNT) {
n = 0U;
}
if (n == USB_RequestIndexI) {
flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
if (flags & 0x80U) {
break;
}
}
}
// Execute DAP Command (process request and prepare response)
DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
// Update Request Index and Count
USB_RequestIndexO++;
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
USB_RequestIndexO = 0U;
}
USB_RequestCountO++;
// Update Response Index and Count
USB_ResponseIndexI++;
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
USB_ResponseIndexI = 0U;
}
USB_ResponseCountI++;
if (USB_ResponseIdle) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
n = USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
USB_ResponseIdle = 0U;
USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
}
}
}
}
}
//! [code_USBD_User_HID]

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/*
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 21. May 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Template MDK5
* Title: main.c CMSIS-DAP Main module
*
*---------------------------------------------------------------------------*/
#include "cmsis_os2.h"
#include "osObjects.h"
#include "rl_usb.h"
#include "DAP_config.h"
#include "DAP.h"
// Application Main program
__NO_RETURN void app_main (void *argument) {
(void)argument;
DAP_Setup(); // DAP Setup
USBD_Initialize(0U); // USB Device Initialization
USBD_Connect(0U); // USB Device Connect
while (!USBD_Configured(0U)); // Wait for USB Device to configure
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
LED_RUNNING_OUT(1U); // Turn on Target Running LED
Delayms(500U); // Wait for 500ms
LED_RUNNING_OUT(0U); // Turn off Target Running LED
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
// Create DAP Thread
DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr);
// Create SWO Thread
SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr);
osDelay(osWaitForever);
for (;;) {}
}
int main (void) {
SystemCoreClockUpdate();
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
if (osKernelGetState() == osKernelReady) {
osKernelStart(); // Start thread execution
}
for (;;) {}
}

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 11. June 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Template MDK5
* Title: osObjects.h CMSIS-DAP RTOS2 Objects
*
*---------------------------------------------------------------------------*/
#ifndef __osObjects_h__
#define __osObjects_h__
#include "cmsis_os2.h"
#ifdef osObjectsExternal
extern osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
#else
static const osThreadAttr_t DAP_ThreadAttr = {
.priority = osPriorityNormal
};
static const osThreadAttr_t SWO_ThreadAttr = {
.priority = osPriorityAboveNormal
};
extern osThreadId_t DAP_ThreadId;
osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
osThreadId_t SWO_ThreadId;
#endif
extern void DAP_Thread (void *argument);
extern void SWO_Thread (void *argument);
extern void app_main (void *argument);
#endif /* __osObjects_h__ */

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CMSIS-DAP debug unit validation
-------------------------------
The following debug functionality is tested:
- Execution breakpoint with hit count
- Breakpoint on read
- Breakpoint on write
- Memory read
- Memory write
- Register read
- Register write
- Single stepping
- Run/stop debugging
The test is self-contained and can be executed on the hardware target.
To configure the test for a specific hardware target:
1. Open the µVision project and select device mounted on hardware target
(automatically selects flash algorithm for download).
2. Select CMSIS-DAP as the debugger (if not already selected).
3. Build the project.
To run the test on the hardware target:
1. Connect the CMSIS-DAP debug unit via JTAG/SWD to the hardware target.
2. Connect the CMSIS-DAP debug unit under test to a PC via USB.
3. Open the µVision project and start a debug session.
4. Test results are printed into a `test.log` file.
To run the test on the target in batch mode, open a Command window and execute:
```
C:\> .\test.bat
```
Test results are printed into a `test_results.txt` file.

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;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

68
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/system_ARMCM3.c vendored Normal file
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/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device Series
* @version V5.00
* @date 07. September 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

21
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/_CMSIS_DAP/RTE_Components.h vendored Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'Validation'
* Target: 'CMSIS_DAP'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM3.h"
#endif /* RTE_COMPONENTS_H */

45
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.CMSIS_DAP.cprj vendored Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<cprj schemaVersion="1.0.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
<created timestamp="2021-12-21T16:44:51" tool="uVision V5.36.0.0"/>
<info>
<name>Validation</name>
<description/>
</info>
<packages>
<package name="CMSIS" vendor="ARM"/>
</packages>
<compilers>
<compiler name="AC5" version="5.0.0:5.99.99"/>
</compilers>
<target Ddsp="NO_DSP" Dendian="Little-endian" Dfpu="NO_FPU" Dmve="NO_MVE" Dname="ARMCM3" Dsecure="Non-secure" Dtz="NO_TZ" Dvendor="ARM:82">
<output intdir="./Objects/" name="Validation" outdir="./Objects/" type="exe"/>
<ldflags add="--strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols --info sizes --info totals --info unused --info veneers --entry=Reset_Handler" compiler="AC5" file="./Validation.CMSIS_DAP.sct"/>
<cflags add="--apcs=interwork --c99 --split_sections -O0 -g" compiler="AC5"/>
<asflags add="--apcs=interwork --xref -g" compiler="AC5"/>
<includes/>
<defines/>
</target>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM"/>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM">
<file attr="config" category="sourceAsm" name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0"/>
<file attr="config" category="sourceC" name="Device/ARM/ARMCM3/Source/system_ARMCM3.c" version="1.0.0"/>
</component>
</components>
<files>
<group name="Source Code">
<file category="sourceC" name="./test.c"/>
</group>
<group name="Documentation">
<file category="doc" name="./README.md"/>
</group>
</files>
</cprj>

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248
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvoptx vendored Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>CMSIS_DAP</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>0</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile>.\test.ini</sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\test.ini</tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name>-T0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"" -O206 -S8 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Code</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\test.c</PathWithFileName>
<FilenameWithoutPath>test.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Documentation</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\README.md</PathWithFileName>
<FilenameWithoutPath>README.md</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

449
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvprojx vendored Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>CMSIS_DAP</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM3</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.7.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>Validation</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Code</GroupName>
<Files>
<File>
<FileName>test.c</FileName>
<FileType>1</FileType>
<FilePath>.\test.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Documentation</GroupName>
<Files>
<File>
<FileName>README.md</FileName>
<FileType>5</FileType>
<FilePath>.\README.md</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
<targetInfos>
<targetInfo name="CMSIS_DAP"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
<targetInfos>
<targetInfo name="CMSIS_DAP"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.2" condition="ARMCM3 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
<targetInfos>
<targetInfo name="CMSIS_DAP"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.2" condition="ARMCM3 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
<targetInfos>
<targetInfo name="CMSIS_DAP"/>
</targetInfos>
</file>
</files>
</RTE>
</Project>

50
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.bat vendored Normal file
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@ -0,0 +1,50 @@
@ECHO off
REM Usage: test.bat [PATH TO UV4.exe]
IF "%1"=="" (
SET UV4_EXE=C:\Keil_v5\UV4\UV4.exe
) ELSE (
SET UV4_EXE=%1
)
ECHO Using %UV4_EXE%
ECHO.
ECHO Building application...
IF EXIST .\Objects\Validation.axf del .\Objects\Validation.axf
%UV4_EXE% -b Validation.uvprojx
IF EXIST .\Objects\Validation.axf (
ECHO Build succeded
) ELSE (
ECHO Build failed
GOTO :done
)
ECHO.
ECHO Loading application to hardware target...
%UV4_EXE% -f Validation.uvprojx -t"CMSIS_DAP"
IF ERRORLEVEL 1 (
ECHO Flash download failed
GOTO :done
)
ECHO.
ECHO Debugging hardware target...
IF EXIST .\test_results.txt del .\test_results.txt
%UV4_EXE% -d Validation.uvprojx -t"CMSIS_DAP"
IF EXIST .\test_results.txt (
TYPE .\test_results.txt
) ELSE (
ECHO Test ended abnormally - file test_results.txt was not produced
GOTO :done
)
ECHO.
ECHO All tests completed
:done

89
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.c vendored Normal file
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@ -0,0 +1,89 @@
/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 1. December 2017
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Validation
* Title: test.c CMSIS-DAP debug unit test module
*
*---------------------------------------------------------------------------*/
// Debug Variables
volatile int test_state = 0;
volatile int test_success = 0;
volatile int bpTestCounter = 0;
volatile char mem_rw_success = 0;
int test_array1[256] = {0};
int test_array2[256] = {0};
// Breakpoint Test function
static void BP_Test (void) {
int i;
for (i = 0; i < 10; i++) {
// increment counter so we know on which iteration breakpoint is hit
bpTestCounter++;
test_state++;
}
}
// Test function
static void Test(void) {
int i;
test_state++; // 'test_state' = 11
i = test_success; // 'test_success' read access
test_state++; // 'test_state' = 12
test_success = i; // 'test_success' write access
test_state++; // 'test_state' = 13
// test_array1 should have already been written by debugger
// copy test_array1 into test_array2 for future comparison
mem_rw_success = 1; // assume all values were written correctly
for (i = 0; i < 256; i++) {
if (test_array1[i] != (0x1000+i)) {
mem_rw_success = 0;
}
test_array2[i] = test_array1[i];
}
test_state++; // 'test_state' = 14
test_state++; // 'test_state' = 15
test_state++; // 'test_state' = 16
// execute 'test_state -= 16' from debugger
test_state++; // 'test_state' = 1
if (test_state == 1) {
test_success = 1;
} else {
test_success = 0;
}
}
// 'main' function
int main (void) {
BP_Test();
Test();
for (;;) {};
}

430
external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.ini vendored Normal file
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@ -0,0 +1,430 @@
/******************************************************************************/
/* test.ini: Initialization file to test the debug functionality */
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2012-2017 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user license from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
// ensure logging into file is turned off
LOG OFF
// overall test success flag
define int testSuccess;
testSuccess = 0;
// flags to show which particular tests succeeded
define char bpExecSuccess;
bpExecSuccess = 0;
define char bpReadSuccess;
bpReadSuccess = 0;
define char bpWriteSuccess;
bpWriteSuccess = 0;
define char memReadSuccess;
memReadSuccess = 0;
define char memWriteSuccess;
memWriteSuccess = 0;
define char regReadSuccess;
regReadSuccess = 0;
define char regWriteSuccess;
regWriteSuccess = 0;
// function to read and write registers
FUNC void RegReadWrite(void) {
unsigned long VR0, VR1, VR2, VR3, VR4, VR5, VR6, VR7, VR8, VR9;
unsigned long VR10, VR11, VR12, VR13, VR14, VR15, VxPSR;
unsigned long VR_0, VR_1, VR_2, VR_3, VR_4, VR_5, VR_6, VR_7, VR_8, VR_9;
unsigned long VR_10, VR_11, VR_12, VR_13, VR_14, VR_15, V_xPSR;
unsigned long bogus;
bogus = 0x0badF00D;
printf("Register read started\n");
// initialize temporary variables with bogus value
VR0 = bogus;
VR1 = bogus;
VR2 = bogus;
VR3 = bogus;
VR4 = bogus;
VR5 = bogus;
VR6 = bogus;
VR7 = bogus;
VR8 = bogus;
VR9 = bogus;
VR10 = bogus;
VR11 = bogus;
VR12 = bogus;
VR13 = bogus;
VR14 = bogus;
VR15 = bogus;
VxPSR = bogus;
// read and save current register values
VR0 = R0;
VR1 = R1;
VR2 = R2;
VR3 = R3;
VR4 = R4;
VR5 = R5;
VR6 = R6;
VR7 = R7;
VR8 = R8;
VR9 = R9;
VR10 = R10;
VR11 = R11;
VR12 = R12;
VR13 = R13;
VR14 = R14;
VR15 = R15;
VxPSR = xPSR;
// print read register values
printf("R0 = 0x%x\n", VR0);
printf("R1 = 0x%x\n", VR1);
printf("R2 = 0x%x\n", VR2);
printf("R3 = 0x%x\n", VR3);
printf("R4 = 0x%x\n", VR4);
printf("R5 = 0x%x\n", VR5);
printf("R6 = 0x%x\n", VR6);
printf("R7 = 0x%x\n", VR7);
printf("R8 = 0x%x\n", VR8);
printf("R9 = 0x%x\n", VR9);
printf("R10 = 0x%x\n", VR10);
printf("R11 = 0x%x\n", VR11);
printf("R12 = 0x%x\n", VR12);
printf("R13 = 0x%x\n", VR13);
printf("R14 = 0x%x\n", VR14);
printf("R15 = 0x%x\n", VR15);
printf("xPSR = 0x%x\n", VxPSR);
// check if all values differ from bogus value
regReadSuccess =
(VR0 != bogus) &&
(VR1 != bogus) &&
(VR2 != bogus) &&
(VR3 != bogus) &&
(VR4 != bogus) &&
(VR5 != bogus) &&
(VR6 != bogus) &&
(VR7 != bogus) &&
(VR8 != bogus) &&
(VR9 != bogus) &&
(VR10 != bogus) &&
(VR11 != bogus) &&
(VR12 != bogus) &&
(VR13 != bogus) &&
(VR14 != bogus) &&
(VR15 != bogus) &&
(VxPSR != bogus);
if (regReadSuccess != 0) {
printf("Register read passed\n");
} else {
printf("Register read failed\n");
// there is no reason to test write if read fails
return;
}
printf("Register write started\n");
// fill all registers with bogus value
R0 = bogus;
R1 = bogus;
R2 = bogus;
R3 = bogus;
R4 = bogus;
R5 = bogus;
R6 = bogus;
R7 = bogus;
R8 = bogus;
R9 = bogus;
R10 = bogus;
R11 = bogus;
R12 = bogus;
// register R13-R15 and xPSR on hardware do not accept 0x0badf00d, use 0x0 instead
R13 = 0x0;
R14 = 0x0;
R15 = 0x0;
xPSR = 0x0;
// read back into another array
VR_0 = R0;
VR_1 = R1;
VR_2 = R2;
VR_3 = R3;
VR_4 = R4;
VR_5 = R5;
VR_6 = R6;
VR_7 = R7;
VR_8 = R8;
VR_9 = R9;
VR_10 = R10;
VR_11 = R11;
VR_12 = R12;
VR_13 = R13;
VR_14 = R14;
VR_15 = R15;
V_xPSR = xPSR;
// print the values again
printf("R0 = 0x%x\n", VR_0);
printf("R1 = 0x%x\n", VR_1);
printf("R2 = 0x%x\n", VR_2);
printf("R3 = 0x%x\n", VR_3);
printf("R4 = 0x%x\n", VR_4);
printf("R5 = 0x%x\n", VR_5);
printf("R6 = 0x%x\n", VR_6);
printf("R7 = 0x%x\n", VR_7);
printf("R8 = 0x%x\n", VR_8);
printf("R9 = 0x%x\n", VR_9);
printf("R10 = 0x%x\n", VR_10);
printf("R11 = 0x%x\n", VR_11);
printf("R12 = 0x%x\n", VR_12);
printf("R13 = 0x%x\n", VR_13);
printf("R14 = 0x%x\n", VR_14);
printf("R15 = 0x%x\n", VR_15);
printf("xPSR = 0x%x\n", V_xPSR);
// check if new values are bogus
regWriteSuccess =
(VR_0 == bogus) &&
(VR_1 == bogus) &&
(VR_2 == bogus) &&
(VR_3 == bogus) &&
(VR_4 == bogus) &&
(VR_5 == bogus) &&
(VR_6 == bogus) &&
(VR_7 == bogus) &&
(VR_8 == bogus) &&
(VR_9 == bogus) &&
(VR_10 == bogus) &&
(VR_11 == bogus) &&
(VR_12 == bogus) &&
(VR_13 == 0x0) &&
(VR_14 == 0x0) &&
(VR_15 == 0x0) &&
(V_xPSR == 0x0);
if (regWriteSuccess != 0) {
printf("Register write passed\n");
} else {
printf("Register write failed\n");
}
// write saved values back into registers
// values are required to be written correctly for the rest of the test
R0 = VR0;
R1 = VR1;
R2 = VR2;
R3 = VR3;
R4 = VR4;
R5 = VR5;
R6 = VR6;
R7 = VR7;
R8 = VR8;
R9 = VR9;
R10 = VR10;
R11 = VR11;
R12 = VR12;
R13 = VR13;
R14 = VR14;
R15 = VR15;
xPSR = VxPSR;
}
// function to write predefined numbers into test_array1
FUNC void MemWrite(unsigned long address) {
unsigned int i;
unsigned int val;
printf("Memory write started\n");
val = 0x1000;
for (i = 0; i < 256; i++) {
_WWORD(address, val);
val++;
address += 4;
}
printf("Memory write completed\n");
}
// function to read from test_array2 and check if write and read was successful
FUNC void MemRead(unsigned long address) {
unsigned int i;
unsigned int val, v;
printf("Memory read started\n");
val = 0x1000;
memReadSuccess = 1; // assume it is true
for (i = 0; i < 256; i++) {
v = _RWORD(address);
if (v != val) {
memReadSuccess = 0;
}
val++;
address += 4;
}
if (memReadSuccess != 0) {
printf("Memory read passed\n");
} else {
printf("Memory read failed\n");
}
}
// check execution breakpoint
FUNC void CheckBpExec(unsigned long address) {
// PC should be at address and value of bpTestCounter variable should be 9
if ((R15 == address) && (`bpTestCounter == 9)) {
bpExecSuccess = 1;
}
printf("Execution breakpoint (%d): %d\n", `bpTestCounter, bpExecSuccess);
}
// check breakpoint on read
FUNC void CheckBpRead(int test_state) {
// PC should be at address
if (`test_state == test_state) {
bpReadSuccess = 1;
}
printf("Breakpoint on read: %d\n",bpReadSuccess);
}
// check breakpoint on write
FUNC void CheckBpWrite(int test_state) {
// PC should be at address
if (`test_state == test_state) {
bpWriteSuccess = 1;
}
printf("Breakpoint on write: %d\n", bpWriteSuccess);
}
// evaluate test
FUNC void EvalSuccess(void) {
char success;
success = testSuccess &&
bpExecSuccess && bpReadSuccess && bpWriteSuccess &&
regReadSuccess && regWriteSuccess &&
memReadSuccess && memWriteSuccess;
exec("LOG >.\\test_results.txt");
// print test results to log file
if (success) {
printf("Test passed!\n");
} else {
printf("Test failed!\n");
}
printf("\nIndividual test results:\n");
printf("Execution breakpoint: ");
if (bpExecSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
printf("Breakpoint on read: ");
if (bpReadSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
printf("Breakpoint on write: ");
if (bpWriteSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
printf("Register read: ");
if (regReadSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
printf("Register write: ");
if (regWriteSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
printf("Memory read: ");
if (memReadSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
printf("Memory write: ");
if (memWriteSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
printf("Control flow: ");
if (testSuccess) {
printf("passed\n");
} else {
printf("failed\n");
}
exec("LOG OFF");
}
LOG >.\\test.log // start logging
RegReadWrite(); // check register read/write
BK * // remove all existing breakpoints
BS \test.c\43, 9 // set execution breakpoint (hit count=9)
G // run to break point
CheckBpExec(\test.c\43); // check execution breakpoint
BK * // remove all existing breakpoints
BS READ test_success // set a read access breakpoint
G // run to break point
CheckBpRead(11); // check breakpoint on read
BK * // remove all existing breakpoints
BS WRITE test_success // set a write access breakpoint
G // run to break point
CheckBpWrite(12); // check breakpoint on write
BK * // remove all existing breakpoints
G,\test.c\61 // run until line 61
MemWrite(&test_array1[0]); // test memory write
G,\test.c\69 // run until line 69
memWriteSuccess = `mem_rw_success; // application memory test result
MemRead(&test_array2[0]); // test memory read
T 3 // step 3 times
`test_state -= 16; // modify 'test_state' application variable
G,\test.c\88 // run until line 88
testSuccess = `test_success; // read 'test_success' application variable
LOG OFF // stop logging
EvalSuccess(); // evaluate test results
EXIT // exit debug mode