Initial commit

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_CAN.c

@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2015-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_CAN.h"
+
+#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) // CAN driver version
+
+// Driver Version
+static const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION };
+
+// Driver Capabilities
+static const ARM_CAN_CAPABILITIES can_driver_capabilities = {
+  32U,  // Number of CAN Objects available
+  0U,   // Does not support reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control.
+  0U,   // Does not support CAN with Flexible Data-rate mode (CAN_FD)
+  0U,   // Does not support restricted operation mode
+  0U,   // Does not support bus monitoring mode
+  0U,   // Does not support internal loopback mode
+  0U,   // Does not support external loopback mode
+  0U    // Reserved (must be zero)
+};
+
+// Object Capabilities
+static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities = {
+  1U,   // Object supports transmission
+  1U,   // Object supports reception
+  0U,   // Object does not support RTR reception and automatic Data transmission
+  0U,   // Object does not support RTR transmission and automatic Data reception
+  0U,   // Object does not allow assignment of multiple filters to it
+  0U,   // Object does not support exact identifier filtering
+  0U,   // Object does not support range identifier filtering
+  0U,   // Object does not support mask identifier filtering
+  0U,   // Object can not buffer messages
+  0U    // Reserved (must be zero)
+};
+
+static uint8_t                     can_driver_powered     = 0U;
+static uint8_t                     can_driver_initialized = 0U;
+static ARM_CAN_SignalUnitEvent_t   CAN_SignalUnitEvent    = NULL;
+static ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent  = NULL;
+
+//
+//   Functions
+//
+
+static ARM_DRIVER_VERSION ARM_CAN_GetVersion (void) {
+  // Return driver version
+  return can_driver_version;
+}
+
+static ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void) {
+  // Return driver capabilities
+  return can_driver_capabilities;
+}
+
+static int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                                   ARM_CAN_SignalObjectEvent_t cb_object_event) {
+
+  if (can_driver_initialized != 0U) { return ARM_DRIVER_OK; }
+
+  CAN_SignalUnitEvent   = cb_unit_event;
+  CAN_SignalObjectEvent = cb_object_event;
+
+  // Add code for pin, memory, RTX objects initialization
+  // ..
+
+  can_driver_initialized = 1U;
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_CAN_Uninitialize (void) {
+
+  // Add code for pin, memory, RTX objects de-initialization
+  // ..
+
+  can_driver_initialized = 0U;
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state) {
+  switch (state) {
+    case ARM_POWER_OFF:
+      can_driver_powered = 0U;
+      // Add code to disable interrupts and put peripheral into reset mode,
+      // and if possible disable clock
+      // ..
+
+      break;
+
+    case ARM_POWER_FULL:
+      if (can_driver_initialized == 0U) { return ARM_DRIVER_ERROR; }
+      if (can_driver_powered     != 0U) { return ARM_DRIVER_OK;    }
+
+      // Add code to enable clocks, reset variables enable interrupts
+      // and put peripheral into operational
+      // ..
+
+      can_driver_powered = 1U;
+      break;
+
+    case ARM_POWER_LOW:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static uint32_t ARM_CAN_GetClock (void) {
+
+  // Add code to return peripheral clock frequency
+  // ..
+}
+
+static int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Add code to setup peripheral parameters to generate specified bitrate
+  // with specified bit segments
+  // ..
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (mode) {
+    case ARM_CAN_MODE_INITIALIZATION:
+      // Add code to put peripheral into initialization mode
+      // ..
+      break;
+    case ARM_CAN_MODE_NORMAL:
+      // Add code to put peripheral into normal operation mode
+      // ..
+      break;
+    case ARM_CAN_MODE_RESTRICTED:
+      // Add code to put peripheral into restricted operation mode
+      // ..
+      break;
+    case ARM_CAN_MODE_MONITOR:
+      // Add code to put peripheral into bus monitoring mode
+      // ..
+      break;
+    case ARM_CAN_MODE_LOOPBACK_INTERNAL:
+      // Add code to put peripheral into internal loopback mode
+      // ..
+      break;
+    case ARM_CAN_MODE_LOOPBACK_EXTERNAL:
+      // Add code to put peripheral into external loopback mode
+      // ..
+      break;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx) {
+  // Return object capabilities
+  return can_object_capabilities;
+}
+
+static int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (operation) {
+    case ARM_CAN_FILTER_ID_EXACT_ADD:
+      // Add code to setup peripheral to receive messages with specified exact ID
+      break;
+    case ARM_CAN_FILTER_ID_MASKABLE_ADD:
+      // Add code to setup peripheral to receive messages with specified maskable ID
+      break;
+    case ARM_CAN_FILTER_ID_RANGE_ADD:
+      // Add code to setup peripheral to receive messages within specified range of IDs
+      break;
+    case ARM_CAN_FILTER_ID_EXACT_REMOVE:
+      // Add code to remove specified exact ID from being received by peripheral
+      break;
+    case ARM_CAN_FILTER_ID_MASKABLE_REMOVE:
+      // Add code to remove specified maskable ID from being received by peripheral
+      break;
+    case ARM_CAN_FILTER_ID_RANGE_REMOVE:
+      // Add code to remove specified range of IDs from being received by peripheral
+      break;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (obj_cfg) {
+    case ARM_CAN_OBJ_INACTIVE:
+      // Deactivate object
+      // ..
+      break;
+    case ARM_CAN_OBJ_RX_RTR_TX_DATA:
+      // Setup object to automatically return data when RTR with it's ID is received
+      // ..
+      break;
+    case ARM_CAN_OBJ_TX_RTR_RX_DATA:
+      // Setup object to send RTR and receive data response
+      // ..
+      break;
+    case ARM_CAN_OBJ_TX:
+      // Setup object to be used for sending messages
+      // ..
+      break;
+    case ARM_CAN_OBJ_RX:
+      // Setup object to be used for receiving messages
+      // ..
+      break;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Add code to send requested message
+  // ..
+
+  return ((int32_t)size);
+}
+
+static int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR;  }
+
+  // Add code to read previously received message
+  // (reception was started when object was configured for reception)
+  // ..
+
+  return ((int32_t)size);
+}
+
+static int32_t ARM_CAN_Control (uint32_t control, uint32_t arg) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (control & ARM_CAN_CONTROL_Msk) {
+    case ARM_CAN_ABORT_MESSAGE_SEND:
+      // Add code to abort message pending to be sent
+      // ..
+      break;
+    case ARM_CAN_SET_FD_MODE:
+      // Add code to enable Flexible Data-rate mode
+      // ..
+      break;
+    case ARM_CAN_SET_TRANSCEIVER_DELAY:
+      // Add code to set transceiver delay
+      // ..
+      break;
+    default:
+      // Handle unknown control code
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static ARM_CAN_STATUS ARM_CAN_GetStatus (void) {
+
+  // Add code to return device bus and error status
+  // ..
+}
+
+
+// IRQ handlers
+// Add interrupt routines to handle transmission, reception, error and status interrupts
+// ..
+
+// CAN driver functions structure
+
+extern \
+ARM_DRIVER_CAN Driver_CAN0;
+ARM_DRIVER_CAN Driver_CAN0 = {
+  ARM_CAN_GetVersion,
+  ARM_CAN_GetCapabilities,
+  ARM_CAN_Initialize,
+  ARM_CAN_Uninitialize,
+  ARM_CAN_PowerControl,
+  ARM_CAN_GetClock,
+  ARM_CAN_SetBitrate,
+  ARM_CAN_SetMode,
+  ARM_CAN_ObjectGetCapabilities,
+  ARM_CAN_ObjectSetFilter,
+  ARM_CAN_ObjectConfigure,
+  ARM_CAN_MessageSend,
+  ARM_CAN_MessageRead,
+  ARM_CAN_Control,
+  ARM_CAN_GetStatus
+};
+

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c

@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_ETH_MAC.h"
+
+#define ARM_ETH_MAC_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_ETH_MAC_API_VERSION,
+    ARM_ETH_MAC_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = {
+    0, /* 1 = IPv4 header checksum verified on receive */
+    0, /* 1 = IPv6 checksum verification supported on receive */
+    0, /* 1 = UDP payload checksum verified on receive */
+    0, /* 1 = TCP payload checksum verified on receive */
+    0, /* 1 = ICMP payload checksum verified on receive */
+    0, /* 1 = IPv4 header checksum generated on transmit */
+    0, /* 1 = IPv6 checksum generation supported on transmit */
+    0, /* 1 = UDP payload checksum generated on transmit */
+    0, /* 1 = TCP payload checksum generated on transmit */
+    0, /* 1 = ICMP payload checksum generated on transmit */
+    0, /* Ethernet Media Interface type */
+    0, /* 1 = driver provides initial valid MAC address */
+    0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated */
+    0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated */
+    0, /* 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated */
+    0, /* 1 = Precision Timer supported */
+    0  /* Reserved (must be zero) */
+};
+
+//
+//  Functions
+//
+
+static ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void)
+{
+  return DriverVersion;
+}
+
+static ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void)
+{
+  return DriverCapabilities;
+}
+
+static int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)
+{
+}
+
+static int32_t ARM_ETH_MAC_Uninitialize(void)
+{
+}
+
+static int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)
+{
+}
+
+static int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)
+{
+}
+
+static int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)
+{
+}
+
+static int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags)
+{
+}
+
+static int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len)
+{
+}
+
+static uint32_t ARM_ETH_MAC_GetRxFrameSize(void)
+{
+}
+
+static int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time)
+{
+}
+
+static int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time)
+{
+}
+
+static int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_ETH_MAC_CONFIGURE:
+
+        switch (arg & ARM_ETH_MAC_SPEED_Msk)
+        {
+        case ARM_ETH_MAC_SPEED_10M:
+            break;
+        case ARM_ETH_SPEED_100M:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+
+        switch (arg & ARM_ETH_MAC_DUPLEX_Msk)
+        {
+        case ARM_ETH_MAC_DUPLEX_FULL:
+            break;
+        }
+
+        if (arg & ARM_ETH_MAC_LOOPBACK)
+        {
+        }
+
+        if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) ||
+            (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX))
+        {
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+
+        if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST))
+        {
+        }
+
+        if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST)
+        {
+        }
+
+        if (arg & ARM_ETH_MAC_ADDRESS_ALL)
+        {
+        }
+
+        break;
+
+    case ARM_ETH_MAC_CONTROL_TX:
+        break;
+
+    case ARM_ETH_MAC_CONTROL_RX:
+        break;
+
+    case ARM_ETH_MAC_FLUSH:
+        if (arg & ARM_ETH_MAC_FLUSH_RX)
+        {
+        }
+        if (arg & ARM_ETH_MAC_FLUSH_TX)
+        {
+        }
+        break;
+
+    case ARM_ETH_MAC_SLEEP:
+        break;
+
+    case ARM_ETH_MAC_VLAN_FILTER:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+static int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)
+{
+}
+
+static int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+{
+}
+
+static int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+{
+}
+
+static void ARM_ETH_MAC_SignalEvent(uint32_t event)
+{
+}
+
+// End ETH MAC Interface
+
+extern \
+ARM_DRIVER_ETH_MAC Driver_ETH_MAC0;
+ARM_DRIVER_ETH_MAC Driver_ETH_MAC0 =
+{
+    ARM_ETH_MAC_GetVersion,
+    ARM_ETH_MAC_GetCapabilities,
+    ARM_ETH_MAC_Initialize,
+    ARM_ETH_MAC_Uninitialize,
+    ARM_ETH_MAC_PowerControl,
+    ARM_ETH_MAC_GetMacAddress,
+    ARM_ETH_MAC_SetMacAddress,
+    ARM_ETH_MAC_SetAddressFilter,
+    ARM_ETH_MAC_SendFrame,
+    ARM_ETH_MAC_ReadFrame,
+    ARM_ETH_MAC_GetRxFrameSize,
+    ARM_ETH_MAC_GetRxFrameTime,
+    ARM_ETH_MAC_GetTxFrameTime,
+    ARM_ETH_MAC_ControlTimer,
+    ARM_ETH_MAC_Control,
+    ARM_ETH_MAC_PHY_Read,
+    ARM_ETH_MAC_PHY_Write
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_ETH_PHY.h"
+
+#define ARM_ETH_PHY_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_ETH_PHY_API_VERSION,
+    ARM_ETH_PHY_DRV_VERSION
+};
+
+//
+// Functions
+//
+
+static ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void)
+{
+  return DriverVersion;
+}
+
+static int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)
+{
+}
+
+static int32_t ARM_ETH_PHY_Uninitialize(void)
+{
+}
+
+static int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_ETH_PHY_SetInterface(uint32_t interface)
+{
+    switch (interface)
+    {
+    case ARM_ETH_INTERFACE_MII:
+        break;
+    case ARM_ETH_INTERFACE_RMII:
+        break;
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+static int32_t ARM_ETH_PHY_SetMode(uint32_t mode)
+{
+    switch (mode & ARM_ETH_PHY_SPEED_Msk)
+    {
+    case ARM_ETH_PHY_SPEED_10M:
+        break;
+    case ARM_ETH_PHY_SPEED_100M:
+        break;
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+
+    switch (mode & ARM_ETH_PHY_DUPLEX_Msk)
+    {
+    case ARM_ETH_PHY_DUPLEX_HALF:
+        break;
+    case ARM_ETH_PHY_DUPLEX_FULL:
+        break;
+    }
+
+    if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE)
+    {
+    }
+
+    if (mode & ARM_ETH_PHY_LOOPBACK)
+    {
+    }
+
+    if (mode & ARM_ETH_PHY_ISOLATE)
+    {
+    }
+}
+
+static ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void)
+{
+}
+
+static ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void)
+{
+}
+
+extern \
+ARM_DRIVER_ETH_PHY Driver_ETH_PHY0;
+ARM_DRIVER_ETH_PHY Driver_ETH_PHY0 =
+{
+    ARM_ETH_PHY_GetVersion,
+    ARM_ETH_PHY_Initialize,
+    ARM_ETH_PHY_Uninitialize,
+    ARM_ETH_PHY_PowerControl,
+    ARM_ETH_PHY_SetInterface,
+    ARM_ETH_PHY_SetMode,
+    ARM_ETH_PHY_GetLinkState,
+    ARM_ETH_PHY_GetLinkInfo,
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Flash.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_Flash.h"
+
+#define ARM_FLASH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Sector Information */
+#ifdef FLASH_SECTORS
+static ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = {
+    FLASH_SECTORS
+};
+#else
+#define FLASH_SECTOR_INFO    NULL
+#endif
+
+/* Flash Information */
+static ARM_FLASH_INFO FlashInfo = {
+    0, /* FLASH_SECTOR_INFO  */
+    0, /* FLASH_SECTOR_COUNT */
+    0, /* FLASH_SECTOR_SIZE  */
+    0, /* FLASH_PAGE_SIZE    */
+    0, /* FLASH_PROGRAM_UNIT */
+    0, /* FLASH_ERASED_VALUE */
+  { 0, 0, 0 }  /* Reserved (must be zero) */
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus;
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_FLASH_API_VERSION,
+    ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+    0, /* event_ready */
+    0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+    0, /* erase_chip */
+    0  /* reserved (must be zero) */
+};
+
+//
+// Functions
+//
+
+static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+  return DriverVersion;
+}
+
+static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+  return DriverCapabilities;
+}
+
+static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+}
+
+static int32_t ARM_Flash_Uninitialize(void)
+{
+}
+
+static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+}
+
+static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
+{
+}
+
+static int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+}
+
+static int32_t ARM_Flash_EraseChip(void)
+{
+}
+
+static ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+  return FlashStatus;
+}
+
+static ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
+{
+  return &FlashInfo;
+}
+
+static void ARM_Flash_SignalEvent(uint32_t event)
+{
+}
+
+// End Flash Interface
+
+extern \
+ARM_DRIVER_FLASH Driver_Flash0;
+ARM_DRIVER_FLASH Driver_Flash0 = {
+    ARM_Flash_GetVersion,
+    ARM_Flash_GetCapabilities,
+    ARM_Flash_Initialize,
+    ARM_Flash_Uninitialize,
+    ARM_Flash_PowerControl,
+    ARM_Flash_ReadData,
+    ARM_Flash_ProgramData,
+    ARM_Flash_EraseSector,
+    ARM_Flash_EraseChip,
+    ARM_Flash_GetStatus,
+    ARM_Flash_GetInfo
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_I2C.c

@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_I2C.h"
+
+#define ARM_I2C_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_I2C_API_VERSION,
+    ARM_I2C_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_I2C_CAPABILITIES DriverCapabilities = {
+    0  /* supports 10-bit addressing */
+};
+
+//
+//  Functions
+//
+
+static ARM_DRIVER_VERSION ARM_I2C_GetVersion(void)
+{
+  return DriverVersion;
+}
+
+static ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void)
+{
+  return DriverCapabilities;
+}
+
+static int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event)
+{
+}
+
+static int32_t ARM_I2C_Uninitialize(void)
+{
+}
+
+static int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+}
+
+static int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+}
+
+static int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num)
+{
+}
+
+static int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num)
+{
+}
+
+static int32_t ARM_I2C_GetDataCount(void)
+{
+}
+
+static int32_t ARM_I2C_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_I2C_OWN_ADDRESS:
+        break;
+
+    case ARM_I2C_BUS_SPEED:
+        switch (arg)
+        {
+        case ARM_I2C_BUS_SPEED_STANDARD:
+            break;
+        case ARM_I2C_BUS_SPEED_FAST:
+            break;
+        case ARM_I2C_BUS_SPEED_FAST_PLUS:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_I2C_BUS_CLEAR:
+        break;
+
+    case ARM_I2C_ABORT_TRANSFER:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+static ARM_I2C_STATUS ARM_I2C_GetStatus(void)
+{
+}
+
+static void ARM_I2C_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End I2C Interface
+
+extern \
+ARM_DRIVER_I2C Driver_I2C0;
+ARM_DRIVER_I2C Driver_I2C0 = {
+    ARM_I2C_GetVersion,
+    ARM_I2C_GetCapabilities,
+    ARM_I2C_Initialize,
+    ARM_I2C_Uninitialize,
+    ARM_I2C_PowerControl,
+    ARM_I2C_MasterTransmit,
+    ARM_I2C_MasterReceive,
+    ARM_I2C_SlaveTransmit,
+    ARM_I2C_SlaveReceive,
+    ARM_I2C_GetDataCount,
+    ARM_I2C_Control,
+    ARM_I2C_GetStatus
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_MCI.c

@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_MCI.h"
+
+#define ARM_MCI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_MCI_API_VERSION,
+    ARM_MCI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_MCI_CAPABILITIES DriverCapabilities = {
+    0, /* cd_state          */
+    0, /* cd_event          */
+    0, /* wp_state          */
+    0, /* vdd               */
+    0, /* vdd_1v8           */
+    0, /* vccq              */
+    0, /* vccq_1v8          */
+    0, /* vccq_1v2          */
+    0, /* data_width_4      */
+    0, /* data_width_8      */
+    0, /* data_width_4_ddr  */
+    0, /* data_width_8_ddr  */
+    0, /* high_speed        */
+    0, /* uhs_signaling     */
+    0, /* uhs_tuning        */
+    0, /* uhs_sdr50         */
+    0, /* uhs_sdr104        */
+    0, /* uhs_ddr50         */
+    0, /* uhs_driver_type_a */
+    0, /* uhs_driver_type_c */
+    0, /* uhs_driver_type_d */
+    0, /* sdio_interrupt    */
+    0, /* read_wait         */
+    0, /* suspend_resume    */
+    0, /* mmc_interrupt     */
+    0, /* mmc_boot          */
+    0, /* rst_n             */
+    0, /* ccs               */
+    0, /* ccs_timeout       */
+    0  /* Reserved          */
+};
+
+//
+//   Functions
+//
+
+static ARM_DRIVER_VERSION ARM_MCI_GetVersion(void)
+{
+  return DriverVersion;
+}
+
+static ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void)
+{
+  return DriverCapabilities;
+}
+
+static int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event)
+{
+}
+
+static int32_t ARM_MCI_Uninitialize(void)
+{
+}
+
+static int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_MCI_CardPower(uint32_t voltage)
+{
+    switch (voltage & ARM_MCI_POWER_VDD_Msk)
+    {
+    case ARM_MCI_POWER_VDD_OFF:
+        return ARM_DRIVER_OK;
+
+    case ARM_MCI_POWER_VDD_3V3:
+        return ARM_DRIVER_OK;
+
+    default:
+        break;
+    }
+    return ARM_DRIVER_ERROR;
+}
+
+static int32_t ARM_MCI_ReadCD(void)
+{
+}
+
+static int32_t ARM_MCI_ReadWP(void)
+{
+}
+
+static int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)
+{
+}
+
+static int32_t ARM_MCI_SetupTransfer(uint8_t  *data, uint32_t block_count, uint32_t block_size, uint32_t mode)
+{
+}
+
+static int32_t ARM_MCI_AbortTransfer(void)
+{
+}
+
+static int32_t ARM_MCI_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_MCI_BUS_SPEED:
+        break;
+
+    case ARM_MCI_BUS_SPEED_MODE:
+        break;
+
+    case ARM_MCI_BUS_CMD_MODE:
+        /* Implement external pull-up control to support MMC cards in open-drain mode */
+        /* Default mode is push-pull and is configured in Driver_MCI0.Initialize()    */
+        if (arg == ARM_MCI_BUS_CMD_PUSH_PULL)
+        {
+            /* Configure external circuit to work in push-pull mode */
+        }
+        else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN)
+        {
+            /* Configure external circuit to work in open-drain mode */
+        }
+        else
+        {
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_MCI_BUS_DATA_WIDTH:
+        switch (arg)
+        {
+        case ARM_MCI_BUS_DATA_WIDTH_1:
+            break;
+        case ARM_MCI_BUS_DATA_WIDTH_4:
+            break;
+        case ARM_MCI_BUS_DATA_WIDTH_8:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_MCI_CONTROL_RESET:
+        break;
+
+    case ARM_MCI_CONTROL_CLOCK_IDLE:
+        break;
+
+    case ARM_MCI_DATA_TIMEOUT:
+        break;
+
+    case ARM_MCI_MONITOR_SDIO_INTERRUPT:
+        break;
+
+    case ARM_MCI_CONTROL_READ_WAIT:
+        break;
+
+    case ARM_MCI_DRIVER_STRENGTH:
+    default: return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+static ARM_MCI_STATUS ARM_MCI_GetStatus(void)
+{
+}
+
+static void ARM_MCI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End MCI Interface
+
+extern \
+ARM_DRIVER_MCI Driver_MCI0;
+ARM_DRIVER_MCI Driver_MCI0 = {
+    ARM_MCI_GetVersion,
+    ARM_MCI_GetCapabilities,
+    ARM_MCI_Initialize,
+    ARM_MCI_Uninitialize,
+    ARM_MCI_PowerControl,
+    ARM_MCI_CardPower,
+    ARM_MCI_ReadCD,
+    ARM_MCI_ReadWP,
+    ARM_MCI_SendCommand,
+    ARM_MCI_SetupTransfer,
+    ARM_MCI_AbortTransfer,
+    ARM_MCI_Control,
+    ARM_MCI_GetStatus
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_NAND.c

@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_NAND.h"
+
+#define ARM_NAND_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)   /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+  ARM_NAND_API_VERSION,
+  ARM_NAND_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_NAND_CAPABILITIES DriverCapabilities = {
+  0,                 /* Signal Device Ready event (R/Bn rising edge)                        */
+  0,                 /* Supports re-entrant operation (SendCommand/Address, Read/WriteData) */
+  0,                 /* Supports Sequence operation (ExecuteSequence, AbortSequence)        */
+  0,                 /* Supports VCC Power Supply Control                                   */
+  0,                 /* Supports 1.8 VCC Power Supply                                       */
+  0,                 /* Supports VCCQ I/O Power Supply Control                              */
+  0,                 /* Supports 1.8 VCCQ I/O Power Supply                                  */
+  0,                 /* Supports VPP High Voltage Power Supply Control                      */
+  0,                 /* Supports WPn (Write Protect) Control                                */
+  0,                 /* Number of CEn (Chip Enable) lines: ce_lines + 1                     */
+  0,                 /* Supports manual CEn (Chip Enable) Control                           */
+  0,                 /* Supports R/Bn (Ready/Busy) Monitoring                               */
+  0,                 /* Supports 16-bit data                                                */
+  0,                 /* Supports NV-DDR  Data Interface (ONFI)                              */
+  0,                 /* Supports NV-DDR2 Data Interface (ONFI)                              */
+  0,                 /* Fastest (highest) SDR     Timing Mode supported (ONFI)              */
+  0,                 /* Fastest (highest) NV_DDR  Timing Mode supported (ONFI)              */
+  0,                 /* Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)              */
+  0,                 /* Supports Driver Strength 2.0x = 18 Ohms                             */
+  0,                 /* Supports Driver Strength 1.4x = 25 Ohms                             */
+  0,                 /* Supports Driver Strength 0.7x = 50 Ohms                             */
+#if (ARM_NAND_API_VERSION > 0x201U)
+  0                  /* Reserved (must be zero)                                             */
+#endif
+};
+
+/* Exported functions */
+
+static ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) {
+  return DriverVersion;
+}
+
+static ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) {
+  return DriverCapabilities;
+}
+
+static int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_Uninitialize (void) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) {
+
+  switch ((int32_t)state) {
+    case ARM_POWER_OFF:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_POWER_LOW:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_POWER_FULL:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_NAND_DevicePower (uint32_t voltage) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                         uint32_t addr_col, uint32_t addr_row,
+                                         void *data, uint32_t data_cnt,
+                                         uint8_t *status, uint32_t *count) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_AbortSequence (uint32_t dev_num) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) {
+
+  switch (control) {
+    case ARM_NAND_BUS_MODE:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_NAND_BUS_DATA_WIDTH:
+      return ARM_DRIVER_ERROR_UNSUPPORTED; 
+
+    case ARM_NAND_DEVICE_READY_EVENT:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_ERROR;
+}
+
+static ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) {
+  ARM_NAND_STATUS stat;
+
+  stat.busy      = 0U;
+  stat.ecc_error = 0U;
+
+  return stat;
+}
+
+static int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+/* NAND Driver Control Block */
+extern \
+ARM_DRIVER_NAND Driver_NAND0;
+ARM_DRIVER_NAND Driver_NAND0 = {
+  ARM_NAND_GetVersion,
+  ARM_NAND_GetCapabilities,
+  ARM_NAND_Initialize,
+  ARM_NAND_Uninitialize,
+  ARM_NAND_PowerControl,
+  ARM_NAND_DevicePower,
+  ARM_NAND_WriteProtect,
+  ARM_NAND_ChipEnable,
+  ARM_NAND_GetDeviceBusy,
+  ARM_NAND_SendCommand,
+  ARM_NAND_SendAddress,
+  ARM_NAND_ReadData,
+  ARM_NAND_WriteData,
+  ARM_NAND_ExecuteSequence,
+  ARM_NAND_AbortSequence,
+  ARM_NAND_Control,
+  ARM_NAND_GetStatus,
+  ARM_NAND_InquireECC
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SAI.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_SAI.h"
+
+#define ARM_SAI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_SAI_API_VERSION,
+    ARM_SAI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_SAI_CAPABILITIES DriverCapabilities = {
+    1, /* supports asynchronous Transmit/Receive */
+    0, /* supports synchronous Transmit/Receive */
+    0, /* supports user defined Protocol */
+    1, /* supports I2S Protocol */
+    0, /* supports MSB/LSB justified Protocol */
+    0, /* supports PCM short/long frame Protocol */
+    0, /* supports AC'97 Protocol */
+    0, /* supports Mono mode */
+    0, /* supports Companding */
+    0, /* supports MCLK (Master Clock) pin */
+    0, /* supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR */
+    0  /* reserved (must be zero) */
+};
+
+//
+//  Functions
+//
+
+static ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
+{
+  return DriverVersion;
+}
+
+static ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
+{
+  return DriverCapabilities;
+}
+
+static int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
+{
+}
+
+static int32_t ARM_SAI_Uninitialize (void)
+{
+}
+
+static int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_SAI_Send (const void *data, uint32_t num)
+{
+}
+
+static int32_t ARM_SAI_Receive (void *data, uint32_t num)
+{
+}
+
+static uint32_t ARM_SAI_GetTxCount (void)
+{
+}
+
+static uint32_t ARM_SAI_GetRxCount (void)
+{
+}
+
+static int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
+{
+}
+
+static ARM_SAI_STATUS ARM_SAI_GetStatus (void)
+{
+}
+
+static void ARM_SAI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End SAI Interface
+
+extern \
+ARM_DRIVER_SAI Driver_SAI0;
+ARM_DRIVER_SAI Driver_SAI0 = {
+    ARM_SAI_GetVersion,
+    ARM_SAI_GetCapabilities,
+    ARM_SAI_Initialize,
+    ARM_SAI_Uninitialize,
+    ARM_SAI_PowerControl,
+    ARM_SAI_Send,
+    ARM_SAI_Receive,
+    ARM_SAI_GetTxCount,
+    ARM_SAI_GetRxCount,
+    ARM_SAI_Control,
+    ARM_SAI_GetStatus
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SPI.c

@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_SPI.h"
+
+#define ARM_SPI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_SPI_API_VERSION,
+    ARM_SPI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_SPI_CAPABILITIES DriverCapabilities = {
+    0, /* Reserved (must be zero) */
+    0, /* TI Synchronous Serial Interface */
+    0, /* Microwire Interface */
+    0, /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
+    0  /* Reserved (must be zero) */
+};
+
+//
+//  Functions
+//
+
+static ARM_DRIVER_VERSION ARM_SPI_GetVersion(void)
+{
+  return DriverVersion;
+}
+
+static ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities(void)
+{
+  return DriverCapabilities;
+}
+
+static int32_t ARM_SPI_Initialize(ARM_SPI_SignalEvent_t cb_event)
+{
+}
+
+static int32_t ARM_SPI_Uninitialize(void)
+{
+}
+
+static int32_t ARM_SPI_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_SPI_Send(const void *data, uint32_t num)
+{
+}
+
+static int32_t ARM_SPI_Receive(void *data, uint32_t num)
+{
+}
+
+static int32_t ARM_SPI_Transfer(const void *data_out, void *data_in, uint32_t num)
+{
+}
+
+static uint32_t ARM_SPI_GetDataCount(void)
+{
+}
+
+static int32_t ARM_SPI_Control(uint32_t control, uint32_t arg)
+{
+    switch (control & ARM_SPI_CONTROL_Msk)
+    {
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_SPI_MODE_INACTIVE:             // SPI Inactive
+        return ARM_DRIVER_OK;
+
+    case ARM_SPI_MODE_MASTER:               // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+        break;
+
+    case ARM_SPI_MODE_SLAVE:                // SPI Slave  (Output on MISO, Input on MOSI)
+        break;
+
+    case ARM_SPI_SET_BUS_SPEED:             // Set Bus Speed in bps; arg = value
+        break;
+
+    case ARM_SPI_GET_BUS_SPEED:             // Get Bus Speed in bps
+        break;
+
+    case ARM_SPI_SET_DEFAULT_TX_VALUE:      // Set default Transmit value; arg = value
+        break;
+
+    case ARM_SPI_CONTROL_SS:                // Control Slave Select; arg = 0:inactive, 1:active
+        break;
+
+    case ARM_SPI_ABORT_TRANSFER:            // Abort current data transfer
+        break;
+    }
+}
+
+static ARM_SPI_STATUS ARM_SPI_GetStatus(void)
+{
+}
+
+static void ARM_SPI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End SPI Interface
+
+extern \
+ARM_DRIVER_SPI Driver_SPI0;
+ARM_DRIVER_SPI Driver_SPI0 = {
+    ARM_SPI_GetVersion,
+    ARM_SPI_GetCapabilities,
+    ARM_SPI_Initialize,
+    ARM_SPI_Uninitialize,
+    ARM_SPI_PowerControl,
+    ARM_SPI_Send,
+    ARM_SPI_Receive,
+    ARM_SPI_Transfer,
+    ARM_SPI_GetDataCount,
+    ARM_SPI_Control,
+    ARM_SPI_GetStatus
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Storage.c

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "Driver_Storage.h"
+
+#define ARM_STORAGE_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_STORAGE_API_VERSION,
+    ARM_STORAGE_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_STORAGE_CAPABILITIES DriverCapabilities = {
+    0,  /* Asynchronous Mode */
+    0,  /* Supports EraseAll operation */
+    0   /* Reserved */
+};
+
+
+//
+// Functions
+//
+
+static ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)  {
+  return DriverVersion;
+}
+
+static ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)  {
+  return DriverCapabilities;
+}
+
+static int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)  {
+}
+
+static int32_t ARM_Storage_Uninitialize (void)  {
+}
+
+static int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)  {
+}
+
+static int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)  {
+}
+
+static int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)  {
+}
+
+static int32_t ARM_Storage_EraseAll (void)  {
+}
+
+static ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)  {
+}
+
+static int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)  {
+}
+
+static uint32_t ARM_Storage_ResolveAddress(uint64_t addr) {
+}
+
+static int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block) {
+}
+
+static int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block) {
+}
+
+// End Storage Interface
+
+extern \
+ARM_DRIVER_STORAGE Driver_Storage0;
+ARM_DRIVER_STORAGE Driver_Storage0 = {
+    ARM_Storage_GetVersion,
+    ARM_Storage_GetCapabilities,
+    ARM_Storage_Initialize,
+    ARM_Storage_Uninitialize,
+    ARM_Storage_PowerControl,
+    ARM_Storage_ReadData,
+    ARM_Storage_ProgramData,
+    ARM_Storage_Erase,
+    ARM_Storage_EraseAll,
+    ARM_Storage_GetStatus,
+    ARM_Storage_GetInfo,
+    ARM_Storage_ResolveAddress,
+    ARM_Storage_GetNextBlock,
+    ARM_Storage_GetBlock
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USART.c

@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_USART.h"
+
+#define ARM_USART_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)  /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = { 
+    ARM_USART_API_VERSION,
+    ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+    1, /* supports UART (Asynchronous) mode */
+    0, /* supports Synchronous Master mode */
+    0, /* supports Synchronous Slave mode */
+    0, /* supports UART Single-wire mode */
+    0, /* supports UART IrDA mode */
+    0, /* supports UART Smart Card mode */
+    0, /* Smart Card Clock generator available */
+    0, /* RTS Flow Control available */
+    0, /* CTS Flow Control available */
+    0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */
+    0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */
+    0, /* RTS Line: 0=not available, 1=available */
+    0, /* CTS Line: 0=not available, 1=available */
+    0, /* DTR Line: 0=not available, 1=available */
+    0, /* DSR Line: 0=not available, 1=available */
+    0, /* DCD Line: 0=not available, 1=available */
+    0, /* RI Line: 0=not available, 1=available */
+    0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */
+    0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */
+    0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */
+    0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */
+    0  /* Reserved (must be zero) */
+};
+
+//
+//   Functions
+//
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+  return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+  return DriverCapabilities;
+}
+
+static int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+}
+
+static int32_t ARM_USART_Uninitialize(void)
+{
+}
+
+static int32_t ARM_USART_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART_Send(const void *data, uint32_t num)
+{
+}
+
+static int32_t ARM_USART_Receive(void *data, uint32_t num)
+{
+}
+
+static int32_t ARM_USART_Transfer(const void *data_out, void *data_in, uint32_t num)
+{
+}
+
+static uint32_t ARM_USART_GetTxCount(void)
+{
+}
+
+static uint32_t ARM_USART_GetRxCount(void)
+{
+}
+
+static int32_t ARM_USART_Control(uint32_t control, uint32_t arg)
+{
+}
+
+static ARM_USART_STATUS ARM_USART_GetStatus(void)
+{
+}
+
+static int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void)
+{
+}
+
+static void ARM_USART_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End USART Interface
+
+extern \
+ARM_DRIVER_USART Driver_USART0;
+ARM_DRIVER_USART Driver_USART0 = {
+    ARM_USART_GetVersion,
+    ARM_USART_GetCapabilities,
+    ARM_USART_Initialize,
+    ARM_USART_Uninitialize,
+    ARM_USART_PowerControl,
+    ARM_USART_Send,
+    ARM_USART_Receive,
+    ARM_USART_Transfer,
+    ARM_USART_GetTxCount,
+    ARM_USART_GetRxCount,
+    ARM_USART_Control,
+    ARM_USART_GetStatus,
+    ARM_USART_SetModemControl,
+    ARM_USART_GetModemStatus
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBD.c

@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_USBD.h"
+
+#define ARM_USBD_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION usbd_driver_version = { 
+    ARM_USBD_API_VERSION,
+    ARM_USBD_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
+    0, /* vbus_detection */
+    0, /* event_vbus_on */
+    0, /* event_vbus_off */
+    0  /* reserved */
+};
+
+//
+// Functions
+//
+
+static ARM_DRIVER_VERSION ARM_USBD_GetVersion(void)
+{
+  return usbd_driver_version;
+}
+
+static ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities(void)
+{
+  return usbd_driver_capabilities;
+}
+
+static int32_t ARM_USBD_Initialize(ARM_USBD_SignalDeviceEvent_t cb_device_event,
+                                   ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+{
+}
+
+static int32_t ARM_USBD_Uninitialize(void)
+{
+}
+
+static int32_t ARM_USBD_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USBD_DeviceConnect(void)
+{
+}
+
+static int32_t ARM_USBD_DeviceDisconnect(void)
+{
+}
+
+static ARM_USBD_STATE ARM_USBD_DeviceGetState(void)
+{
+}
+
+static int32_t ARM_USBD_DeviceRemoteWakeup(void)
+{
+}
+
+static int32_t ARM_USBD_DeviceSetAddress(uint8_t dev_addr)
+{
+}
+
+static int32_t ARM_USBD_ReadSetupPacket(uint8_t *setup)
+{
+}
+
+static int32_t ARM_USBD_EndpointConfigure(uint8_t  ep_addr,
+                                          uint8_t  ep_type,
+                                          uint16_t ep_max_packet_size)
+{
+}
+
+static int32_t ARM_USBD_EndpointUnconfigure(uint8_t ep_addr)
+{
+}
+
+static int32_t ARM_USBD_EndpointStall(uint8_t ep_addr, bool stall)
+{
+}
+
+static int32_t ARM_USBD_EndpointTransfer(uint8_t ep_addr, uint8_t *data, uint32_t num)
+{
+}
+
+static uint32_t ARM_USBD_EndpointTransferGetResult(uint8_t ep_addr)
+{
+}
+
+static int32_t ARM_USBD_EndpointTransferAbort(uint8_t ep_addr)
+{
+}
+
+static uint16_t ARM_USBD_GetFrameNumber(void)
+{
+}
+
+static void ARM_USBD_SignalDeviceEvent(uint32_t event)
+{
+    // function body
+}
+
+static void ARM_USBD_SignalEndpointEvent(uint8_t ep_addr, uint32_t ep_event)
+{
+    // function body
+}
+
+// End USBD Interface
+
+extern \
+ARM_DRIVER_USBD Driver_USBD0;
+ARM_DRIVER_USBD Driver_USBD0 =
+{
+    ARM_USBD_GetVersion,
+    ARM_USBD_GetCapabilities,
+    ARM_USBD_Initialize,
+    ARM_USBD_Uninitialize,
+    ARM_USBD_PowerControl,
+    ARM_USBD_DeviceConnect,
+    ARM_USBD_DeviceDisconnect,
+    ARM_USBD_DeviceGetState,
+    ARM_USBD_DeviceRemoteWakeup,
+    ARM_USBD_DeviceSetAddress,
+    ARM_USBD_ReadSetupPacket,
+    ARM_USBD_EndpointConfigure,
+    ARM_USBD_EndpointUnconfigure,
+    ARM_USBD_EndpointStall,
+    ARM_USBD_EndpointTransfer,
+    ARM_USBD_EndpointTransferGetResult,
+    ARM_USBD_EndpointTransferAbort,
+    ARM_USBD_GetFrameNumber
+};

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBH.c

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_USBH.h"
+
+/* USB Host Driver */
+
+#define ARM_USBH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION usbh_driver_version = { 
+    ARM_USBH_API_VERSION,
+    ARM_USBH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USBH_CAPABILITIES usbd_driver_capabilities = {
+    0x0001, /* Root HUB available Ports Mask   */
+    0,      /* Automatic SPLIT packet handling */
+    0,      /* Signal Connect event */
+    0,      /* Signal Disconnect event */
+    0,      /* Signal Overcurrent event */
+    0       /* Reserved (must be zero) */
+};
+
+//
+// Functions
+//
+
+static ARM_DRIVER_VERSION ARM_USBH_GetVersion(void)
+{
+  return usbh_driver_version;
+}
+
+static ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities(void)
+{
+  return usbd_driver_capabilities;
+}
+
+static int32_t ARM_USBH_Initialize(ARM_USBH_SignalPortEvent_t cb_port_event,
+                                   ARM_USBH_SignalPipeEvent_t cb_pipe_event)
+{
+}
+
+static int32_t ARM_USBH_Uninitialize(void)
+{
+}
+
+static int32_t ARM_USBH_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USBH_PortVbusOnOff(uint8_t port, bool vbus)
+{
+}
+
+static int32_t ARM_USBH_PortReset(uint8_t port)
+{
+}
+
+static int32_t ARM_USBH_PortSuspend(uint8_t port)
+{
+}
+
+static int32_t ARM_USBH_PortResume(uint8_t port)
+{
+}
+
+static ARM_USBH_PORT_STATE ARM_USBH_PortGetState(uint8_t port)
+{
+}
+
+static ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate(uint8_t  dev_addr,
+                                                uint8_t  dev_speed,
+                                                uint8_t  hub_addr,
+                                                uint8_t  hub_port,
+                                                uint8_t  ep_addr,
+                                                uint8_t  ep_type,
+                                                uint16_t ep_max_packet_size,
+                                                uint8_t  ep_interval)
+{
+}
+
+static int32_t ARM_USBH_PipeModify(ARM_USBH_PIPE_HANDLE pipe_hndl,
+                            uint8_t  dev_addr,
+                            uint8_t  dev_speed,
+                            uint8_t  hub_addr,
+                            uint8_t  hub_port,
+                            uint16_t ep_max_packet_size)
+{
+}
+
+static int32_t ARM_USBH_PipeDelete(ARM_USBH_PIPE_HANDLE pipe_hndl)
+{
+}
+
+static int32_t ARM_USBH_PipeReset(ARM_USBH_PIPE_HANDLE pipe_hndl)
+{
+}
+
+static int32_t ARM_USBH_PipeTransfer(ARM_USBH_PIPE_HANDLE pipe_hndl,
+                              uint32_t packet,
+                              uint8_t *data,
+                              uint32_t num)
+{
+}
+
+static uint32_t ARM_USBH_PipeTransferGetResult(ARM_USBH_PIPE_HANDLE pipe_hndl)
+{
+}
+
+static int32_t ARM_USBH_PipeTransferAbort(ARM_USBH_PIPE_HANDLE pipe_hndl)
+{
+}
+
+static uint16_t ARM_USBH_GetFrameNumber(void)
+{
+}
+
+static void ARM_USBH_SignalPortEvent(uint8_t port, uint32_t event)
+{
+    // function body
+}
+
+static void ARM_USBH_SignalPipeEvent(ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)
+{
+    // function body
+}
+
+// End USBH Interface
+
+extern \
+ARM_DRIVER_USBH Driver_USBH0;
+ARM_DRIVER_USBH Driver_USBH0 = {
+  ARM_USBH_GetVersion,
+  ARM_USBH_GetCapabilities,
+  ARM_USBH_Initialize,
+  ARM_USBH_Uninitialize,
+  ARM_USBH_PowerControl,
+  ARM_USBH_PortVbusOnOff,
+  ARM_USBH_PortReset,
+  ARM_USBH_PortSuspend,
+  ARM_USBH_PortResume,
+  ARM_USBH_PortGetState,
+  ARM_USBH_PipeCreate,
+  ARM_USBH_PipeModify,
+  ARM_USBH_PipeDelete,
+  ARM_USBH_PipeReset,
+  ARM_USBH_PipeTransfer,
+  ARM_USBH_PipeTransferGetResult,
+  ARM_USBH_PipeTransferAbort,
+  ARM_USBH_GetFrameNumber
+};
+

external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_WiFi.c

@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_WiFi.h"
+
+#define ARM_WIFI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)        // Driver version
+
+// Driver Version
+static const ARM_DRIVER_VERSION driver_version = {
+  ARM_WIFI_API_VERSION,
+  ARM_WIFI_DRV_VERSION 
+};
+
+// Driver Capabilities
+static const ARM_WIFI_CAPABILITIES driver_capabilities = { 
+  0U,                                   // Station supported
+  0U,                                   // Access Point supported
+  0U,                                   // Concurrent Station and Access Point not supported
+  0U,                                   // WiFi Protected Setup (WPS) for Station supported
+  0U,                                   // WiFi Protected Setup (WPS) for Access Point not supported
+  0U,                                   // Access Point: event generated on Station connect
+  0U,                                   // Access Point: event not generated on Station disconnect
+  0U,                                   // Event not generated on Ethernet frame reception in bypass mode
+  0U,                                   // Bypass or pass-through mode (Ethernet interface) not supported
+  0U,                                   // IP (UDP/TCP) (Socket interface) supported
+  0U,                                   // IPv6 (Socket interface) not supported
+  0U,                                   // Ping (ICMP) supported
+  0U                                    // Reserved (must be zero)
+};
+static ARM_DRIVER_VERSION ARM_WiFi_GetVersion (void) {
+  return driver_version;
+}
+
+static ARM_WIFI_CAPABILITIES ARM_WiFi_GetCapabilities (void) { 
+  return driver_capabilities;
+}
+
+static int32_t ARM_WiFi_Initialize (ARM_WIFI_SignalEvent_t cb_event) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_Uninitialize (void) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_PowerControl (ARM_POWER_STATE state) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_GetModuleInfo (char *module_info, uint32_t max_len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+static int32_t ARM_WiFi_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_Deactivate (uint32_t interface) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_WiFi_IsConnected (void) {
+  return 0U;
+}
+
+static int32_t ARM_WiFi_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_BypassControl (uint32_t interface, uint32_t mode) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len){
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len){
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_WiFi_EthGetRxFrameSize (uint32_t interface){
+  return 0U;
+}
+
+static int32_t ARM_WiFi_SocketCreate (int32_t af, int32_t type, int32_t protocol) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketListen (int32_t socket, int32_t backlog) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketRecv (int32_t socket, void *buf, uint32_t len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketSend (int32_t socket, const void *buf, uint32_t len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketClose (int32_t socket) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_WiFi_Ping (const uint8_t *ip, uint32_t ip_len) {
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+/* WiFi Driver Control Block */
+extern \
+ARM_DRIVER_WIFI Driver_WiFi0;
+ARM_DRIVER_WIFI Driver_WiFi0 = { 
+  ARM_WiFi_GetVersion,
+  ARM_WiFi_GetCapabilities,
+  ARM_WiFi_Initialize,
+  ARM_WiFi_Uninitialize,
+  ARM_WiFi_PowerControl,
+  ARM_WiFi_GetModuleInfo,
+  ARM_WiFi_SetOption,
+  ARM_WiFi_GetOption,
+  ARM_WiFi_Scan,
+  ARM_WiFi_Activate,
+  ARM_WiFi_Deactivate,
+  ARM_WiFi_IsConnected,
+  ARM_WiFi_GetNetInfo,
+  ARM_WiFi_BypassControl,
+  ARM_WiFi_EthSendFrame,
+  ARM_WiFi_EthReadFrame,
+  ARM_WiFi_EthGetRxFrameSize,
+  ARM_WiFi_SocketCreate,
+  ARM_WiFi_SocketBind,
+  ARM_WiFi_SocketListen,
+  ARM_WiFi_SocketAccept,
+  ARM_WiFi_SocketConnect,
+  ARM_WiFi_SocketRecv,
+  ARM_WiFi_SocketRecvFrom,
+  ARM_WiFi_SocketSend,
+  ARM_WiFi_SocketSendTo,
+  ARM_WiFi_SocketGetSockName,
+  ARM_WiFi_SocketGetPeerName,
+  ARM_WiFi_SocketGetOpt,
+  ARM_WiFi_SocketSetOpt,
+  ARM_WiFi_SocketClose,
+  ARM_WiFi_SocketGetHostByName,
+  ARM_WiFi_Ping
+};

external/CMSIS_5/CMSIS/Driver/Include/Driver_CAN.h

@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2015-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V1.3
+ *
+ * Project:      CAN (Controller Area Network) Driver definitions
+ */
+
+/* History:
+ *  Version 1.3
+ *    Removed volatile from ARM_CAN_STATUS
+ *  Version 1.2
+ *    Added ARM_CAN_UNIT_STATE_BUS_OFF unit state and
+ *    ARM_CAN_EVENT_UNIT_INACTIVE unit event
+ *  Version 1.1
+ *    ARM_CAN_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_CAN_H_
+#define DRIVER_CAN_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,3)  /* API version */
+
+
+#define _ARM_Driver_CAN_(n)      Driver_CAN##n
+#define  ARM_Driver_CAN_(n) _ARM_Driver_CAN_(n)
+
+
+/****** CAN Bitrate selection codes *****/
+typedef enum _ARM_CAN_BITRATE_SELECT {
+  ARM_CAN_BITRATE_NOMINAL,              ///< Select nominal (flexible data-rate arbitration) bitrate
+  ARM_CAN_BITRATE_FD_DATA               ///< Select flexible data-rate data bitrate
+} ARM_CAN_BITRATE_SELECT;
+
+/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/
+#define ARM_CAN_BIT_PROP_SEG_Pos        0UL       ///< bits 7..0
+#define ARM_CAN_BIT_PROP_SEG_Msk       (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)
+#define ARM_CAN_BIT_PROP_SEG(x)      (((x)     << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk)
+
+/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG1_Pos      8UL       ///< bits 15..8
+#define ARM_CAN_BIT_PHASE_SEG1_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)
+#define ARM_CAN_BIT_PHASE_SEG1(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk)
+
+/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG2_Pos      16UL      ///< bits 23..16
+#define ARM_CAN_BIT_PHASE_SEG2_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)
+#define ARM_CAN_BIT_PHASE_SEG2(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk)
+
+/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/
+#define ARM_CAN_BIT_SJW_Pos             24UL      ///< bits 28..24
+#define ARM_CAN_BIT_SJW_Msk            (0x1FUL << ARM_CAN_BIT_SJW_Pos)
+#define ARM_CAN_BIT_SJW(x)           (((x)     << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk)
+
+/****** CAN Mode codes *****/
+typedef enum _ARM_CAN_MODE {
+  ARM_CAN_MODE_INITIALIZATION,          ///< Initialization mode
+  ARM_CAN_MODE_NORMAL,                  ///< Normal operation mode
+  ARM_CAN_MODE_RESTRICTED,              ///< Restricted operation mode
+  ARM_CAN_MODE_MONITOR,                 ///< Bus monitoring mode
+  ARM_CAN_MODE_LOOPBACK_INTERNAL,       ///< Loopback internal mode
+  ARM_CAN_MODE_LOOPBACK_EXTERNAL        ///< Loopback external mode
+} ARM_CAN_MODE;
+
+/****** CAN Filter Operation codes *****/
+typedef enum _ARM_CAN_FILTER_OPERATION {
+  ARM_CAN_FILTER_ID_EXACT_ADD,          ///< Add    exact id filter
+  ARM_CAN_FILTER_ID_EXACT_REMOVE,       ///< Remove exact id filter
+  ARM_CAN_FILTER_ID_RANGE_ADD,          ///< Add    range id filter
+  ARM_CAN_FILTER_ID_RANGE_REMOVE,       ///< Remove range id filter
+  ARM_CAN_FILTER_ID_MASKABLE_ADD,       ///< Add    maskable id filter
+  ARM_CAN_FILTER_ID_MASKABLE_REMOVE     ///< Remove maskable id filter
+} ARM_CAN_FILTER_OPERATION;
+
+/****** CAN Object Configuration codes *****/
+typedef enum _ARM_CAN_OBJ_CONFIG {
+  ARM_CAN_OBJ_INACTIVE,                 ///< CAN object inactive
+  ARM_CAN_OBJ_TX,                       ///< CAN transmit object
+  ARM_CAN_OBJ_RX,                       ///< CAN receive object
+  ARM_CAN_OBJ_RX_RTR_TX_DATA,           ///< CAN object that on RTR reception automatically transmits Data Frame
+  ARM_CAN_OBJ_TX_RTR_RX_DATA            ///< CAN object that transmits RTR and automatically receives Data Frame
+} ARM_CAN_OBJ_CONFIG;
+
+/**
+\brief CAN Object Capabilities
+*/
+typedef struct _ARM_CAN_OBJ_CAPABILITIES {
+  uint32_t tx               : 1;        ///< Object supports transmission
+  uint32_t rx               : 1;        ///< Object supports reception
+  uint32_t rx_rtr_tx_data   : 1;        ///< Object supports RTR reception and automatic Data Frame transmission
+  uint32_t tx_rtr_rx_data   : 1;        ///< Object supports RTR transmission and automatic Data Frame reception
+  uint32_t multiple_filters : 1;        ///< Object allows assignment of multiple filters to it
+  uint32_t exact_filtering  : 1;        ///< Object supports exact identifier filtering
+  uint32_t range_filtering  : 1;        ///< Object supports range identifier filtering
+  uint32_t mask_filtering   : 1;        ///< Object supports mask identifier filtering
+  uint32_t message_depth    : 8;        ///< Number of messages buffers (FIFO) for that object
+  uint32_t reserved         : 16;       ///< Reserved (must be zero)
+} ARM_CAN_OBJ_CAPABILITIES;
+
+/****** CAN Control Function Operation codes *****/
+#define ARM_CAN_CONTROL_Pos             0UL
+#define ARM_CAN_CONTROL_Msk            (0xFFUL << ARM_CAN_CONTROL_Pos)
+#define ARM_CAN_SET_FD_MODE            (1UL    << ARM_CAN_CONTROL_Pos)          ///< Set FD operation mode;                   arg: 0 = disable, 1 = enable
+#define ARM_CAN_ABORT_MESSAGE_SEND     (2UL    << ARM_CAN_CONTROL_Pos)          ///< Abort sending of CAN message;            arg = object
+#define ARM_CAN_CONTROL_RETRANSMISSION (3UL    << ARM_CAN_CONTROL_Pos)          ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state)
+#define ARM_CAN_SET_TRANSCEIVER_DELAY  (4UL    << ARM_CAN_CONTROL_Pos)          ///< Set transceiver delay;                   arg = delay in time quanta
+
+/****** CAN ID Frame Format codes *****/
+#define ARM_CAN_ID_IDE_Pos              31UL
+#define ARM_CAN_ID_IDE_Msk             (1UL    << ARM_CAN_ID_IDE_Pos)
+
+/****** CAN Identifier encoding *****/
+#define ARM_CAN_STANDARD_ID(id)        (id & 0x000007FFUL)                      ///< CAN identifier in standard format (11-bits)
+#define ARM_CAN_EXTENDED_ID(id)       ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits)
+
+/**
+\brief CAN Message Information
+*/
+typedef struct _ARM_CAN_MSG_INFO {
+  uint32_t id;                          ///< CAN identifier with frame format specifier (bit 31)
+  uint32_t rtr              : 1;        ///< Remote transmission request frame
+  uint32_t edl              : 1;        ///< Flexible data-rate format extended data length
+  uint32_t brs              : 1;        ///< Flexible data-rate format with bitrate switch 
+  uint32_t esi              : 1;        ///< Flexible data-rate format error state indicator
+  uint32_t dlc              : 4;        ///< Data length code
+  uint32_t reserved         : 24;
+} ARM_CAN_MSG_INFO;
+
+/****** CAN specific error code *****/
+#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1)          ///< Bitrate selection not supported
+#define ARM_CAN_INVALID_BITRATE        (ARM_DRIVER_ERROR_SPECIFIC - 2)          ///< Requested bitrate not supported
+#define ARM_CAN_INVALID_BIT_PROP_SEG   (ARM_DRIVER_ERROR_SPECIFIC - 3)          ///< Propagation segment value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4)          ///< Phase segment 1 value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5)          ///< Phase segment 2 value not supported
+#define ARM_CAN_INVALID_BIT_SJW        (ARM_DRIVER_ERROR_SPECIFIC - 6)          ///< SJW value not supported
+#define ARM_CAN_NO_MESSAGE_AVAILABLE   (ARM_DRIVER_ERROR_SPECIFIC - 7)          ///< Message is not available
+
+/****** CAN Status codes *****/
+#define ARM_CAN_UNIT_STATE_INACTIVE    (0U)             ///< Unit state: Not active on bus (initialization)
+#define ARM_CAN_UNIT_STATE_ACTIVE      (1U)             ///< Unit state: Active on bus (can generate active error frame)
+#define ARM_CAN_UNIT_STATE_PASSIVE     (2U)             ///< Unit state: Error passive (can not generate active error frame)
+#define ARM_CAN_UNIT_STATE_BUS_OFF     (3U)             ///< Unit state: Bus-off (can recover to active state)
+#define ARM_CAN_LEC_NO_ERROR           (0U)             ///< Last error code: No error
+#define ARM_CAN_LEC_BIT_ERROR          (1U)             ///< Last error code: Bit error
+#define ARM_CAN_LEC_STUFF_ERROR        (2U)             ///< Last error code: Bit stuffing error
+#define ARM_CAN_LEC_CRC_ERROR          (3U)             ///< Last error code: CRC error
+#define ARM_CAN_LEC_FORM_ERROR         (4U)             ///< Last error code: Illegal fixed-form bit
+#define ARM_CAN_LEC_ACK_ERROR          (5U)             ///< Last error code: Acknowledgment error
+
+/**
+\brief CAN Status
+*/
+typedef struct _ARM_CAN_STATUS {
+  uint32_t unit_state       : 4;        ///< Unit bus state
+  uint32_t last_error_code  : 4;        ///< Last error code
+  uint32_t tx_error_count   : 8;        ///< Transmitter error count
+  uint32_t rx_error_count   : 8;        ///< Receiver error count
+  uint32_t reserved         : 8;
+} ARM_CAN_STATUS;
+
+
+/****** CAN Unit Event *****/
+#define ARM_CAN_EVENT_UNIT_INACTIVE    (0U)             ///< Unit entered Inactive state
+#define ARM_CAN_EVENT_UNIT_ACTIVE      (1U)             ///< Unit entered Error Active state
+#define ARM_CAN_EVENT_UNIT_WARNING     (2U)             ///< Unit entered Error Warning state (one or both error counters >= 96)
+#define ARM_CAN_EVENT_UNIT_PASSIVE     (3U)             ///< Unit entered Error Passive state
+#define ARM_CAN_EVENT_UNIT_BUS_OFF     (4U)             ///< Unit entered Bus-off state
+
+/****** CAN Send/Receive Event *****/
+#define ARM_CAN_EVENT_SEND_COMPLETE    (1UL << 0)       ///< Send complete
+#define ARM_CAN_EVENT_RECEIVE          (1UL << 1)       ///< Message received
+#define ARM_CAN_EVENT_RECEIVE_OVERRUN  (1UL << 2)       ///< Received message overrun
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_CAN_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                                           ARM_CAN_SignalObjectEvent_t cb_object_event)
+  \brief       Initialize CAN interface and register signal (callback) functions.
+  \param[in]   cb_unit_event   Pointer to \ref ARM_CAN_SignalUnitEvent callback function
+  \param[in]   cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_Uninitialize (void)
+  \brief       De-initialize CAN interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)
+  \brief       Control CAN interface power.
+  \param[in]   state  Power state
+                 - \ref ARM_POWER_OFF :  power off: no operation possible
+                 - \ref ARM_POWER_LOW :  low power mode: retain state, detect and signal wake-up events
+                 - \ref ARM_POWER_FULL : power on: full operation at maximum performance
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_CAN_GetClock (void)
+  \brief       Retrieve CAN base clock frequency.
+  \return      base clock frequency
+
+  \fn          int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)
+  \brief       Set bitrate for CAN interface.
+  \param[in]   select       Bitrate selection
+                 - \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate
+                 - \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate
+  \param[in]   bitrate      Bitrate
+  \param[in]   bit_segments Bit segments settings
+                 - \ref ARM_CAN_BIT_PROP_SEG(x) :   number of time quanta for propagation time segment
+                 - \ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1
+                 - \ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2
+                 - \ref ARM_CAN_BIT_SJW(x) :        number of time quanta for (re-)synchronization jump width
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)
+  \brief       Set operating mode for CAN interface.
+  \param[in]   mode   Operating mode
+                 - \ref ARM_CAN_MODE_INITIALIZATION :    initialization mode
+                 - \ref ARM_CAN_MODE_NORMAL :            normal operation mode
+                 - \ref ARM_CAN_MODE_RESTRICTED :        restricted operation mode
+                 - \ref ARM_CAN_MODE_MONITOR :           bus monitoring mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)
+  \brief       Retrieve capabilities of an object.
+  \param[in]   obj_idx  Object index
+  \return      \ref ARM_CAN_OBJ_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)
+  \brief       Add or remove filter for message reception.
+  \param[in]   obj_idx      Object index of object that filter should be or is assigned to
+  \param[in]   operation    Operation on filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_ADD :       add    exact id filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_REMOVE :    remove exact id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_ADD :       add    range id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_REMOVE :    remove range id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_ADD :    add    maskable id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter
+  \param[in]   id           ID or start of ID range (depending on filter type)
+  \param[in]   arg          Mask or end of ID range (depending on filter type)
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)
+  \brief       Configure object.
+  \param[in]   obj_idx  Object index
+  \param[in]   obj_cfg  Object configuration state
+                 - \ref ARM_CAN_OBJ_INACTIVE :       deactivate object
+                 - \ref ARM_CAN_OBJ_RX :             configure object for reception
+                 - \ref ARM_CAN_OBJ_TX :             configure object for transmission
+                 - \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame
+                 - \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)
+  \brief       Send message on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[in]   msg_info Pointer to CAN message information
+  \param[in]   data     Pointer to data buffer
+  \param[in]   size     Number of data bytes to send
+  \return      value >= 0  number of data bytes accepted to send
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)
+  \brief       Read message received on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[out]  msg_info Pointer to read CAN message information
+  \param[out]  data     Pointer to data buffer for read data
+  \param[in]   size     Maximum number of data bytes to read
+  \return      value >= 0  number of data bytes read
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)
+  \brief       Control CAN interface.
+  \param[in]   control  Operation
+                 - \ref ARM_CAN_SET_FD_MODE :            set FD operation mode
+                 - \ref ARM_CAN_ABORT_MESSAGE_SEND :     abort sending of CAN message
+                 - \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission
+                 - \ref ARM_CAN_SET_TRANSCEIVER_DELAY :  set transceiver delay
+  \param[in]   arg      Argument of operation
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_STATUS ARM_CAN_GetStatus (void)
+  \brief       Get CAN status.
+  \return      CAN status \ref ARM_CAN_STATUS
+
+  \fn          void ARM_CAN_SignalUnitEvent (uint32_t event)
+  \brief       Signal CAN unit event.
+  \param[in]   event \ref CAN_unit_events
+  \return      none
+
+  \fn          void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)
+  \brief       Signal CAN object event.
+  \param[in]   obj_idx  Object index
+  \param[in]   event \ref CAN_events
+  \return      none
+*/
+
+typedef void (*ARM_CAN_SignalUnitEvent_t)   (uint32_t event);                   ///< Pointer to \ref ARM_CAN_SignalUnitEvent   : Signal CAN Unit Event.
+typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event.
+
+
+/**
+\brief CAN Device Driver Capabilities.
+*/
+typedef struct _ARM_CAN_CAPABILITIES {
+  uint32_t num_objects            : 8;  ///< Number of \ref can_objects available
+  uint32_t reentrant_operation    : 1;  ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control
+  uint32_t fd_mode                : 1;  ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control)
+  uint32_t restricted_mode        : 1;  ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode)
+  uint32_t monitor_mode           : 1;  ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode)
+  uint32_t internal_loopback      : 1;  ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t external_loopback      : 1;  ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t reserved               : 18; ///< Reserved (must be zero)
+} ARM_CAN_CAPABILITIES;
+
+
+/**
+\brief Access structure of the CAN Driver.
+*/
+typedef struct _ARM_DRIVER_CAN {
+  ARM_DRIVER_VERSION       (*GetVersion)            (void);                             ///< Pointer to \ref ARM_CAN_GetVersion            : Get driver version.
+  ARM_CAN_CAPABILITIES     (*GetCapabilities)       (void);                             ///< Pointer to \ref ARM_CAN_GetCapabilities       : Get driver capabilities.
+  int32_t                  (*Initialize)            (ARM_CAN_SignalUnitEvent_t   cb_unit_event,                     
+                                                     ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface.
+  int32_t                  (*Uninitialize)          (void);                             ///< Pointer to \ref ARM_CAN_Uninitialize          : De-initialize CAN interface.
+  int32_t                  (*PowerControl)          (ARM_POWER_STATE          state);   ///< Pointer to \ref ARM_CAN_PowerControl          : Control CAN interface power.
+  uint32_t                 (*GetClock)              (void);                             ///< Pointer to \ref ARM_CAN_GetClock              : Retrieve CAN base clock frequency.
+  int32_t                  (*SetBitrate)            (ARM_CAN_BITRATE_SELECT   select,
+                                                     uint32_t                 bitrate,
+                                                     uint32_t                 bit_segments);       ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface.
+  int32_t                  (*SetMode)               (ARM_CAN_MODE             mode);    ///< Pointer to \ref ARM_CAN_SetMode               : Set operating mode for CAN interface.
+  ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t                 obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object.
+  int32_t                  (*ObjectSetFilter)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_FILTER_OPERATION operation,
+                                                     uint32_t                 id,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_ObjectSetFilter       : Add or remove filter for message reception.
+  int32_t                  (*ObjectConfigure)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_OBJ_CONFIG       obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure       : Configure object.
+  int32_t                  (*MessageSend)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     const uint8_t           *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageSend           : Send message on CAN bus.
+  int32_t                  (*MessageRead)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     uint8_t                 *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageRead           : Read message received on CAN bus.
+  int32_t                  (*Control)               (uint32_t                 control,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_Control               : Control CAN interface.
+  ARM_CAN_STATUS           (*GetStatus)             (void);                             ///< Pointer to \ref ARM_CAN_GetStatus             : Get CAN status.
+} const ARM_DRIVER_CAN;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_CAN_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_Common.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.0
+ *
+ * Project:      Common Driver definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Added General return codes definitions
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_COMMON_H_
+#define DRIVER_COMMON_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded 
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors 
+
+/**
+\brief General power states
+*/ 
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* DRIVER_COMMON_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.2
+ *
+ * Project:      Ethernet PHY and MAC Driver common definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    Removed volatile from ARM_ETH_LINK_INFO
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    Removed ARM_ETH_STATUS enumerator
+ *    Removed ARM_ETH_MODE enumerator
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_H_
+#define DRIVER_ETH_H_
+
+#include "Driver_Common.h"
+
+/**
+\brief Ethernet Media Interface type
+*/
+#define ARM_ETH_INTERFACE_MII           (0U)    ///< Media Independent Interface (MII)
+#define ARM_ETH_INTERFACE_RMII          (1U)    ///< Reduced Media Independent Interface (RMII)
+#define ARM_ETH_INTERFACE_SMII          (2U)    ///< Serial Media Independent Interface (SMII)
+
+/**
+\brief Ethernet link speed
+*/
+#define ARM_ETH_SPEED_10M               (0U)    ///< 10 Mbps link speed
+#define ARM_ETH_SPEED_100M              (1U)    ///< 100 Mbps link speed
+#define ARM_ETH_SPEED_1G                (2U)    ///< 1 Gpbs link speed
+
+/**
+\brief Ethernet duplex mode
+*/
+#define ARM_ETH_DUPLEX_HALF             (0U)    ///< Half duplex link
+#define ARM_ETH_DUPLEX_FULL             (1U)    ///< Full duplex link
+
+/**
+\brief Ethernet link state
+*/
+typedef enum _ARM_ETH_LINK_STATE {
+  ARM_ETH_LINK_DOWN,                    ///< Link is down
+  ARM_ETH_LINK_UP                       ///< Link is up
+} ARM_ETH_LINK_STATE;
+
+/**
+\brief Ethernet link information
+*/
+typedef struct _ARM_ETH_LINK_INFO {
+  uint32_t speed    : 2;                ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
+  uint32_t duplex   : 1;                ///< Duplex mode: 0= Half, 1= Full
+  uint32_t reserved : 29;
+} ARM_ETH_LINK_INFO;
+
+/**
+\brief Ethernet MAC Address
+*/
+typedef struct _ARM_ETH_MAC_ADDR {
+  uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first
+} ARM_ETH_MAC_ADDR;
+
+#endif /* DRIVER_ETH_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_MAC.h

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.2
+ *
+ * Project:      Ethernet MAC (Media Access Control) Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    Removed volatile from ARM_ETH_LINK_INFO
+ *  Version 2.1
+ *    Added ARM_ETH_MAC_SLEEP Control
+ *  Version 2.0
+ *    Changed MAC Address handling:
+ *      moved from ARM_ETH_MAC_Initialize
+ *      to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress
+ *    Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter
+ *    Extended ARM_ETH_MAC_SendFrame function with flags
+ *    Added ARM_ETH_MAC_Control function:
+ *      more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)
+ *      replaces ARM_ETH_MAC_SetMode
+ *      replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx
+ *    Added optional event on transmitted frame
+ *    Added support for PTP (Precision Time Protocol) through new functions:
+ *       ARM_ETH_MAC_ControlTimer
+ *       ARM_ETH_MAC_GetRxFrameTime
+ *       ARM_ETH_MAC_GetTxFrameTime
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Name space prefix ARM_ added
+ *  Version 1.01
+ *    Renamed capabilities items for checksum offload
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_MAC_H_
+#define DRIVER_ETH_MAC_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+#define _ARM_Driver_ETH_MAC_(n)      Driver_ETH_MAC##n
+#define  ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)
+
+
+/****** Ethernet MAC Control Codes *****/
+
+#define ARM_ETH_MAC_CONFIGURE           (0x01UL)    ///< Configure MAC; arg = configuration
+#define ARM_ETH_MAC_CONTROL_TX          (0x02UL)    ///< Transmitter; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_CONTROL_RX          (0x03UL)    ///< Receiver; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_FLUSH               (0x04UL)    ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...
+#define ARM_ETH_MAC_SLEEP               (0x05UL)    ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
+#define ARM_ETH_MAC_VLAN_FILTER         (0x06UL)    ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
+
+/*----- Ethernet MAC Configuration -----*/
+#define ARM_ETH_MAC_SPEED_Pos            0
+#define ARM_ETH_MAC_SPEED_Msk           (3UL                 << ARM_ETH_MAC_SPEED_Pos)
+#define ARM_ETH_MAC_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_MAC_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_MAC_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_MAC_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_MAC_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_MAC_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_MAC_DUPLEX_Pos           2
+#define ARM_ETH_MAC_DUPLEX_Msk          (1UL                 << ARM_ETH_MAC_DUPLEX_Pos)
+#define ARM_ETH_MAC_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_MAC_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_MAC_LOOPBACK            (1UL << 4)  ///< Loop-back test mode
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5)  ///< Receiver Checksum offload
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6)  ///< Transmitter Checksum offload
+#define ARM_ETH_MAC_ADDRESS_BROADCAST   (1UL << 7)  ///< Accept frames with Broadcast address
+#define ARM_ETH_MAC_ADDRESS_MULTICAST   (1UL << 8)  ///< Accept frames with any Multicast address
+#define ARM_ETH_MAC_ADDRESS_ALL         (1UL << 9)  ///< Accept frames with any address (Promiscuous Mode)
+
+/*----- Ethernet MAC Flush Flags -----*/
+#define ARM_ETH_MAC_FLUSH_RX            (1UL << 0)  ///< Flush Receive buffer
+#define ARM_ETH_MAC_FLUSH_TX            (1UL << 1)  ///< Flush Transmit buffer
+
+/*----- Ethernet MAC VLAN Filter Flag -----*/
+#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
+
+
+/****** Ethernet MAC Frame Transmit Flags *****/
+#define ARM_ETH_MAC_TX_FRAME_FRAGMENT   (1UL << 0)  ///< Indicate frame fragment
+#define ARM_ETH_MAC_TX_FRAME_EVENT      (1UL << 1)  ///< Generate event when frame is transmitted
+#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP  (1UL << 2)  ///< Capture frame time stamp
+
+
+/****** Ethernet MAC Timer Control Codes *****/
+#define ARM_ETH_MAC_TIMER_GET_TIME      (0x01UL)    ///< Get current time
+#define ARM_ETH_MAC_TIMER_SET_TIME      (0x02UL)    ///< Set new time
+#define ARM_ETH_MAC_TIMER_INC_TIME      (0x03UL)    ///< Increment current time
+#define ARM_ETH_MAC_TIMER_DEC_TIME      (0x04UL)    ///< Decrement current time
+#define ARM_ETH_MAC_TIMER_SET_ALARM     (0x05UL)    ///< Set alarm time
+#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK  (0x06UL)    ///< Adjust clock frequency; time->ns: correction factor * 2^31
+
+
+/**
+\brief Ethernet MAC Time
+*/
+typedef struct _ARM_ETH_MAC_TIME {
+  uint32_t ns;                          ///< Nano seconds
+  uint32_t sec;                         ///< Seconds
+} ARM_ETH_MAC_TIME;
+
+
+/****** Ethernet MAC Event *****/
+#define ARM_ETH_MAC_EVENT_RX_FRAME      (1UL << 0)  ///< Frame Received
+#define ARM_ETH_MAC_EVENT_TX_FRAME      (1UL << 1)  ///< Frame Transmitted
+#define ARM_ETH_MAC_EVENT_WAKEUP        (1UL << 2)  ///< Wake-up (on Magic Packet)
+#define ARM_ETH_MAC_EVENT_TIMER_ALARM   (1UL << 3)  ///< Timer Alarm
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_ETH_MAC_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
+  \brief       Initialize Ethernet MAC Device.
+  \param[in]   cb_event  Pointer to \ref ARM_ETH_MAC_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Uninitialize (void)
+  \brief       De-initialize Ethernet MAC Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet MAC Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Get Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Set Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
+                                                           uint32_t          num_addr)
+  \brief       Configure Address Filter.
+  \param[in]   ptr_addr  Pointer to addresses
+  \param[in]   num_addr  Number of addresses to configure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
+  \brief       Send Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer with data to send
+  \param[in]   len    Frame buffer length in bytes
+  \param[in]   flags  Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)
+  \brief       Read data of received Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer for data to read into
+  \param[in]   len    Frame buffer length in bytes
+  \return      number of data bytes read or execution status
+                 - value >= 0: number of data bytes read
+                 - value < 0: error occurred, value is execution status as defined with \ref execution_status 
+*/
+/**
+  \fn          uint32_t ARM_ETH_MAC_GetRxFrameSize (void)
+  \brief       Get size of received Ethernet frame.
+  \return      number of bytes in received frame
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of received Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of transmitted Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)
+  \brief       Control Ethernet Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
+  \brief       Control Precision Timer.
+  \param[in]   control  Operation
+  \param[in]   time     Pointer to time structure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+  \brief       Read Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[out]  data      Pointer where the result is written to
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+  \brief       Write Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[in]   data      16-bit data to write
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_ETH_MAC_SignalEvent (uint32_t event)
+  \brief       Callback function that signals a Ethernet Event.
+  \param[in]   event  event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.
+
+
+/**
+\brief Ethernet MAC Capabilities
+*/
+typedef struct _ARM_ETH_MAC_CAPABILITIES {
+  uint32_t checksum_offload_rx_ip4  : 1;        ///< 1 = IPv4 header checksum verified on receive
+  uint32_t checksum_offload_rx_ip6  : 1;        ///< 1 = IPv6 checksum verification supported on receive
+  uint32_t checksum_offload_rx_udp  : 1;        ///< 1 = UDP payload checksum verified on receive
+  uint32_t checksum_offload_rx_tcp  : 1;        ///< 1 = TCP payload checksum verified on receive
+  uint32_t checksum_offload_rx_icmp : 1;        ///< 1 = ICMP payload checksum verified on receive
+  uint32_t checksum_offload_tx_ip4  : 1;        ///< 1 = IPv4 header checksum generated on transmit
+  uint32_t checksum_offload_tx_ip6  : 1;        ///< 1 = IPv6 checksum generation supported on transmit
+  uint32_t checksum_offload_tx_udp  : 1;        ///< 1 = UDP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_tcp  : 1;        ///< 1 = TCP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_icmp : 1;        ///< 1 = ICMP payload checksum generated on transmit
+  uint32_t media_interface          : 2;        ///< Ethernet Media Interface type
+  uint32_t mac_address              : 1;        ///< 1 = driver provides initial valid MAC address
+  uint32_t event_rx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated
+  uint32_t event_tx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated
+  uint32_t event_wakeup             : 1;        ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated
+  uint32_t precision_timer          : 1;        ///< 1 = Precision Timer supported
+  uint32_t reserved                 : 15;       ///< Reserved (must be zero)
+} ARM_ETH_MAC_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Ethernet MAC Driver
+*/
+typedef struct _ARM_DRIVER_ETH_MAC {
+  ARM_DRIVER_VERSION       (*GetVersion)      (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version.
+  ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)      (ARM_ETH_MAC_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.
+  int32_t                  (*Uninitialize)    (void);                                                ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.
+  int32_t                  (*PowerControl)    (ARM_POWER_STATE state);                               ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.
+  int32_t                  (*GetMacAddress)   (      ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.
+  int32_t                  (*SetMacAddress)   (const ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.
+  int32_t                  (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.
+  int32_t                  (*SendFrame)       (const uint8_t *frame, uint32_t len, uint32_t flags);  ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.
+  int32_t                  (*ReadFrame)       (      uint8_t *frame, uint32_t len);                  ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.
+  uint32_t                 (*GetRxFrameSize)  (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.
+  int32_t                  (*GetRxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.
+  int32_t                  (*GetTxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.
+  int32_t                  (*ControlTimer)    (uint32_t control, ARM_ETH_MAC_TIME *time);            ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.
+  int32_t                  (*Control)         (uint32_t control, uint32_t arg);                      ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface.
+  int32_t                  (*PHY_Read)        (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.
+  int32_t                  (*PHY_Write)       (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.
+} const ARM_DRIVER_ETH_MAC;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_MAC_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_PHY.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.2
+ *
+ * Project:      Ethernet PHY (Physical Transceiver) Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    Removed volatile from ARM_ETH_LINK_INFO
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    changed parameter "mode" in function ARM_ETH_PHY_SetMode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_PHY_H_
+#define DRIVER_ETH_PHY_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+#define _ARM_Driver_ETH_PHY_(n)      Driver_ETH_PHY##n
+#define  ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)
+
+
+/****** Ethernet PHY Mode *****/
+#define ARM_ETH_PHY_SPEED_Pos            0
+#define ARM_ETH_PHY_SPEED_Msk           (3UL                 << ARM_ETH_PHY_SPEED_Pos)
+#define ARM_ETH_PHY_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_PHY_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_PHY_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_PHY_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_PHY_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_PHY_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_PHY_DUPLEX_Pos           2
+#define ARM_ETH_PHY_DUPLEX_Msk          (1UL                 << ARM_ETH_PHY_DUPLEX_Pos)
+#define ARM_ETH_PHY_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_PHY_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_PHY_AUTO_NEGOTIATE      (1UL << 3)                                      ///< Auto Negotiation mode
+#define ARM_ETH_PHY_LOOPBACK            (1UL << 4)                                      ///< Loop-back test mode
+#define ARM_ETH_PHY_ISOLATE             (1UL << 5)                                      ///< Isolate PHY from MII/RMII interface
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t  fn_read,
+                                               ARM_ETH_PHY_Write_t fn_write)
+  \brief       Initialize Ethernet PHY Device.
+  \param[in]   fn_read   Pointer to \ref ARM_ETH_MAC_PHY_Read
+  \param[in]   fn_write  Pointer to \ref ARM_ETH_MAC_PHY_Write
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Uninitialize (void)
+  \brief       De-initialize Ethernet PHY Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet PHY Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)
+  \brief       Set Ethernet Media Interface.
+  \param[in]   interface  Media Interface type
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetMode (uint32_t mode)
+  \brief       Set Ethernet PHY Device Operation mode.
+  \param[in]   mode  Operation Mode
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)
+  \brief       Get Ethernet PHY Device Link state.
+  \return      current link status \ref ARM_ETH_LINK_STATE
+*/
+/**
+  \fn          ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)
+  \brief       Get Ethernet PHY Device Link information.
+  \return      current link parameters \ref ARM_ETH_LINK_INFO
+*/
+
+
+typedef int32_t (*ARM_ETH_PHY_Read_t)  (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.
+typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.
+
+
+/**
+\brief Access structure of the Ethernet PHY Driver
+*/
+typedef struct _ARM_DRIVER_ETH_PHY {
+  ARM_DRIVER_VERSION (*GetVersion)   (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version.
+  int32_t            (*Initialize)   (ARM_ETH_PHY_Read_t  fn_read,
+                                      ARM_ETH_PHY_Write_t fn_write);  ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device.
+  int32_t            (*Uninitialize) (void);                          ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.
+  int32_t            (*PowerControl) (ARM_POWER_STATE state);         ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.
+  int32_t            (*SetInterface) (uint32_t interface);            ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.
+  int32_t            (*SetMode)      (uint32_t mode);                 ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.
+  ARM_ETH_LINK_STATE (*GetLinkState) (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.
+  ARM_ETH_LINK_INFO  (*GetLinkInfo)  (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.
+} const ARM_DRIVER_ETH_PHY;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_PHY_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_Flash.h

@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.3
+ *
+ * Project:      Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Removed volatile from ARM_FLASH_STATUS
+ *  Version 2.2
+ *    Padding bytes added to ARM_FLASH_INFO
+ *  Version 2.1
+ *    ARM_FLASH_STATUS made volatile
+ *  Version 2.0
+ *    Renamed driver NOR -> Flash (more generic)
+ *    Non-blocking operation
+ *    Added Events, Status and Capabilities
+ *    Linked Flash information (GetInfo)
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_FLASH_H_
+#define DRIVER_FLASH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_Flash_(n)      Driver_Flash##n
+#define  ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
+
+
+#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
+
+/**
+\brief Flash Sector information
+*/
+typedef struct _ARM_FLASH_SECTOR {
+  uint32_t start;                       ///< Sector Start address
+  uint32_t end;                         ///< Sector End address (start+size-1)
+} const ARM_FLASH_SECTOR;
+
+/**
+\brief Flash information
+*/
+typedef struct _ARM_FLASH_INFO {
+  ARM_FLASH_SECTOR *sector_info;        ///< Sector layout information (NULL=Uniform sectors)
+  uint32_t          sector_count;       ///< Number of sectors
+  uint32_t          sector_size;        ///< Uniform sector size in bytes (0=sector_info used) 
+  uint32_t          page_size;          ///< Optimal programming page size in bytes
+  uint32_t          program_unit;       ///< Smallest programmable unit in bytes
+  uint8_t           erased_value;       ///< Contents of erased memory (usually 0xFF)
+  uint8_t           reserved[3];        ///< Reserved (must be zero)
+} const ARM_FLASH_INFO;
+
+
+/**
+\brief Flash Status
+*/
+typedef struct _ARM_FLASH_STATUS {
+  uint32_t busy     : 1;                ///< Flash busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_FLASH_STATUS;
+
+
+/****** Flash Event *****/
+#define ARM_FLASH_EVENT_READY           (1UL << 0)  ///< Flash Ready
+#define ARM_FLASH_EVENT_ERROR           (1UL << 1)  ///< Read/Program/Erase Error
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_FLASH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
+  \brief       Initialize the Flash Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_Flash_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_Uninitialize (void)
+  \brief       De-initialize the Flash Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Flash interface power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
+  \brief       Read data from Flash.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   cnt   Number of data items to read.
+  \return      number of data items read or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
+  \brief       Program data to Flash.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseSector (uint32_t addr)
+  \brief       Erase Flash Sector.
+  \param[in]   addr  Sector address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseChip (void)
+  \brief       Erase complete Flash.
+               Optional function for faster full chip erase.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
+  \brief       Get Flash status.
+  \return      Flash status \ref ARM_FLASH_STATUS
+*/
+/**
+  \fn          ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
+  \brief       Get Flash information.
+  \return      Pointer to Flash information \ref ARM_FLASH_INFO
+*/
+
+/**
+  \fn          void ARM_Flash_SignalEvent (uint32_t event)
+  \brief       Signal Flash event.
+  \param[in]   event  Event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event);    ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
+
+
+/**
+\brief Flash Driver Capabilities.
+*/
+typedef struct _ARM_FLASH_CAPABILITIES {
+  uint32_t event_ready  : 1;            ///< Signal Flash Ready event
+  uint32_t data_width   : 2;            ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
+  uint32_t erase_chip   : 1;            ///< Supports EraseChip operation
+  uint32_t reserved     : 28;           ///< Reserved (must be zero)
+} ARM_FLASH_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Flash Driver
+*/
+typedef struct _ARM_DRIVER_FLASH {
+  ARM_DRIVER_VERSION     (*GetVersion)     (void);                                          ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
+  ARM_FLASH_CAPABILITIES (*GetCapabilities)(void);                                          ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)     (ARM_Flash_SignalEvent_t cb_event);              ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
+  int32_t                (*Uninitialize)   (void);                                          ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
+  int32_t                (*PowerControl)   (ARM_POWER_STATE state);                         ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
+  int32_t                (*ReadData)       (uint32_t addr,       void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
+  int32_t                (*ProgramData)    (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
+  int32_t                (*EraseSector)    (uint32_t addr);                                 ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
+  int32_t                (*EraseChip)      (void);                                          ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
+  ARM_FLASH_STATUS       (*GetStatus)      (void);                                          ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
+  ARM_FLASH_INFO *       (*GetInfo)        (void);                                          ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
+} const ARM_DRIVER_FLASH;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_FLASH_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_I2C.h

@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      I2C (Inter-Integrated Circuit) Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_I2C_STATUS
+ *  Version 2.3
+ *    ARM_I2C_STATUS made volatile
+ *  Version 2.2
+ *    Removed function ARM_I2C_MasterTransfer in order to simplify drivers
+ *      and added back parameter "xfer_pending" to functions
+ *      ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *  Version 2.1
+ *    Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending"
+ *      from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *    Added function ARM_I2C_GetDataCount
+ *    Removed flag "address_nack" from ARM_I2C_STATUS
+ *    Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE
+ *      with event ARM_I2C_EVENT_TRANSFER_DONE
+ *    Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE
+ *    Removed parameter "arg" from function ARM_I2C_SignalEvent
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_I2C_H_
+#define DRIVER_I2C_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_I2C_(n)      Driver_I2C##n
+#define  ARM_Driver_I2C_(n) _ARM_Driver_I2C_(n)
+
+
+/****** I2C Control Codes *****/
+
+#define ARM_I2C_OWN_ADDRESS             (0x01UL)    ///< Set Own Slave Address; arg = address 
+#define ARM_I2C_BUS_SPEED               (0x02UL)    ///< Set Bus Speed; arg = speed
+#define ARM_I2C_BUS_CLEAR               (0x03UL)    ///< Execute Bus clear: send nine clock pulses
+#define ARM_I2C_ABORT_TRANSFER          (0x04UL)    ///< Abort Master/Slave Transmit/Receive
+
+/*----- I2C Bus Speed -----*/
+#define ARM_I2C_BUS_SPEED_STANDARD      (0x01UL)    ///< Standard Speed (100kHz)
+#define ARM_I2C_BUS_SPEED_FAST          (0x02UL)    ///< Fast Speed     (400kHz)
+#define ARM_I2C_BUS_SPEED_FAST_PLUS     (0x03UL)    ///< Fast+ Speed    (  1MHz)
+#define ARM_I2C_BUS_SPEED_HIGH          (0x04UL)    ///< High Speed     (3.4MHz)
+
+
+/****** I2C Address Flags *****/
+
+#define ARM_I2C_ADDRESS_10BIT           (0x0400UL)  ///< 10-bit address flag
+#define ARM_I2C_ADDRESS_GC              (0x8000UL)  ///< General Call flag
+
+
+/**
+\brief I2C Status
+*/
+typedef struct _ARM_I2C_STATUS {
+  uint32_t busy             : 1;        ///< Busy flag
+  uint32_t mode             : 1;        ///< Mode: 0=Slave, 1=Master
+  uint32_t direction        : 1;        ///< Direction: 0=Transmitter, 1=Receiver
+  uint32_t general_call     : 1;        ///< General Call indication (cleared on start of next Slave operation)
+  uint32_t arbitration_lost : 1;        ///< Master lost arbitration (cleared on start of next Master operation)
+  uint32_t bus_error        : 1;        ///< Bus error detected (cleared on start of next Master/Slave operation)
+  uint32_t reserved         : 26;
+} ARM_I2C_STATUS;
+
+
+/****** I2C Event *****/
+#define ARM_I2C_EVENT_TRANSFER_DONE       (1UL << 0)  ///< Master/Slave Transmit/Receive finished
+#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1)  ///< Master/Slave Transmit/Receive incomplete transfer
+#define ARM_I2C_EVENT_SLAVE_TRANSMIT      (1UL << 2)  ///< Addressed as Slave Transmitter but transmit operation is not set.
+#define ARM_I2C_EVENT_SLAVE_RECEIVE       (1UL << 3)  ///< Addressed as Slave Receiver but receive operation is not set.
+#define ARM_I2C_EVENT_ADDRESS_NACK        (1UL << 4)  ///< Address not acknowledged from Slave
+#define ARM_I2C_EVENT_GENERAL_CALL        (1UL << 5)  ///< Slave addressed with general call address
+#define ARM_I2C_EVENT_ARBITRATION_LOST    (1UL << 6)  ///< Master lost arbitration
+#define ARM_I2C_EVENT_BUS_ERROR           (1UL << 7)  ///< Bus error detected (START/STOP at illegal position)
+#define ARM_I2C_EVENT_BUS_CLEAR           (1UL << 8)  ///< Bus clear finished
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_I2C_CAPABILITIES
+
+  \fn          int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
+  \brief       Initialize I2C Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_I2C_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_Uninitialize (void)
+  \brief       De-initialize I2C Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)
+  \brief       Control I2C Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start transmitting data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[in]   data          Pointer to buffer with data to transmit to I2C Slave
+  \param[in]   num           Number of data bytes to transmit
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start receiving data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[out]  data          Pointer to buffer for data to receive from I2C Slave
+  \param[in]   num           Number of data bytes to receive
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)
+  \brief       Start transmitting data as I2C Slave.
+  \param[in]   data  Pointer to buffer with data to transmit to I2C Master
+  \param[in]   num   Number of data bytes to transmit
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)
+  \brief       Start receiving data as I2C Slave.
+  \param[out]  data  Pointer to buffer for data to receive from I2C Master
+  \param[in]   num   Number of data bytes to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data bytes transferred; -1 when Slave is not addressed by Master
+
+  \fn          int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)
+  \brief       Control I2C Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+
+  \fn          ARM_I2C_STATUS ARM_I2C_GetStatus (void)
+  \brief       Get I2C status.
+  \return      I2C status \ref ARM_I2C_STATUS
+
+  \fn          void ARM_I2C_SignalEvent (uint32_t event)
+  \brief       Signal I2C Events.
+  \param[in]   event  \ref I2C_events notification mask
+*/
+
+typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event.
+
+
+/**
+\brief I2C Driver Capabilities.
+*/
+typedef struct _ARM_I2C_CAPABILITIES {
+  uint32_t address_10_bit : 1;          ///< supports 10-bit addressing
+  uint32_t reserved       : 31;         ///< Reserved (must be zero)
+} ARM_I2C_CAPABILITIES;
+
+
+/**
+\brief Access structure of the I2C Driver.
+*/
+typedef struct _ARM_DRIVER_I2C {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                                                                ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version.
+  ARM_I2C_CAPABILITIES (*GetCapabilities)(void);                                                                ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_I2C_SignalEvent_t cb_event);                                      ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface.
+  int32_t              (*Uninitialize)   (void);                                                                ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);                                               ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power.
+  int32_t              (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.
+  int32_t              (*MasterReceive)  (uint32_t addr,       uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.
+  int32_t              (*SlaveTransmit)  (               const uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.
+  int32_t              (*SlaveReceive)   (                     uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.
+  int32_t              (*GetDataCount)   (void);                                                                ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg);                                      ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface.
+  ARM_I2C_STATUS       (*GetStatus)      (void);                                                                ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status.
+} const ARM_DRIVER_I2C;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_I2C_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_MCI.h

@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      MCI (Memory Card Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_MCI_STATUS
+ *  Version 2.3
+ *    ARM_MCI_STATUS made volatile
+ *  Version 2.2
+ *    Added timeout and error flags to ARM_MCI_STATUS
+ *    Added support for controlling optional RST_n pin (eMMC)
+ *    Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)
+ *    Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT
+ *  Version 2.1
+ *    Decoupled SPI mode from MCI driver
+ *    Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP
+ *  Version 2.0
+ *    Added support for:
+ *      SD UHS-I (Ultra High Speed)
+ *      SD I/O Interrupt
+ *      Read Wait (SD I/O)
+ *      Suspend/Resume (SD I/O)
+ *      MMC Interrupt
+ *      MMC Boot
+ *      Stream Data transfer (MMC)
+ *      VCCQ Power Supply Control (eMMC)
+ *      Command Completion Signal (CCS) for CE-ATA
+ *    Added ARM_MCI_Control function
+ *    Added ARM_MCI_GetStatus function
+ *    Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions
+ *      (replaced by ARM_MCI_Control)
+ *    Changed ARM_MCI_CardPower function (voltage parameter)
+ *    Changed ARM_MCI_SendCommnad function (flags parameter)
+ *    Changed ARM_MCI_SetupTransfer function (mode parameter)
+ *    Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_MCI_H_
+#define DRIVER_MCI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_MCI_(n)      Driver_MCI##n
+#define  ARM_Driver_MCI_(n) _ARM_Driver_MCI_(n)
+
+
+/****** MCI Send Command Flags *****/
+#define ARM_MCI_RESPONSE_Pos             0
+#define ARM_MCI_RESPONSE_Msk            (3UL << ARM_MCI_RESPONSE_Pos)
+#define ARM_MCI_RESPONSE_NONE           (0UL << ARM_MCI_RESPONSE_Pos)   ///< No response expected (default)
+#define ARM_MCI_RESPONSE_SHORT          (1UL << ARM_MCI_RESPONSE_Pos)   ///< Short response (48-bit)
+#define ARM_MCI_RESPONSE_SHORT_BUSY     (2UL << ARM_MCI_RESPONSE_Pos)   ///< Short response with busy signal (48-bit)
+#define ARM_MCI_RESPONSE_LONG           (3UL << ARM_MCI_RESPONSE_Pos)   ///< Long response (136-bit)
+
+#define ARM_MCI_RESPONSE_INDEX          (1UL << 2)  ///< Check command index in response
+#define ARM_MCI_RESPONSE_CRC            (1UL << 3)  ///< Check CRC in response
+
+#define ARM_MCI_WAIT_BUSY               (1UL << 4)  ///< Wait until busy before sending the command
+
+#define ARM_MCI_TRANSFER_DATA           (1UL << 5)  ///< Activate Data transfer
+
+#define ARM_MCI_CARD_INITIALIZE         (1UL << 6)  ///< Execute Memory Card initialization sequence
+
+#define ARM_MCI_INTERRUPT_COMMAND       (1UL << 7)  ///< Send Interrupt command (CMD40 - MMC only)
+#define ARM_MCI_INTERRUPT_RESPONSE      (1UL << 8)  ///< Send Interrupt response (CMD40 - MMC only)
+
+#define ARM_MCI_BOOT_OPERATION          (1UL << 9)  ///< Execute Boot operation (MMC only)
+#define ARM_MCI_BOOT_ALTERNATIVE        (1UL << 10) ///< Execute Alternative Boot operation (MMC only)
+#define ARM_MCI_BOOT_ACK                (1UL << 11) ///< Expect Boot Acknowledge (MMC only)
+
+#define ARM_MCI_CCSD                    (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device
+#define ARM_MCI_CCS                     (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device
+
+
+/****** MCI Setup Transfer Mode *****/
+#define ARM_MCI_TRANSFER_READ           (0UL << 0)  ///< Data Read Transfer (from MCI)
+#define ARM_MCI_TRANSFER_WRITE          (1UL << 0)  ///< Data Write Transfer (to MCI)
+#define ARM_MCI_TRANSFER_BLOCK          (0UL << 1)  ///< Block Data transfer (default)
+#define ARM_MCI_TRANSFER_STREAM         (1UL << 1)  ///< Stream Data transfer (MMC only)
+
+
+/****** MCI Control Codes *****/
+#define ARM_MCI_BUS_SPEED               (0x01UL)    ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s
+#define ARM_MCI_BUS_SPEED_MODE          (0x02UL)    ///< Set Bus Speed Mode as specified with arg
+#define ARM_MCI_BUS_CMD_MODE            (0x03UL)    ///< Set CMD Line Mode as specified with arg
+#define ARM_MCI_BUS_DATA_WIDTH          (0x04UL)    ///< Set Bus Data Width as specified with arg
+#define ARM_MCI_DRIVER_STRENGTH         (0x05UL)    ///< Set SD UHS-I Driver Strength as specified with arg 
+#define ARM_MCI_CONTROL_RESET           (0x06UL)    ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active 
+#define ARM_MCI_CONTROL_CLOCK_IDLE      (0x07UL)    ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled
+#define ARM_MCI_UHS_TUNING_OPERATION    (0x08UL)    ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute
+#define ARM_MCI_UHS_TUNING_RESULT       (0x09UL)    ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error
+#define ARM_MCI_DATA_TIMEOUT            (0x0AUL)    ///< Set Data timeout; arg = timeout in bus cycles
+#define ARM_MCI_CSS_TIMEOUT             (0x0BUL)    ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles
+#define ARM_MCI_MONITOR_SDIO_INTERRUPT  (0x0CUL)    ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled
+#define ARM_MCI_CONTROL_READ_WAIT       (0x0DUL)    ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled
+#define ARM_MCI_SUSPEND_TRANSFER        (0x0EUL)    ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer
+#define ARM_MCI_RESUME_TRANSFER         (0x0FUL)    ///< Resume Data transfer (SD I/O)
+
+/*----- MCI Bus Speed Mode -----*/
+#define ARM_MCI_BUS_DEFAULT_SPEED       (0x00UL)    ///< SD/MMC: Default Speed mode up to 25/26MHz
+#define ARM_MCI_BUS_HIGH_SPEED          (0x01UL)    ///< SD/MMC: High    Speed mode up to 50/52MHz
+#define ARM_MCI_BUS_UHS_SDR12           (0x02UL)    ///< SD: SDR12  (Single Data Rate) up to  25MHz,  12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR25           (0x03UL)    ///< SD: SDR25  (Single Data Rate) up to  50MHz,  25  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR50           (0x04UL)    ///< SD: SDR50  (Single Data Rate) up to 100MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR104          (0x05UL)    ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_DDR50           (0x06UL)    ///< SD: DDR50  (Dual Data Rate)   up to  50MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+
+/*----- MCI CMD Line Mode -----*/
+#define ARM_MCI_BUS_CMD_PUSH_PULL       (0x00UL)    ///< Push-Pull CMD line (default)
+#define ARM_MCI_BUS_CMD_OPEN_DRAIN      (0x01UL)    ///< Open Drain CMD line (MMC only)
+
+/*----- MCI Bus Data Width -----*/
+#define ARM_MCI_BUS_DATA_WIDTH_1        (0x00UL)    ///< Bus data width: 1 bit (default)
+#define ARM_MCI_BUS_DATA_WIDTH_4        (0x01UL)    ///< Bus data width: 4 bits
+#define ARM_MCI_BUS_DATA_WIDTH_8        (0x02UL)    ///< Bus data width: 8 bits
+#define ARM_MCI_BUS_DATA_WIDTH_4_DDR    (0x03UL)    ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only
+#define ARM_MCI_BUS_DATA_WIDTH_8_DDR    (0x04UL)    ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only
+
+/*----- MCI Driver Strength -----*/
+#define ARM_MCI_DRIVER_TYPE_A           (0x01UL)    ///< SD UHS-I Driver Type A
+#define ARM_MCI_DRIVER_TYPE_B           (0x00UL)    ///< SD UHS-I Driver Type B (default)
+#define ARM_MCI_DRIVER_TYPE_C           (0x02UL)    ///< SD UHS-I Driver Type C
+#define ARM_MCI_DRIVER_TYPE_D           (0x03UL)    ///< SD UHS-I Driver Type D
+
+
+/****** MCI Card Power *****/
+#define ARM_MCI_POWER_VDD_Pos            0
+#define ARM_MCI_POWER_VDD_Msk           (0x0FUL << ARM_MCI_POWER_VDD_Pos)
+#define ARM_MCI_POWER_VDD_OFF           (0x01UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) turned off
+#define ARM_MCI_POWER_VDD_3V3           (0x02UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 3.3V
+#define ARM_MCI_POWER_VDD_1V8           (0x03UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 1.8V
+#define ARM_MCI_POWER_VCCQ_Pos           4
+#define ARM_MCI_POWER_VCCQ_Msk          (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
+#define ARM_MCI_POWER_VCCQ_OFF          (0x01UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ turned off
+#define ARM_MCI_POWER_VCCQ_3V3          (0x02UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 3.3V
+#define ARM_MCI_POWER_VCCQ_1V8          (0x03UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.8V
+#define ARM_MCI_POWER_VCCQ_1V2          (0x04UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.2V
+
+
+/**
+\brief MCI Status
+*/
+typedef struct _ARM_MCI_STATUS {
+  uint32_t command_active   : 1;        ///< Command active flag
+  uint32_t command_timeout  : 1;        ///< Command timeout flag (cleared on start of next command)
+  uint32_t command_error    : 1;        ///< Command error flag (cleared on start of next command)
+  uint32_t transfer_active  : 1;        ///< Transfer active flag
+  uint32_t transfer_timeout : 1;        ///< Transfer timeout flag (cleared on start of next command)
+  uint32_t transfer_error   : 1;        ///< Transfer error flag (cleared on start of next command)
+  uint32_t sdio_interrupt   : 1;        ///< SD I/O Interrupt flag (cleared on start of monitoring)
+  uint32_t ccs              : 1;        ///< CCS flag (cleared on start of next command)
+  uint32_t reserved         : 24;
+} ARM_MCI_STATUS;
+
+
+/****** MCI Card Event *****/
+#define ARM_MCI_EVENT_CARD_INSERTED     (1UL << 0)  ///< Memory Card inserted
+#define ARM_MCI_EVENT_CARD_REMOVED      (1UL << 1)  ///< Memory Card removed
+#define ARM_MCI_EVENT_COMMAND_COMPLETE  (1UL << 2)  ///< Command completed
+#define ARM_MCI_EVENT_COMMAND_TIMEOUT   (1UL << 3)  ///< Command timeout
+#define ARM_MCI_EVENT_COMMAND_ERROR     (1UL << 4)  ///< Command response error (CRC error or invalid response)
+#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5)  ///< Data transfer completed
+#define ARM_MCI_EVENT_TRANSFER_TIMEOUT  (1UL << 6)  ///< Data transfer timeout
+#define ARM_MCI_EVENT_TRANSFER_ERROR    (1UL << 7)  ///< Data transfer CRC failed
+#define ARM_MCI_EVENT_SDIO_INTERRUPT    (1UL << 8)  ///< SD I/O Interrupt
+#define ARM_MCI_EVENT_CCS               (1UL << 9)  ///< Command Completion Signal (CCS)
+#define ARM_MCI_EVENT_CCS_TIMEOUT       (1UL << 10) ///< Command Completion Signal (CCS) Timeout
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_MCI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)
+  \brief         Initialize the Memory Card Interface
+  \param[in]     cb_event  Pointer to \ref ARM_MCI_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Uninitialize (void)
+  \brief         De-initialize Memory Card Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control Memory Card Interface Power.
+  \param[in]     state   Power state \ref ARM_POWER_STATE
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_CardPower (uint32_t voltage)
+  \brief         Set Memory Card Power supply voltage.
+  \param[in]     voltage  Memory Card Power supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadCD (void)
+  \brief         Read Card Detect (CD) state.
+  \return        1:card detected, 0:card not detected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadWP (void)
+  \brief         Read Write Protect (WP) state.
+  \return        1:write protected, 0:not write protected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_SendCommand (uint32_t  cmd,
+                                              uint32_t  arg,
+                                              uint32_t  flags,
+                                              uint32_t *response)
+  \brief         Send Command to card and get the response.
+  \param[in]     cmd       Memory Card command
+  \param[in]     arg       Command argument
+  \param[in]     flags     Command flags
+  \param[out]    response  Pointer to buffer for response
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_SetupTransfer (uint8_t *data,
+                                                uint32_t block_count,
+                                                uint32_t block_size,
+                                                uint32_t mode)
+  \brief         Setup read or write transfer operation.
+  \param[in,out] data         Pointer to data block(s) to be written or read
+  \param[in]     block_count  Number of blocks
+  \param[in]     block_size   Size of a block in bytes
+  \param[in]     mode         Transfer mode
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_AbortTransfer (void)
+  \brief         Abort current read/write data transfer.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)
+  \brief         Control MCI Interface.
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation (optional)
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_MCI_STATUS ARM_MCI_GetStatus (void)
+  \brief         Get MCI status.
+  \return        MCI status \ref ARM_MCI_STATUS
+*/
+
+/**
+  \fn            void ARM_MCI_SignalEvent (uint32_t event)
+  \brief         Callback function that signals a MCI Card Event.
+  \param[in]     event \ref mci_event_gr
+  \return        none
+*/
+
+typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event.
+
+
+/**
+\brief  MCI Driver Capabilities.
+*/
+typedef struct _ARM_MCI_CAPABILITIES {
+  uint32_t cd_state          : 1;       ///< Card Detect State available
+  uint32_t cd_event          : 1;       ///< Signal Card Detect change event
+  uint32_t wp_state          : 1;       ///< Write Protect State available
+  uint32_t vdd               : 1;       ///< Supports VDD Card Power Supply Control
+  uint32_t vdd_1v8           : 1;       ///< Supports 1.8 VDD Card Power Supply
+  uint32_t vccq              : 1;       ///< Supports VCCQ Card Power Supply Control (eMMC)
+  uint32_t vccq_1v8          : 1;       ///< Supports 1.8 VCCQ Card Power Supply (eMMC)
+  uint32_t vccq_1v2          : 1;       ///< Supports 1.2 VCCQ Card Power Supply (eMMC)
+  uint32_t data_width_4      : 1;       ///< Supports 4-bit data
+  uint32_t data_width_8      : 1;       ///< Supports 8-bit data
+  uint32_t data_width_4_ddr  : 1;       ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t data_width_8_ddr  : 1;       ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t high_speed        : 1;       ///< Supports SD/MMC High Speed Mode
+  uint32_t uhs_signaling     : 1;       ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling 
+  uint32_t uhs_tuning        : 1;       ///< Supports SD UHS-I tuning 
+  uint32_t uhs_sdr50         : 1;       ///< Supports SD UHS-I SDR50  (Single Data Rate) up to  50MB/s
+  uint32_t uhs_sdr104        : 1;       ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s
+  uint32_t uhs_ddr50         : 1;       ///< Supports SD UHS-I DDR50  (Dual   Data Rate) up to  50MB/s
+  uint32_t uhs_driver_type_a : 1;       ///< Supports SD UHS-I Driver Type A
+  uint32_t uhs_driver_type_c : 1;       ///< Supports SD UHS-I Driver Type C
+  uint32_t uhs_driver_type_d : 1;       ///< Supports SD UHS-I Driver Type D 
+  uint32_t sdio_interrupt    : 1;       ///< Supports SD I/O Interrupt 
+  uint32_t read_wait         : 1;       ///< Supports Read Wait (SD I/O)
+  uint32_t suspend_resume    : 1;       ///< Supports Suspend/Resume (SD I/O)
+  uint32_t mmc_interrupt     : 1;       ///< Supports MMC Interrupt 
+  uint32_t mmc_boot          : 1;       ///< Supports MMC Boot 
+  uint32_t rst_n             : 1;       ///< Supports RST_n Pin Control (eMMC)
+  uint32_t ccs               : 1;       ///< Supports Command Completion Signal (CCS) for CE-ATA
+  uint32_t ccs_timeout       : 1;       ///< Supports Command Completion Signal (CCS) timeout for CE-ATA
+  uint32_t reserved          : 3;       ///< Reserved (must be zero)
+} ARM_MCI_CAPABILITIES;
+
+
+/**
+\brief  Access structure of the MCI Driver.
+*/
+typedef struct _ARM_DRIVER_MCI {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                           ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version.
+  ARM_MCI_CAPABILITIES (*GetCapabilities)(void);                           ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface.
+  int32_t              (*Uninitialize)   (void);                           ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);          ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power.
+  int32_t              (*CardPower)      (uint32_t voltage);               ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage.
+  int32_t              (*ReadCD)         (void);                           ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state.
+  int32_t              (*ReadWP)         (void);                           ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state.
+  int32_t              (*SendCommand)    (uint32_t cmd, 
+                                          uint32_t arg, 
+                                          uint32_t flags,
+                                          uint32_t *response);             ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response.
+  int32_t              (*SetupTransfer)  (uint8_t *data,
+                                          uint32_t block_count,
+                                          uint32_t block_size,
+                                          uint32_t mode);                  ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation.
+  int32_t              (*AbortTransfer)  (void);                           ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface.
+  ARM_MCI_STATUS       (*GetStatus)      (void);                           ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status.
+} const ARM_DRIVER_MCI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_MCI_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_NAND.h

@@ -0,0 +1,426 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      NAND Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_NAND_STATUS
+ *  Version 2.3
+ *    Extended ARM_NAND_ECC_INFO structure
+ *  Version 2.2
+ *    ARM_NAND_STATUS made volatile
+ *  Version 2.1
+ *    Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (command agnostic)
+ *    Added support for:
+ *      NV-DDR & NV-DDR2 Interface (ONFI specification)
+ *      VCC, VCCQ and VPP Power Supply Control
+ *      WP (Write Protect) Control
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_NAND_H_
+#define DRIVER_NAND_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_NAND_(n)      Driver_NAND##n
+#define  ARM_Driver_NAND_(n) _ARM_Driver_NAND_(n)
+
+
+/****** NAND Device Power *****/
+#define ARM_NAND_POWER_VCC_Pos           0
+#define ARM_NAND_POWER_VCC_Msk          (0x07UL << ARM_NAND_POWER_VCC_Pos)
+#define ARM_NAND_POWER_VCC_OFF          (0x01UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC Power off
+#define ARM_NAND_POWER_VCC_3V3          (0x02UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 3.3V
+#define ARM_NAND_POWER_VCC_1V8          (0x03UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 1.8V
+#define ARM_NAND_POWER_VCCQ_Pos          3
+#define ARM_NAND_POWER_VCCQ_Msk         (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
+#define ARM_NAND_POWER_VCCQ_OFF         (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
+#define ARM_NAND_POWER_VCCQ_3V3         (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
+#define ARM_NAND_POWER_VCCQ_1V8         (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
+#define ARM_NAND_POWER_VPP_OFF          (1UL << 6)                          ///< VPP off
+#define ARM_NAND_POWER_VPP_ON           (1UL << 7)                          ///< VPP on
+
+
+/****** NAND Control Codes *****/
+#define ARM_NAND_BUS_MODE               (0x01UL)    ///< Set Bus Mode as specified with arg
+#define ARM_NAND_BUS_DATA_WIDTH         (0x02UL)    ///< Set Bus Data Width as specified with arg
+#define ARM_NAND_DRIVER_STRENGTH        (0x03UL)    ///< Set Driver Strength as specified with arg
+#define ARM_NAND_DEVICE_READY_EVENT     (0x04UL)    ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled 
+#define ARM_NAND_DRIVER_READY_EVENT     (0x05UL)    ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled 
+
+/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_BUS_INTERFACE_Pos       4
+#define ARM_NAND_BUS_INTERFACE_Msk      (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
+#define ARM_NAND_BUS_SDR                (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface:    SDR  (Single Data Rate) - Traditional interface (default)
+#define ARM_NAND_BUS_DDR                (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR  (Double Data Rate)
+#define ARM_NAND_BUS_DDR2               (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR2 (Double Data Rate)
+#define ARM_NAND_BUS_TIMING_MODE_Pos     0
+#define ARM_NAND_BUS_TIMING_MODE_Msk    (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
+#define ARM_NAND_BUS_TIMING_MODE_0      (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 0 (default)
+#define ARM_NAND_BUS_TIMING_MODE_1      (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 1
+#define ARM_NAND_BUS_TIMING_MODE_2      (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 2
+#define ARM_NAND_BUS_TIMING_MODE_3      (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 3
+#define ARM_NAND_BUS_TIMING_MODE_4      (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 4 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_5      (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 5 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_6      (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 6 (NV-DDR2 only)
+#define ARM_NAND_BUS_TIMING_MODE_7      (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 7 (NV-DDR2 only)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos    8
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DO_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DO_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos    12
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DI_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DI_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_VEN           (1UL << 16)                               ///< DDR2 Enable external VREFQ as reference
+#define ARM_NAND_BUS_DDR2_CMPD          (1UL << 17)                               ///< DDR2 Enable complementary DQS (DQS_c) signal
+#define ARM_NAND_BUS_DDR2_CMPR          (1UL << 18)                               ///< DDR2 Enable complementary RE_n (RE_c) signal
+
+/*----- NAND Data Bus Width -----*/
+#define ARM_NAND_BUS_DATA_WIDTH_8       (0x00UL)   ///< Bus Data Width:  8 bit (default)
+#define ARM_NAND_BUS_DATA_WIDTH_16      (0x01UL)   ///< Bus Data Width: 16 bit
+
+/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_DRIVER_STRENGTH_18     (0x00UL)   ///< Driver Strength 2.0x = 18 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_25     (0x01UL)   ///< Driver Strength 1.4x = 25 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_35     (0x02UL)   ///< Driver Strength 1.0x = 35 Ohms (default)
+#define ARM_NAND_DRIVER_STRENGTH_50     (0x03UL)   ///< Driver Strength 0.7x = 50 Ohms
+
+
+/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_ECC_INDEX_Pos           0
+#define ARM_NAND_ECC_INDEX_Msk          (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
+#define ARM_NAND_ECC(n)                 ((n) & ARM_NAND_ECC_INDEX_Msk)     ///< Select ECC
+#define ARM_NAND_ECC0                   (1UL << 8)                         ///< Use ECC0 of selected ECC
+#define ARM_NAND_ECC1                   (1UL << 9)                         ///< Use ECC1 of selected ECC
+
+/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_DRIVER_DONE_EVENT      (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
+
+/****** NAND Sequence Execution Code *****/
+#define ARM_NAND_CODE_SEND_CMD1         (1UL << 17) ///< Send Command 1
+#define ARM_NAND_CODE_SEND_ADDR_COL1    (1UL << 18) ///< Send Column Address 1
+#define ARM_NAND_CODE_SEND_ADDR_COL2    (1UL << 19) ///< Send Column Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW1    (1UL << 20) ///< Send Row Address 1
+#define ARM_NAND_CODE_SEND_ADDR_ROW2    (1UL << 21) ///< Send Row Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW3    (1UL << 22) ///< Send Row Address 3
+#define ARM_NAND_CODE_INC_ADDR_ROW      (1UL << 23) ///< Auto-increment Row Address
+#define ARM_NAND_CODE_WRITE_DATA        (1UL << 24) ///< Write Data
+#define ARM_NAND_CODE_SEND_CMD2         (1UL << 25) ///< Send Command 2
+#define ARM_NAND_CODE_WAIT_BUSY         (1UL << 26) ///< Wait while R/Bn busy
+#define ARM_NAND_CODE_READ_DATA         (1UL << 27) ///< Read Data
+#define ARM_NAND_CODE_SEND_CMD3         (1UL << 28) ///< Send Command 3
+#define ARM_NAND_CODE_READ_STATUS       (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
+
+/*----- NAND Sequence Execution Code: Command -----*/
+#define ARM_NAND_CODE_CMD1_Pos           0
+#define ARM_NAND_CODE_CMD1_Msk          (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
+#define ARM_NAND_CODE_CMD2_Pos           8
+#define ARM_NAND_CODE_CMD2_Msk          (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
+#define ARM_NAND_CODE_CMD3_Pos           16
+#define ARM_NAND_CODE_CMD3_Msk          (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
+
+/*----- NAND Sequence Execution Code: Column Address -----*/
+#define ARM_NAND_CODE_ADDR_COL1_Pos      0
+#define ARM_NAND_CODE_ADDR_COL1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
+#define ARM_NAND_CODE_ADDR_COL2_Pos      8
+#define ARM_NAND_CODE_ADDR_COL2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
+
+/*----- NAND Sequence Execution Code: Row Address -----*/
+#define ARM_NAND_CODE_ADDR_ROW1_Pos      0
+#define ARM_NAND_CODE_ADDR_ROW1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
+#define ARM_NAND_CODE_ADDR_ROW2_Pos      8
+#define ARM_NAND_CODE_ADDR_ROW2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
+#define ARM_NAND_CODE_ADDR_ROW3_Pos      16
+#define ARM_NAND_CODE_ADDR_ROW3_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
+
+
+/****** NAND specific error codes *****/
+#define ARM_NAND_ERROR_ECC              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< ECC generation/correction failed
+
+
+/**
+\brief NAND ECC (Error Correction Code) Information
+*/
+typedef struct _ARM_NAND_ECC_INFO {
+  uint32_t type             :  2;       ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare
+  uint32_t page_layout      :  1;       ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|
+  uint32_t page_count       :  3;       ///< Number of virtual pages: N = 2 ^ page_count
+  uint32_t page_size        :  4;       ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description)
+  uint32_t reserved         : 14;       ///< Reserved (must be zero)
+  uint32_t correctable_bits :  8;       ///< Number of correctable bits (based on 512 byte codeword size)
+  uint16_t codeword_size     [2];       ///< Number of bytes over which ECC is calculated
+  uint16_t ecc_size          [2];       ///< ECC size in bytes (rounded up)
+  uint16_t ecc_offset        [2];       ///< ECC offset in bytes (where ECC starts in Spare)
+  /* Extended description */
+  uint16_t virtual_page_size [2];       ///< Virtual Page size in bytes (Main/Spare)
+  uint16_t codeword_offset   [2];       ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare)
+  uint16_t codeword_gap      [2];       ///< Codeword gap in bytes till next protected data
+  uint16_t ecc_gap           [2];       ///< ECC gap in bytes till next generated ECC
+} ARM_NAND_ECC_INFO;
+
+
+/**
+\brief NAND Status
+*/
+typedef struct _ARM_NAND_STATUS {
+  uint32_t busy      : 1;               ///< Driver busy flag
+  uint32_t ecc_error : 1;               ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
+  uint32_t reserved  : 30;
+} ARM_NAND_STATUS;
+
+
+/****** NAND Event *****/
+#define ARM_NAND_EVENT_DEVICE_READY     (1UL << 0)  ///< Device Ready: R/Bn rising edge
+#define ARM_NAND_EVENT_DRIVER_READY     (1UL << 1)  ///< Driver Ready
+#define ARM_NAND_EVENT_DRIVER_DONE      (1UL << 2)  ///< Driver operation done
+#define ARM_NAND_EVENT_ECC_ERROR        (1UL << 3)  ///< ECC could not correct data
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_NAND_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
+  \brief         Initialize the NAND Interface.
+  \param[in]     cb_event  Pointer to \ref ARM_NAND_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Uninitialize (void)
+  \brief         De-initialize the NAND Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
+  \brief         Control the NAND interface power.
+  \param[in]     state  Power state
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_DevicePower (uint32_t voltage)
+  \brief         Set device power supply voltage.
+  \param[in]     voltage  NAND Device supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
+  \brief         Control WPn (Write Protect).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Write Protect off
+                - \b true  Write Protect on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
+  \brief         Control CEn (Chip Enable).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Chip Enable off
+                - \b true  Chip Enable on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
+  \brief         Get Device Busy pin state.
+  \param[in]     dev_num  Device number
+  \return        1=busy, 0=not busy, or error
+*/
+/**
+  \fn            int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
+  \brief         Send command to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     cmd      Command
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
+  \brief         Send address to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     addr     Address
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
+  \brief         Read data from NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer for data to read from NAND device
+  \param[in]     cnt      Number of data items to read
+  \param[in]     mode     Operation mode
+  \return        number of data items read or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
+  \brief         Write data to NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer with data to write to NAND device
+  \param[in]     cnt      Number of data items to write
+  \param[in]     mode     Operation mode
+  \return        number of data items written or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                                   uint32_t addr_col, uint32_t addr_row,
+                                                   void *data, uint32_t data_cnt,
+                                                   uint8_t *status, uint32_t *count)
+  \brief         Execute sequence of operations.
+  \param[in]     dev_num  Device number
+  \param[in]     code     Sequence code
+  \param[in]     cmd      Command(s)
+  \param[in]     addr_col Column address
+  \param[in]     addr_row Row address
+  \param[in,out] data     Pointer to data to be written or read 
+  \param[in]     data_cnt Number of data items in one iteration
+  \param[out]    status   Pointer to status read
+  \param[in,out] count    Number of iterations
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
+  \brief         Abort sequence execution.
+  \param[in]     dev_num  Device number
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
+  \brief         Control NAND Interface.
+  \param[in]     dev_num  Device number
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
+  \brief         Get NAND status.
+  \param[in]     dev_num  Device number
+  \return        NAND status \ref ARM_NAND_STATUS
+*/
+/**
+  \fn            int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
+  \brief         Inquire about available ECC.
+  \param[in]     index   Inquire ECC index
+  \param[out]    info    Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
+  \return        \ref execution_status
+*/
+
+/**
+  \fn            void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
+  \brief         Signal NAND event.
+  \param[in]     dev_num  Device number
+  \param[in]     event    Event notification mask
+  \return        none
+*/
+
+typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event);    ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
+
+
+/**
+\brief NAND Driver Capabilities.
+*/
+typedef struct _ARM_NAND_CAPABILITIES {
+  uint32_t event_device_ready  : 1;     ///< Signal Device Ready event (R/Bn rising edge)
+  uint32_t reentrant_operation : 1;     ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
+  uint32_t sequence_operation  : 1;     ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
+  uint32_t vcc                 : 1;     ///< Supports VCC Power Supply Control
+  uint32_t vcc_1v8             : 1;     ///< Supports 1.8 VCC Power Supply
+  uint32_t vccq                : 1;     ///< Supports VCCQ I/O Power Supply Control
+  uint32_t vccq_1v8            : 1;     ///< Supports 1.8 VCCQ I/O Power Supply
+  uint32_t vpp                 : 1;     ///< Supports VPP High Voltage Power Supply Control
+  uint32_t wp                  : 1;     ///< Supports WPn (Write Protect) Control
+  uint32_t ce_lines            : 4;     ///< Number of CEn (Chip Enable) lines: ce_lines + 1
+  uint32_t ce_manual           : 1;     ///< Supports manual CEn (Chip Enable) Control
+  uint32_t rb_monitor          : 1;     ///< Supports R/Bn (Ready/Busy) Monitoring
+  uint32_t data_width_16       : 1;     ///< Supports 16-bit data
+  uint32_t ddr                 : 1;     ///< Supports NV-DDR  Data Interface (ONFI)
+  uint32_t ddr2                : 1;     ///< Supports NV-DDR2 Data Interface (ONFI)
+  uint32_t sdr_timing_mode     : 3;     ///< Fastest (highest) SDR     Timing Mode supported (ONFI)
+  uint32_t ddr_timing_mode     : 3;     ///< Fastest (highest) NV_DDR  Timing Mode supported (ONFI)
+  uint32_t ddr2_timing_mode    : 3;     ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
+  uint32_t driver_strength_18  : 1;     ///< Supports Driver Strength 2.0x = 18 Ohms
+  uint32_t driver_strength_25  : 1;     ///< Supports Driver Strength 1.4x = 25 Ohms
+  uint32_t driver_strength_50  : 1;     ///< Supports Driver Strength 0.7x = 50 Ohms
+  uint32_t reserved            : 2;     ///< Reserved (must be zero)
+} ARM_NAND_CAPABILITIES;
+
+
+/**
+\brief Access structure of the NAND Driver.
+*/
+typedef struct _ARM_DRIVER_NAND {
+  ARM_DRIVER_VERSION    (*GetVersion)     (void);                                                             ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
+  ARM_NAND_CAPABILITIES (*GetCapabilities)(void);                                                             ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)     (ARM_NAND_SignalEvent_t cb_event);                                  ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
+  int32_t               (*Uninitialize)   (void);                                                             ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
+  int32_t               (*PowerControl)   (ARM_POWER_STATE state);                                            ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
+  int32_t               (*DevicePower)    (uint32_t voltage);                                                 ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
+  int32_t               (*WriteProtect)   (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
+  int32_t               (*ChipEnable)     (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
+  int32_t               (*GetDeviceBusy)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
+  int32_t               (*SendCommand)    (uint32_t dev_num, uint8_t cmd);                                    ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
+  int32_t               (*SendAddress)    (uint32_t dev_num, uint8_t addr);                                   ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
+  int32_t               (*ReadData)       (uint32_t dev_num,       void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
+  int32_t               (*WriteData)      (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
+  int32_t               (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                           uint32_t addr_col, uint32_t addr_row,
+                                           void *data, uint32_t data_cnt,
+                                           uint8_t *status, uint32_t *count);                                 ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
+  int32_t               (*AbortSequence)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. 
+  int32_t               (*Control)        (uint32_t dev_num, uint32_t control, uint32_t arg);                 ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
+  ARM_NAND_STATUS       (*GetStatus)      (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
+  int32_t               (*InquireECC)     ( int32_t index, ARM_NAND_ECC_INFO *info);                          ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. 
+} const ARM_DRIVER_NAND;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_NAND_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_SAI.h

@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V1.2
+ *
+ * Project:      SAI (Serial Audio Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 1.2
+ *    Removed volatile from ARM_SAI_STATUS
+ *  Version 1.1
+ *    ARM_SAI_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_SAI_H_
+#define DRIVER_SAI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */
+
+
+#define _ARM_Driver_SAI_(n)      Driver_SAI##n
+#define  ARM_Driver_SAI_(n) _ARM_Driver_SAI_(n)
+
+
+/****** SAI Control Codes *****/
+
+#define ARM_SAI_CONTROL_Msk             (0xFFUL)
+#define ARM_SAI_CONFIGURE_TX            (0x01UL)    ///< Configure Transmitter;  arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONFIGURE_RX            (0x02UL)    ///< Configure Receiver;     arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONTROL_TX              (0x03UL)    ///< Control Transmitter;    arg1.0: 0=disable (default), 1=enable; arg1.1: mute
+#define ARM_SAI_CONTROL_RX              (0x04UL)    ///< Control Receiver;       arg1.0: 0=disable (default), 1=enable
+#define ARM_SAI_MASK_SLOTS_TX           (0x05UL)    ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_MASK_SLOTS_RX           (0x06UL)    ///< Mask Receiver    slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_ABORT_SEND              (0x07UL)    ///< Abort \ref ARM_SAI_Send
+#define ARM_SAI_ABORT_RECEIVE           (0x08UL)    ///< Abort \ref ARM_SAI_Receive
+
+/*----- SAI Control Codes: Configuration Parameters: Mode -----*/
+#define ARM_SAI_MODE_Pos                 8
+#define ARM_SAI_MODE_Msk                (1UL << ARM_SAI_MODE_Pos)
+#define ARM_SAI_MODE_MASTER             (1UL << ARM_SAI_MODE_Pos)               ///< Master Mode
+#define ARM_SAI_MODE_SLAVE              (0UL << ARM_SAI_MODE_Pos)               ///< Slave Mode (default)
+
+/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/
+#define ARM_SAI_SYNCHRONIZATION_Pos      9
+#define ARM_SAI_SYNCHRONIZATION_Msk     (1UL << ARM_SAI_SYNCHRONIZATION_Pos)
+#define ARM_SAI_ASYNCHRONOUS            (0UL << ARM_SAI_SYNCHRONIZATION_Pos)    ///< Asynchronous (default)
+#define ARM_SAI_SYNCHRONOUS             (1UL << ARM_SAI_SYNCHRONIZATION_Pos)    ///< Synchronous
+
+/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/
+#define ARM_SAI_PROTOCOL_Pos             10
+#define ARM_SAI_PROTOCOL_Msk            (7UL << ARM_SAI_PROTOCOL_Pos)
+#define ARM_SAI_PROTOCOL_USER           (0UL << ARM_SAI_PROTOCOL_Pos)           ///< User defined (default) 
+#define ARM_SAI_PROTOCOL_I2S            (1UL << ARM_SAI_PROTOCOL_Pos)           ///< I2S
+#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED  (2UL << ARM_SAI_PROTOCOL_Pos)           ///< MSB (left) justified 
+#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED  (3UL << ARM_SAI_PROTOCOL_Pos)           ///< LSB (right) justified
+#define ARM_SAI_PROTOCOL_PCM_SHORT      (4UL << ARM_SAI_PROTOCOL_Pos)           ///< PCM with short frame
+#define ARM_SAI_PROTOCOL_PCM_LONG       (5UL << ARM_SAI_PROTOCOL_Pos)           ///< PCM with long frame
+#define ARM_SAI_PROTOCOL_AC97           (6UL << ARM_SAI_PROTOCOL_Pos)           ///< AC'97
+
+/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/
+#define ARM_SAI_DATA_SIZE_Pos            13
+#define ARM_SAI_DATA_SIZE_Msk                      (0x1FUL  << ARM_SAI_DATA_SIZE_Pos)
+#define ARM_SAI_DATA_SIZE(n)            ((((n)-1UL)&0x1FUL) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32)
+
+/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/
+#define ARM_SAI_BIT_ORDER_Pos            18
+#define ARM_SAI_BIT_ORDER_Msk           (1UL << ARM_SAI_BIT_ORDER_Pos)
+#define ARM_SAI_MSB_FIRST               (0UL << ARM_SAI_BIT_ORDER_Pos)          ///< Data is transferred with MSB first (default)
+#define ARM_SAI_LSB_FIRST               (1UL << ARM_SAI_BIT_ORDER_Pos)          ///< Data is transferred with LSB first; User Protocol only (ignored otherwise)
+
+/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/
+#define ARM_SAI_MONO_MODE               (1UL << 19)                             ///< Mono Mode (only for I2S, MSB/LSB justified)
+
+/*----- SAI Control Codes:Configuration Parameters: Companding -----*/
+#define ARM_SAI_COMPANDING_Pos           20
+#define ARM_SAI_COMPANDING_Msk          (3UL << ARM_SAI_COMPANDING_Pos)
+#define ARM_SAI_COMPANDING_NONE         (0UL << ARM_SAI_COMPANDING_Pos)         ///< No companding (default)
+#define ARM_SAI_COMPANDING_A_LAW        (2UL << ARM_SAI_COMPANDING_Pos)         ///< A-Law companding
+#define ARM_SAI_COMPANDING_U_LAW        (3UL << ARM_SAI_COMPANDING_Pos)         ///< u-Law companding
+
+/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/
+#define ARM_SAI_CLOCK_POLARITY_Pos       23
+#define ARM_SAI_CLOCK_POLARITY_Msk      (1UL << ARM_SAI_CLOCK_POLARITY_Pos)
+#define ARM_SAI_CLOCK_POLARITY_0        (0UL << ARM_SAI_CLOCK_POLARITY_Pos)     ///< Drive on falling edge, Capture on rising  edge (default)
+#define ARM_SAI_CLOCK_POLARITY_1        (1UL << ARM_SAI_CLOCK_POLARITY_Pos)     ///< Drive on rising  edge, Capture on falling edge
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/
+#define ARM_SAI_MCLK_PIN_Pos             24
+#define ARM_SAI_MCLK_PIN_Msk            (3UL << ARM_SAI_MCLK_PIN_Pos)
+#define ARM_SAI_MCLK_PIN_INACTIVE       (0UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK not used (default)
+#define ARM_SAI_MCLK_PIN_OUTPUT         (1UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK is output (Master only)
+#define ARM_SAI_MCLK_PIN_INPUT          (2UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK is input  (Master only)
+
+
+/****** SAI Configuration (arg1) *****/
+
+/*----- SAI Configuration (arg1): Frame Length -----*/
+#define ARM_SAI_FRAME_LENGTH_Pos          0
+#define ARM_SAI_FRAME_LENGTH_Msk                    (0x3FFUL  << ARM_SAI_FRAME_LENGTH_Pos)
+#define ARM_SAI_FRAME_LENGTH(n)          ((((n)-1UL)&0x3FFUL) << ARM_SAI_FRAME_LENGTH_Pos)  ///< Frame length in bits (8..1024); default depends on protocol and data
+
+/*----- SAI Configuration (arg1): Frame Sync Width -----*/
+#define ARM_SAI_FRAME_SYNC_WIDTH_Pos      10
+#define ARM_SAI_FRAME_SYNC_WIDTH_Msk                (0xFFUL  << ARM_SAI_FRAME_SYNC_WIDTH_Pos)
+#define ARM_SAI_FRAME_SYNC_WIDTH(n)      ((((n)-1UL)&0xFFUL) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/
+#define ARM_SAI_FRAME_SYNC_POLARITY_Pos   18
+#define ARM_SAI_FRAME_SYNC_POLARITY_Msk  (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)
+#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)           ///< Frame Sync is active high (default); User Protocol only (ignored otherwise)
+#define ARM_SAI_FRAME_SYNC_POLARITY_LOW  (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)           ///< Frame Sync is active low; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Early -----*/
+#define ARM_SAI_FRAME_SYNC_EARLY         (1UL << 19)                                        ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Count -----*/
+#define ARM_SAI_SLOT_COUNT_Pos            20
+#define ARM_SAI_SLOT_COUNT_Msk                      (0x1FUL  << ARM_SAI_SLOT_COUNT_Pos)
+#define ARM_SAI_SLOT_COUNT(n)            ((((n)-1UL)&0x1FUL) << ARM_SAI_SLOT_COUNT_Pos)     ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Size -----*/
+#define ARM_SAI_SLOT_SIZE_Pos             25
+#define ARM_SAI_SLOT_SIZE_Msk            (3UL << ARM_SAI_SLOT_SIZE_Pos)
+#define ARM_SAI_SLOT_SIZE_DEFAULT        (0UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size is equal to data size (default)
+#define ARM_SAI_SLOT_SIZE_16             (1UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size = 16 bits; User Protocol only (ignored otherwise)
+#define ARM_SAI_SLOT_SIZE_32             (3UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size = 32 bits; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Offset -----*/
+#define ARM_SAI_SLOT_OFFSET_Pos           27
+#define ARM_SAI_SLOT_OFFSET_Msk               (0x1FUL  << ARM_SAI_SLOT_OFFSET_Pos)
+#define ARM_SAI_SLOT_OFFSET(n)           (((n)&0x1FUL) << ARM_SAI_SLOT_OFFSET_Pos)          ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise)
+
+/****** SAI Configuration (arg2) *****/
+
+/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/
+#define ARM_SAI_AUDIO_FREQ_Msk          (0x0FFFFFUL)                                        ///< Audio frequency mask
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/
+#define ARM_SAI_MCLK_PRESCALER_Pos       20
+#define ARM_SAI_MCLK_PRESCALER_Msk      (0xFFFUL << ARM_SAI_MCLK_PRESCALER_Pos)
+#define ARM_SAI_MCLK_PRESCALER(n)       ((((n)-1UL)&0xFFFUL) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1)
+
+
+/****** SAI specific error codes *****/
+#define ARM_SAI_ERROR_SYNCHRONIZATION       (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Synchronization not supported
+#define ARM_SAI_ERROR_PROTOCOL              (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Protocol not supported
+#define ARM_SAI_ERROR_DATA_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified Data size not supported
+#define ARM_SAI_ERROR_BIT_ORDER             (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SAI_ERROR_MONO_MODE             (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Mono mode not supported
+#define ARM_SAI_ERROR_COMPANDING            (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Companding not supported
+#define ARM_SAI_ERROR_CLOCK_POLARITY        (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock polarity not supported
+#define ARM_SAI_ERROR_AUDIO_FREQ            (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Audio frequency not supported
+#define ARM_SAI_ERROR_MCLK_PIN              (ARM_DRIVER_ERROR_SPECIFIC - 9)     ///< Specified MCLK Pin setting not supported
+#define ARM_SAI_ERROR_MCLK_PRESCALER        (ARM_DRIVER_ERROR_SPECIFIC - 10)    ///< Specified MCLK Prescaler not supported
+#define ARM_SAI_ERROR_FRAME_LENGTH          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported
+#define ARM_SAI_ERROR_FRAME_LENGHT          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported @deprecated use \ref ARM_SAI_ERROR_FRAME_LENGTH instead
+#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH      (ARM_DRIVER_ERROR_SPECIFIC - 12)    ///< Specified Frame Sync width not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY   (ARM_DRIVER_ERROR_SPECIFIC - 13)    ///< Specified Frame Sync polarity not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_EARLY      (ARM_DRIVER_ERROR_SPECIFIC - 14)    ///< Specified Frame Sync early not supported
+#define ARM_SAI_ERROR_SLOT_COUNT            (ARM_DRIVER_ERROR_SPECIFIC - 15)    ///< Specified Slot count not supported
+#define ARM_SAI_ERROR_SLOT_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 16)    ///< Specified Slot size not supported
+#define ARM_SAI_ERROR_SLOT_OFFESET          (ARM_DRIVER_ERROR_SPECIFIC - 17)    ///< Specified Slot offset not supported
+
+
+/**
+\brief SAI Status
+*/
+typedef struct _ARM_SAI_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t frame_error      : 1;        ///< Sync Frame error detected (cleared on start of next send/receive operation)
+  uint32_t reserved         : 27;
+} ARM_SAI_STATUS;
+
+
+/****** SAI Event *****/
+#define ARM_SAI_EVENT_SEND_COMPLETE     (1UL << 0)  ///< Send completed
+#define ARM_SAI_EVENT_RECEIVE_COMPLETE  (1UL << 1)  ///< Receive completed
+#define ARM_SAI_EVENT_TX_UNDERFLOW      (1UL << 2)  ///< Transmit data not available
+#define ARM_SAI_EVENT_RX_OVERFLOW       (1UL << 3)  ///< Receive data overflow
+#define ARM_SAI_EVENT_FRAME_ERROR       (1UL << 4)  ///< Sync Frame error in Slave mode (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SAI_CAPABILITIES
+
+  \fn          int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
+  \brief       Initialize SAI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SAI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Uninitialize (void)
+  \brief       De-initialize SAI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SAI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SAI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SAI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SAI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SAI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SAI_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_SAI_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
+  \brief       Control SAI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg1     Argument 1 of operation (optional)
+  \param[in]   arg2     Argument 2 of operation (optional)
+  \return      common \ref execution_status and driver specific \ref sai_execution_status
+
+  \fn          ARM_SAI_STATUS ARM_SAI_GetStatus (void)
+  \brief       Get SAI status.
+  \return      SAI status \ref ARM_SAI_STATUS
+
+  \fn          void ARM_SAI_SignalEvent (uint32_t event)
+  \brief       Signal SAI Events.
+  \param[in]   event \ref SAI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event.
+
+
+/**
+\brief SAI Driver Capabilities.
+*/
+typedef struct _ARM_SAI_CAPABILITIES {
+  uint32_t asynchronous          : 1;   ///< supports asynchronous Transmit/Receive
+  uint32_t synchronous           : 1;   ///< supports synchronous Transmit/Receive
+  uint32_t protocol_user         : 1;   ///< supports user defined Protocol
+  uint32_t protocol_i2s          : 1;   ///< supports I2S Protocol
+  uint32_t protocol_justified    : 1;   ///< supports MSB/LSB justified Protocol
+  uint32_t protocol_pcm          : 1;   ///< supports PCM short/long frame Protocol
+  uint32_t protocol_ac97         : 1;   ///< supports AC'97 Protocol
+  uint32_t mono_mode             : 1;   ///< supports Mono mode
+  uint32_t companding            : 1;   ///< supports Companding
+  uint32_t mclk_pin              : 1;   ///< supports MCLK (Master Clock) pin
+  uint32_t event_frame_error     : 1;   ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
+  uint32_t reserved              : 21;  ///< Reserved (must be zero)
+} ARM_SAI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SAI Driver.
+*/
+typedef struct _ARM_DRIVER_SAI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                                            ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version.
+  ARM_SAI_CAPABILITIES (*GetCapabilities) (void);                                            ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SAI_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface.
+  int32_t              (*Uninitialize)    (void);                                            ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);                           ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface.
+  uint32_t             (*GetTxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count.
+  uint32_t             (*GetRxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg1, uint32_t arg2);  ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface.
+  ARM_SAI_STATUS       (*GetStatus)       (void);                                            ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status.
+} const ARM_DRIVER_SAI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SAI_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_SPI.h

@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.3
+ *
+ * Project:      SPI (Serial Peripheral Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Removed Simplex Mode (deprecated)
+ *    Removed volatile from ARM_SPI_STATUS
+ *  Version 2.2
+ *    ARM_SPI_STATUS made volatile
+ *  Version 2.1
+ *    Renamed status flag "tx_rx_busy" to "busy"
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *      Half-duplex Modes
+ *      Configurable number of data bits
+ *      Support for TI Mode and Microwire
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added "send_done_event" to Capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_SPI_H_
+#define DRIVER_SPI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_SPI_(n)      Driver_SPI##n
+#define  ARM_Driver_SPI_(n) _ARM_Driver_SPI_(n)
+
+
+/****** SPI Control Codes *****/
+
+#define ARM_SPI_CONTROL_Pos              0
+#define ARM_SPI_CONTROL_Msk             (0xFFUL << ARM_SPI_CONTROL_Pos)
+
+/*----- SPI Control Codes: Mode -----*/
+#define ARM_SPI_MODE_INACTIVE           (0x00UL << ARM_SPI_CONTROL_Pos)     ///< SPI Inactive
+#define ARM_SPI_MODE_MASTER             (0x01UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE              (0x02UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output on MISO, Input on MOSI)
+#define ARM_SPI_MODE_MASTER_SIMPLEX     (0x03UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps @deprecated Simplex Mode has been removed
+#define ARM_SPI_MODE_SLAVE_SIMPLEX      (0x04UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output/Input on MISO) @deprecated Simplex Mode has been removed
+
+/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
+#define ARM_SPI_FRAME_FORMAT_Pos         8
+#define ARM_SPI_FRAME_FORMAT_Msk        (7UL << ARM_SPI_FRAME_FORMAT_Pos)
+#define ARM_SPI_CPOL0_CPHA0             (0UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 0 (default)
+#define ARM_SPI_CPOL0_CPHA1             (1UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 1
+#define ARM_SPI_CPOL1_CPHA0             (2UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 0
+#define ARM_SPI_CPOL1_CPHA1             (3UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 1
+#define ARM_SPI_TI_SSI                  (4UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Texas Instruments Frame Format
+#define ARM_SPI_MICROWIRE               (5UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< National Semiconductor Microwire Frame Format
+
+/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_SPI_DATA_BITS_Pos            12
+#define ARM_SPI_DATA_BITS_Msk           (0x3FUL << ARM_SPI_DATA_BITS_Pos)
+#define ARM_SPI_DATA_BITS(n)            (((n) & 0x3FUL) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits
+
+/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
+#define ARM_SPI_BIT_ORDER_Pos            18
+#define ARM_SPI_BIT_ORDER_Msk           (1UL << ARM_SPI_BIT_ORDER_Pos)
+#define ARM_SPI_MSB_LSB                 (0UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from MSB to LSB (default)
+#define ARM_SPI_LSB_MSB                 (1UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from LSB to MSB
+
+/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
+#define ARM_SPI_SS_MASTER_MODE_Pos       19
+#define ARM_SPI_SS_MASTER_MODE_Msk      (3UL << ARM_SPI_SS_MASTER_MODE_Pos)
+#define ARM_SPI_SS_MASTER_UNUSED        (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)
+#define ARM_SPI_SS_MASTER_SW            (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled
+#define ARM_SPI_SS_MASTER_HW_OUTPUT     (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output
+#define ARM_SPI_SS_MASTER_HW_INPUT      (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input
+#define ARM_SPI_SS_SLAVE_MODE_Pos        21
+#define ARM_SPI_SS_SLAVE_MODE_Msk       (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)
+#define ARM_SPI_SS_SLAVE_HW             (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Hardware monitored (default)
+#define ARM_SPI_SS_SLAVE_SW             (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Software controlled
+
+
+/*----- SPI Control Codes: Miscellaneous Controls  -----*/
+#define ARM_SPI_SET_BUS_SPEED           (0x10UL << ARM_SPI_CONTROL_Pos)     ///< Set Bus Speed in bps; arg = value
+#define ARM_SPI_GET_BUS_SPEED           (0x11UL << ARM_SPI_CONTROL_Pos)     ///< Get Bus Speed in bps
+#define ARM_SPI_SET_DEFAULT_TX_VALUE    (0x12UL << ARM_SPI_CONTROL_Pos)     ///< Set default Transmit value; arg = value
+#define ARM_SPI_CONTROL_SS              (0x13UL << ARM_SPI_CONTROL_Pos)     ///< Control Slave Select; arg: 0=inactive, 1=active 
+#define ARM_SPI_ABORT_TRANSFER          (0x14UL << ARM_SPI_CONTROL_Pos)     ///< Abort current data transfer
+
+
+/****** SPI Slave Select Signal definitions *****/
+#define ARM_SPI_SS_INACTIVE              0UL                                ///< SPI Slave Select Signal Inactive
+#define ARM_SPI_SS_ACTIVE                1UL                                ///< SPI Slave Select Signal Active
+
+
+/****** SPI specific error codes *****/
+#define ARM_SPI_ERROR_MODE              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_SPI_ERROR_FRAME_FORMAT      (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Frame Format not supported
+#define ARM_SPI_ERROR_DATA_BITS         (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_SPI_ERROR_BIT_ORDER         (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SPI_ERROR_SS_MODE           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Slave Select Mode not supported
+
+
+/**
+\brief SPI Status
+*/
+typedef struct _ARM_SPI_STATUS {
+  uint32_t busy       : 1;              ///< Transmitter/Receiver busy flag
+  uint32_t data_lost  : 1;              ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
+  uint32_t mode_fault : 1;              ///< Mode fault detected; optional (cleared on start of transfer operation)
+  uint32_t reserved   : 29;
+} ARM_SPI_STATUS;
+
+
+/****** SPI Event *****/
+#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0)  ///< Data Transfer completed
+#define ARM_SPI_EVENT_DATA_LOST         (1UL << 1)  ///< Data lost: Receive overflow / Transmit underflow
+#define ARM_SPI_EVENT_MODE_FAULT        (1UL << 2)  ///< Master Mode Fault (SS deactivated when Master)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SPI_CAPABILITIES
+
+  \fn          int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)
+  \brief       Initialize SPI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SPI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Uninitialize (void)
+  \brief       De-initialize SPI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SPI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SPI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SPI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SPI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Transfer (const void *data_out,
+                                               void *data_in,
+                                         uint32_t    num)
+  \brief       Start sending/receiving data to/from SPI transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to SPI transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SPI_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data items transferred
+
+  \fn          int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)
+  \brief       Control SPI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref spi_execution_status
+
+  \fn          ARM_SPI_STATUS ARM_SPI_GetStatus (void)
+  \brief       Get SPI status.
+  \return      SPI status \ref ARM_SPI_STATUS
+
+  \fn          void ARM_SPI_SignalEvent (uint32_t event)
+  \brief       Signal SPI Events.
+  \param[in]   event \ref SPI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event.
+
+
+/**
+\brief SPI Driver Capabilities.
+*/
+typedef struct _ARM_SPI_CAPABILITIES {
+  uint32_t simplex          : 1;        ///< supports Simplex Mode (Master and Slave) @deprecated Reserved (must be zero)
+  uint32_t ti_ssi           : 1;        ///< supports TI Synchronous Serial Interface
+  uint32_t microwire        : 1;        ///< supports Microwire Interface
+  uint32_t event_mode_fault : 1;        ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
+  uint32_t reserved         : 28;       ///< Reserved (must be zero)
+} ARM_SPI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SPI Driver.
+*/
+typedef struct _ARM_DRIVER_SPI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                             ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version.
+  ARM_SPI_CAPABILITIES (*GetCapabilities) (void);                             ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SPI_SignalEvent_t cb_event);   ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface.
+  int32_t              (*Uninitialize)    (void);                             ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);            ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface.
+  int32_t              (*Transfer)        (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num);                  ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.
+  uint32_t             (*GetDataCount)    (void);                             ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg);   ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface.
+  ARM_SPI_STATUS       (*GetStatus)       (void);                             ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status.
+} const ARM_DRIVER_SPI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SPI_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_Storage.h

@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V1.2
+ *
+ * Project:      Storage Driver definitions
+ */
+
+/* History:
+ *  Version 1.2
+ *    Removed volatile from ARM_STORAGE_STATUS
+ *  Version 1.1
+ *    ARM_STORAGE_STATUS made volatile
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_STORAGE_H_
+#define DRIVER_STORAGE_H_
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */
+
+
+#define _ARM_Driver_Storage_(n)      Driver_Storage##n
+#define  ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
+
+#define ARM_STORAGE_INVALID_OFFSET  (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
+                                                            ///  address space). A storage block may never start at this address.
+
+#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL)          ///< Invalid address within the processor's memory address space.
+                                                            ///  Refer to memory-mapped storage, i.e. \ref ARM_DRIVER_STORAGE::ResolveAddress().
+
+/****** Storage specific error codes *****/
+#define ARM_STORAGE_ERROR_NOT_ERASABLE      (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
+#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE  (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
+#define ARM_STORAGE_ERROR_PROTECTED         (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
+
+/**
+ * \brief Attributes of the storage range within a storage block.
+ */
+typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
+  uint32_t erasable      :  1;   ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
+                                 ///   @note if 'erasable' is 0 (i.e. the 'erase' operation isn't available) then
+                                 ///   'erase_unit' (see below) is immaterial and should be 0.
+  uint32_t programmable  :  1;   ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
+                                 ///    Writes are typically achieved through the ProgramData operation (following an erase);
+                                 ///    if storage isn't erasable (see 'erasable' above) but is memory-mapped
+                                 ///    (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
+  uint32_t executable    :  1;   ///< This storage block can hold program data; the processor can fetch and execute code
+                                 ///    sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
+  uint32_t protectable   :  1;   ///< The entire block can be protected from program and erase operations. Once protection
+                                 ///    is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
+  uint32_t reserved      : 28;
+  uint32_t erase_unit;           ///< Minimum erase size in bytes.
+                                 ///    The offset of the start of the erase-range should also be aligned with this value.
+                                 ///    Applicable if the 'erasable' attribute is set for the block.
+                                 ///    @note if 'erasable' (see above) is 0 (i.e. the 'erase' operation isn't available) then
+                                 ///    'erase_unit' is immaterial and should be 0.
+  uint32_t protection_unit;      ///< Minimum protectable size in bytes. Applicable if the 'protectable'
+                                 ///    attribute is set for the block. This should be a divisor of the block's size. A
+                                 ///    block can be considered to be made up of consecutive, individually-protectable fragments.
+} ARM_STORAGE_BLOCK_ATTRIBUTES;
+
+/**
+ * \brief A storage block is a range of memory with uniform attributes.
+ */
+typedef struct _ARM_STORAGE_BLOCK {
+  uint64_t                     addr;       ///< This is the start address of the storage block. It is
+                                           ///    expressed as an offset from the start of the storage map
+                                           ///    maintained by the owning storage controller.
+  uint64_t                     size;       ///< This is the size of the storage block, in units of bytes.
+                                           ///    Together with addr, it describes a range [addr, addr+size).
+  ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
+} ARM_STORAGE_BLOCK;
+
+/**
+ * The check for a valid ARM_STORAGE_BLOCK.
+ */
+#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
+
+/**
+ * \brief Values for encoding storage memory-types with respect to programmability.
+ *
+ * Please ensure that the maximum of the following memory types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
+ */
+#define ARM_STORAGE_PROGRAMMABILITY_RAM       (0U)
+#define ARM_STORAGE_PROGRAMMABILITY_ROM       (1U)  ///< Read-only memory.
+#define ARM_STORAGE_PROGRAMMABILITY_WORM      (2U)  ///< write-once-read-only-memory (WORM).
+#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE  (3U)  ///< re-programmable based on erase. Supports multiple writes.
+
+/**
+ * Values for encoding data-retention levels for storage blocks.
+ *
+ * Please ensure that the maximum of the following retention types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
+ */
+#define ARM_RETENTION_WHILE_DEVICE_ACTIVE     (0U)  ///< Data is retained only during device activity.
+#define ARM_RETENTION_ACROSS_SLEEP            (1U)  ///< Data is retained across processor sleep.
+#define ARM_RETENTION_ACROSS_DEEP_SLEEP       (2U)  ///< Data is retained across processor deep-sleep.
+#define ARM_RETENTION_BATTERY_BACKED          (3U)  ///< Data is battery-backed. Device can be powered off.
+#define ARM_RETENTION_NVM                     (4U)  ///< Data is retained in non-volatile memory.
+
+/**
+ * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
+ */
+typedef struct _ARM_STORAGE_SECURITY_FEATURES {
+  uint32_t acls                :  1; ///< Protection against internal software attacks using ACLs.
+  uint32_t rollback_protection :  1; ///< Roll-back protection. Set to true if the creator of the storage
+                                     ///    can ensure that an external attacker can't force an
+                                     ///    older firmware to run or to revert back to a previous state.
+  uint32_t tamper_proof        :  1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
+  uint32_t internal_flash      :  1; ///< Internal flash.
+  uint32_t reserved1           : 12;
+
+  /**
+   * Encode support for hardening against various classes of attacks.
+   */
+  uint32_t software_attacks     :  1; ///< device software (malware running on the device).
+  uint32_t board_level_attacks  :  1; ///< board level attacks (debug probes, copy protection fuses.)
+  uint32_t chip_level_attacks   :  1; ///< chip level attacks (tamper-protection).
+  uint32_t side_channel_attacks :  1; ///< side channel attacks.
+  uint32_t reserved2            : 12;
+} ARM_STORAGE_SECURITY_FEATURES;
+
+#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
+
+/**
+ * Device level metadata regarding the Storage implementation.
+ */
+typedef struct _ARM_STORAGE_INFO {
+  uint64_t                      total_storage;        ///< Total available storage, in bytes.
+  uint32_t                      program_unit;         ///< Minimum programming size in bytes.
+                                                      ///    The offset of the start of the program-range should also be aligned with this value.
+                                                      ///    Applicable only if the 'programmable' attribute is set for a block.
+                                                      ///    @note setting program_unit to 0 has the effect of disabling the size and alignment
+                                                      ///    restrictions (setting it to 1 also has the same effect).
+  uint32_t                      optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
+                                                      ///    have internal buffers into which to receive data. Writing in chunks of
+                                                      ///    'optimal_program_unit' would achieve maximum programming speed.
+                                                      ///    Applicable only if the 'programmable' attribute is set for the underlying block(s).
+  uint32_t                      program_cycles;       ///< A measure of endurance for reprogramming.
+                                                      ///    Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
+  uint32_t                      erased_value    :  1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
+  uint32_t                      memory_mapped   :  1; ///< This storage device has a mapping onto the processor's memory address space.
+                                                      ///    @note For a memory-mapped block which isn't erasable but is programmable (i.e. if
+                                                      ///    'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
+                                                      ///    the memory-mapped storage without going through the ProgramData operation.
+  uint32_t                      programmability :  4; ///< A value to indicate storage programmability.
+  uint32_t                      retention_level :  4;
+  uint32_t                      reserved        : 22;
+  ARM_STORAGE_SECURITY_FEATURES security;             ///< \ref ARM_STORAGE_SECURITY_FEATURES
+} ARM_STORAGE_INFO;
+
+/**
+\brief Operating status of the storage controller.
+*/
+typedef struct _ARM_STORAGE_STATUS {
+  uint32_t busy     : 1;                ///< Controller busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_STORAGE_STATUS;
+
+/**
+ * \brief Storage Driver API Capabilities.
+ */
+typedef struct _ARM_STORAGE_CAPABILITIES {
+  uint32_t asynchronous_ops :  1; ///< Used to indicate if APIs like initialize,
+                                  ///    read, erase, program, etc. can operate in asynchronous mode.
+                                  ///    Setting this bit to 1 means that the driver is capable
+                                  ///    of launching asynchronous operations; command completion is
+                                  ///    signaled by the invocation of a completion callback. If
+                                  ///    set to 1, drivers may still complete asynchronous
+                                  ///    operations synchronously as necessary (in which case they
+                                  ///    return a positive error code to indicate synchronous completion).
+  uint32_t erase_all        :  1; ///< Supports EraseAll operation.
+  uint32_t reserved         : 30; ///< Reserved (must be zero)
+} ARM_STORAGE_CAPABILITIES;
+
+/**
+ * Command opcodes for Storage.
+ */
+typedef enum _ARM_STORAGE_OPERATION {
+  ARM_STORAGE_OPERATION_GET_VERSION,
+  ARM_STORAGE_OPERATION_GET_CAPABILITIES,
+  ARM_STORAGE_OPERATION_INITIALIZE,
+  ARM_STORAGE_OPERATION_UNINITIALIZE,
+  ARM_STORAGE_OPERATION_POWER_CONTROL,
+  ARM_STORAGE_OPERATION_READ_DATA,
+  ARM_STORAGE_OPERATION_PROGRAM_DATA,
+  ARM_STORAGE_OPERATION_ERASE,
+  ARM_STORAGE_OPERATION_ERASE_ALL,
+  ARM_STORAGE_OPERATION_GET_STATUS,
+  ARM_STORAGE_OPERATION_GET_INFO,
+  ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
+  ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
+  ARM_STORAGE_OPERATION_GET_BLOCK
+} ARM_STORAGE_OPERATION;
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_STORAGE_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)
+  \brief       Initialize the Storage interface.
+  \param [in]  callback Pointer to \ref ARM_Storage_Callback_t.
+               Caller-defined callback to be invoked upon command completion
+               for asynchronous APIs (including the completion of
+               initialization). Use a NULL pointer when no callback
+               signals are required.
+  \return      If asynchronous activity is launched, invocation
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_Uninitialize (void)
+  \brief       De-initialize the Storage Interface.
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Storage interface power.
+  \param[in]   state  Power state
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)
+  \brief       Read data from Storage.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Storage.
+  \param[in]   size  Number of bytes to read. The data buffer
+               should be at least as large as this size.
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with the number of successfully transferred bytes passed in as
+               the 'status' parameter. In the case of synchronous execution, control
+               returns after completion with a positive transfer-count. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)
+  \brief       Program data to Storage.
+  \param [in] addr This is the start address of the range to be written into. It
+               needs to be aligned to the device's \em program_unit
+               specified in \ref ARM_STORAGE_INFO.
+  \param [in] data The source of the write operation. The buffer is owned by the
+               caller and should remain accessible for the lifetime of this
+               command.
+  \param [in] size The number of bytes requested to be written. The buffer
+               should be at least as large as this size. \note 'size' should
+               be a multiple of the device's 'program_unit' (see \ref
+               ARM_STORAGE_INFO).
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with the number of successfully transferred bytes passed in as
+               the 'status' parameter. In the case of synchronous execution, control
+               returns after completion with a positive transfer-count. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)
+  \brief       Erase Storage range.
+  \param [in]  addr This is the start-address of the range to be erased. It must
+               start at an 'erase_unit' boundary of the underlying block.
+  \param [in]  size Size (in bytes) of the range to be erased. 'addr + size'
+               must be aligned with the 'erase_unit' of the underlying
+               block.
+  \return      If the range to be erased doesn't align with the erase_units of the
+               respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is
+               returned. If any part of the range is protected,
+               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the range
+               is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
+               such sanity-check failures result in the error code being
+               returned synchronously and the storage bytes within the range
+               remain unaffected. Otherwise the function executes in the
+               following ways: If asynchronous activity is launched, an
+               invocation returns ARM_DRIVER_OK, and the caller can expect to
+               receive a callback in the future with the number of successfully
+               erased bytes passed in as the 'status' parameter. In the case of
+               synchronous execution, control returns after completion with a
+               positive erase-count. Return values less than ARM_DRIVER_OK (0)
+               signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_EraseAll (void)
+  \brief       Erase complete Storage.
+  \return      If any part of the storage range is protected,
+               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the
+               storage range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is
+               returned. All such sanity-check failures result in the error code
+               being returned synchronously and the storage bytes within the
+               range remain unaffected. Otherwise the function executes in the
+               following ways: If asynchronous activity is launched, an
+               invocation returns ARM_DRIVER_OK, and the caller can expect to
+               receive a callback in the future with ARM_DRIVER_OK passed in as
+               the 'status' parameter. In the case of synchronous execution,
+               control returns after completion with a value of 1. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)
+  \brief       Get Storage status.
+  \return      Storage status \ref ARM_STORAGE_STATUS
+*/
+/**
+  \fn          int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)
+  \brief       Get Storage information.
+  \param[out]  info  A caller-supplied buffer capable of being filled in with an \ref ARM_STORAGE_INFO.
+  \return      ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
+               metadata about the storage controller is filled into the supplied
+               buffer, else an appropriate error value.
+*/
+/**
+  \fn          uint32_t ARM_Storage_ResolveAddress(uint64_t addr)
+  \brief       Resolve an address relative to the storage controller into a memory address.
+  \param[in]   addr The address for which we want a resolution to the processor's physical address space. It is an offset from the
+               start of the storage map maintained by the owning storage
+               controller.
+  \return      The resolved address in the processor's address space, else ARM_STORAGE_INVALID_ADDRESS.
+*/
+/**
+  \fn          int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
+  \brief       Advance to the successor of the current block (iterator).
+  \param[in]   prev_block An existing block (iterator) within the same storage
+               controller. The memory buffer holding this block is owned
+               by the caller. This pointer may be NULL; if so, the
+               invocation fills in the first block into the out parameter:
+               'next_block'.
+  \param[out]  next_block A caller-owned buffer large enough to be filled in with
+               the following ARM_STORAGE_BLOCK. It is legal to provide the
+               same buffer using 'next_block' as was passed in with 'prev_block'. It
+               is also legal to pass a NULL into this parameter if the
+               caller isn't interested in populating a buffer with the next
+               block, i.e. if the caller only wishes to establish the
+               presence of a next block.
+  \return      ARM_DRIVER_OK if a valid next block is found (or first block, if
+               prev_block is passed as NULL); upon successful operation, the contents
+               of the next (or first) block are filled into the buffer pointed to by
+               the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
+               guaranteed to be true. Upon reaching the end of the sequence of blocks
+               (iterators), or in case the driver is unable to fetch information about
+               the next (or first) block, an error (negative) value is returned and an
+               invalid StorageBlock is populated into the supplied buffer. If
+               prev_block is NULL, the first block is returned.
+*/
+/**
+  \fn          int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block);
+  \brief       Find the storage block (iterator) encompassing a given storage address.
+  \param[in]   addr Storage address in bytes.
+  \param[out]  block A caller-owned buffer large enough to be filled in with the
+               ARM_STORAGE_BLOCK encapsulating the given address. This value
+               can also be passed in as NULL if the caller isn't interested
+               in populating a buffer with the block, if the caller only
+               wishes to establish the presence of a containing storage
+               block.
+  \return      ARM_DRIVER_OK if a containing storage-block is found. In this case,
+               if block is non-NULL, the buffer pointed to by it is populated with
+               the contents of the storage block, i.e. if block is valid and a block is
+               found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
+               call. If there is no storage block containing the given offset, or in
+               case the driver is unable to resolve an address to a storage-block, an
+               error (negative) value is returned and an invalid StorageBlock is
+               populated into the supplied buffer.
+*/
+
+/**
+ * Provides the typedef for the callback function \ref ARM_Storage_Callback_t.
+ */
+typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
+
+/**
+ * The set of operations constituting the Storage driver.
+ */
+typedef struct _ARM_DRIVER_STORAGE {
+  ARM_DRIVER_VERSION       (*GetVersion)     (void);                                           ///< Pointer to \ref ARM_Storage_GetVersion : Get driver version.
+  ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);                                           ///< Pointer to \ref ARM_Storage_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)     (ARM_Storage_Callback_t callback);                ///< Pointer to \ref ARM_Storage_Initialize : Initialize the Storage Interface.
+  int32_t                  (*Uninitialize)   (void);                                           ///< Pointer to \ref ARM_Storage_Uninitialize : De-initialize the Storage Interface.
+  int32_t                  (*PowerControl)   (ARM_POWER_STATE state);                          ///< Pointer to \ref ARM_Storage_PowerControl : Control the Storage interface power.
+  int32_t                  (*ReadData)       (uint64_t addr, void *data, uint32_t size);       ///< Pointer to \ref ARM_Storage_ReadData : Read data from Storage.
+  int32_t                  (*ProgramData)    (uint64_t addr, const void *data, uint32_t size); ///< Pointer to \ref ARM_Storage_ProgramData : Program data to Storage.
+  int32_t                  (*Erase)          (uint64_t addr, uint32_t size);                   ///< Pointer to \ref ARM_Storage_Erase : Erase Storage range.
+  int32_t                  (*EraseAll)       (void);                                           ///< Pointer to \ref ARM_Storage_EraseAll : Erase complete Storage.
+  ARM_STORAGE_STATUS       (*GetStatus)      (void);                                           ///< Pointer to \ref ARM_Storage_GetStatus : Get Storage status.
+  int32_t                  (*GetInfo)        (ARM_STORAGE_INFO *info);                         ///< Pointer to \ref ARM_Storage_GetInfo : Get Storage information.
+  uint32_t                 (*ResolveAddress) (uint64_t addr);                                  ///< Pointer to \ref ARM_Storage_ResolveAddress : Resolve a storage address.
+  int32_t                  (*GetNextBlock)   (const ARM_STORAGE_BLOCK* prev, ARM_STORAGE_BLOCK *next); ///< Pointer to \ref ARM_Storage_GetNextBlock : fetch successor for current block.
+  int32_t                  (*GetBlock)       (uint64_t addr, ARM_STORAGE_BLOCK *block);        ///< Pointer to \ref ARM_Storage_GetBlock :
+} const ARM_DRIVER_STORAGE;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_STORAGE_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_USART.h

@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ *               Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_USART_STATUS and ARM_USART_MODEM_STATUS
+ *  Version 2.3
+ *    ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
+ *  Version 2.2
+ *    Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions 
+ *  Version 2.1
+ *    Removed optional argument parameter from Signal Event
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *      renamed driver UART -> USART (Asynchronous & Synchronous)
+ *    Added modes:
+ *      Synchronous
+ *      Single-wire
+ *      IrDA
+ *      Smart Card  
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added events:
+ *      ARM_UART_EVENT_TX_EMPTY,     ARM_UART_EVENT_RX_TIMEOUT
+ *      ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ *    Added functions: SetTxThreshold, SetRxThreshold
+ *    Added "rx_timeout_event" to capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USART_H_
+#define DRIVER_USART_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_USART_(n)      Driver_USART##n
+#define  ARM_Driver_USART_(n) _ARM_Driver_USART_(n)
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos                0
+#define ARM_USART_CONTROL_Msk               (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS         (0x01UL << ARM_USART_CONTROL_Pos)   ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER   (0x02UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE    (0x03UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE          (0x04UL << ARM_USART_CONTROL_Pos)   ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA                 (0x05UL << ARM_USART_CONTROL_Pos)   ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD           (0x06UL << ARM_USART_CONTROL_Pos)   ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos              8
+#define ARM_USART_DATA_BITS_Msk             (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5               (5UL << ARM_USART_DATA_BITS_Pos)    ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6               (6UL << ARM_USART_DATA_BITS_Pos)    ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7               (7UL << ARM_USART_DATA_BITS_Pos)    ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8               (0UL << ARM_USART_DATA_BITS_Pos)    ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9               (1UL << ARM_USART_DATA_BITS_Pos)    ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos                 12
+#define ARM_USART_PARITY_Msk                (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE               (0UL << ARM_USART_PARITY_Pos)       ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN               (1UL << ARM_USART_PARITY_Pos)       ///< Even Parity
+#define ARM_USART_PARITY_ODD                (2UL << ARM_USART_PARITY_Pos)       ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos              14
+#define ARM_USART_STOP_BITS_Msk             (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1               (0UL << ARM_USART_STOP_BITS_Pos)    ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2               (1UL << ARM_USART_STOP_BITS_Pos)    ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5             (2UL << ARM_USART_STOP_BITS_Pos)    ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5             (3UL << ARM_USART_STOP_BITS_Pos)    ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos           16
+#define ARM_USART_FLOW_CONTROL_Msk          (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE         (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS          (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS          (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS      (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos                   18
+#define ARM_USART_CPOL_Msk                  (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0                     (0UL << ARM_USART_CPOL_Pos)         ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1                     (1UL << ARM_USART_CPOL_Pos)         ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos                   19
+#define ARM_USART_CPHA_Msk                  (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0                     (0UL << ARM_USART_CPHA_Pos)         ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1                     (1UL << ARM_USART_CPHA_Pos)         ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls  -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE      (0x10UL << ARM_USART_CONTROL_Pos)   ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE            (0x11UL << ARM_USART_CONTROL_Pos)   ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period  
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK      (0x13UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK   (0x14UL << ARM_USART_CONTROL_Pos)   ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX                (0x15UL << ARM_USART_CONTROL_Pos)   ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX                (0x16UL << ARM_USART_CONTROL_Pos)   ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK             (0x17UL << ARM_USART_CONTROL_Pos)   ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND                (0x18UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE             (0x19UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER            (0x1AUL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE                (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE            (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY              (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL        (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL                (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA                (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Clock Phase not supported
+
+
+/**
+\brief USART Status
+*/
+typedef struct _ARM_USART_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+  uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+  uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+  uint32_t reserved         : 25;
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+  ARM_USART_RTS_CLEAR,                  ///< Deactivate RTS
+  ARM_USART_RTS_SET,                    ///< Activate RTS
+  ARM_USART_DTR_CLEAR,                  ///< Deactivate DTR
+  ARM_USART_DTR_SET                     ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef struct _ARM_USART_MODEM_STATUS {
+  uint32_t cts      : 1;                ///< CTS state: 1=Active, 0=Inactive
+  uint32_t dsr      : 1;                ///< DSR state: 1=Active, 0=Inactive
+  uint32_t dcd      : 1;                ///< DCD state: 1=Active, 0=Inactive
+  uint32_t ri       : 1;                ///< RI  state: 1=Active, 0=Inactive
+  uint32_t reserved : 28;
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE       (1UL << 0)  ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE    (1UL << 1)  ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE   (1UL << 2)  ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE         (1UL << 3)  ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW        (1UL << 4)  ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW         (1UL << 5)  ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT          (1UL << 6)  ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK            (1UL << 7)  ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR    (1UL << 8)  ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR     (1UL << 9)  ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS                 (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR                 (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD                 (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI                  (1UL << 13) ///< RI  state changed (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+  \brief       Get driver capabilities
+  \return      \ref ARM_USART_CAPABILITIES
+
+  \fn          int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+  \brief       Initialize USART Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_USART_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Uninitialize (void)
+  \brief       De-initialize USART Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USART Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Send (const void *data, uint32_t num)
+  \brief       Start sending data to USART transmitter.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from USART receiver.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Transfer (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num)
+  \brief       Start sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_USART_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_USART_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+  \brief       Control USART Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref usart_execution_status
+
+  \fn          ARM_USART_STATUS ARM_USART_GetStatus (void)
+  \brief       Get USART status.
+  \return      USART status \ref ARM_USART_STATUS
+
+  \fn          int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+  \brief       Set USART Modem Control line state.
+  \param[in]   control  \ref ARM_USART_MODEM_CONTROL
+  \return      \ref execution_status 
+
+  \fn          ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+  \brief       Get USART Modem Status lines state.
+  \return      modem status \ref ARM_USART_MODEM_STATUS
+
+  \fn          void ARM_USART_SignalEvent (uint32_t event)
+  \brief       Signal USART Events.
+  \param[in]   event  \ref USART_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+  uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode 
+  uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+  uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+  uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+  uint32_t irda               : 1;      ///< supports UART IrDA mode
+  uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+  uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+  uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+  uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+  uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+  uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+  uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+  uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+  uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+  uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+  uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+  uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+  uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+  uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+  uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+  uint32_t event_ri           : 1;      ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+  uint32_t reserved           : 11;     ///< Reserved (must be zero)
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+  ARM_DRIVER_VERSION     (*GetVersion)      (void);                              ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+  ARM_USART_CAPABILITIES (*GetCapabilities) (void);                              ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)      (ARM_USART_SignalEvent_t cb_event);  ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+  int32_t                (*Uninitialize)    (void);                              ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+  int32_t                (*PowerControl)    (ARM_POWER_STATE state);             ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+  int32_t                (*Send)            (const void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+  int32_t                (*Receive)         (      void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+  int32_t                (*Transfer)        (const void *data_out,
+                                                   void *data_in,
+                                             uint32_t    num);                   ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+  uint32_t               (*GetTxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+  uint32_t               (*GetRxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+  int32_t                (*Control)         (uint32_t control, uint32_t arg);    ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+  ARM_USART_STATUS       (*GetStatus)       (void);                              ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+  int32_t                (*SetModemControl) (ARM_USART_MODEM_CONTROL control);   ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+  ARM_USART_MODEM_STATUS (*GetModemStatus)  (void);                              ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USART_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_USB.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.0
+ *
+ * Project:      USB Driver common definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added PID Types
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USB_H_
+#define DRIVER_USB_H_
+
+#include "Driver_Common.h"
+
+/* USB Role */
+#define ARM_USB_ROLE_NONE               (0U)
+#define ARM_USB_ROLE_HOST               (1U)
+#define ARM_USB_ROLE_DEVICE             (2U)
+
+/* USB Pins */
+#define ARM_USB_PIN_DP                  (1U << 0) ///< USB D+ pin
+#define ARM_USB_PIN_DM                  (1U << 1) ///< USB D- pin
+#define ARM_USB_PIN_VBUS                (1U << 2) ///< USB VBUS pin
+#define ARM_USB_PIN_OC                  (1U << 3) ///< USB OverCurrent pin
+#define ARM_USB_PIN_ID                  (1U << 4) ///< USB ID pin
+
+/* USB Speed */
+#define ARM_USB_SPEED_LOW               (0U)      ///< Low-speed USB
+#define ARM_USB_SPEED_FULL              (1U)      ///< Full-speed USB
+#define ARM_USB_SPEED_HIGH              (2U)      ///< High-speed USB
+
+/* USB PID Types */
+#define ARM_USB_PID_OUT                 (1U)
+#define ARM_USB_PID_IN                  (9U)
+#define ARM_USB_PID_SOF                 (5U)
+#define ARM_USB_PID_SETUP               (13U)
+#define ARM_USB_PID_DATA0               (3U)
+#define ARM_USB_PID_DATA1               (11U)
+#define ARM_USB_PID_DATA2               (7U)
+#define ARM_USB_PID_MDATA               (15U)
+#define ARM_USB_PID_ACK                 (2U)
+#define ARM_USB_PID_NAK                 (10U)
+#define ARM_USB_PID_STALL               (14U)
+#define ARM_USB_PID_NYET                (6U)
+#define ARM_USB_PID_PRE                 (12U)
+#define ARM_USB_PID_ERR                 (12U)
+#define ARM_USB_PID_SPLIT               (8U)
+#define ARM_USB_PID_PING                (4U)
+#define ARM_USB_PID_RESERVED            (0U)
+
+/* USB Endpoint Address (bEndpointAddress) */
+#define ARM_USB_ENDPOINT_NUMBER_MASK    (0x0FU)
+#define ARM_USB_ENDPOINT_DIRECTION_MASK (0x80U)
+
+/* USB Endpoint Type */
+#define ARM_USB_ENDPOINT_CONTROL        (0U)     ///< Control Endpoint
+#define ARM_USB_ENDPOINT_ISOCHRONOUS    (1U)     ///< Isochronous Endpoint
+#define ARM_USB_ENDPOINT_BULK           (2U)     ///< Bulk Endpoint
+#define ARM_USB_ENDPOINT_INTERRUPT      (3U)     ///< Interrupt Endpoint
+
+/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */
+#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK           (0x07FFU)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK   (0x1800U)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1      (0x0000U)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2      (0x0800U)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3      (0x1000U)
+
+#endif /* DRIVER_USB_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_USBD.h

@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.3
+ *
+ * Project:      USB Device Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Removed volatile from ARM_USBD_STATE
+ *  Version 2.2
+ *    ARM_USBD_STATE made volatile
+ *  Version 2.1
+ *    Added ARM_USBD_ReadSetupPacket function
+ *  Version 2.0
+ *    Removed ARM_USBD_DeviceConfigure function
+ *    Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function
+ *    Removed ARM_USBD_EndpointReadStart function
+ *    Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer
+ *    Added ARM_USBD_EndpointTransferGetResult function
+ *    Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBD_H_
+#define DRIVER_USBD_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_USBD_(n)      Driver_USBD##n
+#define  ARM_Driver_USBD_(n) _ARM_Driver_USBD_(n)
+
+
+/**
+\brief USB Device State
+*/
+typedef struct _ARM_USBD_STATE {
+  uint32_t vbus     : 1;                ///< USB Device VBUS flag
+  uint32_t speed    : 2;                ///< USB Device speed setting (ARM_USB_SPEED_xxx)
+  uint32_t active   : 1;                ///< USB Device active flag
+  uint32_t reserved : 28;
+} ARM_USBD_STATE;
+
+
+/****** USB Device Event *****/
+#define ARM_USBD_EVENT_VBUS_ON          (1UL << 0)      ///< USB Device VBUS On
+#define ARM_USBD_EVENT_VBUS_OFF         (1UL << 1)      ///< USB Device VBUS Off
+#define ARM_USBD_EVENT_RESET            (1UL << 2)      ///< USB Reset occurred
+#define ARM_USBD_EVENT_HIGH_SPEED       (1UL << 3)      ///< USB switch to High Speed occurred
+#define ARM_USBD_EVENT_SUSPEND          (1UL << 4)      ///< USB Suspend occurred
+#define ARM_USBD_EVENT_RESUME           (1UL << 5)      ///< USB Resume occurred
+
+/****** USB Endpoint Event *****/
+#define ARM_USBD_EVENT_SETUP            (1UL << 0)      ///< SETUP Packet
+#define ARM_USBD_EVENT_OUT              (1UL << 1)      ///< OUT Packet(s)
+#define ARM_USBD_EVENT_IN               (1UL << 2)      ///< IN Packet(s)
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBD_STATE ARM_USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointConfigure (uint8_t  ep_addr,
+                                                   uint8_t  ep_type,
+                                                   uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBD_SignalDeviceEvent (uint32_t event)
+  \brief       Signal USB Device Event.
+  \param[in]   event \ref USBD_dev_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)
+  \brief       Signal USB Endpoint Event.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   event \ref USBD_ep_events
+  \return      none
+*/
+
+typedef void (*ARM_USBD_SignalDeviceEvent_t)   (uint32_t event);                    ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event.
+typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event);   ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event.
+
+
+/**
+\brief USB Device Driver Capabilities.
+*/
+typedef struct _ARM_USBD_CAPABILITIES {
+  uint32_t vbus_detection  : 1;         ///< VBUS detection
+  uint32_t event_vbus_on   : 1;         ///< Signal VBUS On event
+  uint32_t event_vbus_off  : 1;         ///< Signal VBUS Off event
+  uint32_t reserved        : 29;        ///< Reserved (must be zero)
+} ARM_USBD_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USB Device Driver.
+*/
+typedef struct _ARM_DRIVER_USBD {
+  ARM_DRIVER_VERSION    (*GetVersion)                (void);                                              ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version.
+  ARM_USBD_CAPABILITIES (*GetCapabilities)           (void);                                              ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)                (ARM_USBD_SignalDeviceEvent_t   cb_device_event,                     
+                                                      ARM_USBD_SignalEndpointEvent_t cb_endpoint_event);  ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. 
+  int32_t               (*Uninitialize)              (void);                                              ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface.
+  int32_t               (*PowerControl)              (ARM_POWER_STATE state);                             ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power.
+  int32_t               (*DeviceConnect)             (void);                                              ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device.
+  int32_t               (*DeviceDisconnect)          (void);                                              ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device.
+  ARM_USBD_STATE        (*DeviceGetState)            (void);                                              ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State.
+  int32_t               (*DeviceRemoteWakeup)        (void);                                              ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup.
+  int32_t               (*DeviceSetAddress)          (uint8_t dev_addr);                                  ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address.
+  int32_t               (*ReadSetupPacket)           (uint8_t *setup);                                    ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint.
+  int32_t               (*EndpointConfigure)         (uint8_t ep_addr,
+                                                      uint8_t ep_type,
+                                                      uint16_t ep_max_packet_size);                       ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint.
+  int32_t               (*EndpointUnconfigure)       (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.
+  int32_t               (*EndpointStall)             (uint8_t ep_addr, bool stall);                       ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.
+  int32_t               (*EndpointTransfer)          (uint8_t ep_addr, uint8_t *data, uint32_t num);      ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint.
+  uint32_t              (*EndpointTransferGetResult) (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer.
+  int32_t               (*EndpointTransferAbort)     (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer.
+  uint16_t              (*GetFrameNumber)            (void);                                              ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number.
+} const ARM_DRIVER_USBD;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBD_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_USBH.h

@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+  *
+ * $Date:        31. March 2020
+ * $Revision:    V2.3
+ *
+ * Project:      USB Host Driver definitions
+*/
+
+/* History:
+ *  Version 2.3
+ *    Removed volatile from ARM_USBH_PORT_STATE
+ *  Version 2.2
+ *    ARM_USBH_PORT_STATE made volatile
+ *  Version 2.1
+ *    Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE
+ *    Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe...
+ *    Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent
+ *  Version 2.0
+ *    Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff
+ *    Changed function ARM_USBH_EndpointCreate parameters
+ *    Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify
+ *    Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset
+ *    Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer
+ *    Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort
+ *    Added function ARM_USBH_EndpointTransferGetResult
+ *    Added function ARM_USBH_GetFrameNumber
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.20
+ *    Added API for OHCI/EHCI Host Controller Interface (HCI)
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBH_H_
+#define DRIVER_USBH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_USBH_(n)      Driver_USBH##n
+#define  ARM_Driver_USBH_(n) _ARM_Driver_USBH_(n)
+
+
+/**
+\brief USB Host Port State
+*/
+typedef struct _ARM_USBH_PORT_STATE {
+  uint32_t connected   : 1;             ///< USB Host Port connected flag
+  uint32_t overcurrent : 1;             ///< USB Host Port overcurrent flag
+  uint32_t speed       : 2;             ///< USB Host Port speed setting (ARM_USB_SPEED_xxx)
+  uint32_t reserved    : 28;
+} ARM_USBH_PORT_STATE;
+
+/**
+\brief USB Host Pipe Handle
+*/
+typedef uint32_t ARM_USBH_PIPE_HANDLE;
+#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE  /* Legacy name */
+
+
+/****** USB Host Packet Information *****/
+#define ARM_USBH_PACKET_TOKEN_Pos         0
+#define ARM_USBH_PACKET_TOKEN_Msk        (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos)
+#define ARM_USBH_PACKET_SETUP            (0x01UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< SETUP Packet
+#define ARM_USBH_PACKET_OUT              (0x02UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< OUT Packet
+#define ARM_USBH_PACKET_IN               (0x03UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< IN Packet
+#define ARM_USBH_PACKET_PING             (0x04UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< PING Packet
+
+#define ARM_USBH_PACKET_DATA_Pos          4
+#define ARM_USBH_PACKET_DATA_Msk         (0x0FUL << ARM_USBH_PACKET_DATA_Pos)
+#define ARM_USBH_PACKET_DATA0            (0x01UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA0 PID
+#define ARM_USBH_PACKET_DATA1            (0x02UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA1 PID
+
+#define ARM_USBH_PACKET_SPLIT_Pos         8
+#define ARM_USBH_PACKET_SPLIT_Msk        (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos)
+#define ARM_USBH_PACKET_SSPLIT           (0x08UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet
+#define ARM_USBH_PACKET_SSPLIT_S         (0x09UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data Start
+#define ARM_USBH_PACKET_SSPLIT_E         (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data End
+#define ARM_USBH_PACKET_SSPLIT_S_E       (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data All
+#define ARM_USBH_PACKET_CSPLIT           (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< CSPLIT Packet
+
+#define ARM_USBH_PACKET_PRE              (1UL << 12)                            ///< PRE Token
+
+
+/****** USB Host Port Event *****/
+#define ARM_USBH_EVENT_CONNECT           (1UL << 0)     ///< USB Device Connected to Port
+#define ARM_USBH_EVENT_DISCONNECT        (1UL << 1)     ///< USB Device Disconnected from Port
+#define ARM_USBH_EVENT_OVERCURRENT       (1UL << 2)     ///< USB Device caused Overcurrent
+#define ARM_USBH_EVENT_RESET             (1UL << 3)     ///< USB Reset completed
+#define ARM_USBH_EVENT_SUSPEND           (1UL << 4)     ///< USB Suspend occurred
+#define ARM_USBH_EVENT_RESUME            (1UL << 5)     ///< USB Resume occurred
+#define ARM_USBH_EVENT_REMOTE_WAKEUP     (1UL << 6)     ///< USB Device activated Remote Wakeup
+
+/****** USB Host Pipe Event *****/
+#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0)     ///< Transfer completed
+#define ARM_USBH_EVENT_HANDSHAKE_NAK     (1UL << 1)     ///< NAK Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_NYET    (1UL << 2)     ///< NYET Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_MDATA   (1UL << 3)     ///< MDATA Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_STALL   (1UL << 4)     ///< STALL Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_ERR     (1UL << 5)     ///< ERR Handshake received
+#define ARM_USBH_EVENT_BUS_ERROR         (1UL << 6)     ///< Bus Error detected
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,
+                                            ARM_USBH_SignalPipeEvent_t cb_pipe_event)
+  \brief       Initialize USB Host Interface.
+  \param[in]   cb_port_event  Pointer to \ref ARM_USBH_SignalPortEvent
+  \param[in]   cb_pipe_event  Pointer to \ref ARM_USBH_SignalPipeEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_Uninitialize (void)
+  \brief       De-initialize USB Host Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortReset (uint8_t port)
+  \brief       Do Root HUB Port Reset.
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortSuspend (uint8_t port)
+  \brief       Suspend Root HUB Port (stop generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortResume (uint8_t port)
+  \brief       Resume Root HUB Port (start generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)
+  \brief       Get current Root HUB Port State.
+  \param[in]   port  Root HUB Port Number
+  \return      Port State \ref ARM_USBH_PORT_STATE
+*/
+/**
+  \fn          ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t  dev_addr,
+                                                         uint8_t  dev_speed,
+                                                         uint8_t  hub_addr,
+                                                         uint8_t  hub_port,
+                                                         uint8_t  ep_addr,
+                                                         uint8_t  ep_type,
+                                                         uint16_t ep_max_packet_size,
+                                                         uint8_t  ep_interval)
+  \brief       Create Pipe in System.
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_addr    Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type    Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \param[in]   ep_interval        Endpoint Polling Interval
+  \return      Pipe Handle \ref ARM_USBH_PIPE_HANDLE
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                            uint8_t              dev_addr,
+                                            uint8_t              dev_speed,
+                                            uint8_t              hub_addr,
+                                            uint8_t              hub_port,
+                                            uint16_t             ep_max_packet_size)
+  \brief       Modify Pipe in System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Delete Pipe from System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Reset Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                              uint32_t             packet,
+                                              uint8_t             *data,
+                                              uint32_t             num)
+  \brief       Transfer packets through USB Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   packet     Packet information
+  \param[in]   data       Pointer to buffer with data to send or for data to receive
+  \param[in]   num        Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Get result of USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Abort current USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBH_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)
+  \brief       Signal Root HUB Port Event.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   event \ref USBH_port_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)
+  \brief       Signal Pipe Event.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   event  \ref USBH_pipe_events
+  \return      none
+*/
+
+typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event);                    ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event.
+typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event);  ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event.
+#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t  /* Legacy name */
+
+
+/**
+\brief USB Host Driver Capabilities.
+*/
+typedef struct _ARM_USBH_CAPABILITIES {
+  uint32_t port_mask          : 15;     ///< Root HUB available Ports Mask
+  uint32_t auto_split         :  1;     ///< Automatic SPLIT packet handling
+  uint32_t event_connect      :  1;     ///< Signal Connect event
+  uint32_t event_disconnect   :  1;     ///< Signal Disconnect event
+  uint32_t event_overcurrent  :  1;     ///< Signal Overcurrent event
+  uint32_t reserved           : 13;     ///< Reserved (must be zero)
+} ARM_USBH_CAPABILITIES;
+
+
+/**
+\brief Access structure of USB Host Driver.
+*/
+typedef struct _ARM_DRIVER_USBH {
+  ARM_DRIVER_VERSION    (*GetVersion)            (void);                                     ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version.
+  ARM_USBH_CAPABILITIES (*GetCapabilities)       (void);                                     ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)            (ARM_USBH_SignalPortEvent_t cb_port_event,            
+                                                  ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface.
+  int32_t               (*Uninitialize)          (void);                                     ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface.
+  int32_t               (*PowerControl)          (ARM_POWER_STATE state);                    ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power.
+  int32_t               (*PortVbusOnOff)         (uint8_t port, bool vbus);                  ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off.
+  int32_t               (*PortReset)             (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset.
+  int32_t               (*PortSuspend)           (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs).
+  int32_t               (*PortResume)            (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs).
+  ARM_USBH_PORT_STATE   (*PortGetState)          (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State.
+  ARM_USBH_PIPE_HANDLE  (*PipeCreate)            (uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint8_t ep_addr,
+                                                  uint8_t ep_type,
+                                                  uint16_t ep_max_packet_size,
+                                                  uint8_t ep_interval);                      ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System.
+  int32_t               (*PipeModify)            (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                                  uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint16_t ep_max_packet_size);              ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System.
+  int32_t               (*PipeDelete)            (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System.
+  int32_t               (*PipeReset)             (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe.
+  int32_t               (*PipeTransfer)          (ARM_USBH_PIPE_HANDLE pipe_hndl, 
+                                                  uint32_t packet,
+                                                  uint8_t *data,
+                                                  uint32_t num);                             ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe.
+  uint32_t              (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer.
+  int32_t               (*PipeTransferAbort)     (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer.
+  uint16_t              (*GetFrameNumber)        (void);                                     ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number.                    
+} const ARM_DRIVER_USBH;
+
+
+// HCI (OHCI/EHCI)
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)
+  \brief       Get USB Host HCI (OHCI/EHCI) driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_HCI_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+  \brief       Initialize USB Host HCI (OHCI/EHCI) Interface.
+  \param[in]   cb_interrupt Pointer to Interrupt Handler Routine
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Uninitialize (void)
+  \brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host HCI (OHCI/EHCI) Interface Power.
+  \param[in]   state Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_USBH_HCI_Interrupt (void)
+  \brief       USB Host HCI Interrupt Handler.
+  \return      none
+*/
+
+typedef void (*ARM_USBH_HCI_Interrupt_t) (void);  ///< Pointer to Interrupt Handler Routine.
+
+
+/**
+\brief USB Host HCI (OHCI/EHCI) Driver Capabilities.
+*/
+typedef struct _ARM_USBH_HCI_CAPABILITIES {
+  uint32_t port_mask : 15;              ///< Root HUB available Ports Mask
+  uint32_t reserved  : 17;              ///< Reserved (must be zero)
+} ARM_USBH_HCI_CAPABILITIES;
+
+
+/**
+  \brief Access structure of USB Host HCI (OHCI/EHCI) Driver.
+*/
+typedef struct _ARM_DRIVER_USBH_HCI {
+  ARM_DRIVER_VERSION        (*GetVersion)      (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version.
+  ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities.
+  int32_t                   (*Initialize)      (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*Uninitialize)    (void);                                  ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*PowerControl)    (ARM_POWER_STATE state);                 ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power.
+  int32_t                   (*PortVbusOnOff)   (uint8_t port, bool vbus);               ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+} const ARM_DRIVER_USBH_HCI;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBH_H_ */

external/CMSIS_5/CMSIS/Driver/Include/Driver_WiFi.h

@@ -0,0 +1,666 @@
+/*
+ * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        30. March 2022
+ * $Revision:    V1.1
+ *
+ * Project:      WiFi (Wireless Fidelity Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 1.1
+ *    Extended Socket Receive/RecvFrom/Send/SendTo (support for polling)
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_WIFI_H_
+#define DRIVER_WIFI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_WIFI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1)  /* API version */
+
+
+#define _ARM_Driver_WiFi_(n)      Driver_WiFi##n
+#define  ARM_Driver_WiFi_(n) _ARM_Driver_WiFi_(n)
+
+
+/****** WiFi SetOption/GetOption Function Option Codes *****/
+#define ARM_WIFI_BSSID                      1U          ///< Station/AP Set/Get BSSID of AP to connect or of AP;        data = &bssid,    len =  6, uint8_t[6]
+#define ARM_WIFI_TX_POWER                   2U          ///< Station/AP Set/Get transmit power;                         data = &power,    len =  4, uint32_t: 0 .. 20 [dBm]
+#define ARM_WIFI_LP_TIMER                   3U          ///< Station    Set/Get low-power deep-sleep time;              data = &time,     len =  4, uint32_t [seconds]: 0 = disable (default)
+#define ARM_WIFI_DTIM                       4U          ///< Station/AP Set/Get DTIM interval;                          data = &dtim,     len =  4, uint32_t [beacons]
+#define ARM_WIFI_BEACON                     5U          ///<         AP Set/Get beacon interval;                        data = &interval, len =  4, uint32_t [ms]
+#define ARM_WIFI_MAC                        6U          ///< Station/AP Set/Get MAC;                                    data = &mac,      len =  6, uint8_t[6]
+#define ARM_WIFI_IP                         7U          ///< Station/AP Set/Get IPv4 static/assigned address;           data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_SUBNET_MASK             8U          ///< Station/AP Set/Get IPv4 subnet mask;                       data = &mask,     len =  4, uint8_t[4]
+#define ARM_WIFI_IP_GATEWAY                 9U          ///< Station/AP Set/Get IPv4 gateway address;                   data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DNS1                    10U         ///< Station/AP Set/Get IPv4 primary   DNS address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DNS2                    11U         ///< Station/AP Set/Get IPv4 secondary DNS address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP                    12U         ///< Station/AP Set/Get IPv4 DHCP client/server enable/disable; data = &dhcp,     len =  4, uint32_t: 0 = disable, non-zero = enable (default)
+#define ARM_WIFI_IP_DHCP_POOL_BEGIN         13U         ///<         AP Set/Get IPv4 DHCP pool begin address;           data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP_POOL_END           14U         ///<         AP Set/Get IPv4 DHCP pool end address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP_LEASE_TIME         15U         ///<         AP Set/Get IPv4 DHCP lease time;                   data = &time,     len =  4, uint32_t [seconds]
+#define ARM_WIFI_IP6_GLOBAL                 16U         ///< Station/AP Set/Get IPv6 global address;                    data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_LINK_LOCAL             17U         ///< Station/AP Set/Get IPv6 link local address;                data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_SUBNET_PREFIX_LEN      18U         ///< Station/AP Set/Get IPv6 subnet prefix length;              data = &len,      len =  4, uint32_t: 1 .. 127
+#define ARM_WIFI_IP6_GATEWAY                19U         ///< Station/AP Set/Get IPv6 gateway address;                   data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DNS1                   20U         ///< Station/AP Set/Get IPv6 primary   DNS address;             data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DNS2                   21U         ///< Station/AP Set/Get IPv6 secondary DNS address;             data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DHCP_MODE              22U         ///< Station/AP Set/Get IPv6 DHCPv6 client mode;                data = &mode,     len =  4, uint32_t: ARM_WIFI_IP6_DHCP_xxx (default Off)
+
+/****** WiFi Security Type *****/
+#define ARM_WIFI_SECURITY_OPEN              0U          ///< Open
+#define ARM_WIFI_SECURITY_WEP               1U          ///< Wired Equivalent Privacy (WEP) with Pre-Sheared Key (PSK)
+#define ARM_WIFI_SECURITY_WPA               2U          ///< WiFi Protected Access (WPA) with PSK
+#define ARM_WIFI_SECURITY_WPA2              3U          ///< WiFi Protected Access II (WPA2) with PSK
+#define ARM_WIFI_SECURITY_UNKNOWN           255U        ///< Unknown
+
+/****** WiFi Protected Setup (WPS) Method *****/
+#define ARM_WIFI_WPS_METHOD_NONE            0U          ///< Not used
+#define ARM_WIFI_WPS_METHOD_PBC             1U          ///< Push Button Configuration
+#define ARM_WIFI_WPS_METHOD_PIN             2U          ///< PIN
+
+/****** WiFi IPv6 Dynamic Host Configuration Protocol (DHCP) Mode *****/
+#define ARM_WIFI_IP6_DHCP_OFF               0U          ///< Static Host Configuration (default)
+#define ARM_WIFI_IP6_DHCP_STATELESS         1U          ///< Dynamic Host Configuration stateless DHCPv6
+#define ARM_WIFI_IP6_DHCP_STATEFULL         2U          ///< Dynamic Host Configuration statefull DHCPv6
+
+/****** WiFi Event *****/
+#define ARM_WIFI_EVENT_AP_CONNECT          (1UL << 0)   ///< Access Point: Station has connected;           arg = &mac, mac (uint8_t[6])
+#define ARM_WIFI_EVENT_AP_DISCONNECT       (1UL << 1)   ///< Access Point: Station has disconnected;        arg = &mac, mac (uint8_t[6])
+#define ARM_WIFI_EVENT_ETH_RX_FRAME        (1UL << 4)   ///< Ethernet Frame Received (in bypass mode only); arg = interface (0 = Station, 1 = Access Point)
+
+
+/**
+\brief WiFi Configuration
+*/
+typedef struct ARM_WIFI_CONFIG_s {
+  const char   *ssid;                                   ///< Pointer to Service Set Identifier (SSID) null-terminated string
+  const char   *pass;                                   ///< Pointer to Password null-terminated string
+        uint8_t security;                               ///< Security type (ARM_WIFI_SECURITY_xxx)
+        uint8_t ch;                                     ///< WiFi Channel (0 = auto, otherwise = exact channel)
+        uint8_t reserved;                               ///< Reserved
+        uint8_t wps_method;                             ///< WiFi Protected Setup (WPS) method (ARM_WIFI_WPS_METHOD_xxx)
+  const char   *wps_pin;                                ///< Pointer to WiFi Protected Setup (WPS) PIN null-terminated string
+} ARM_WIFI_CONFIG_t;
+
+/**
+\brief WiFi Scan Information
+*/
+typedef struct ARM_WIFI_SCAN_INFO_s {
+  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string
+  uint8_t bssid[6];                                     ///< Basic Service Set Identifier (BSSID)
+  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)
+  uint8_t ch;                                           ///< WiFi Channel
+  uint8_t rssi;                                         ///< Received Signal Strength Indicator
+} ARM_WIFI_SCAN_INFO_t;
+
+/**
+\brief WiFi Network Information
+*/
+typedef struct ARM_WIFI_NET_INFO_s {
+  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string
+  char    pass[64+1];                                   ///< Password null-terminated string
+  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)
+  uint8_t ch;                                           ///< WiFi Channel
+  uint8_t rssi;                                         ///< Received Signal Strength Indicator
+} ARM_WIFI_NET_INFO_t;
+
+/****** Socket Address Family definitions *****/
+#define ARM_SOCKET_AF_INET                  1           ///< IPv4
+#define ARM_SOCKET_AF_INET6                 2           ///< IPv6
+
+/****** Socket Type definitions *****/
+#define ARM_SOCKET_SOCK_STREAM              1           ///< Stream socket
+#define ARM_SOCKET_SOCK_DGRAM               2           ///< Datagram socket
+
+/****** Socket Protocol definitions *****/
+#define ARM_SOCKET_IPPROTO_TCP              1           ///< TCP
+#define ARM_SOCKET_IPPROTO_UDP              2           ///< UDP
+
+/****** Socket Option definitions *****/
+#define ARM_SOCKET_IO_FIONBIO               1           ///< Non-blocking I/O (Set only, default = 0); opt_val = &nbio, opt_len = sizeof(nbio), nbio (integer): 0=blocking, non-blocking otherwise
+#define ARM_SOCKET_SO_RCVTIMEO              2           ///< Receive timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)
+#define ARM_SOCKET_SO_SNDTIMEO              3           ///< Send timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)
+#define ARM_SOCKET_SO_KEEPALIVE             4           ///< Keep-alive messages (default = 0); opt_val = &keepalive, opt_len = sizeof(keepalive), keepalive (integer): 0=disabled, enabled otherwise
+#define ARM_SOCKET_SO_TYPE                  5           ///< Socket Type (Get only); opt_val = &socket_type, opt_len = sizeof(socket_type), socket_type (integer): ARM_SOCKET_SOCK_xxx
+
+/****** Socket Function return codes *****/
+#define ARM_SOCKET_ERROR                   (-1)         ///< Unspecified error
+#define ARM_SOCKET_ESOCK                   (-2)         ///< Invalid socket
+#define ARM_SOCKET_EINVAL                  (-3)         ///< Invalid argument
+#define ARM_SOCKET_ENOTSUP                 (-4)         ///< Operation not supported
+#define ARM_SOCKET_ENOMEM                  (-5)         ///< Not enough memory
+#define ARM_SOCKET_EAGAIN                  (-6)         ///< Operation would block or timed out
+#define ARM_SOCKET_EINPROGRESS             (-7)         ///< Operation in progress
+#define ARM_SOCKET_ETIMEDOUT               (-8)         ///< Operation timed out
+#define ARM_SOCKET_EISCONN                 (-9)         ///< Socket is connected
+#define ARM_SOCKET_ENOTCONN                (-10)        ///< Socket is not connected
+#define ARM_SOCKET_ECONNREFUSED            (-11)        ///< Connection rejected by the peer
+#define ARM_SOCKET_ECONNRESET              (-12)        ///< Connection reset by the peer
+#define ARM_SOCKET_ECONNABORTED            (-13)        ///< Connection aborted locally
+#define ARM_SOCKET_EALREADY                (-14)        ///< Connection already in progress
+#define ARM_SOCKET_EADDRINUSE              (-15)        ///< Address in use
+#define ARM_SOCKET_EHOSTNOTFOUND           (-16)        ///< Host not found
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_WIFI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_WIFI_CAPABILITIES ARM_WIFI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_WIFI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_WIFI_Initialize (ARM_WIFI_SignalEvent_t cb_event)
+  \brief         Initialize WiFi Module.
+  \param[in]     cb_event Pointer to \ref ARM_WIFI_SignalEvent_t
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+*/
+/**
+  \fn            int32_t ARM_WIFI_Uninitialize (void)
+  \brief         De-initialize WiFi Module.
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+*/
+/**
+  \fn            int32_t ARM_WIFI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control WiFi Module Power.
+  \param[in]     state     Power state
+                   - \ref ARM_POWER_OFF                : Power off: no operation possible
+                   - \ref ARM_POWER_LOW                : Low-power mode: sleep or deep-sleep depending on \ref ARM_WIFI_LP_TIMER option set
+                   - \ref ARM_POWER_FULL               : Power on: full operation at maximum performance
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid state)
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetModuleInfo (char *module_info, uint32_t max_len)
+  \brief         Get Module information.
+  \param[out]    module_info Pointer to character buffer were info string will be returned
+  \param[in]     max_len     Maximum length of string to return (including null terminator)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL module_info pointer or max_len equals to 0)
+*/
+/**
+  \fn            int32_t ARM_WIFI_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len)
+  \brief         Set WiFi Module Options.
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     option    Option to set
+  \param[in]     data      Pointer to data relevant to selected option
+  \param[in]     len       Length of data (in bytes)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data pointer or len less than option specifies)
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len)
+  \brief         Get WiFi Module Options.
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     option    Option to get
+  \param[out]    data      Pointer to memory where data for selected option will be returned
+  \param[in,out] len       Pointer to length of data (input/output)
+                   - input: maximum length of data that can be returned (in bytes)
+                   - output: length of returned data (in bytes)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data or len pointer, or *len less than option specifies)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num)
+  \brief         Scan for available networks in range.
+  \param[out]    scan_info Pointer to array of ARM_WIFI_SCAN_INFO_t structures where available Scan Information will be returned
+  \param[in]     max_num   Maximum number of Network Information structures to return
+  \return        number of ARM_WIFI_SCAN_INFO_t structures returned or error code
+                   - value >= 0                        : Number of ARM_WIFI_SCAN_INFO_t structures returned
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL scan_info pointer or max_num equal to 0)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config)
+  \brief         Activate interface (Connect to a wireless network or activate an access point).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     config    Pointer to ARM_WIFI_CONFIG_t structure where Configuration parameters are located
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported (security type, channel autodetect or WPS not supported)
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL config pointer or invalid configuration)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Deactivate (uint32_t interface)
+  \brief         Deactivate interface (Disconnect from a wireless network or deactivate an access point).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface)
+*/
+/**
+  \fn            uint32_t ARM_WIFI_IsConnected (void)
+  \brief         Get station connection status.
+  \return        station connection status
+                   - value != 0: Station connected
+                   - value = 0: Station not connected
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info)
+  \brief         Get station Network Information.
+  \param[out]    net_info  Pointer to ARM_WIFI_NET_INFO_t structure where station Network Information will be returned
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed (station not connected)
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL net_info pointer)
+*/
+/**
+  \fn            int32_t ARM_WIFI_BypassControl (uint32_t interface, uint32_t mode)
+  \brief         Enable or disable bypass (pass-through) mode. Transmit and receive Ethernet frames (IP layer bypassed and WiFi/Ethernet translation).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     mode
+                   - value = 1: all packets bypass internal IP stack
+                   - value = 0: all packets processed by internal IP stack
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or mode)
+*/
+/**
+  \fn            int32_t ARM_WIFI_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len)
+  \brief         Send Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     frame    Pointer to frame buffer with data to send
+  \param[in]     len      Frame buffer length in bytes
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_BUSY        : Driver is busy
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)
+*/
+/**
+  \fn            int32_t ARM_WIFI_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len)
+  \brief         Read data of received Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     frame    Pointer to frame buffer for data to read into
+  \param[in]     len      Frame buffer length in bytes
+  \return        number of data bytes read or error code
+                   - value >= 0                        : Number of data bytes read
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)
+*/
+/**
+  \fn            uint32_t ARM_WIFI_EthGetRxFrameSize (uint32_t interface)
+  \brief         Get size of received Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \return        number of bytes in received frame
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketCreate (int32_t af, int32_t type, int32_t protocol)
+  \brief         Create a communication socket.
+  \param[in]     af       Address family
+  \param[in]     type     Socket type
+  \param[in]     protocol Socket protocol
+  \return        status information
+                   - Socket identification number (>=0)
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ENOMEM            : Not enough memory
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Assign a local address to a socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     ip       Pointer to local IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Local port number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (address or socket already bound)
+                   - \ref ARM_SOCKET_EADDRINUSE        : Address already in use
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketListen (int32_t socket, int32_t backlog)
+  \brief         Listen for socket connections.
+  \param[in]     socket   Socket identification number
+  \param[in]     backlog  Number of connection requests that can be queued
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (socket not bound)
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_EISCONN           : Socket is already connected
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Accept a new connection on a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where address of connecting socket shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where port of connecting socket shall be returned (NULL for none)
+  \return        status information
+                   - socket identification number of accepted socket (>=0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (socket not in listen mode)
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported (socket type does not support accepting connections)
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Connect a socket to a remote host.
+  \param[in]     socket   Socket identification number
+  \param[in]     ip       Pointer to remote IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Remote port number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_EALREADY          : Connection already in progress
+                   - \ref ARM_SOCKET_EINPROGRESS       : Operation in progress
+                   - \ref ARM_SOCKET_EISCONN           : Socket is connected
+                   - \ref ARM_SOCKET_ECONNREFUSED      : Connection rejected by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EADDRINUSE        : Address already in use
+                   - \ref ARM_SOCKET_ETIMEDOUT         : Operation timed out
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketRecv (int32_t socket, void *buf, uint32_t len)
+  \brief         Receive data or check if data is available on a connected socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    buf      Pointer to buffer where data should be stored
+  \param[in]     len      Length of buffer (in bytes), set len = 0 to check if data is available
+  \return        status information
+                   - number of bytes received (>=0), if len != 0
+                   - 0                                 : Data is available (len = 0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Receive data or check if data is available on a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    buf      Pointer to buffer where data should be stored
+  \param[in]     len      Length of buffer (in bytes), set len = 0 to check if data is available
+  \param[out]    ip       Pointer to buffer where remote source address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where remote source port shall be returned (NULL for none)
+  \return        status information
+                   - number of bytes received (>=0), if len != 0
+                   - 0                                 : Data is available (len = 0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSend (int32_t socket, const void *buf, uint32_t len)
+  \brief         Send data or check if data can be sent on a connected socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     buf      Pointer to buffer containing data to send
+  \param[in]     len      Length of data (in bytes), set len = 0 to check if data can be sent
+  \return        status information
+                   - number of bytes sent (>=0), if len != 0
+                   - 0                                 : Data can be sent (len = 0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Send data or check if data can be sent on a socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     buf      Pointer to buffer containing data to send
+  \param[in]     len      Length of data (in bytes), set len = 0 to check if data can be sent
+  \param[in]     ip       Pointer to remote destination IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Remote destination port number
+  \return        status information
+                   - number of bytes sent (>=0), if len != 0
+                   - 0                                 : Data can be sent (len = 0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Retrieve local IP address and port of a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where local address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where local port shall be returned (NULL for none)
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Retrieve remote IP address and port of a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where remote address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where remote port shall be returned (NULL for none)
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len)
+  \brief         Get socket option.
+  \param[in]     socket   Socket identification number
+  \param[in]     opt_id   Option identifier
+  \param[out]    opt_val  Pointer to the buffer that will receive the option value
+  \param[in,out] opt_len  Pointer to length of the option value
+                   - length of buffer on input
+                   - length of data on output
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len)
+  \brief         Set socket option.
+  \param[in]     socket   Socket identification number
+  \param[in]     opt_id   Option identifier
+  \param[in]     opt_val  Pointer to the option value
+  \param[in]     opt_len  Length of the option value in bytes
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketClose (int32_t socket)
+  \brief         Close and release a socket.
+  \param[in]     socket   Socket identification number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len)
+  \brief         Retrieve host IP address from host name.
+  \param[in]     name     Host name
+  \param[in]     af       Address family
+  \param[out]    ip       Pointer to buffer where resolved IP address shall be returned
+  \param[in,out] ip_len   Pointer to length of 'ip'
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ETIMEDOUT         : Operation timed out
+                   - \ref ARM_SOCKET_EHOSTNOTFOUND     : Host not found
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_Ping (const uint8_t *ip, uint32_t ip_len)
+  \brief         Probe remote host with Ping command.
+  \param[in]     ip       Pointer to remote host IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL ip pointer or ip_len different than 4 or 16)
+*/
+/**
+  \fn            void ARM_WIFI_SignalEvent (uint32_t event, void *arg)
+  \brief         Signal WiFi Events.
+  \param[in]     event    \ref wifi_event notification mask
+  \param[in]     arg      Pointer to argument of signaled event
+  \return        none
+*/
+
+typedef void (*ARM_WIFI_SignalEvent_t) (uint32_t event, void *arg); ///< Pointer to \ref ARM_WIFI_SignalEvent : Signal WiFi Event.
+
+
+/**
+\brief WiFi Driver Capabilities.
+*/
+typedef struct _ARM_WIFI_CAPABILITIES {
+  uint32_t station               : 1;   ///< Station
+  uint32_t ap                    : 1;   ///< Access Point
+  uint32_t station_ap            : 1;   ///< Concurrent Station and Access Point
+  uint32_t wps_station           : 1;   ///< WiFi Protected Setup (WPS) for Station
+  uint32_t wps_ap                : 1;   ///< WiFi Protected Setup (WPS) for Access Point
+  uint32_t event_ap_connect      : 1;   ///< Access Point: event generated on Station connect
+  uint32_t event_ap_disconnect   : 1;   ///< Access Point: event generated on Station disconnect
+  uint32_t event_eth_rx_frame    : 1;   ///< Event generated on Ethernet frame reception in bypass mode
+  uint32_t bypass_mode           : 1;   ///< Bypass or pass-through mode (Ethernet interface)
+  uint32_t ip                    : 1;   ///< IP (UDP/TCP) (Socket interface)
+  uint32_t ip6                   : 1;   ///< IPv6 (Socket interface)
+  uint32_t ping                  : 1;   ///< Ping (ICMP)
+  uint32_t reserved              : 20;  ///< Reserved (must be zero)
+} ARM_WIFI_CAPABILITIES;
+
+/**
+\brief Access structure of the WiFi Driver.
+*/
+typedef struct _ARM_DRIVER_WIFI {
+  ARM_DRIVER_VERSION    (*GetVersion)                  (void);
+  ARM_WIFI_CAPABILITIES (*GetCapabilities)             (void);
+  int32_t               (*Initialize)                  (ARM_WIFI_SignalEvent_t cb_event);
+  int32_t               (*Uninitialize)                (void);
+  int32_t               (*PowerControl)                (ARM_POWER_STATE state);
+  int32_t               (*GetModuleInfo)               (char *module_info, uint32_t max_len);
+  int32_t               (*SetOption)                   (uint32_t interface, uint32_t option, const void *data, uint32_t  len);
+  int32_t               (*GetOption)                   (uint32_t interface, uint32_t option,       void *data, uint32_t *len);
+  int32_t               (*Scan)                        (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num);
+  int32_t               (*Activate)                    (uint32_t interface, const ARM_WIFI_CONFIG_t *config);
+  int32_t               (*Deactivate)                  (uint32_t interface);
+  uint32_t              (*IsConnected)                 (void);
+  int32_t               (*GetNetInfo)                  (ARM_WIFI_NET_INFO_t *net_info);
+  int32_t               (*BypassControl)               (uint32_t interface, uint32_t mode);
+  int32_t               (*EthSendFrame)                (uint32_t interface, const uint8_t *frame, uint32_t len);
+  int32_t               (*EthReadFrame)                (uint32_t interface,       uint8_t *frame, uint32_t len);
+  uint32_t              (*EthGetRxFrameSize)           (uint32_t interface);
+  int32_t               (*SocketCreate)                (int32_t af, int32_t type, int32_t protocol);
+  int32_t               (*SocketBind)                  (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);
+  int32_t               (*SocketListen)                (int32_t socket, int32_t backlog);
+  int32_t               (*SocketAccept)                (int32_t socket,       uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketConnect)               (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);
+  int32_t               (*SocketRecv)                  (int32_t socket, void *buf, uint32_t len);
+  int32_t               (*SocketRecvFrom)              (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketSend)                  (int32_t socket, const void *buf, uint32_t len);
+  int32_t               (*SocketSendTo)                (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port);
+  int32_t               (*SocketGetSockName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketGetPeerName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketGetOpt)                (int32_t socket, int32_t opt_id,       void *opt_val, uint32_t *opt_len);
+  int32_t               (*SocketSetOpt)                (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t  opt_len);
+  int32_t               (*SocketClose)                 (int32_t socket);
+  int32_t               (*SocketGetHostByName)         (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len);
+  int32_t               (*Ping)                        (const uint8_t *ip, uint32_t ip_len);
+} const ARM_DRIVER_WIFI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_WIFI_H_ */

external/CMSIS_5/CMSIS/Driver/VIO/Include/cmsis_vio.h

@@ -0,0 +1,175 @@
+/******************************************************************************
+ * @file     cmsis_vio.h
+ * @brief    CMSIS Virtual I/O header file
+ * @version  V0.1.0
+ * @date     23. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_VIO_H
+#define __CMSIS_VIO_H
+
+#include <stdint.h>
+
+/*******************************************************************************
+ * Generic I/O mapping recommended for CMSIS-VIO
+ * Note: not every I/O must be physically available
+ */
+ 
+// vioSetSignal: mask values 
+#define vioLED0             (1U << 0)   ///< \ref vioSetSignal \a mask parameter: LED 0 (for 3-color: red)
+#define vioLED1             (1U << 1)   ///< \ref vioSetSignal \a mask parameter: LED 1 (for 3-color: green)
+#define vioLED2             (1U << 2)   ///< \ref vioSetSignal \a mask parameter: LED 2 (for 3-color: blue)
+#define vioLED3             (1U << 3)   ///< \ref vioSetSignal \a mask parameter: LED 3
+#define vioLED4             (1U << 4)   ///< \ref vioSetSignal \a mask parameter: LED 4
+#define vioLED5             (1U << 5)   ///< \ref vioSetSignal \a mask parameter: LED 5
+#define vioLED6             (1U << 6)   ///< \ref vioSetSignal \a mask parameter: LED 6
+#define vioLED7             (1U << 7)   ///< \ref vioSetSignal \a mask parameter: LED 7
+
+// vioSetSignal: signal values
+#define vioLEDon            (0xFFU)     ///< \ref vioSetSignal \a signal parameter: pattern to turn any LED on
+#define vioLEDoff           (0x00U)     ///< \ref vioSetSignal \a signal parameter: pattern to turn any LED off
+
+// vioGetSignal: mask values and return values
+#define vioBUTTON0          (1U << 0)   ///< \ref vioGetSignal \a mask parameter: Push button 0
+#define vioBUTTON1          (1U << 1)   ///< \ref vioGetSignal \a mask parameter: Push button 1
+#define vioBUTTON2          (1U << 2)   ///< \ref vioGetSignal \a mask parameter: Push button 2
+#define vioBUTTON3          (1U << 3)   ///< \ref vioGetSignal \a mask parameter: Push button 3
+#define vioJOYup            (1U << 4)   ///< \ref vioGetSignal \a mask parameter: Joystick button: up
+#define vioJOYdown          (1U << 5)   ///< \ref vioGetSignal \a mask parameter: Joystick button: down
+#define vioJOYleft          (1U << 6)   ///< \ref vioGetSignal \a mask parameter: Joystick button: left
+#define vioJOYright         (1U << 7)   ///< \ref vioGetSignal \a mask parameter: Joystick button: right
+#define vioJOYselect        (1U << 8)   ///< \ref vioGetSignal \a mask parameter: Joystick button: select
+#define vioJOYall           (vioJOYup    | \
+                             vioJOYdown  | \
+                             vioJOYleft  | \
+                             vioJOYright | \
+                             vioJOYselect)  ///< \ref vioGetSignal \a mask Joystick button: all
+
+// vioSetValue / vioGetValue: id values
+#define vioAIN0             (0U)        ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 0
+#define vioAIN1             (1U)        ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 1
+#define vioAIN2             (2U)        ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 2
+#define vioAIN3             (3U)        ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 3
+#define vioAOUT0            (3U)        ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog output value 0
+
+// vioSetXYZ / vioGetXZY: id values
+#define vioMotionGyro       (0U)        ///< \ref vioSetXYZ / \ref vioGetXYZ \a id parameter: for Gyroscope
+#define vioMotionAccelero   (1U)        ///< \ref vioSetXYZ / \ref vioGetXYZ \a id parameter: for Accelerometer
+#define vioMotionMagneto    (2U)        ///< \ref vioSetXYZ / \ref vioGetXYZ \a id parameter: for Magnetometer
+
+// vioPrint: levels
+#define vioLevelNone        (0U)        ///< \ref vioPrint \a level parameter: None
+#define vioLevelHeading     (1U)        ///< \ref vioPrint \a level parameter: Heading
+#define vioLevelMessage     (2U)        ///< \ref vioPrint \a level parameter: Message
+#define vioLevelError       (3U)        ///< \ref vioPrint \a level parameter: Error
+
+/// 3-D vector value
+typedef struct {
+  int32_t   X;                          ///< X coordinate
+  int32_t   Y;                          ///< Y coordinate
+  int32_t   Z;                          ///< Z coordinate
+} vioValueXYZ_t;
+
+/// IPv4 Internet Address
+typedef struct {
+  uint8_t   addr[4];                    ///< IPv4 address value used in \ref vioSetIPv4 / \ref vioGetIPv4 
+} vioAddrIPv4_t;
+
+/// IPv6 Internet Address
+typedef struct {
+  uint8_t   addr[16];                   ///< IPv6 address value used in \ref vioSetIPv6 / \ref vioGetIPv6
+} vioAddrIPv6_t;
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+/// Initialize test input, output.
+/// \return none.
+void vioInit (void);
+
+/// Print formated string to test terminal.
+/// \param[in]     level        level (vioLevel...).
+/// \param[in]     format       formated string to print.
+/// \param[in]     ...          optional arguments (depending on format string).
+/// \return number of characters written or -1 in case of error.
+int32_t vioPrint (uint32_t level, const char *format, ...);
+
+/// Set signal output.
+/// \param[in]     mask         bit mask of signals to set.
+/// \param[in]     signal       signal value to set.
+/// \return none.
+void vioSetSignal (uint32_t mask, uint32_t signal);
+
+/// Get signal input.
+/// \param[in]     mask         bit mask of signals to read.
+/// \return signal value.
+uint32_t vioGetSignal (uint32_t mask);
+
+/// Set value output.
+/// \param[in]     id           output identifier.
+/// \param[in]     value        value to set.
+/// \return none.
+void vioSetValue (uint32_t id, int32_t value);
+
+/// Get value input.
+/// \param[in]     id           input identifier.
+/// \return  value retrieved from input.
+int32_t vioGetValue (uint32_t id);
+
+/// Set XYZ value output.
+/// \param[in]     id           output identifier.
+/// \param[in]     valueXYZ     XYZ data to set.
+/// \return none.
+void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ);
+
+/// Get XYZ value input.
+/// \param[in]     id           input identifier.
+/// \return  XYZ data retrieved from XYZ peripheral.
+vioValueXYZ_t vioGetXYZ (uint32_t id);
+
+/// Set IPv4 address output.
+/// \param[in]     id           output identifier.
+/// \param[in]     addrIPv4     pointer to IPv4 address.
+/// \return none.
+void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4);
+
+/// Get IPv4 address input.
+/// \param[in]     id           input identifier.
+/// \return IPv4 address retrieved from peripheral.
+vioAddrIPv4_t vioGetIPv4 (uint32_t id);
+
+/// Set IPv6 address output.
+/// \param[in]     id           output identifier.
+/// \param[in]     addrIPv6     pointer to IPv6 address.
+/// \return none.
+void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6);
+
+/// Get IPv6 address from peripheral.
+/// \param[in]     id           input identifier.
+/// \return IPv6 address retrieved from peripheral.
+vioAddrIPv6_t vioGetIPv6 (uint32_t id);
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_VIO_H */

external/CMSIS_5/CMSIS/Driver/VIO/Source/vio.c

@@ -0,0 +1,337 @@
+/******************************************************************************
+ * @file     vio.c
+ * @brief    Virtual I/O implementation template
+ * @version  V1.0.0
+ * @date     23. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+#include "cmsis_vio.h"
+
+#include "RTE_Components.h"             // Component selection
+#include CMSIS_device_header
+
+#if !defined CMSIS_VOUT || !defined CMSIS_VIN
+// Add user includes here:
+
+#endif
+
+// VIO input, output definitions
+#define VIO_PRINT_MAX_SIZE      64U     // maximum size of print memory
+#define VIO_PRINTMEM_NUM         4U     // number of print memories
+#define VIO_VALUE_NUM            3U     // number of values
+#define VIO_VALUEXYZ_NUM         3U     // number of XYZ values
+#define VIO_IPV4_ADDRESS_NUM     2U     // number of IPv4 addresses
+#define VIO_IPV6_ADDRESS_NUM     2U     // number of IPv6 addresses
+
+// VIO input, output variables
+__USED uint32_t      vioSignalIn;                                       // Memory for incoming signal
+__USED uint32_t      vioSignalOut;                                      // Memory for outgoing signal
+__USED char          vioPrintMem[VIO_PRINTMEM_NUM][VIO_PRINT_MAX_SIZE]; // Memory for the last value for each level
+__USED int32_t       vioValue   [VIO_VALUE_NUM];                        // Memory for value used in vioGetValue/vioSetValue
+__USED vioValueXYZ_t vioValueXYZ[VIO_VALUEXYZ_NUM];                     // Memory for XYZ value for 3-D vector
+__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM];                 // Memory for IPv4 address value used in vioSetIPv4/vioGetIPv4
+__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM];                 // Memory for IPv6 address value used in vioSetIPv6/vioGetIPv6
+
+#if !defined CMSIS_VOUT
+// Add global user types, variables, functions here:
+
+#endif
+
+#if !defined CMSIS_VIN
+// Add global user types, variables, functions here:
+
+#endif
+
+// Initialize test input, output.
+void vioInit (void) {
+#if !defined CMSIS_VOUT
+// Add user variables here:
+
+#endif
+#if !defined CMSIS_VIN
+// Add user variables here:
+
+#endif
+
+  vioSignalIn  = 0U;
+  vioSignalOut = 0U;
+
+  memset (vioPrintMem, 0, sizeof(vioPrintMem));
+  memset (vioValue,    0, sizeof(vioValue));
+  memset (vioValueXYZ, 0, sizeof(vioValueXYZ));
+  memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4));
+  memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6));
+
+#if !defined CMSIS_VOUT
+// Add user code here:
+
+#endif
+
+#if !defined CMSIS_VIN
+// Add user code here:
+
+#endif
+}
+
+// Print formated string to test terminal.
+int32_t vioPrint (uint32_t level, const char *format, ...) {
+  va_list args;
+  int32_t ret;
+#if !defined CMSIS_VOUT
+// Add user variables here:
+
+#endif
+
+  if (level > vioLevelError) {
+    return (-1);
+  }
+
+  if (level > VIO_PRINTMEM_NUM) {
+    return (-1);
+  }
+
+  va_start(args, format);
+
+  ret = vsnprintf((char *)vioPrintMem[level], sizeof(vioPrintMem[level]), format, args);
+
+  va_end(args);
+
+#if !defined CMSIS_VOUT
+// Add user code here:
+
+#endif
+
+  return (ret);
+}
+
+// Set signal output.
+void vioSetSignal (uint32_t mask, uint32_t signal) {
+#if !defined CMSIS_VOUT
+// Add user variables here:
+
+#endif
+
+  vioSignalOut &= ~mask;
+  vioSignalOut |=  mask & signal;
+
+#if !defined CMSIS_VOUT
+// Add user code here:
+
+#endif
+}
+
+// Get signal input.
+uint32_t vioGetSignal (uint32_t mask) {
+  uint32_t signal;
+#if !defined CMSIS_VIN
+// Add user variables here:
+
+#endif
+
+#if !defined CMSIS_VIN
+// Add user code here:
+
+//   vioSignalIn = ...;
+#endif
+
+  signal = vioSignalIn;
+
+  return (signal & mask);
+}
+
+// Set value output.
+void vioSetValue (uint32_t id, int32_t value) {
+  uint32_t index = id;
+#if !defined CMSIS_VOUT
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_VALUE_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioValue[index] = value;
+
+#if !defined CMSIS_VOUT
+// Add user code here:
+
+#endif
+}
+
+// Get value input.
+int32_t vioGetValue (uint32_t id) {
+  uint32_t index = id;
+  int32_t  value = 0;
+#if !defined CMSIS_VIN
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_VALUE_NUM) {
+    return value;                       /* return default in case of out-of-range index */
+  }
+
+#if !defined CMSIS_VIN
+// Add user code here:
+
+//   vioValue[index] = ...;
+#endif
+
+  value = vioValue[index];
+
+  return value;
+}
+
+// Set XYZ value output.
+void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) {
+  uint32_t index = id;
+#if !defined CMSIS_VOUT
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_VALUEXYZ_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioValueXYZ[index] = valueXYZ;
+
+#if !defined CMSIS_VOUT
+// Add user code here:
+
+#endif
+}
+
+// Get XYZ value input.
+vioValueXYZ_t vioGetXYZ (uint32_t id) {
+  uint32_t index = id;
+  vioValueXYZ_t valueXYZ = {0, 0, 0};
+#if !defined CMSIS_VIN
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_VALUEXYZ_NUM) {
+    return valueXYZ;                    /* return default in case of out-of-range index */
+  }
+
+#if !defined CMSIS_VIN
+// Add user code here:
+
+//   vioValueXYZ[index] = ...;
+#endif
+
+  valueXYZ = vioValueXYZ[index];
+
+  return valueXYZ;
+}
+
+// Set IPv4 address output.
+void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) {
+  uint32_t index = id;
+#if !defined CMSIS_VOUT
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_IPV4_ADDRESS_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioAddrIPv4[index] = addrIPv4;
+
+#if !defined CMSIS_VOUT
+// Add user code here:
+
+#endif
+}
+
+// Get IPv4 address input.
+vioAddrIPv4_t vioGetIPv4 (uint32_t id) {
+  uint32_t index = id;
+  vioAddrIPv4_t addrIPv4 = {0U, 0U, 0U, 0U};
+#if !defined CMSIS_VIN
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_IPV4_ADDRESS_NUM) {
+    return addrIPv4;                    /* return default in case of out-of-range index */
+  }
+
+#if !defined CMSIS_VIN
+// Add user code here:
+
+//   vioAddrIPv4[index] = ...;
+#endif
+
+  addrIPv4 = vioAddrIPv4[index];
+
+  return addrIPv4;
+}
+
+// Set IPv6 address output.
+void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) {
+  uint32_t index = id;
+#if !defined CMSIS_VOUT
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_IPV6_ADDRESS_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioAddrIPv6[index] = addrIPv6;
+
+#if !defined CMSIS_VOUT
+// Add user code here:
+
+#endif
+}
+
+// Get IPv6 address input.
+vioAddrIPv6_t vioGetIPv6 (uint32_t id) {
+  uint32_t index = id;
+  vioAddrIPv6_t addrIPv6 = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U,
+                            0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U};
+#if !defined CMSIS_VIN
+// Add user variables here:
+
+#endif
+
+  if (index >= VIO_IPV6_ADDRESS_NUM) {
+    return addrIPv6;                    /* return default in case of out-of-range index */
+  }
+
+#if !defined CMSIS_VIN
+// Add user code here:
+
+//   vioAddrIPv6[index] = ...;
+#endif
+
+  addrIPv6 = vioAddrIPv6[index];
+
+  return addrIPv6;
+}

external/CMSIS_5/CMSIS/Driver/VIO/Source/vio_memory.c

@@ -0,0 +1,208 @@
+/******************************************************************************
+ * @file     vio_memory.c
+ * @brief    Virtual I/O implementation using memory only
+ * @version  V1.0.0
+ * @date     23. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+#include "cmsis_vio.h"
+
+#include "RTE_Components.h"             // Component selection
+#include CMSIS_device_header
+
+// VIO input, output definitions
+#define VIO_PRINT_MAX_SIZE      64U     // maximum size of print memory
+#define VIO_PRINTMEM_NUM         4U     // number of print memories
+#ifndef VIO_VALUE_NUM
+#define VIO_VALUE_NUM            3U     // number of values
+#endif
+#ifndef VIO_VALUEXYZ_NUM
+#define VIO_VALUEXYZ_NUM         3U     // number of XYZ values
+#endif
+#ifndef VIO_IPV4_ADDRESS_NUM
+#define VIO_IPV4_ADDRESS_NUM     2U     // number of IPv4 addresses
+#endif
+#ifndef VIO_IPV6_ADDRESS_NUM
+#define VIO_IPV6_ADDRESS_NUM     2U     // number of IPv6 addresses
+#endif
+
+// VIO input, output variables
+__USED uint32_t      vioSignalIn;
+__USED uint32_t      vioSignalOut;
+__USED char          vioPrintMem[VIO_PRINTMEM_NUM][VIO_PRINT_MAX_SIZE];
+__USED int32_t       vioValue   [VIO_VALUE_NUM];
+__USED vioValueXYZ_t vioValueXYZ[VIO_VALUEXYZ_NUM];
+__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM];
+__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM];
+
+// Initialize test input, output.
+void vioInit (void) {
+
+  vioSignalIn  = 0U;
+  vioSignalOut = 0U;
+
+  memset (vioPrintMem, 0, sizeof(vioPrintMem));
+  memset (vioValue,    0, sizeof(vioValue));
+  memset (vioValueXYZ, 0, sizeof(vioValueXYZ));
+  memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4));
+  memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6));
+}
+
+// Print formated string to test terminal.
+int32_t vioPrint (uint32_t level, const char *format, ...) {
+  va_list args;
+  int32_t ret;
+
+  if (level > vioLevelError) {
+    return (-1);
+  }
+
+  if (level > VIO_PRINTMEM_NUM) {
+    return (-1);
+  }
+
+  va_start(args, format);
+
+  ret = vsnprintf((char *)vioPrintMem[level], sizeof(vioPrintMem[level]), format, args);
+
+  va_end(args);
+
+  return (ret);
+}
+
+// Set signal output.
+void vioSetSignal (uint32_t mask, uint32_t signal) {
+
+  vioSignalOut &= ~mask;
+  vioSignalOut |=  mask & signal;
+}
+
+// Get signal input.
+uint32_t vioGetSignal (uint32_t mask) {
+  uint32_t signal;
+
+  signal = vioSignalIn;
+
+  return (signal & mask);
+}
+
+// Set value output.
+void vioSetValue (uint32_t id, int32_t value) {
+  uint32_t index = id;
+
+  if (index >= VIO_VALUE_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioValue[index] = value;
+}
+
+// Get value input.
+int32_t vioGetValue (uint32_t id) {
+  uint32_t index = id;
+  int32_t  value = 0;
+
+  if (index >= VIO_VALUE_NUM) {
+    return value;                       /* return default in case of out-of-range index */
+  }
+
+  value = vioValue[index];
+
+  return value;
+}
+
+// Set XYZ value output.
+void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) {
+  uint32_t index = id;
+
+  if (index >= VIO_VALUEXYZ_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioValueXYZ[index] = valueXYZ;
+}
+
+// Get XYZ value input.
+vioValueXYZ_t vioGetXYZ (uint32_t id) {
+  uint32_t index = id;
+  vioValueXYZ_t valueXYZ = {0, 0, 0};
+
+  if (index >= VIO_VALUEXYZ_NUM) {
+    return valueXYZ;                    /* return default in case of out-of-range index */
+  }
+
+  valueXYZ = vioValueXYZ[index];
+
+  return valueXYZ;
+}
+
+// Set IPv4 address output.
+void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) {
+  uint32_t index = id;
+
+  if (index >= VIO_IPV4_ADDRESS_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioAddrIPv4[index] = addrIPv4;
+}
+
+// Get IPv4 address input.
+vioAddrIPv4_t vioGetIPv4 (uint32_t id) {
+  uint32_t index = id;
+  vioAddrIPv4_t addrIPv4 = {0U, 0U, 0U, 0U};
+
+  if (index >= VIO_IPV4_ADDRESS_NUM) {
+    return addrIPv4;                    /* return default in case of out-of-range index */
+  }
+
+  addrIPv4 = vioAddrIPv4[index];
+
+  return addrIPv4;
+}
+
+// Set IPv6 address output.
+void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) {
+  uint32_t index = id;
+
+  if (index >= VIO_IPV6_ADDRESS_NUM) {
+    return;                             /* return in case of out-of-range index */
+  }
+
+  vioAddrIPv6[index] = addrIPv6;
+}
+
+// Get IPv6 address input.
+vioAddrIPv6_t vioGetIPv6 (uint32_t id) {
+  uint32_t index = id;
+  vioAddrIPv6_t addrIPv6 = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U,
+                            0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U};
+
+  if (index >= VIO_IPV6_ADDRESS_NUM) {
+    return addrIPv6;                    /* return default in case of out-of-range index */
+  }
+
+  addrIPv6 = vioAddrIPv6[index];
+
+  return addrIPv6;
+}

external/CMSIS_5/CMSIS/Driver/VIO/cmsis_vio.scvd

@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="utf-8"?>
+<component_viewer schemaVersion="1.2.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+<component name="CMSIS-Driver VIO" version="1.0.0"/>
+
+  <typedefs>
+    <typedef name="vioPrintMem_t" size="64">
+      <member name="mem" type="uint8_t" size="64" offset="0"/>
+    </typedef>
+
+    <typedef name="vioValueXYZ_t" size="12">
+      <member name="X" type="int32_t" offset="0"/>
+      <member name="Y" type="int32_t" offset="4"/>
+      <member name="Z" type="int32_t" offset="8"/>
+    </typedef>
+
+    <typedef name="vioAddrIPv4_t" size="4">
+      <member name="addr" type="uint8_t" size="4"  offset="0"/>
+    </typedef>
+
+    <typedef name="vioAddrIPv6_t" size="16">
+      <member name="addr" type="uint8_t" size="16" offset="0"/>
+    </typedef>
+
+  </typedefs>
+
+  <objects>
+    <object name="VIO Object">
+      <var name="i" type="int32_t" value="0"/>
+
+      <read     name="SignalIn"    type="uint32_t"      symbol="vioSignalIn"/>
+      <read     name="SignalOut"   type="uint32_t"      symbol="vioSignalOut"/>
+      <readlist name="PrintMem"    type="vioPrintMem_t" symbol="vioPrintMem" count="4"/>
+      <read     name="Value"       type="int32_t"       symbol="vioValue"    size="__size_of(&quot;vioValue&quot;)"/>
+      <readlist name="ValueXYZ"    type="vioValueXYZ_t" symbol="vioValueXYZ" count="__size_of(&quot;vioValueXYZ&quot;)"/>
+      <readlist name="IPv4Address" type="vioAddrIPv4_t" symbol="vioAddrIPv4" count="__size_of(&quot;vioAddrIPv4&quot;)"/>
+      <readlist name="IPv6Address" type="vioAddrIPv6_t" symbol="vioAddrIPv6" count="__size_of(&quot;vioAddrIPv6&quot;)"/>
+
+      <out name="CMSIS-Driver VIO">
+        <item property="Signal Bits (Input)"  value="%x[SignalIn]"/>
+        <item property="Signal Bits (Output)" value="%x[SignalOut]"/>
+
+        <item property="Print Memory Array">
+           <list name="i" start="0" limit="PrintMem._count">
+             <item property="Print Memory[%d[i]]" value="%t[PrintMem[i].mem]"/>
+           </list>
+        </item>
+
+        <item property="Value Array">
+           <list name="i" start="0" limit="Value._count">
+             <item property="Value[%d[i]]"  value="%d[Value[i]]"/>
+           </list>
+        </item>
+
+        <item property="ValueXYZ Array">
+           <list name="i" start="0" limit="ValueXYZ._count">
+             <item property="ValueXYZ[%d[i]]" value="X: %d[ValueXYZ[i].X] Y: %d[ValueXYZ[i].Y] Z: %d[ValueXYZ[i].Z]"/>
+           </list>
+        </item>
+
+        <item property="IP4 Address Array">
+           <list name="i" start="0" limit="IPv4Address._count">
+             <item property="IP4 Address[%d[i]]" value="%I[IPv4Address[i].addr]"/>
+           </list>
+        </item>
+
+        <item property="IP6 Address Array">
+           <list name="i" start="0" limit="IPv6Address._count">
+             <item property="IP6 Address[%d[i]]" value="%J[IPv6Address[i].addr]"/>
+           </list>
+        </item>
+
+      </out>
+
+    </object>
+
+  </objects>
+
+</component_viewer>