mirror of
https://github.com/OneOfEleven/uv-k5-firmware-custom.git
synced 2025-06-20 15:08:37 +03:00
Initial commit
This commit is contained in:
OneOfEleven
30
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Abstract.txt
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30
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Abstract.txt
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@ -0,0 +1,30 @@
|
||||
The RTX_Blinky project is a simple RTX Kernel based example
|
||||
for a simulated Cortex-M3 device
|
||||
|
||||
Example functionality:
|
||||
- Clock Settings:
|
||||
- XTAL = 50 MHz
|
||||
- Core = 25 MHz
|
||||
|
||||
The simple RTX Kernel based example simulates the step-motor
|
||||
driver. Four LEDs are blinking simulating the activation of
|
||||
the four output driver stages
|
||||
The simulation does not provide LEDs, so the state changes
|
||||
are output on the Debug printf window:
|
||||
|
||||
- phase A
|
||||
- phase B
|
||||
- phase C
|
||||
- phase D
|
||||
|
||||
This example simulates Half step driver mode and
|
||||
CW rotation direction.
|
||||
|
||||
|
||||
The BLINKY example program is available for one target:
|
||||
|
||||
Simulation: configured for a simulated on-chip Flash
|
||||
|
||||
The example is compatible with other Cortex-M class devices.
|
||||
Simply open the project settings, navigate to Device tab and
|
||||
select another Cortex-M class device.
|
||||
169
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.c
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169
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.c
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|
||||
/* --------------------------------------------------------------------------
|
||||
* Copyright (c) 2013-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* Name: Blinky.c
|
||||
* Purpose: RTX example program
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "cmsis_os.h" // ARM::CMSIS:RTOS:Keil RTX5
|
||||
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
osThreadId_t tid_phaseA; /* Thread id of thread: phase_a */
|
||||
osThreadId_t tid_phaseB; /* Thread id of thread: phase_b */
|
||||
osThreadId_t tid_phaseC; /* Thread id of thread: phase_c */
|
||||
osThreadId_t tid_phaseD; /* Thread id of thread: phase_d */
|
||||
osThreadId_t tid_clock; /* Thread id of thread: clock */
|
||||
|
||||
struct phases_t {
|
||||
int_fast8_t phaseA;
|
||||
int_fast8_t phaseB;
|
||||
int_fast8_t phaseC;
|
||||
int_fast8_t phaseD;
|
||||
} g_phases;
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Switch LED on
|
||||
*---------------------------------------------------------------------------*/
|
||||
void Switch_On (unsigned char led) {
|
||||
printf("LED On: #%d\n\r", led);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Switch LED off
|
||||
*---------------------------------------------------------------------------*/
|
||||
void Switch_Off (unsigned char led) {
|
||||
printf("LED Off: #%d\n\r", led);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Function 'signal_func' called from multiple threads
|
||||
*---------------------------------------------------------------------------*/
|
||||
void signal_func (osThreadId_t tid) {
|
||||
osThreadFlagsSet(tid_clock, 0x0100); /* set signal to clock thread */
|
||||
osDelay(500); /* delay 500ms */
|
||||
osThreadFlagsSet(tid_clock, 0x0100); /* set signal to clock thread */
|
||||
osDelay(500); /* delay 500ms */
|
||||
osThreadFlagsSet(tid, 0x0001); /* set signal to thread 'thread' */
|
||||
osDelay(500); /* delay 500ms */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Thread 1 'phaseA': Phase A output
|
||||
*---------------------------------------------------------------------------*/
|
||||
void phaseA (void *argument) {
|
||||
for (;;) {
|
||||
osThreadFlagsWait(0x0001, osFlagsWaitAny ,osWaitForever); /* wait for an event flag 0x0001 */
|
||||
Switch_On(0);
|
||||
g_phases.phaseA = 1;
|
||||
signal_func(tid_phaseB); /* call common signal function */
|
||||
g_phases.phaseA = 0;
|
||||
Switch_Off(0);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Thread 2 'phaseB': Phase B output
|
||||
*---------------------------------------------------------------------------*/
|
||||
void phaseB (void *argument) {
|
||||
for (;;) {
|
||||
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
|
||||
Switch_On(1);
|
||||
g_phases.phaseB = 1;
|
||||
signal_func(tid_phaseC); /* call common signal function */
|
||||
g_phases.phaseB = 0;
|
||||
Switch_Off(1);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Thread 3 'phaseC': Phase C output
|
||||
*---------------------------------------------------------------------------*/
|
||||
void phaseC (void *argument) {
|
||||
for (;;) {
|
||||
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
|
||||
Switch_On(2);
|
||||
g_phases.phaseC = 1;
|
||||
signal_func(tid_phaseD); /* call common signal function */
|
||||
g_phases.phaseC = 0;
|
||||
Switch_Off(2);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Thread 4 'phaseD': Phase D output
|
||||
*---------------------------------------------------------------------------*/
|
||||
void phaseD (void *argument) {
|
||||
for (;;) {
|
||||
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
|
||||
Switch_On(3);
|
||||
g_phases.phaseD = 1;
|
||||
signal_func(tid_phaseA); /* call common signal function */
|
||||
g_phases.phaseD = 0;
|
||||
Switch_Off(3);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Thread 5 'clock': Signal Clock
|
||||
*---------------------------------------------------------------------------*/
|
||||
void clock (void const *argument) {
|
||||
for (;;) {
|
||||
osSignalWait(0x0100, osWaitForever); /* wait for an event flag 0x0100 */
|
||||
osDelay(80); /* delay 80ms */
|
||||
}
|
||||
}
|
||||
|
||||
/* Define the API v1 thread */
|
||||
osThreadDef(clock, osPriorityNormal, 1, 0);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Main: Initialize and start RTX Kernel
|
||||
*---------------------------------------------------------------------------*/
|
||||
void app_main (void *argument) {
|
||||
|
||||
tid_phaseA = osThreadNew(phaseA, NULL, NULL);
|
||||
tid_phaseB = osThreadNew(phaseB, NULL, NULL);
|
||||
tid_phaseC = osThreadNew(phaseC, NULL, NULL);
|
||||
tid_phaseD = osThreadNew(phaseD, NULL, NULL);
|
||||
tid_clock = osThreadCreate(osThread(clock), NULL);
|
||||
|
||||
osThreadFlagsSet(tid_phaseA, 0x0001); /* set signal to phaseA thread */
|
||||
|
||||
osDelay(osWaitForever);
|
||||
}
|
||||
|
||||
int main (void) {
|
||||
|
||||
// System Initialization
|
||||
SystemCoreClockUpdate();
|
||||
// ...
|
||||
osKernelInitialize(); // Initialize CMSIS-RTOS
|
||||
osThreadNew(app_main, NULL, NULL); // Create application main thread
|
||||
if (osKernelGetState() == osKernelReady) {
|
||||
osKernelStart(); // Start thread execution
|
||||
}
|
||||
|
||||
while(1);
|
||||
}
|
||||
3619
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvguix
vendored
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3619
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvguix
vendored
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File diff suppressed because one or more lines are too long
312
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvoptx
vendored
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312
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvoptx
vendored
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@ -0,0 +1,312 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>Simulation</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>50000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Flash\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>1</uSim>
|
||||
<uTrg>0</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>PWSTATINFO</Key>
|
||||
<Name>200,50,700</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T0</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV0510N9E -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FC1000 -FD20000000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>g_phases</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<ScvdPack>
|
||||
<Filename>C:\Arm\Packs\ARM\CMSIS\5.9.1\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
|
||||
<Type>ARM.CMSIS.5.9.1</Type>
|
||||
<SubType>1</SubType>
|
||||
</ScvdPack>
|
||||
<ScvdPack>
|
||||
<Filename>C:\Arm\Packs\Keil\ARM_Compiler\1.7.2\EventRecorder.scvd</Filename>
|
||||
<Type>Keil.ARM_Compiler.1.7.2</Type>
|
||||
<SubType>1</SubType>
|
||||
</ScvdPack>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>1</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>1</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<LogicAnalyzers>
|
||||
<Wi>
|
||||
<IntNumber>0</IntNumber>
|
||||
<FirstString>`g_phases.phaseA</FirstString>
|
||||
<SecondString>FF0000000000000000000000000000000000F03F00000000000000000000000000000000675F7068617365732E70686173654100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000D03F19000000000000000000000000000000000000009A020000</SecondString>
|
||||
</Wi>
|
||||
<Wi>
|
||||
<IntNumber>1</IntNumber>
|
||||
<FirstString>`g_phases.phaseB</FirstString>
|
||||
<SecondString>008000000000000000000000000000000000F03F00000000000000000000000000000000675F7068617365732E70686173654200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000002000000000000000000D03F19000000000000000000000000000000000000009A020000</SecondString>
|
||||
</Wi>
|
||||
<Wi>
|
||||
<IntNumber>2</IntNumber>
|
||||
<FirstString>`g_phases.phaseC</FirstString>
|
||||
<SecondString>000080000000000000000000000000000000F03F00000000000000000000000000000000675F7068617365732E70686173654300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000003000000000000000000D03F19000000000000000000000000000000000000009A020000</SecondString>
|
||||
</Wi>
|
||||
<Wi>
|
||||
<IntNumber>3</IntNumber>
|
||||
<FirstString>`g_phases.phaseD</FirstString>
|
||||
<SecondString>000000000000C0FFFFFFDFC10000C0FFFFFFDF4101000000000000000000000000000000675F7068617365732E70686173654400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000004000000000000000000D03F19000000000000000000000000000000000000009A020000</SecondString>
|
||||
</Wi>
|
||||
</LogicAnalyzers>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>10000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Files</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\Blinky.c</PathWithFileName>
|
||||
<FilenameWithoutPath>Blinky.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\Abstract.txt</PathWithFileName>
|
||||
<FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Compiler</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
522
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvprojx
vendored
Normal file
522
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvprojx
vendored
Normal file
@ -0,0 +1,522 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>Simulation</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM3</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.5.9.1</PackID>
|
||||
<PackURL>https://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile></SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Flash\</OutputDirectory>
|
||||
<OutputName>Blinky</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Flash\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4097</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M3"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>1</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<nBranchProt>0</nBranchProt>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>7</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>3</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>1</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange></TextAddressRange>
|
||||
<DataAddressRange></DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\RTE\Device\ARMCM3\ARMCM3_ac6.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source Files</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>Blinky.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Blinky.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>Abstract.txt</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Abstract.txt</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Compiler</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis>
|
||||
<api Capiversion="1.0" Cclass="CMSIS" Cgroup="RTOS" exclusive="1">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
<api Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta11"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
</apis>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.4.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Capiversion="1.0.0" Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cvendor="ARM" Cversion="5.5.3" condition="RTOS RTX5">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Capiversion="2.2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.7.0" condition="RTOS2 RTX5">
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="ARM" version="5.9.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM3 CMSIS">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device">
|
||||
<package name="ARM_Compiler" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.3"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="EVR" Cvendor="Keil" Cversion="1.2.0" condition="ARMCC Cortex-M with EVR">
|
||||
<package name="ARM_Compiler" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.3"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.2.0">
|
||||
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
|
||||
<component Capiversion="2.2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.7.0" condition="RTOS2 RTX5"/>
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="ARM" version="5.9.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.6.0">
|
||||
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
|
||||
<component Capiversion="2.2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.7.0" condition="RTOS2 RTX5"/>
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="ARM" version="5.9.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
|
||||
<instance index="0">RTE\Compiler\EventRecorderConf.h</instance>
|
||||
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.5.1" condition="Cortex-M Device"/>
|
||||
<package name="ARM_Compiler" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="Keil" version="1.7.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM3\Source\ARM\ARMCM3_ac6.sct" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM3\ARMCM3_ac6.sct</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM3 CMSIS" isDefaultVariant="1"/>
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="ARM" version="5.9.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\startup_ARMCM3.c" version="2.0.3">
|
||||
<instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM3 CMSIS" isDefaultVariant="1"/>
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="ARM" version="5.9.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.1">
|
||||
<instance index="0">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM3 CMSIS" isDefaultVariant="1"/>
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="ARM" version="5.9.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Simulation"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
67
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.c
vendored
Normal file
67
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.c
vendored
Normal file
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*
|
||||
* $Revision: V5.2.0
|
||||
*
|
||||
* Project: CMSIS-RTOS RTX
|
||||
* Title: RTX Configuration
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "cmsis_compiler.h"
|
||||
#include "rtx_os.h"
|
||||
|
||||
// OS Idle Thread
|
||||
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {}
|
||||
}
|
||||
|
||||
// OS Error Callback function
|
||||
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
|
||||
(void)object_id;
|
||||
|
||||
switch (code) {
|
||||
case osRtxErrorStackOverflow:
|
||||
// Stack overflow detected for thread (thread_id=object_id)
|
||||
break;
|
||||
case osRtxErrorISRQueueOverflow:
|
||||
// ISR Queue overflow detected when inserting object (object_id)
|
||||
break;
|
||||
case osRtxErrorTimerQueueOverflow:
|
||||
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
|
||||
break;
|
||||
case osRtxErrorClibSpace:
|
||||
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
|
||||
break;
|
||||
case osRtxErrorClibMutex:
|
||||
// Standard C/C++ library mutex initialization failed
|
||||
break;
|
||||
case osRtxErrorSVC:
|
||||
// Invalid SVC function called (function=object_id)
|
||||
break;
|
||||
default:
|
||||
// Reserved
|
||||
break;
|
||||
}
|
||||
for (;;) {}
|
||||
//return 0U;
|
||||
}
|
||||
663
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.h
vendored
Normal file
663
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.h
vendored
Normal file
@ -0,0 +1,663 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*
|
||||
* $Revision: V5.6.0
|
||||
*
|
||||
* Project: CMSIS-RTOS RTX
|
||||
* Title: RTX Configuration definitions
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef RTX_CONFIG_H_
|
||||
#define RTX_CONFIG_H_
|
||||
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#ifdef RTE_RTX_CONFIG_H
|
||||
#include RTE_RTX_CONFIG_H
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>System Configuration
|
||||
// =======================
|
||||
|
||||
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined global dynamic memory size.
|
||||
// <i> Default: 32768
|
||||
#ifndef OS_DYNAMIC_MEM_SIZE
|
||||
#define OS_DYNAMIC_MEM_SIZE 4096
|
||||
#endif
|
||||
|
||||
// <o>Kernel Tick Frequency [Hz] <1-1000000>
|
||||
// <i> Defines base time unit for delays and timeouts.
|
||||
// <i> Default: 1000 (1ms tick)
|
||||
#ifndef OS_TICK_FREQ
|
||||
#define OS_TICK_FREQ 1000
|
||||
#endif
|
||||
|
||||
// <e>Round-Robin Thread switching
|
||||
// <i> Enables Round-Robin Thread switching.
|
||||
#ifndef OS_ROBIN_ENABLE
|
||||
#define OS_ROBIN_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o>Round-Robin Timeout <1-1000>
|
||||
// <i> Defines how many ticks a thread will execute before a thread switch.
|
||||
// <i> Default: 5
|
||||
#ifndef OS_ROBIN_TIMEOUT
|
||||
#define OS_ROBIN_TIMEOUT 5
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e>Safety features (Source variant only)
|
||||
// <i> Enables FuSa related features.
|
||||
// <i> Requires RTX Source variant.
|
||||
// <i> Enables:
|
||||
// <i> - selected features from this group
|
||||
// <i> - Thread functions: osThreadProtectPrivileged
|
||||
#ifndef OS_SAFETY_FEATURES
|
||||
#define OS_SAFETY_FEATURES 0
|
||||
#endif
|
||||
|
||||
// <q>Safety Class
|
||||
// <i> Threads assigned to lower classes cannot modify higher class threads.
|
||||
// <i> Enables:
|
||||
// <i> - Object attributes: osSafetyClass
|
||||
// <i> - Kernel functions: osKernelProtect, osKernelDestroyClass
|
||||
// <i> - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass
|
||||
#ifndef OS_SAFETY_CLASS
|
||||
#define OS_SAFETY_CLASS 1
|
||||
#endif
|
||||
|
||||
// <q>MPU Protected Zone
|
||||
// <i> Access protection via MPU (Spatial isolation).
|
||||
// <i> Enables:
|
||||
// <i> - Thread attributes: osThreadZone
|
||||
// <i> - Thread functions: osThreadGetZone, osThreadTerminateZone
|
||||
// <i> - Zone Management: osZoneSetup_Callback
|
||||
#ifndef OS_EXECUTION_ZONE
|
||||
#define OS_EXECUTION_ZONE 1
|
||||
#endif
|
||||
|
||||
// <q>Thread Watchdog
|
||||
// <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).
|
||||
// <i> Enables:
|
||||
// <i> - Thread functions: osThreadFeedWatchdog
|
||||
// <i> - Handler functions: osWatchdogAlarm_Handler
|
||||
#ifndef OS_THREAD_WATCHDOG
|
||||
#define OS_THREAD_WATCHDOG 1
|
||||
#endif
|
||||
|
||||
// <q>Object Pointer checking
|
||||
// <i> Check object pointer alignment and memory region.
|
||||
#ifndef OS_OBJ_PTR_CHECK
|
||||
#define OS_OBJ_PTR_CHECK 0
|
||||
#endif
|
||||
|
||||
// <q>SVC Function Pointer checking
|
||||
// <i> Check SVC function pointer alignment and memory region.
|
||||
// <i> User needs to define a linker execution region RTX_SVC_VENEERS
|
||||
// <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)
|
||||
#ifndef OS_SVC_PTR_CHECK
|
||||
#define OS_SVC_PTR_CHECK 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>ISR FIFO Queue
|
||||
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
|
||||
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
|
||||
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
|
||||
// <i> RTOS Functions called from ISR store requests to this buffer.
|
||||
// <i> Default: 16 entries
|
||||
#ifndef OS_ISR_FIFO_QUEUE
|
||||
#define OS_ISR_FIFO_QUEUE 16
|
||||
#endif
|
||||
|
||||
// <q>Object Memory usage counters
|
||||
// <i> Enables object memory usage counters (requires RTX source variant).
|
||||
#ifndef OS_OBJ_MEM_USAGE
|
||||
#define OS_OBJ_MEM_USAGE 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Thread Configuration
|
||||
// =======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_THREAD_OBJ_MEM
|
||||
#define OS_THREAD_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of user Threads <1-1000>
|
||||
// <i> Defines maximum number of user threads that can be active at the same time.
|
||||
// <i> Applies to user threads with system provided memory for control blocks.
|
||||
#ifndef OS_THREAD_NUM
|
||||
#define OS_THREAD_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Number of user Threads with default Stack size <0-1000>
|
||||
// <i> Defines maximum number of user threads with default stack size.
|
||||
// <i> Applies to user threads with zero stack size specified.
|
||||
#ifndef OS_THREAD_DEF_STACK_NUM
|
||||
#define OS_THREAD_DEF_STACK_NUM 0
|
||||
#endif
|
||||
|
||||
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
|
||||
// <i> Defines the combined stack size for user threads with user-provided stack size.
|
||||
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_THREAD_USER_STACK_SIZE
|
||||
#define OS_THREAD_USER_STACK_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
|
||||
// <i> Defines stack size for threads with zero stack size specified.
|
||||
// <i> Default: 3072
|
||||
#ifndef OS_STACK_SIZE
|
||||
#define OS_STACK_SIZE 512
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
|
||||
// <i> Defines stack size for Idle thread.
|
||||
// <i> Default: 512
|
||||
#ifndef OS_IDLE_THREAD_STACK_SIZE
|
||||
#define OS_IDLE_THREAD_STACK_SIZE 512
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread TrustZone Module Identifier
|
||||
// <i> Defines TrustZone Thread Context Management Identifier.
|
||||
// <i> Applies only to cores with TrustZone technology.
|
||||
// <i> Default: 0 (not used)
|
||||
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
|
||||
#define OS_IDLE_THREAD_TZ_MOD_ID 0
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread Safety Class <0-15>
|
||||
// <i> Defines the Safety Class number.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_IDLE_THREAD_CLASS
|
||||
#define OS_IDLE_THREAD_CLASS 0
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread Zone <0-127>
|
||||
// <i> Defines Thread Zone.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_IDLE_THREAD_ZONE
|
||||
#define OS_IDLE_THREAD_ZONE 0
|
||||
#endif
|
||||
|
||||
// <q>Stack overrun checking
|
||||
// <i> Enables stack overrun check at thread switch (requires RTX source variant).
|
||||
// <i> Enabling this option increases slightly the execution time of a thread switch.
|
||||
#ifndef OS_STACK_CHECK
|
||||
#define OS_STACK_CHECK 1
|
||||
#endif
|
||||
|
||||
// <q>Stack usage watermark
|
||||
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
|
||||
// <i> Enabling this option increases significantly the execution time of thread creation.
|
||||
#ifndef OS_STACK_WATERMARK
|
||||
#define OS_STACK_WATERMARK 0
|
||||
#endif
|
||||
|
||||
// <o>Default Processor mode for Thread execution
|
||||
// <0=> Unprivileged mode
|
||||
// <1=> Privileged mode
|
||||
// <i> Default: Unprivileged mode
|
||||
#ifndef OS_PRIVILEGE_MODE
|
||||
#define OS_PRIVILEGE_MODE 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Timer Configuration
|
||||
// ======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_TIMER_OBJ_MEM
|
||||
#define OS_TIMER_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Timer objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_TIMER_NUM
|
||||
#define OS_TIMER_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>Timer Thread Priority
|
||||
// <8=> Low
|
||||
// <16=> Below Normal <24=> Normal <32=> Above Normal
|
||||
// <40=> High
|
||||
// <48=> Realtime
|
||||
// <i> Defines priority for timer thread
|
||||
// <i> Default: High
|
||||
#ifndef OS_TIMER_THREAD_PRIO
|
||||
#define OS_TIMER_THREAD_PRIO 40
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
|
||||
// <i> Defines stack size for Timer thread.
|
||||
// <i> May be set to 0 when timers are not used.
|
||||
// <i> Default: 512
|
||||
#ifndef OS_TIMER_THREAD_STACK_SIZE
|
||||
#define OS_TIMER_THREAD_STACK_SIZE 512
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread TrustZone Module Identifier
|
||||
// <i> Defines TrustZone Thread Context Management Identifier.
|
||||
// <i> Applies only to cores with TrustZone technology.
|
||||
// <i> Default: 0 (not used)
|
||||
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
|
||||
#define OS_TIMER_THREAD_TZ_MOD_ID 0
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Safety Class <0-15>
|
||||
// <i> Defines the Safety Class number.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_TIMER_THREAD_CLASS
|
||||
#define OS_TIMER_THREAD_CLASS 0
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Zone <0-127>
|
||||
// <i> Defines Thread Zone.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_TIMER_THREAD_ZONE
|
||||
#define OS_TIMER_THREAD_ZONE 0
|
||||
#endif
|
||||
|
||||
// <o>Timer Callback Queue entries <0-256>
|
||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> May be set to 0 when timers are not used.
|
||||
// <i> Default: 4
|
||||
#ifndef OS_TIMER_CB_QUEUE
|
||||
#define OS_TIMER_CB_QUEUE 4
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Event Flags Configuration
|
||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_EVFLAGS_OBJ_MEM
|
||||
#define OS_EVFLAGS_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Event Flags objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_EVFLAGS_NUM
|
||||
#define OS_EVFLAGS_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Mutex Configuration
|
||||
// ======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MUTEX_OBJ_MEM
|
||||
#define OS_MUTEX_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Mutex objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MUTEX_NUM
|
||||
#define OS_MUTEX_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Semaphore Configuration
|
||||
// ==========================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_SEMAPHORE_OBJ_MEM
|
||||
#define OS_SEMAPHORE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Semaphore objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_SEMAPHORE_NUM
|
||||
#define OS_SEMAPHORE_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Memory Pool Configuration
|
||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MEMPOOL_OBJ_MEM
|
||||
#define OS_MEMPOOL_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Memory Pool objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MEMPOOL_NUM
|
||||
#define OS_MEMPOOL_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MEMPOOL_DATA_SIZE
|
||||
#define OS_MEMPOOL_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Message Queue Configuration
|
||||
// ==============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MSGQUEUE_OBJ_MEM
|
||||
#define OS_MSGQUEUE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Message Queue objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MSGQUEUE_NUM
|
||||
#define OS_MSGQUEUE_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MSGQUEUE_DATA_SIZE
|
||||
#define OS_MSGQUEUE_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Event Recorder Configuration
|
||||
// ===============================
|
||||
|
||||
// <e>Global Initialization
|
||||
// <i> Initialize Event Recorder during 'osKernelInitialize'.
|
||||
#ifndef OS_EVR_INIT
|
||||
#define OS_EVR_INIT 1
|
||||
#endif
|
||||
|
||||
// <q>Start recording
|
||||
// <i> Start event recording after initialization.
|
||||
#ifndef OS_EVR_START
|
||||
#define OS_EVR_START 1
|
||||
#endif
|
||||
|
||||
// <h>Global Event Filter Setup
|
||||
// <i> Initial recording level applied to all components.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_LEVEL
|
||||
#define OS_EVR_LEVEL 0x00U
|
||||
#endif
|
||||
|
||||
// <h>RTOS Event Filter Setup
|
||||
// <i> Recording levels for RTX components.
|
||||
// <i> Only applicable if events for the respective component are generated.
|
||||
|
||||
// <e.7>Memory Management
|
||||
// <i> Recording level for Memory Management events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MEMORY_LEVEL
|
||||
#define OS_EVR_MEMORY_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Kernel
|
||||
// <i> Recording level for Kernel events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_KERNEL_LEVEL
|
||||
#define OS_EVR_KERNEL_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Thread
|
||||
// <i> Recording level for Thread events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_THREAD_LEVEL
|
||||
#define OS_EVR_THREAD_LEVEL 0x85U
|
||||
#endif
|
||||
|
||||
// <e.7>Generic Wait
|
||||
// <i> Recording level for Generic Wait events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_WAIT_LEVEL
|
||||
#define OS_EVR_WAIT_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Thread Flags
|
||||
// <i> Recording level for Thread Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_THFLAGS_LEVEL
|
||||
#define OS_EVR_THFLAGS_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Event Flags
|
||||
// <i> Recording level for Event Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_EVFLAGS_LEVEL
|
||||
#define OS_EVR_EVFLAGS_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Timer
|
||||
// <i> Recording level for Timer events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_TIMER_LEVEL
|
||||
#define OS_EVR_TIMER_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Mutex
|
||||
// <i> Recording level for Mutex events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MUTEX_LEVEL
|
||||
#define OS_EVR_MUTEX_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Semaphore
|
||||
// <i> Recording level for Semaphore events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_SEMAPHORE_LEVEL
|
||||
#define OS_EVR_SEMAPHORE_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Memory Pool
|
||||
// <i> Recording level for Memory Pool events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MEMPOOL_LEVEL
|
||||
#define OS_EVR_MEMPOOL_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Message Queue
|
||||
// <i> Recording level for Message Queue events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MSGQUEUE_LEVEL
|
||||
#define OS_EVR_MSGQUEUE_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <h>RTOS Event Generation
|
||||
// <i> Enables event generation for RTX components (requires RTX source variant).
|
||||
|
||||
// <q>Memory Management
|
||||
// <i> Enables Memory Management event generation.
|
||||
#ifndef OS_EVR_MEMORY
|
||||
#define OS_EVR_MEMORY 1
|
||||
#endif
|
||||
|
||||
// <q>Kernel
|
||||
// <i> Enables Kernel event generation.
|
||||
#ifndef OS_EVR_KERNEL
|
||||
#define OS_EVR_KERNEL 1
|
||||
#endif
|
||||
|
||||
// <q>Thread
|
||||
// <i> Enables Thread event generation.
|
||||
#ifndef OS_EVR_THREAD
|
||||
#define OS_EVR_THREAD 1
|
||||
#endif
|
||||
|
||||
// <q>Generic Wait
|
||||
// <i> Enables Generic Wait event generation.
|
||||
#ifndef OS_EVR_WAIT
|
||||
#define OS_EVR_WAIT 1
|
||||
#endif
|
||||
|
||||
// <q>Thread Flags
|
||||
// <i> Enables Thread Flags event generation.
|
||||
#ifndef OS_EVR_THFLAGS
|
||||
#define OS_EVR_THFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Event Flags
|
||||
// <i> Enables Event Flags event generation.
|
||||
#ifndef OS_EVR_EVFLAGS
|
||||
#define OS_EVR_EVFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Timer
|
||||
// <i> Enables Timer event generation.
|
||||
#ifndef OS_EVR_TIMER
|
||||
#define OS_EVR_TIMER 1
|
||||
#endif
|
||||
|
||||
// <q>Mutex
|
||||
// <i> Enables Mutex event generation.
|
||||
#ifndef OS_EVR_MUTEX
|
||||
#define OS_EVR_MUTEX 1
|
||||
#endif
|
||||
|
||||
// <q>Semaphore
|
||||
// <i> Enables Semaphore event generation.
|
||||
#ifndef OS_EVR_SEMAPHORE
|
||||
#define OS_EVR_SEMAPHORE 1
|
||||
#endif
|
||||
|
||||
// <q>Memory Pool
|
||||
// <i> Enables Memory Pool event generation.
|
||||
#ifndef OS_EVR_MEMPOOL
|
||||
#define OS_EVR_MEMPOOL 1
|
||||
#endif
|
||||
|
||||
// <q>Message Queue
|
||||
// <i> Enables Message Queue event generation.
|
||||
#ifndef OS_EVR_MSGQUEUE
|
||||
#define OS_EVR_MSGQUEUE 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </h>
|
||||
|
||||
// Number of Threads which use standard C/C++ library libspace
|
||||
// (when thread specific memory allocation is not used).
|
||||
#if (OS_THREAD_OBJ_MEM == 0)
|
||||
#ifndef OS_THREAD_LIBSPACE_NUM
|
||||
#define OS_THREAD_LIBSPACE_NUM 4
|
||||
#endif
|
||||
#else
|
||||
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
|
||||
#endif
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
|
||||
#endif // RTX_CONFIG_H_
|
||||
34
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Compiler/EventRecorderConf.h
vendored
Normal file
34
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Compiler/EventRecorderConf.h
vendored
Normal file
@ -0,0 +1,34 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK - Component ::Event Recorder
|
||||
* Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: EventRecorderConf.h
|
||||
* Purpose: Event Recorder Configuration
|
||||
* Rev.: V1.1.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>Event Recorder
|
||||
|
||||
// <o>Number of Records
|
||||
// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
|
||||
// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
|
||||
// <65536=>65536
|
||||
// <i>Configures size of Event Record Buffer (each record is 16 bytes)
|
||||
// <i>Must be 2^n (min=8, max=65536)
|
||||
#define EVENT_RECORD_COUNT 64U
|
||||
|
||||
// <o>Time Stamp Source
|
||||
// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer
|
||||
// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset)
|
||||
// <i>Selects source for 32-bit time stamp
|
||||
#define EVENT_TIMESTAMP_SOURCE 2
|
||||
|
||||
// <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
|
||||
// <i>Defines initial time stamp clock frequency (0 when not used)
|
||||
#define EVENT_TIMESTAMP_FREQ 25000000U
|
||||
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
95
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/ARMCM3_ac6.sct
vendored
Normal file
95
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/ARMCM3_ac6.sct
vendored
Normal file
@ -0,0 +1,95 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
|
||||
; command above MUST be in first line (no comment above!)
|
||||
|
||||
/*
|
||||
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Flash Configuration ----------------------------------
|
||||
; <h> Flash Configuration
|
||||
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x00000000
|
||||
#define __ROM_SIZE 0x00040000
|
||||
|
||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
||||
; <h> RAM Configuration
|
||||
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x20000000
|
||||
#define __RAM_SIZE 0x00020000
|
||||
|
||||
/*--------------------- Event Recorder Configuration -------------------------
|
||||
; <h> Event Recorder Configuration
|
||||
; <o> Event Recorder RAM Size (in Bytes) <0x0-0xFFFFFFFF:16>
|
||||
; <i> Memory requirement = 256 + (16 x Number_of_Records)
|
||||
; <i> (defined by EVENT_RECORD_COUNT in EventRecorderConf.h)
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_EVR_SIZE 0x00000800
|
||||
|
||||
/*--------------------- Stack / Heap Configuration ---------------------------
|
||||
; <h> Stack / Heap Configuration
|
||||
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_SIZE 0x00000400
|
||||
#define __HEAP_SIZE 0x00000C00
|
||||
|
||||
/*
|
||||
;------------- <<< end of configuration section >>> ---------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Stack, Heap and Event Recorder boundary definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
|
||||
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after previous section, 8 byte aligned */
|
||||
#define __RAM_EVR_BASE (AlignExpr(+0, 4)) /* starts after previous section, 4 byte aligned */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Scatter File Definitions definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RO_BASE __ROM_BASE
|
||||
#define __RO_SIZE __ROM_SIZE
|
||||
|
||||
#define __RW_BASE __RAM_BASE
|
||||
#define __RW_SIZE (__RAM_SIZE - __RAM_EVR_SIZE - __HEAP_SIZE - __STACK_SIZE)
|
||||
|
||||
|
||||
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
|
||||
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
|
||||
*(.bss.noinit)
|
||||
}
|
||||
|
||||
RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
|
||||
*(+RW +ZI)
|
||||
}
|
||||
|
||||
#if __RAM_EVR_SIZE > 0
|
||||
RW_EVR __RAM_EVR_BASE UNINIT __RAM_EVR_SIZE { ; Event Recorder RAM region
|
||||
EventRecorder.o (+ZI)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if __HEAP_SIZE > 0
|
||||
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
|
||||
}
|
||||
#endif
|
||||
|
||||
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
|
||||
}
|
||||
}
|
||||
150
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/startup_ARMCM3.c
vendored
Normal file
150
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/startup_ARMCM3.c
vendored
Normal file
@ -0,0 +1,150 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM3.c
|
||||
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
|
||||
* @version V2.0.3
|
||||
* @date 31. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM3)
|
||||
#include "ARMCM3.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
|
||||
extern __NO_RETURN void __PROGRAM_START(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler (void);
|
||||
void Default_Handler(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak));
|
||||
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpedantic"
|
||||
#endif
|
||||
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
|
||||
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
MemManage_Handler, /* -12 MPU Fault Handler */
|
||||
BusFault_Handler, /* -11 Bus Fault Handler */
|
||||
UsageFault_Handler, /* -10 Usage Fault Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* -5 SVCall Handler */
|
||||
DebugMon_Handler, /* -4 Debug Monitor Handler */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* -2 PendSV Handler */
|
||||
SysTick_Handler, /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
Interrupt0_Handler, /* 0 Interrupt 0 */
|
||||
Interrupt1_Handler, /* 1 Interrupt 1 */
|
||||
Interrupt2_Handler, /* 2 Interrupt 2 */
|
||||
Interrupt3_Handler, /* 3 Interrupt 3 */
|
||||
Interrupt4_Handler, /* 4 Interrupt 4 */
|
||||
Interrupt5_Handler, /* 5 Interrupt 5 */
|
||||
Interrupt6_Handler, /* 6 Interrupt 6 */
|
||||
Interrupt7_Handler, /* 7 Interrupt 7 */
|
||||
Interrupt8_Handler, /* 8 Interrupt 8 */
|
||||
Interrupt9_Handler /* 9 Interrupt 9 */
|
||||
/* Interrupts 10 .. 223 are left out */
|
||||
};
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler(void)
|
||||
{
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wmissing-noreturn"
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Hard Fault Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic pop
|
||||
#endif
|
||||
|
||||
65
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/system_ARMCM3.c
vendored
Normal file
65
external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/system_ARMCM3.c
vendored
Normal file
@ -0,0 +1,65 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM3.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM3 Device
|
||||
* @version V1.0.1
|
||||
* @date 15. November 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ARMCM3.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (50000000UL) /* Oscillator frequency */
|
||||
|
||||
#define SYSTEM_CLOCK (XTAL / 2U)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System initialization function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
|
||||
#endif
|
||||
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
Reference in New Issue
Block a user