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https://github.com/OneOfEleven/uv-k5-firmware-custom.git
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Initial commit
This commit is contained in:
OneOfEleven
181
external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld
vendored
Normal file
181
external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld
vendored
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@ -0,0 +1,181 @@
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#include "mem_ARMCA7.h"
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MEMORY
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{
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ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
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L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
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RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
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}
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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Image$$VECTORS$$Base = .;
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* (RESET)
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KEEP(*(.isr_vector))
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Image$$VECTORS$$Limit = .;
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*(SVC_TABLE)
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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Image$$RO_DATA$$Base = .;
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*(.rodata*)
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Image$$RO_DATA$$Limit = .;
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KEEP(*(.eh_frame*))
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} > ROM
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > ROM
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > ROM
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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__copy_table_end__ = .;
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} > ROM
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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__zero_table_end__ = .;
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} > ROM
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__etext = .;
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.ttb :
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{
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Image$$TTB$$ZI$$Base = .;
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. += __TTB_SIZE;
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Image$$TTB$$ZI$$Limit = .;
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} > L_TTB
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.data : AT (__etext)
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{
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Image$$RW_DATA$$Base = .;
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__data_start__ = .;
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*(vtable)
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*(.data*)
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Image$$RW_DATA$$Limit = .;
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. = ALIGN(4);
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/* preinit data */
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PROVIDE (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE (__fini_array_end = .);
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > RAM
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.bss ALIGN(0x400):
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{
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Image$$ZI_DATA$$Base = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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__bss_end__ = .;
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Image$$ZI_DATA$$Limit = .;
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__end__ = .;
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end = __end__;
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} > RAM
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#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
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.heap (NOLOAD):
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{
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. = ALIGN(8);
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Image$$HEAP$$ZI$$Base = .;
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. += __HEAP_SIZE;
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Image$$HEAP$$ZI$$Limit = .;
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__HeapLimit = .;
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} > RAM
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#endif
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.stack (NOLOAD):
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{
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. = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
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. = ALIGN(8);
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__StackTop = .;
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Image$$SYS_STACK$$ZI$$Base = .;
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. += __STACK_SIZE;
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Image$$SYS_STACK$$ZI$$Limit = .;
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__stack = .;
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Image$$FIQ_STACK$$ZI$$Base = .;
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. += __FIQ_STACK_SIZE;
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Image$$FIQ_STACK$$ZI$$Limit = .;
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Image$$IRQ_STACK$$ZI$$Base = .;
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. += __IRQ_STACK_SIZE;
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Image$$IRQ_STACK$$ZI$$Limit = .;
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Image$$SVC_STACK$$ZI$$Base = .;
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. += __SVC_STACK_SIZE;
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Image$$SVC_STACK$$ZI$$Limit = .;
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Image$$ABT_STACK$$ZI$$Base = .;
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. += __ABT_STACK_SIZE;
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Image$$ABT_STACK$$ZI$$Limit = .;
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Image$$UND_STACK$$ZI$$Base = .;
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. += __UND_STACK_SIZE;
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Image$$UND_STACK$$ZI$$Limit = .;
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} > RAM
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}
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136
external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
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136
external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
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/******************************************************************************
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* @file startup_ARMCA7.c
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* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
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* @version V1.0.1
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* @date 10. January 2021
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******************************************************************************/
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/*
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* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <ARMCA7.h>
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/*----------------------------------------------------------------------------
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Definitions
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*----------------------------------------------------------------------------*/
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#define USR_MODE 0x10 // User mode
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#define FIQ_MODE 0x11 // Fast Interrupt Request mode
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#define IRQ_MODE 0x12 // Interrupt Request mode
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#define SVC_MODE 0x13 // Supervisor mode
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#define ABT_MODE 0x17 // Abort mode
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#define UND_MODE 0x1B // Undefined Instruction mode
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#define SYS_MODE 0x1F // System mode
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/*----------------------------------------------------------------------------
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Internal References
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*----------------------------------------------------------------------------*/
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void Vectors (void) __attribute__ ((naked, section("RESET")));
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void Reset_Handler (void) __attribute__ ((naked));
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void Default_Handler(void);
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/*----------------------------------------------------------------------------
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Exception / Interrupt Handler
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*----------------------------------------------------------------------------*/
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void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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/*----------------------------------------------------------------------------
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Exception / Interrupt Vector Table
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*----------------------------------------------------------------------------*/
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void Vectors(void) {
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__ASM volatile(
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"LDR PC, =Reset_Handler \n"
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"LDR PC, =Undef_Handler \n"
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"LDR PC, =SVC_Handler \n"
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"LDR PC, =PAbt_Handler \n"
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"LDR PC, =DAbt_Handler \n"
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"NOP \n"
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"LDR PC, =IRQ_Handler \n"
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"LDR PC, =FIQ_Handler \n"
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);
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}
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/*----------------------------------------------------------------------------
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Reset Handler called on controller reset
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*----------------------------------------------------------------------------*/
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void Reset_Handler(void) {
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__ASM volatile(
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// Mask interrupts
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"CPSID if \n"
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// Put any cores other than 0 to sleep
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"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
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"ANDS R0, R0, #3 \n"
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"goToSleep: \n"
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"WFINE \n"
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"BNE goToSleep \n"
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// Reset SCTLR Settings
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"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
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"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
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"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
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"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
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"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
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"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
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"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
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"ISB \n"
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// Configure ACTLR
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"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
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"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
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"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
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// Set Vector Base Address Register (VBAR) to point to this application's vector table
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"LDR R0, =Vectors \n"
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"MCR p15, 0, R0, c12, c0, 0 \n"
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// Setup Stack for each exceptional mode
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"CPS #0x11 \n"
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"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
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"CPS #0x12 \n"
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"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
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"CPS #0x13 \n"
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"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
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"CPS #0x17 \n"
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"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
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"CPS #0x1B \n"
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"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
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"CPS #0x1F \n"
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"LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n"
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// Call SystemInit
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"BL SystemInit \n"
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// Unmask interrupts
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"CPSIE if \n"
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// Call __main
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"BL _start \n"
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);
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}
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/*----------------------------------------------------------------------------
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Default Handler for Exceptions / Interrupts
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*----------------------------------------------------------------------------*/
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void Default_Handler(void) {
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while(1);
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}
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