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OneOfEleven
2023-09-09 08:03:56 +01:00
parent 92305117f1
commit 54441e27d9
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67
external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf vendored Normal file
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/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
define symbol __ICFEDIT_region_TTB_start__ = 0x80500000;
define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x100;
define symbol __ICFEDIT_size_svcstack__ = 0x100;
define symbol __ICFEDIT_size_abtstack__ = 0x100;
define symbol __ICFEDIT_size_undstack__ = 0x100;
define symbol __ICFEDIT_size_heap__ = 0x8000;
define symbol __ICFEDIT_size_ttb__ = 0x4000;
define memory mem with size = 4G;
define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
| mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
| mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ];
define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB };
do not initialize { section .noinit };
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
place in IROM_region { readonly };
place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
place in TTB_region { block TTB };

140
external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s vendored Normal file
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/******************************************************************************
* @file startup_ARMCA7.s
* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
* @version V1.00
* @date 01 Nov 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
MODULE ?startup_ARMCA7
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
PUBLIC Reset_Handler
PUBWEAK Undef_Handler
PUBWEAK SVC_Handler
PUBWEAK PAbt_Handler
PUBWEAK DAbt_Handler
PUBWEAK IRQ_Handler
PUBWEAK FIQ_Handler
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION USR_STACK:DATA:NOROOT(3)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector Table
*----------------------------------------------------------------------------*/
section RESET:CODE:NOROOT(2)
PUBLIC Vectors
Vectors:
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
section .text:CODE:NOROOT(4)
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
EXTERN SystemInit
EXTERN __iar_program_start
Reset_Handler:
// Mask interrupts
CPSID if
// Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5
ANDS R0, R0, #3
goToSleep:
WFINE
BNE goToSleep
// Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
ISB
// Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exception mode
CPS #0x11
LDR SP, =SFE(FIQ_STACK)
CPS #0x12
LDR SP, =SFE(IRQ_STACK)
CPS #0x13
LDR SP, =SFE(SVC_STACK)
CPS #0x17
LDR SP, =SFE(ABT_STACK)
CPS #0x1B
LDR SP, =SFE(UND_STACK)
CPS #0x1F
LDR SP, =SFE(USR_STACK)
// Call SystemInit
BL SystemInit
// Unmask interrupts
CPSIE if
// Call __iar_program_start
BL __iar_program_start
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
Undef_Handler:
SVC_Handler:
PAbt_Handler:
DAbt_Handler:
IRQ_Handler:
FIQ_Handler:
Default_Handler:
B .
END