mirror of
https://github.com/OneOfEleven/uv-k5-firmware-custom.git
synced 2025-06-20 06:58:39 +03:00
Initial commit
This commit is contained in:
OneOfEleven
133
external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7.h
vendored
Normal file
133
external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7.h
vendored
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@ -0,0 +1,133 @@
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/**************************************************************************//**
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* @file ARMCM7.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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* ARMCM7 Device (configured for CM7 without FPU)
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* @version V5.3.3
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* @date 01. May 2023
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******************************************************************************/
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/*
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* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ARMCM7_H
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#define ARMCM7_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/* ------------------- Processor Exceptions Numbers ----------------------------- */
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NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /* 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
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BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /* 11 SVC Interrupt */
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DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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/* ------------------- Processor Interrupt Numbers ------------------------------ */
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Interrupt0_IRQn = 0,
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Interrupt1_IRQn = 1,
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Interrupt2_IRQn = 2,
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Interrupt3_IRQn = 3,
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Interrupt4_IRQn = 4,
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Interrupt5_IRQn = 5,
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Interrupt6_IRQn = 6,
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Interrupt7_IRQn = 7,
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Interrupt8_IRQn = 8,
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Interrupt9_IRQn = 9,
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/* Interrupts 10 .. 223 are left out */
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Interrupt224_IRQn = 224
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} IRQn_Type;
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* ------- Start of section using anonymous unions and disabling warnings ------- */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* -------- Configuration of Core Peripherals ----------------------------------- */
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#define __CM7_REV 0x0000U /* Core revision r0p0 */
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#define __MPU_PRESENT 1U /* MPU present */
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#define __VTOR_PRESENT 1U /* VTOR present */
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#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 0U /* no FPU present */
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#define __FPU_DP 0U /* unused */
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#define __ICACHE_PRESENT 1U /* Instruction Cache present */
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#define __DCACHE_PRESENT 1U /* Data Cache present */
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#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */
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#include "core_cm7.h" /* Processor and core peripherals */
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#include "system_ARMCM7.h" /* System Header */
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/* -------- End of section using anonymous unions and disabling warnings -------- */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARMCM7_H */
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133
external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
vendored
Normal file
133
external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
vendored
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@ -0,0 +1,133 @@
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/**************************************************************************//**
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* @file ARMCM7_DP.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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* ARMCM7 Device (configured for CM7 with double precision FPU)
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* @version V5.3.3
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* @date 01. May 2023
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******************************************************************************/
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/*
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* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ARMCM7_DP_H
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#define ARMCM7_DP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/* ------------------- Processor Exceptions Numbers ----------------------------- */
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NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /* 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
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BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /* 11 SVC Interrupt */
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DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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/* ------------------- Processor Interrupt Numbers ------------------------------ */
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Interrupt0_IRQn = 0,
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Interrupt1_IRQn = 1,
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Interrupt2_IRQn = 2,
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Interrupt3_IRQn = 3,
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Interrupt4_IRQn = 4,
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Interrupt5_IRQn = 5,
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Interrupt6_IRQn = 6,
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Interrupt7_IRQn = 7,
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Interrupt8_IRQn = 8,
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Interrupt9_IRQn = 9,
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/* Interrupts 10 .. 223 are left out */
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Interrupt224_IRQn = 224
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} IRQn_Type;
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* ------- Start of section using anonymous unions and disabling warnings ------- */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* -------- Configuration of Core Peripherals ----------------------------------- */
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#define __CM7_REV 0x0000U /* Core revision r0p0 */
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#define __MPU_PRESENT 1U /* MPU present */
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#define __VTOR_PRESENT 1U /* VTOR present */
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#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1U /* FPU present */
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#define __FPU_DP 1U /* double precision FPU */
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#define __ICACHE_PRESENT 1U /* Instruction Cache present */
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#define __DCACHE_PRESENT 1U /* Data Cache present */
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#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */
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#include "core_cm7.h" /* Processor and core peripherals */
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#include "system_ARMCM7.h" /* System Header */
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/* -------- End of section using anonymous unions and disabling warnings -------- */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARMCM7_DP_H */
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133
external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
vendored
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133
external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
vendored
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@ -0,0 +1,133 @@
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/**************************************************************************//**
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* @file ARMCM7_SP.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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* ARMCM7 Device (configured for CM7 with single precision FPU)
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* @version V5.3.3
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* @date 01. May 2023
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******************************************************************************/
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/*
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* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
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*
|
||||
* www.apache.org/licenses/LICENSE-2.0
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||||
*
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||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
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#ifndef ARMCM7_SP_H
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#define ARMCM7_SP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
|
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|
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typedef enum IRQn
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||||
{
|
||||
/* ------------------- Processor Exceptions Numbers ----------------------------- */
|
||||
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
|
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UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
|
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SVCall_IRQn = -5, /* 11 SVC Interrupt */
|
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DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
|
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PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
|
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SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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|
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/* ------------------- Processor Interrupt Numbers ------------------------------ */
|
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Interrupt0_IRQn = 0,
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Interrupt1_IRQn = 1,
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Interrupt2_IRQn = 2,
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Interrupt3_IRQn = 3,
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Interrupt4_IRQn = 4,
|
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Interrupt5_IRQn = 5,
|
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Interrupt6_IRQn = 6,
|
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Interrupt7_IRQn = 7,
|
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Interrupt8_IRQn = 8,
|
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Interrupt9_IRQn = 9,
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/* Interrupts 10 .. 223 are left out */
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Interrupt224_IRQn = 224
|
||||
} IRQn_Type;
|
||||
|
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|
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/* ================================================================================ */
|
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/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
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/* ------- Start of section using anonymous unions and disabling warnings ------- */
|
||||
#if defined (__CC_ARM)
|
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#pragma push
|
||||
#pragma anon_unions
|
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#elif defined (__ICCARM__)
|
||||
#pragma language=extended
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wc11-extensions"
|
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
|
||||
#elif defined (__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TMS470__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TASKING__)
|
||||
#pragma warning 586
|
||||
#elif defined (__CSMC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#else
|
||||
#warning Not supported compiler type
|
||||
#endif
|
||||
|
||||
|
||||
/* -------- Configuration of Core Peripherals ----------------------------------- */
|
||||
#define __CM7_REV 0x0000U /* Core revision r0p0 */
|
||||
#define __MPU_PRESENT 1U /* MPU present */
|
||||
#define __VTOR_PRESENT 1U /* VTOR present */
|
||||
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /* FPU present */
|
||||
#define __FPU_DP 0U /* single precision FPU */
|
||||
#define __ICACHE_PRESENT 1U /* Instruction Cache present */
|
||||
#define __DCACHE_PRESENT 1U /* Data Cache present */
|
||||
#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */
|
||||
|
||||
#include "core_cm7.h" /* Processor and core peripherals */
|
||||
#include "system_ARMCM7.h" /* System Header */
|
||||
|
||||
|
||||
|
||||
/* -------- End of section using anonymous unions and disabling warnings -------- */
|
||||
#if defined (__CC_ARM)
|
||||
#pragma pop
|
||||
#elif defined (__ICCARM__)
|
||||
/* leave anonymous unions enabled */
|
||||
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
#pragma clang diagnostic pop
|
||||
#elif defined (__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TMS470__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TASKING__)
|
||||
#pragma warning restore
|
||||
#elif defined (__CSMC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#else
|
||||
#warning Not supported compiler type
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARMCM7_SP_H */
|
||||
64
external/CMSIS_5/Device/ARM/ARMCM7/Include/system_ARMCM7.h
vendored
Normal file
64
external/CMSIS_5/Device/ARM/ARMCM7/Include/system_ARMCM7.h
vendored
Normal file
@ -0,0 +1,64 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM7.h
|
||||
* @brief CMSIS Device System Header File for
|
||||
* ARMCM7 Device
|
||||
* @version V5.3.3
|
||||
* @date 11. July 2022
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_ARMCM7_H
|
||||
#define SYSTEM_ARMCM7_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
\brief Exception / Interrupt Handler Function Prototype
|
||||
*/
|
||||
typedef void(*VECTOR_TABLE_Type)(void);
|
||||
|
||||
/**
|
||||
\brief System Clock Frequency (Core Clock)
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
\brief Setup the microcontroller system.
|
||||
|
||||
Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Update SystemCoreClock variable.
|
||||
|
||||
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_ARMCM7_H */
|
||||
Reference in New Issue
Block a user