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71
external/CMSIS_5/Device/_Template_Vendor/ReadMe.txt vendored Normal file
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/*****************************************************************************
* @file ReadMe.txt
* @brief Explanation how to use the Device folder and template files
* @version V3.0.4
* @date 20. January 2021
*****************************************************************************/
Following directory structure and template files are given:
- <Vendor>
|
+-- <Device>
|
+-- Include
| +-- Template only Armv8-M/v8.1-M TrustZone
| | +- partition_<Device>.h Secure/Non-Secure configuration
| +- <Device>.h header file
| +- system_<Device>.h system include file
+-- Source
|
+- startup_<Device>.c C startup file file
+- system_<Device>.c system source file
|
+-- ARM Arm ARMCLang toolchain
| +- startup_<Device>.s ASM startup file for ARMCC (deprecated)
| +- startup_<Device>.S ASM startup file for ARMCLang (deprecated)
| +- <Device>.sct Scatter file
|
+-- GCC Arm GNU toolchain
| +- startup_<Device>.S ASM startup file (deprecated)
| +- <Device>.ld Linker description file
|
+-- IAR IAR toolchain
+- startup_<Device>.s ASM startup file
Copy the complete folder including files and replace:
- folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
- folder name 'Device' with your specific device name e.g.: LPC17xx.
- in the filenames 'Device' with your specific device name e.g.: LPC17xx.
The template files contain comments starting with 'ToDo: '
There it is described what you need to do.
The template files contain following placeholder:
<Device>
<Device> should be replaced with your specific device name.
e.g.: LPC17xx
<DeviceInterrupt>
<DeviceInterrupt> should be replaced with a specific device interrupt name.
e.g.: TIM1 for Timer#1 interrupt.
<DeviceAbbreviation>
<DeviceAbbreviation> should be replaced with a dedicated device family
abbreviation (e.g.: LPC for LPC17xx device family)
Cortex-M#
Cortex-M# can be replaced with the specific Cortex-M number
e.g.: Cortex-M3
Note:
Template files (i.e. startup_Device.s, system_Device.c) are application
specific and therefore expected to be copied into the application project
folder prior to use!

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external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Device.h vendored Normal file
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/*************************************************************************//**
* @file <Device>.h
* @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
* Device <Device>
* @version V1.0.0
* @date 20. January 2021
*****************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef <Device>_H /* ToDo: Replace '<Device>' with your device name */
#define <Device>_H
#ifdef __cplusplus
extern "C" {
#endif
/* ========================================================================= */
/* ============ Interrupt Number Definition ============ */
/* ========================================================================= */
typedef enum IRQn
{
/* ================ Cortex-M Core Exception Numbers ================ */
/* ToDo: Add Cortex exception numbers according the used Cortex-Core */
Reset_IRQn = -15, /* 1 Reset Vector
invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt
cannot be stopped or preempted */
HardFault_IRQn = -13, /* 3 Hard Fault
all classes of Fault */
MemoryManagement_IRQn = -12, /* 4 Memory Management
MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /* 5 Bus Fault
Pre-Fetch-, Memory Access, other address/memory Fault */
UsageFault_IRQn = -10, /* 6 Usage Fault
i.e. Undef Instruction, Illegal State Transition */
SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor */
PendSV_IRQn = -2, /* 14 Pendable request for system service */
SysTick_IRQn = -1, /* 15 System Tick Timer */
/* ================ <Device> Interrupt Numbers ================ */
/* ToDo: Add here your device specific interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
<DeviceInterrupt first>_IRQn = 0, /* first Device Interrupt*/
...
<DeviceInterrupt last>_IRQn = n /* last Device Interrupt */
} IRQn_Type;
/* ========================================================================= */
/* ============ Processor and Core Peripheral Section ============ */
/* ========================================================================= */
/* ================ Start of section using anonymous unions ================ */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* ================ Configuration of Core Peripherals ================ */
/* ToDo: Set the defines according your Device */
/* ToDo: Define the correct core revision
valid CMSIS core revision macro names are:
__CM0_REV, __CM0PLUS_REV, __CM1_REV, __CM3_REV, __CM4_REV, __CM7_REV
__CM23_REV, __CM33_REV, __CM35P_REV, __CM55_REV
__SC000_REV, __SC300_REV */
#define __CM#_REV 0x0201U /* Core Revision r2p1 */
/* ToDo: define the correct core features for the <Device> */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __VTOR_PRESENT 1U /* Set to 1 if VTOR is present */
#define __MPU_PRESENT 1U /* Set to 1 if MPU is present */
#define __FPU_PRESENT 0U /* Set to 1 if FPU is present */
#define __FPU_DP 0U /* Set to 1 if FPU is double precision FPU (default is single precision FPU) */
#define __DSP_PRESENT 1U /* Set to 1 if DSP extension are present */
#define __SAUREGION_PRESENT 1U /* Set to 1 if SAU regions are present */
#define __PMU_PRESENT 1U /* Set to 1 if PMU is present */
#define __PMU_NUM_EVENTCNT 8U /* Set number of PMU Event Counters */
#define __ICACHE_PRESENT 0U /* Set to 1 if I-Cache is present */
#define __DCACHE_PRESENT 0U /* Set to 1 if D-Cache is present */
#define __DTCM_PRESENT 0U /* Set to 1 if DTCM is present */
/* ToDo: Include the CMSIS core header file according your device.
valid CMSIS core header files are:
core_cm0.h, core_cm0plus.h, core_cm1.h, core_cm3.h, core_cm4.h, core_cm7.h
core_cm23.h, core_cm33.h, core_cm35p.h, core_cm55.h
core_sc000.h, core_sc300.h */
#include <core_cm#.h> /* Processor and core peripherals */
/* ToDo: Include your system_<Device>.h file
replace '<Device>' with your device name */
#include "system_<Device>.h" /* System Header */
/* ========================================================================= */
/* ============ Device Specific Peripheral Section ============ */
/* ========================================================================= */
/* ToDo: Add here your device specific peripheral access structure typedefs
including bit definitions for Pos/Msk macros
following is an example for a timer */
/* ========================================================================= */
/* ============ TMR ============ */
/* ========================================================================= */
typedef struct
{
__IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Load Register */
__IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Value Register */
__IOM uint32_t CONTROL; /* Offset: 0x008 (R/W) Control Register */
__OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Clear Interrupt Register */
__IM uint32_t RIS; /* Offset: 0x010 (R/ ) Raw Interrupt Status Register */
__IM uint32_t MIS; /* Offset: 0x014 (R/ ) Interrupt Status Register */
__IOM uint32_t BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */
} <DeviceAbbreviation>_TMR_TypeDef;
/* <DeviceAbbreviation>_TMR LOAD Register Definitions */
#define <DeviceAbbreviation>_TMR_LOAD_Pos 0
#define <DeviceAbbreviation>_TMR_LOAD_Msk (0xFFFFFFFFUL /*<< <DeviceAbbreviation>_TMR_LOAD_Pos*/)
/* <DeviceAbbreviation>_TMR VALUE Register Definitions */
#define <DeviceAbbreviation>_TMR_VALUE_Pos 0
#define <DeviceAbbreviation>_TMR_VALUE_Msk (0xFFFFFFFFUL /*<< <DeviceAbbreviation>_TMR_VALUE_Pos*/)
/* <DeviceAbbreviation>_TMR CONTROL Register Definitions */
#define <DeviceAbbreviation>_TMR_CONTROL_SIZE_Pos 1
#define <DeviceAbbreviation>_TMR_CONTROL_SIZE_Msk (1UL << <DeviceAbbreviation>_TMR_CONTROL_SIZE_Pos)
#define <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Pos 0
#define <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Msk (1UL /*<< <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Pos*/)
/* ================ End of section using anonymous unions ================ */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* ========================================================================= */
/* ============ Device Specific Peripheral Address Map ============ */
/* ========================================================================= */
/* ToDo: Add here your device peripherals base addresses
following is an example for timer */
/* Peripheral and SRAM base address */
#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /* (FLASH ) Base Address */
#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /* (SRAM ) Base Address */
#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /* (Peripheral) Base Address */
/* Peripheral memory map */
#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /* (Timer0 ) Base Address */
#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /* (Timer1 ) Base Address */
#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /* (Timer2 ) Base Address */
/* ========================================================================= */
/* ============ Peripheral declaration ============ */
/* ========================================================================= */
/* ToDo: Add here your device peripherals pointer definitions
following is an example for timer */
#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#ifdef __cplusplus
}
#endif
#endif /* <Device>_H */

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/*************************************************************************//**
* @file system_<Device>.h
* @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
* Device <Device>
* @version V1.0.1
* @date 11. July 2022
*****************************************************************************/
/*
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_<Device>_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_<Device>_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
\brief Exception / Interrupt Handler Function Prototype
*/
typedef void(*VECTOR_TABLE_Type)(void);
/**
\brief System Clock Frequency (Core Clock)
*/
extern uint32_t SystemCoreClock;
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */

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external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac5.sct vendored Normal file
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#! armcc -E
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Region base & size definition
*----------------------------------------------------------------------------*/
#define __RO_BASE ( __ROM_BASE )
#define __RO_SIZE ( __ROM_SIZE )
#define __RW_BASE ( __RAM_BASE )
#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
/*----------------------------------------------------------------------------
Scatter Region definition
*----------------------------------------------------------------------------*/
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

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#! armclang -E --target=arm-arm-none-eabi -mcpu=<CPU> -xc
; command above MUST be in first line (no comment above!)
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=<CPU> -xc -mcmse
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*--------------------- CMSE Veneer Configuration ---------------------------
; <h> CMSE Veneer Configuration
; <o0> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
; </h>
*----------------------------------------------------------------------------*/
#define __CMSEVENEER_SIZE 0x200
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Region base & size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
#define __CV_SIZE ( __CMSEVENEER_SIZE )
#else
#define __CV_SIZE ( 0 )
#endif
#define __RO_BASE ( __ROM_BASE )
#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
#define __RW_BASE ( __RAM_BASE )
#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
/*----------------------------------------------------------------------------
Scatter Region definition
*----------------------------------------------------------------------------*/
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
ER_CMSE_VENEER __CV_BASE __CV_SIZE {
*(Veneer$$CMSE)
}
}
#endif

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;/*************************************************************************//**
; * @file startup_<Device>.s
; * @brief CMSIS-Core(M) Device Startup File for
; * Device <Device> (using Arm Compiler 5 with scatter file)
; * @version V1.0.0
; * @date 20. January 2021
; ****************************************************************************/
;/*
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
; ToDo: Add Cortex exception vectors according the used Cortex-Core
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; ToDo: Add your device specific interrupt vectors
; Interrupts
DCD <DeviceInterrupt first>_Handler ; first Device Interrupt
...
DCD <DeviceInterrupt last>_Handler ; last Device Interrupt
; ToDo: calculate the empty space according the used Cortex-Core
SPACE (x * 4) ; Interrupts x .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; The default macro is not used for HardFault_Handler
; because this results in a poor debug illusion.
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; ToDo: Add Cortex exception handler according the used Cortex-Core
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
; Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
; ToDo: Add your device specific interrupt handler
Set_Default_Handler <DeviceInterrupt first>_Handler
...
Set_Default_Handler <DeviceInterrupt last>_Handler
ALIGN
; User setup Stack & Heap
IF :LNOT::DEF:__MICROLIB
IMPORT __use_two_region_memory
ENDIF
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

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;/*************************************************************************//**
; * @file startup_<Device>.s
; * @brief CMSIS-Core(M) Device Startup File for
; * Device <Device> (using Arm Compiler 5 without scatter file)
; * @version V1.0.0
; * @date 20. January 2021
; ****************************************************************************/
;/*
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
; ToDo: Add Cortex exception vectors according the used Cortex-Core
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; ToDo: Add your device specific interrupt vectors
; Interrupts
DCD <DeviceInterrupt first>_Handler ; first Device Interrupt
...
DCD <DeviceInterrupt last>_Handler ; last Device Interrupt
; ToDo: calculate the empty space according the used Cortex-Core
SPACE (x * 4) ; Interrupts x .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; The default macro is not used for HardFault_Handler
; because this results in a poor debug illusion.
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; ToDo: Add Cortex exception handler according the used Cortex-Core
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
; Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
; ToDo: Add your device specific interrupt handler
Set_Default_Handler <DeviceInterrupt first>_Handler
...
Set_Default_Handler <DeviceInterrupt last>_Handler
ALIGN
; User setup Stack & Heap
IF :LNOT::DEF:__MICROLIB
IMPORT __use_two_region_memory
ENDIF
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

151
external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac6.S vendored Normal file
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/**************************************************************************//**
* @file startup_<Device>.S
* @brief CMSIS-Core(M) Device Startup File for
* Device <Device> (using Arm Compiler 6 with scatter file)
* @version V1.0.0
* @date 20. January 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
/* ToDo: Set .arch to the architecture according the used Cortex-Core */
.arch armv8-m.main
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
#endif
.section RESET
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
/* ToDo: Add Cortex exception vectors according the used Cortex-Core */
__Vectors:
.long __INITIAL_SP /* Initial Stack Pointer */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* -14 NMI Handler */
.long HardFault_Handler /* -13 Hard Fault Handler */
.long MemManage_Handler /* -12 MPU Fault Handler */
.long BusFault_Handler /* -11 Bus Fault Handler */
.long UsageFault_Handler /* -10 Usage Fault Handler */
.long SecureFault_Handler /* -9 Secure Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVCall Handler */
.long DebugMon_Handler /* -4 Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* ToDo: Add your device specific interrupt vectors */
/* Interrupts */
.long <DeviceInterrupt first>_Handler /* first Device Interrupt */
...
.long <DeviceInterrupt last>_Handler /* last Device Interrupt */
/* ToDo: calculate the empty space according the used Cortex-Core */
.space (x * 4) /* Interrupts x .. 480 are left out */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
.thumb
.section .text
.align 2
.thumb_func
.type Reset_Handler, %function
.globl Reset_Handler
.fnstart
Reset_Handler:
ldr r0, =__INITIAL_SP
msr psp, r0
ldr r0, =__STACK_LIMIT
msr msplim, r0
msr psplim, r0
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ldr r0, =__STACK_SEAL
ldr r1, =0xFEF5EDA5U
strd r1,r1,[r0,#0]
#endif
bl SystemInit
bl __main
.fnend
.size Reset_Handler, . - Reset_Handler
/* The default macro is not used for HardFault_Handler
* because this results in a poor debug illusion.
*/
.thumb_func
.type HardFault_Handler, %function
.weak HardFault_Handler
.fnstart
HardFault_Handler:
b .
.fnend
.size HardFault_Handler, . - HardFault_Handler
.thumb_func
.type Default_Handler, %function
.weak Default_Handler
.fnstart
Default_Handler:
b .
.fnend
.size Default_Handler, . - Default_Handler
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Set_Default_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* ToDo: Add Cortex exception handler according the used Cortex-Core */
/* Default exception/interrupt handler */
Set_Default_Handler NMI_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SecureFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
/* ToDo: Add your device specific interrupt handler */
Set_Default_Handler <DeviceInterrupt first>_Handler
...
Set_Default_Handler <DeviceInterrupt last>_Handler
.end

316
external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_arm.ld vendored Normal file
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/******************************************************************************
* @file gcc_arm.ld
* @brief GNU Linker Script for Cortex-M based device
* @version V2.2.0
* @date 20. January 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
*-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*---------------------- Flash Configuration ----------------------------------
<h> Flash Configuration
<o0> Flash Base Address <0x0-0xFFFFFFFF:8>
<o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
-----------------------------------------------------------------------------*/
__ROM_BASE = 0x00000000;
__ROM_SIZE = 0x00040000;
/*--------------------- Embedded RAM Configuration ----------------------------
<h> RAM Configuration
<o0> RAM Base Address <0x0-0xFFFFFFFF:8>
<o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
-----------------------------------------------------------------------------*/
__RAM_BASE = 0x20000000;
__RAM_SIZE = 0x00020000;
/*--------------------- Stack / Heap Configuration ----------------------------
<h> Stack / Heap Configuration
<o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
-----------------------------------------------------------------------------*/
__STACK_SIZE = 0x00000400;
__HEAP_SIZE = 0x00000C00;
/*
*-------------------- <<< end of configuration section >>> -------------------
*/
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
*/
__STACKSEAL_SIZE = 0;
MEMORY
{
FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __StackSeal (only if ARMv8-M stack sealing is used)
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
/*
* SG veneers:
* All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
* must be set, either with the command line option <20>--section-start<72> or in a linker script,
* to indicate where to place these veneers in memory.
*/
/*
.gnu.sgstubs :
{
. = ALIGN(32);
} > FLASH
*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG ((__data_end__ - __data_start__) / 4)
/* Add each additional data section here */
/*
LONG (__etext2)
LONG (__data2_start__)
LONG ((__data2_end__ - __data2_start__) / 4)
*/
__copy_table_end__ = .;
} > FLASH
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
/* Add each additional bss section here */
/*
LONG (__bss2_start__)
LONG ((__bss2_end__ - __bss2_start__) / 4)
*/
__zero_table_end__ = .;
} > FLASH
/**
* Location counter can end up 2byte aligned with narrow Thumb code but
* __etext is assumed by startup code to be the LMA of a section in RAM
* which must be 4byte aligned
*/
__etext = ALIGN (4);
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
/*
* Secondary data section, optional
*
* Remember to add each additional data section
* to the .copy.table above to asure proper
* initialization during startup.
*/
/*
__etext2 = ALIGN (4);
.data2 : AT (__etext2)
{
. = ALIGN(4);
__data2_start__ = .;
*(.data2)
*(.data2.*)
. = ALIGN(4);
__data2_end__ = .;
} > RAM2
*/
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM AT > RAM
/*
* Secondary bss section, optional
*
* Remember to add each additional bss section
* to the .zero.table above to asure proper
* initialization during startup.
*/
/*
.bss2 :
{
. = ALIGN(4);
__bss2_start__ = .;
*(.bss2)
*(.bss2.*)
. = ALIGN(4);
__bss2_end__ = .;
} > RAM2 AT > RAM2
*/
.heap (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
} > RAM
.stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
} > RAM
PROVIDE(__stack = __StackTop);
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing uncomment '.stackseal' section
*/
/*
.stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackSeal = .;
. = . + 8;
. = ALIGN(8);
} > RAM
*/
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

194
external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S vendored Normal file
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/**************************************************************************//**
* @file startup_<Device>.S
* @brief CMSIS-Core(M) Device Startup File for
* Device <Device>
* @version V1.0.0
* @date 20. January 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
/* ToDo: Set .arch to the architecture according the used Cortex-Core */
.arch armv8-m.main
#define __INITIAL_SP __StackTop
#define __STACK_LIMIT __StackLimit
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACK_SEAL __StackSeal
#endif
.section .vectors
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
/* ToDo: Add Cortex exception vectors according the used Cortex-Core */
__Vectors:
.long __INITIAL_SP /* Initial Stack Pointer */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* -14 NMI Handler */
.long HardFault_Handler /* -13 Hard Fault Handler */
.long MemManage_Handler /* -12 MPU Fault Handler */
.long BusFault_Handler /* -11 Bus Fault Handler */
.long UsageFault_Handler /* -10 Usage Fault Handler */
.long SecureFault_Handler /* -9 Secure Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVCall Handler */
.long DebugMon_Handler /* -4 Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* ToDo: Add your device specific interrupt vectors */
/* Interrupts */
.long <DeviceInterrupt first>_Handler /* first Device Interrupt */
...
.long <DeviceInterrupt last>_Handler /* last Device Interrupt */
/* ToDo: calculate the empty space according the used Cortex-Core */
.space (x * 4) /* Interrupts x .. 480 are left out */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
.thumb
.section .text
.align 2
.thumb_func
.type Reset_Handler, %function
.globl Reset_Handler
.fnstart
Reset_Handler:
ldr r0, =__INITIAL_SP
msr psp, r0
ldr r0, =__STACK_LIMIT
msr msplim, r0
msr psplim, r0
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ldr r0, =__STACK_SEAL
ldr r1, =0xFEF5EDA5U
strd r1,r1,[r0,#0]
#endif
bl SystemInit
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4] /* source address */
ldr r2, [r4, #4] /* destination address */
ldr r3, [r4, #8] /* word count */
lsl r3, r3, #2 /* byte count */
.L_loop0_0:
subs r3, #4 /* decrement byte count */
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3] /* destination address */
ldr r2, [r3, #4] /* word count */
lsl r2, r2, #2 /* byte count */
movs r0, 0
.L_loop2_0:
subs r2, #4 /* decrement byte count */
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
bl _start
.fnend
.size Reset_Handler, . - Reset_Handler
/* The default macro is not used for HardFault_Handler
* because this results in a poor debug illusion.
*/
.thumb_func
.type HardFault_Handler, %function
.weak HardFault_Handler
.fnstart
HardFault_Handler:
b .
.fnend
.size HardFault_Handler, . - HardFault_Handler
.thumb_func
.type Default_Handler, %function
.weak Default_Handler
.fnstart
Default_Handler:
b .
.fnend
.size Default_Handler, . - Default_Handler
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Set_Default_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* ToDo: Add Cortex exception handler according the used Cortex-Core */
/* Default exception/interrupt handler */
Set_Default_Handler NMI_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SecureFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
/* ToDo: Add your device specific interrupt handler */
Set_Default_Handler <DeviceInterrupt first>_Handler
...
Set_Default_Handler <DeviceInterrupt last>_Handler
.end

156
external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/IAR/startup_Device.s vendored Normal file
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;/**************************************************************************//**
; * @file startup_<Device>.s
; * @brief CMSIS Cortex-M# Core Device Startup File for
; * Device <Device>
; * @version V1.0.0
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
DS32 (214) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
THUMB
; Reset Handler
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK Interrupt0_Handler
PUBWEAK Interrupt1_Handler
PUBWEAK Interrupt2_Handler
PUBWEAK Interrupt3_Handler
PUBWEAK Interrupt4_Handler
PUBWEAK Interrupt5_Handler
PUBWEAK Interrupt6_Handler
PUBWEAK Interrupt7_Handler
PUBWEAK Interrupt8_Handler
PUBWEAK Interrupt9_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
Interrupt0_Handler
Interrupt1_Handler
Interrupt2_Handler
Interrupt3_Handler
Interrupt4_Handler
Interrupt5_Handler
Interrupt6_Handler
Interrupt7_Handler
Interrupt8_Handler
Interrupt9_Handler
Default_Handler
B .
END

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external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/startup_Device.c vendored Normal file
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/******************************************************************************
* @file startup_<Device>.c
* @brief CMSIS-Core(M) Device Startup File for
* Device <Device>
* @version V1.0.0
* @date 20. January 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "<Device>.h"
/*---------------------------------------------------------------------------
External References
*---------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif
extern __NO_RETURN void __PROGRAM_START(void);
/*---------------------------------------------------------------------------
Internal References
*---------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler (void);
__NO_RETURN void Default_Handler(void);
/* ToDo: Add Cortex exception handler according the used Cortex-Core */
/*---------------------------------------------------------------------------
Exception / Interrupt Handler
*---------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/* ToDo: Add your device specific interrupt handler */
void <DeviceInterrupt first>_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
...
void <DeviceInterrupt last>_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
/* ToDo: Add Cortex exception vectors according the used Cortex-Core */
extern const VECTOR_TABLE_Type __VECTOR_TABLE[<Device vector table entries>];
const VECTOR_TABLE_Type __VECTOR_TABLE[<Device vector table entries>] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* ToDo: Add your device specific interrupt vectors */
/* Interrupts */
<DeviceInterrupt first>_Handler, /* first Device Interrupt */
...
<DeviceInterrupt last>_Handler /* last Device Interrupt */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*---------------------------------------------------------------------------
Reset Handler called on controller reset
*---------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));
/* ToDo: Initialize stack limit register for Armv8-M Main Extension based processors*/
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));
/* ToDo: Add stack sealing for Armv8-M based processors */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*---------------------------------------------------------------------------
Hard Fault Handler
*---------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*---------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*---------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif

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external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c vendored Normal file
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/*************************************************************************//**
* @file system_<Device>.c
* @brief CMSIS-Core(M) Device Peripheral Access Layer Source File for
* Device <Device>
* @version V1.0.0
* @date 20. January 2021
*****************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "<Device>.h"
/* ToDo: Include partition header file if TZ is used */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_<Device>.h"
#endif
/*---------------------------------------------------------------------------
Define clocks
*---------------------------------------------------------------------------*/
/* ToDo: Add here your necessary defines for device initialization
following is an example for different system frequencies */
#define XTAL (12000000U) /* Oscillator frequency */
#define SYSTEM_CLOCK (5 * XTAL)
/*---------------------------------------------------------------------------
Exception / Interrupt Vector table
*---------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*---------------------------------------------------------------------------
System Core Clock Variable
*---------------------------------------------------------------------------*/
/* ToDo: Initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/
/*---------------------------------------------------------------------------
System Core Clock function
*---------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
/* ToDo: Add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = SYSTEM_CLOCK;
}
/*---------------------------------------------------------------------------
System initialization function
*---------------------------------------------------------------------------*/
void SystemInit (void)
{
/* ToDo: Add code to initialize the system.
Do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
/* ToDo: Initialize VTOR if available */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif
/* ToDo: Enable co-processor if it is used */
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
/* ToDo: Initialize SAU if TZ is used */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

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/**************************************************************************//**
* @file <Device>.h
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
* @version V1.01
* @date 23. June 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */
#define <Device>_H
#ifdef __cplusplus
extern "C" {
#endif
/* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment */
/** @addtogroup <Vendor>
* @{
*/
/* ToDo: replace '<Device>' with device name; add your doxyGen comment */
/** @addtogroup <Device>
* @{
*/
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum IRQn
{
/* ======================================= ARM Cortex-A Specific Interrupt Numbers ========================================= */
/* Software Generated Interrupts */
SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */
SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */
SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */
SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */
SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */
SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */
SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */
SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */
SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */
SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */
SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */
SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */
SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */
SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */
SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */
SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */
/* Private Peripheral Interrupts */
VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */
HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */
VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */
Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */
SecurePhyTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */
NonSecurePhyTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */
Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */
/* Shared Peripheral Interrupts */
/* ToDo: add here your device specific external interrupt numbers */
<DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the Arm Cortex-A Processor and Core Peripherals ============================ */
/* ToDo: set the defines according your Device */
/* ToDo: define the correct core revision
5U if your device is a CORTEX-A5 device
7U if your device is a CORTEX-A7 device
9U if your device is a CORTEX-A9 device */
#define __CORTEX_A #U /*!< Cortex-A# Core */
#define __CA_REV 0x0000U /*!< Core revision r0p0 */
/* ToDo: define the correct core features for the <Device> */
#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */
#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */
#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */
#define __L2C_PRESENT 1U /*!< Set to 1 if L2C is present */
/** @} */ /* End of group Configuration_of_CMSIS */
/* ToDo: include the correct core_ca#.h file
core_ca5.h if your device is a CORTEX-A5 device
core_ca7.h if your device is a CORTEX-A7 device
core_ca9.h if your device is a CORTEX-A9 device */
#include <core_ca#.h> /*!< Arm Cortex-A# processor and core peripherals */
/* ToDo: include your system_<Device>.h file
replace '<Device>' with your device name */
#include "system_<Device>.h" /*!< <Device> System */
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* ToDo: add here your device specific peripheral access structure typedefs
following is an example for a timer */
/* =========================================================================================================================== */
/* ================ TMR ================ */
/* =========================================================================================================================== */
/**
* @brief Timer (TMR)
*/
typedef struct
{ /*!< (@ 0x40000000) TIM Structure */
__IOM uint32_t TimerLoad; /*!< (@ 0x00000004) Timer Load */
__IM uint32_t TimerValue; /*!< (@ 0x00000008) Timer Counter Current Value */
__IOM uint32_t TimerControl; /*!< (@ 0x0000000C) Timer Control */
__OM uint32_t TimerIntClr; /*!< (@ 0x00000010) Timer Interrupt Clear */
__IM uint32_t TimerRIS; /*!< (@ 0x00000014) Timer Raw Interrupt Status */
__IM uint32_t TimerMIS; /*!< (@ 0x00000018) Timer Masked Interrupt Status */
__IM uint32_t RESERVED[1];
__IOM uint32_t TimerBGLoad; /*!< (@ 0x00000020) Background Load Register */
} <DeviceAbbreviation>_TMR_TypeDef;
/*@}*/ /* end of group <Device>_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/* ToDo: add here your device peripherals base addresses
following is an example for timer */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
/* Peripheral and SRAM base address */
#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
/* Peripheral memory map */
#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */
#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */
#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/* ToDo: add here your device peripherals pointer definitions
following is an example for timer */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
/** @} */ /* End of group <Device> */
/** @} */ /* End of group <Vendor> */
#ifdef __cplusplus
}
#endif
#endif /* <Device>_H */

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/**************************************************************************//**
* @file mem_<Device>.h
* @brief CMSIS Cortex-A Memory base and size definitions (used in scatter file)
* @version V1.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MEM_<Device>_H /* ToDo: replace '<Device>' with your device name */
#define MEM_<Device>_H
/*----------------------------------------------------------------------------
User Stack & Heap size definition
*----------------------------------------------------------------------------*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- ROM Configuration ------------------------------------
//
// <h> ROM Configuration
// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x80000000
#define __ROM_SIZE 0x00200000
/*--------------------- RAM Configuration -----------------------------------
// <h> RAM Configuration
// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <h> Stack / Heap Configuration
// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <h> Exceptional Modes
// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// </h>
// </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x80200000
#define __RAM_SIZE 0x00200000
#define __RW_DATA_SIZE 0x00100000
#define __ZI_DATA_SIZE 0x000F0000
#define __STACK_SIZE 0x00001000
#define __HEAP_SIZE 0x00008000
#define __UND_STACK_SIZE 0x00000100
#define __ABT_STACK_SIZE 0x00000100
#define __SVC_STACK_SIZE 0x00000100
#define __IRQ_STACK_SIZE 0x00000100
#define __FIQ_STACK_SIZE 0x00000100
/*----------------------------------------------------------------------------*/
/*--------------------- TTB Configuration ------------------------------------
//
// <h> TTB Configuration
// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*----------------------------------------------------------------------------*/
#define __TTB_BASE 0x80500000
#define __TTB_SIZE 0x00004000
#endif /* MEM_<Device>_H */

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/**************************************************************************//**
* @file system_<Device>.h
* @brief CMSIS Cortex-A Device Peripheral Access Layer
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_<Device>_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_<Device>_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */

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external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/Device.sct vendored Normal file
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#! armcc -E
;**************************************************
; Copyright (c) 2017 ARM Ltd. All rights reserved.
;**************************************************
; Scatter-file for Cortex-A
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
#include "mem_<Device>.h"
SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
{
VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
{
* (RESET, +FIRST) ; Vector table and other startup code
* (InRoot$$Sections) ; All (library) code that must be in a root region
* (+RO-CODE) ; Application RO code (.text)
* (+RO-DATA) ; Application RO data (.constdata)
}
RW_DATA __RAM_BASE __RW_DATA_SIZE
{ * (+RW) } ; Application RW data (.data)
ZI_DATA (__RAM_BASE+
__RW_DATA_SIZE) __ZI_DATA_SIZE
{ * (+ZI) } ; Application ZI data (.bss)
ARM_LIB_HEAP (__RAM_BASE
+__RW_DATA_SIZE
+__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
{ }
ARM_LIB_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE
-__SVC_STACK_SIZE
-__ABT_STACK_SIZE
-__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
{ }
UND_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE
-__SVC_STACK_SIZE
-__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
{ }
ABT_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE
-__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
{ }
SVC_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
{ }
IRQ_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
{ }
FIQ_STACK (__RAM_BASE
+__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
{ }
TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
{ }
}

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/******************************************************************************
* @file startup_<Device>.c
* @brief CMSIS Cortex-A Device Startup
* @version V1.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
/*----------------------------------------------------------------------------
Definitions
*----------------------------------------------------------------------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Vectors (void) __attribute__ ((section("RESET")));
void Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector Table
*----------------------------------------------------------------------------*/
__ASM void Vectors(void) {
IMPORT Undef_Handler
IMPORT SVC_Handler
IMPORT PAbt_Handler
IMPORT DAbt_Handler
IMPORT IRQ_Handler
IMPORT FIQ_Handler
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
}
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__ASM void Reset_Handler(void) {
// Mask interrupts
CPSID if
// Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
ANDS R0, R0, #3
goToSleep
WFINE
BNE goToSleep
// Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
ISB
// Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exceptional mode
IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
IMPORT |Image$$SVC_STACK$$ZI$$Limit|
IMPORT |Image$$ABT_STACK$$ZI$$Limit|
IMPORT |Image$$UND_STACK$$ZI$$Limit|
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
CPS #0x11
LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
CPS #0x12
LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
CPS #0x13
LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
CPS #0x17
LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
CPS #0x1B
LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
CPS #0x1F
LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
// Call SystemInit
IMPORT SystemInit
BL SystemInit
// Unmask interrupts
CPSIE if
// Call __main
IMPORT __main
BL __main
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
while(1);
}

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/**************************************************************************//**
* @file system_Device.c
* @brief MMU Configuration
* Device <DeviceAbbreviation>
* @version V1.1.0
* @date 23. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Memory map description
ToDo: add in this file your device memory map description
following is an example of a Cortex-A9 Arm FVP device
Memory Type
0xFFFFFFFF |--------------------------| ------------
| FLAG SYNC | Device Memory
0xFFFFF000 |--------------------------| ------------
| Fault | Fault
0xFFF00000 |--------------------------| ------------
| | Normal
| |
| Daughterboard |
| memory |
| |
0x80505000 |--------------------------| ------------
|TTB (L2 Sync Flags ) 4k | Normal
0x80504C00 |--------------------------| ------------
|TTB (L2 Peripherals-B) 16k| Normal
0x80504800 |--------------------------| ------------
|TTB (L2 Peripherals-A) 16k| Normal
0x80504400 |--------------------------| ------------
|TTB (L2 Priv Periphs) 4k | Normal
0x80504000 |--------------------------| ------------
| TTB (L1 Descriptors) | Normal
0x80500000 |--------------------------| ------------
| Heap | Normal
|--------------------------| ------------
| Stack | Normal
0x80400000 |--------------------------| ------------
| ZI Data | Normal
0x80300000 |--------------------------| ------------
| RW Data | Normal
0x80200000 |--------------------------| ------------
| RO Data | Normal
|--------------------------| ------------
| RO Code | USH Normal
0x80000000 |--------------------------| ------------
| Daughterboard | Fault
| HSB AXI buses |
0x40000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x2C002000 |--------------------------| ------------
| Private Address | Device Memory
0x2C000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x20000000 |--------------------------| ------------
| Peripherals | Device Memory RW/RO
| | & Fault
0x00000000 |--------------------------|
*/
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
// Note: You should use the Shareable attribute carefully.
// For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
// Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
// Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
// Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
// When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
// When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
// Following MMU configuration is expected
// SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
// SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
// Domain 0 is always the Client domain
// Descriptors should place all memory in domain 0
#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
// L2 table pointers
//-----------------------------------------------------
#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1
#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2
//--------------------- PERIPHERALS -------------------
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1C000000)
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1C000000)
//--------------------- SYNC FLAGS --------------------
#define FLAG_SYNC 0xFFFFF000
#define F_SYNC_BASE 0xFFF00000 //1M aligned
//Import symbols from linker
extern uint32_t Image$$VECTORS$$Base;
extern uint32_t Image$$RW_DATA$$Base;
extern uint32_t Image$$ZI_DATA$$Base;
extern uint32_t Image$$TTB$$ZI$$Base;
static uint32_t Sect_Normal; // outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; // outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; // as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; // as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; // device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; // as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; // generic
static uint32_t Page_L1_64k = 0x0; // generic
static uint32_t Page_4k_Device_RW; // shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; // shared device, not executable, rw, domain 0
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
// Create 4GB of faulting entries
MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
// Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
// Create descriptors for peripherals
section_Device_ro(Sect_Device_RO, region);
section_Device_rw(Sect_Device_RW, region);
// Create descriptors for 64k pages
page64k_Device_rw(Page_L1_64k, Page_64k_Device_RW, region);
// Create descriptors for 4k pages
page4k_Device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
// Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , 1U, Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , 1U, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base , 1U, Sect_Normal_RW);
// All DRAM executable, RW, cacheable - applications may choose to divide memory into RO executable
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base , 2043U, Sect_Normal);
//--------------------- PERIPHERALS -------------------
MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE0 , 64U, Sect_Device_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE1 , 64U, Sect_Device_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SRAM_BASE , 64U, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_VRAM_BASE , 32U, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_ETHERNET_BASE , 16U, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_USB_BASE , 16U, Sect_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DAP_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SYSTEM_REG_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SERIAL_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_AACI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_MMCI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_KMI0_BASE , 2U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART_BASE , 4U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_WDT_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_TIMER_BASE , 2U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DVI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_RTC_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART4_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_CLCD_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 256U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define private address space entry
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 2U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Define L2CC entry
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_L2C_BASE , 1U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define synchronization space entry.
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x1 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x01 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x0 (Inner WB WA) */
__set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}

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/******************************************************************************
* @file system_<Device>.c
* @brief CMSIS Cortex-A Device Peripheral Access Layer
* @version V1.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
#include "irq_ctrl.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define XTAL (12000000U) /* Oscillator frequency */
#define SYSTEM_CLOCK (5 * XTAL)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System Initialization
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
/* ToDo: add code to initialize the system
Do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
SystemCoreClock = SYSTEM_CLOCK;
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}