mirror of
https://github.com/OneOfEleven/uv-k5-firmware-custom.git
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Initial commit
This commit is contained in:
OneOfEleven
49
hardware/dp32g030/aes.def
Normal file
49
hardware/dp32g030/aes.def
Normal file
@ -0,0 +1,49 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[AES]
|
||||
@ = 0x400BD000, 0x800
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CR = 0x0000
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> CCFC, 7, 1
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= SET, 1
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|
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> CHMOD, 5, 2
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= ECB, 0
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= CBC, 1
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= CTR, 2
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|
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> EN, 0, 1
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= DISABLE, 0
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||||
= ENABLE, 1
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||||
|
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SR = 0x0004
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> CCF, 0, 1
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= NOT_COMPLETE, 0
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= COMPLETE, 1
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DINR = 0x0008
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DOUTR = 0x000C
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KEYR0 = 0x0010
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KEYR1 = 0x0014
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KEYR2 = 0x0018
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KEYR3 = 0x001C
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IVR0 = 0x0020
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IVR1 = 0x0024
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IVR2 = 0x0028
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IVR3 = 0x002C
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58
hardware/dp32g030/crc.def
Normal file
58
hardware/dp32g030/crc.def
Normal file
@ -0,0 +1,58 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[CRC]
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@ = 0x40003000, 0x800
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CR = 0x0000
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> CRC_EN, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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> INPUT_REV, 1, 1
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= NORMAL, 0
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= REVERSED, 1
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> INPUT_INV, 2, 2
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= NORMAL, 0
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= BIT_INVERTED, 1
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= BYTE_INVERTED, 2
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= BIT_BYTE_INVERTED, 3
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> OUTPUT_REV, 4, 1
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= NORMAL, 0
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= REVERSED, 1
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> OUTPUT_INV, 5, 2
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= NORMAL, 0
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= BIT_INVERTED, 1
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= BYTE_INVERTED, 2
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= BIT_BYTE_INVERTED, 3
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> DATA_WIDTH, 7, 2
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= 32, 0
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= 16, 1
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= 8, 2
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> CRC_SEL, 9, 2
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= CRC_16_CCITT, 0
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= CRC_8_ATM, 1
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= CRC_16, 2
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= CRC_32_IEEE802_3, 3
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IV = 0x0004
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DATAIN = 0x0008
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DATAOUT = 0x000C
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169
hardware/dp32g030/dma.def
Normal file
169
hardware/dp32g030/dma.def
Normal file
@ -0,0 +1,169 @@
|
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# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[DMA]
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@ = 0x40001000, 0x100
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CTR = 0x0000
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> DMAEN, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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INTEN = 0x0004
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> CH0_TC_INTEN, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH1_TC_INTEN, 1, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH2_TC_INTEN, 2, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH3_TC_INTEN, 3, 1
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= DISABLE, 0
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= ENABLE, 1
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|
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> CH0_THC_INTEN, 8, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH1_THC_INTEN, 9, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH2_THC_INTEN, 10, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH3_THC_INTEN, 11, 1
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= DISABLE, 0
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= ENABLE, 1
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|
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INTST = 0x0008
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> CH0_TC_INTST, 0, 1
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= NOT_SET, 0
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= SET, 1
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> CH1_TC_INTST, 1, 1
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= NOT_SET, 0
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= SET, 1
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|
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> CH2_TC_INTST, 2, 1
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= NOT_SET, 0
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= SET, 1
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> CH3_TC_INTST, 3, 1
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= NOT_SET, 0
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= SET, 1
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> CH0_THC_INTST, 8, 1
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= NOT_SET, 0
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= SET, 1
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> CH1_THC_INTST, 9, 1
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= NOT_SET, 0
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= SET, 1
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> CH2_THC_INTST, 10, 1
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= NOT_SET, 0
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= SET, 1
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> CH3_THC_INTST, 11, 1
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= NOT_SET, 0
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||||
= SET, 1
|
||||
|
||||
[DMA_CH]
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$ = DMA_Channel_t
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|
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CTR = 0x0000
|
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> CH_EN, 0, 1
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= DISABLE, 0
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||||
= ENABLE, 1
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||||
|
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> LENGTH, 1, 12
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||||
|
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> LOOP, 13, 1
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||||
= DISABLE, 0
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||||
= ENABLE, 1
|
||||
|
||||
> PRI, 14, 2
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= LOW, 0
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= MEDIUM, 1
|
||||
= HIGH, 2
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= HIGHEST, 3
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|
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> SWREQ, 16, 1
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= SET, 1
|
||||
|
||||
MOD = 0x0004
|
||||
> MS_ADDMOD, 0, 1
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= NONE, 0
|
||||
= INCREMENT, 1
|
||||
|
||||
> MS_SIZE, 1, 2
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||||
= 8BIT, 0
|
||||
= 16BIT, 1
|
||||
= 32BIT, 2
|
||||
= KEEP, 3
|
||||
|
||||
> MS_SEL, 3, 3
|
||||
= SRAM, 0
|
||||
= HSREQ_MS0, 1
|
||||
= HSREQ_MS1, 2
|
||||
= HSREQ_MS2, 3
|
||||
= HSREQ_MS3, 4
|
||||
= HSREQ_MS4, 5
|
||||
= HSREQ_MS5, 6
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= HSREQ_MS6, 7
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|
||||
> MD_ADDMOD, 8, 1
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= NONE, 0
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= INCREMENT, 1
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||||
|
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> MD_SIZE, 9, 2
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= 8BIT, 0
|
||||
= 16BIT, 1
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= 32BIT, 2
|
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= KEEP, 3
|
||||
|
||||
> MD_SEL, 11, 3
|
||||
= SRAM, 0
|
||||
= HSREQ_MS0, 1
|
||||
= HSREQ_MS1, 2
|
||||
= HSREQ_MS2, 3
|
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= HSREQ_MS3, 4
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= HSREQ_MS4, 5
|
||||
= HSREQ_MS5, 6
|
||||
= HSREQ_MS6, 7
|
||||
|
||||
MSADDR = 0x0008
|
||||
MDADDR = 0x000C
|
||||
ST = 0x0010
|
||||
|
||||
[DMA_CH0]
|
||||
@ = 0x40001100, 0x20, $DMA_CH
|
||||
|
||||
[DMA_CH1]
|
||||
@ = 0x40001120, 0x20, $DMA_CH
|
||||
|
||||
[DMA_CH2]
|
||||
@ = 0x40001140, 0x20, $DMA_CH
|
||||
|
||||
[DMA_CH3]
|
||||
@ = 0x40001160, 0x20, $DMA_CH
|
||||
|
||||
85
hardware/dp32g030/flash.def
Normal file
85
hardware/dp32g030/flash.def
Normal file
@ -0,0 +1,85 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[FLASH]
|
||||
@ = 0x4006F000, 0x800
|
||||
|
||||
CFG = 0x0000
|
||||
> READ_MD, 0, 1
|
||||
= 1_CYCLE, 0
|
||||
= 2_CYCLE, 1
|
||||
|
||||
> NVR_SEL, 1, 1
|
||||
= MAIN, 0
|
||||
= NVR, 1
|
||||
|
||||
> MODE, 2, 3
|
||||
= READ_AHB, 0
|
||||
= PROGRAM, 1
|
||||
= ERASE, 2
|
||||
= READ_APB, 5
|
||||
|
||||
> DEEP_PD, 31, 1
|
||||
= NORMAL, 0
|
||||
= LOW_POWER, 1
|
||||
|
||||
ADDR = 0x0004
|
||||
WDATA = 0x0008
|
||||
RDATA = 0x000C
|
||||
|
||||
START = 0x0010
|
||||
> START, 0, 1
|
||||
= START, 1
|
||||
|
||||
ST = 0x0014
|
||||
> INIT_BUSY, 0, 1
|
||||
= COMPLETE, 0
|
||||
= BUSY, 1
|
||||
|
||||
> BUSY, 1, 1
|
||||
= READY, 0
|
||||
= BUSY, 1
|
||||
|
||||
> PROG_BUF_EMPTY, 2, 1
|
||||
= NOT_EMPTY, 0
|
||||
= EMPTY, 1
|
||||
|
||||
LOCK = 0x0018
|
||||
> LOCK, 0, 8
|
||||
= LOCK, 0x55
|
||||
|
||||
UNLOCK = 0x001C
|
||||
> UNLOCK, 0, 8
|
||||
= UNLOCK, 0xAA
|
||||
|
||||
MASK = 0x0020
|
||||
> SEL, 0, 2
|
||||
= NONE, 0
|
||||
= 2KB, 1
|
||||
= 4KB, 2
|
||||
= 8KB, 3
|
||||
|
||||
> LOCK, 2, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
ERASETIME = 0x0024
|
||||
> TERASE, 0, 19
|
||||
> TRCV, 19, 12
|
||||
|
||||
PROGTIME = 0x0028
|
||||
> TPROG, 0, 11
|
||||
> TPGS, 11, 11
|
||||
|
||||
93
hardware/dp32g030/gpio.def
Normal file
93
hardware/dp32g030/gpio.def
Normal file
@ -0,0 +1,93 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[GPIO]
|
||||
$ = GPIO_Bank_t
|
||||
|
||||
DATA = 0x0000
|
||||
DIR = 0x0004
|
||||
> 0, 0, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 1, 1, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 2, 2, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 3, 3, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 4, 4, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 5, 5, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 6, 6, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 7, 7, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 8, 8, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 9, 9, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 10, 10, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 11, 11, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 12, 12, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 13, 13, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 14, 14, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 15, 15, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
[GPIOA]
|
||||
@ = 0x40060000, 0x800, $GPIO
|
||||
|
||||
[GPIOB]
|
||||
@ = 0x40060800, 0x800, $GPIO
|
||||
|
||||
[GPIOC]
|
||||
@ = 0x40061000, 0x800, $GPIO
|
||||
|
||||
37
hardware/dp32g030/pmu.def
Normal file
37
hardware/dp32g030/pmu.def
Normal file
@ -0,0 +1,37 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[PMU]
|
||||
@ = 0x40000800, 0x800
|
||||
|
||||
SRC_CFG = 0x0010
|
||||
> RCHF_SEL, 1, 1
|
||||
= 48MHZ, 0
|
||||
= 24MHZ, 1
|
||||
|
||||
> RCHF_EN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
TRIM_POW0 = 0x0020
|
||||
TRIM_POW1 = 0x0024
|
||||
TRIM_POW2 = 0x0028
|
||||
TRIM_POW3 = 0x002C
|
||||
|
||||
TRIM_RCHF = 0x0030
|
||||
TRIM_RCLF = 0x0034
|
||||
TRIM_OPA = 0x0038
|
||||
TRIM_PLL = 0x003C
|
||||
|
||||
1090
hardware/dp32g030/portcon.def
Normal file
1090
hardware/dp32g030/portcon.def
Normal file
File diff suppressed because it is too large
Load Diff
132
hardware/dp32g030/saradc.def
Normal file
132
hardware/dp32g030/saradc.def
Normal file
@ -0,0 +1,132 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[SARADC]
|
||||
@ = 0x400BA000, 0x800
|
||||
|
||||
CFG = 0x0000
|
||||
> CH_SEL, 0, 15
|
||||
|
||||
> AVG, 16, 2
|
||||
= 1_SAMPLE, 0
|
||||
= 2_SAMPLE, 1
|
||||
= 4_SAMPLE, 2
|
||||
= 8_SAMPLE, 3
|
||||
|
||||
> CONT, 18, 1
|
||||
= SINGLE, 0
|
||||
= CONTINUOUS, 1
|
||||
|
||||
> SMPL_SETUP, 19, 3
|
||||
= 1_CYCLE, 0
|
||||
= 2_CYCLE, 1
|
||||
= 4_CYCLE, 2
|
||||
= 8_CYCLE, 3
|
||||
= 16_CYCLE, 4
|
||||
= 32_CYCLE, 5
|
||||
= 64_CYCLE, 6
|
||||
= 128_CYCLE, 7
|
||||
|
||||
> MEM_MODE, 22, 1
|
||||
= FIFO, 0
|
||||
= CHANNEL, 1
|
||||
|
||||
> SMPL_CLK, 23, 1
|
||||
= EXTERNAL, 0
|
||||
= INTERNAL, 1
|
||||
|
||||
> SMPL_WIN, 24, 3
|
||||
= 1_CYCLE, 0
|
||||
= 3_CYCLE, 1
|
||||
= 5_CYCLE, 2
|
||||
= 7_CYCLE, 3
|
||||
= 9_CYCLE, 4
|
||||
= 11_CYCLE, 5
|
||||
= 13_CYCLE, 6
|
||||
= 15_CYCLE, 7
|
||||
|
||||
> ADC_EN, 27, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> ADC_TRIG, 28, 1
|
||||
= CPU, 0
|
||||
= EXTERNAL, 1
|
||||
|
||||
> DMA_EN, 29, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
START = 0x0004
|
||||
> START, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SOFT_RESET, 2, 1
|
||||
= ASSERT, 0
|
||||
= DEASSERT, 1
|
||||
|
||||
IE = 0x0008
|
||||
> CHx_EOC, 0, 16
|
||||
= NONE, 0x0000
|
||||
= ALL, 0xFFFF
|
||||
|
||||
> FIFO_FULL, 16, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> FIFO_HFULL, 17, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
IF = 0x000C
|
||||
> CHx_EOC, 0, 16
|
||||
|
||||
> FIFO_FULL, 16, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> FIFO_HFULL, 17, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
CH0 = 0x0010
|
||||
|
||||
EXTTRIG_SEL = 0x00B0
|
||||
|
||||
CALIB_OFFSET = 0x00F0
|
||||
> OFFSET, 0, 8
|
||||
> VALID, 16, 1
|
||||
= NO, 0
|
||||
= YES, 1
|
||||
|
||||
CALIB_KD = 0x00F4
|
||||
> KD, 0, 8
|
||||
> VALID, 16, 1
|
||||
= NO, 0
|
||||
= YES, 1
|
||||
|
||||
[ADC_CHx]
|
||||
$ = ADC_Channel_t
|
||||
|
||||
STAT = 0x0000
|
||||
> EOC, 0, 1
|
||||
= NOT_COMPLETE, 0
|
||||
= COMPLETE, 1
|
||||
|
||||
DATA = 0x0004
|
||||
> DATA, 0, 12
|
||||
> NUM, 12, 4
|
||||
|
||||
124
hardware/dp32g030/spi.def
Normal file
124
hardware/dp32g030/spi.def
Normal file
@ -0,0 +1,124 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[SPI]
|
||||
$ = SPI_Port_t
|
||||
|
||||
CR = 0x0000
|
||||
> TF_CLR, 16, 1
|
||||
> RF_CLR, 15, 1
|
||||
> TXDMAEN, 14, 1
|
||||
> RXDMAEN, 13, 1
|
||||
|
||||
> MSR_SSN, 12, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CPHA_DATA_HOLD_S, 8, 4
|
||||
> LSB, 7, 1
|
||||
> MSTR, 6, 1
|
||||
> CPOL, 5, 1
|
||||
> CPHA, 4, 1
|
||||
|
||||
> SPE, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SPR, 0, 3
|
||||
= FPCLK_DIV_4, 0
|
||||
= FPCLK_DIV_8, 1
|
||||
= FPCLK_DIV_16, 2
|
||||
= FPCLK_DIV_32, 3
|
||||
= FPCLK_DIV_64, 4
|
||||
= FPCLK_DIV_128, 5
|
||||
= FPCLK_DIV_256, 6
|
||||
= FPCLK_DIV_512, 7
|
||||
|
||||
WDR = 0x0004
|
||||
RDR = 0x0008
|
||||
|
||||
IE = 0x0010
|
||||
> RXFIFO_OVF, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO_FULL, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO_HFULL, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXFIFO_EMPTY, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXFIFO_HFULL, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
IF = 0x0014
|
||||
FIFOST = 0x0018
|
||||
> RFE, 0, 1
|
||||
= NOT_EMPTY, 0
|
||||
= EMPTY, 1
|
||||
|
||||
> RFF, 1, 1
|
||||
= NOT_FULL, 0
|
||||
= FULL, 1
|
||||
|
||||
> RFHF, 2, 1
|
||||
= NOT_HALF_FULL, 0
|
||||
= HALF_FULL, 1
|
||||
|
||||
> TFE, 3, 1
|
||||
= NOT_EMPTY, 0
|
||||
= EMPTY, 1
|
||||
|
||||
> TFF, 4, 1
|
||||
= NOT_FULL, 0
|
||||
= FULL, 1
|
||||
|
||||
> TFHF, 5, 1
|
||||
= NOT_HALF_FULL, 0
|
||||
= HALF_FULL, 1
|
||||
|
||||
> RF_LEVEL, 6, 3
|
||||
= 0_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
> TF_LEVEL, 9, 3
|
||||
= 0_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
[SPI0]
|
||||
@ = 0x400B8000, 0x800, $SPI
|
||||
|
||||
[SPI1]
|
||||
@ = 0x400B8800, 0x800, $SPI
|
||||
|
||||
178
hardware/dp32g030/syscon.def
Normal file
178
hardware/dp32g030/syscon.def
Normal file
@ -0,0 +1,178 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[SYSCON]
|
||||
@ = 0x40000000, 0x800
|
||||
|
||||
CLK_SEL = 0x0000
|
||||
> SYS, 0, 1
|
||||
= RCHF, 0
|
||||
= DIV_CLK, 1
|
||||
|
||||
> DIV, 1, 3
|
||||
= 1, 0
|
||||
= 2, 1
|
||||
= 4, 2
|
||||
= 8, 3
|
||||
= 16, 4
|
||||
= 32, 5
|
||||
|
||||
> SRC, 4, 3
|
||||
= RCHF, 0
|
||||
= RCLF, 1
|
||||
= XTAH, 2
|
||||
= XTAL, 3
|
||||
= PLL, 4
|
||||
|
||||
> W_PLL, 7, 1
|
||||
= RCHF, 0
|
||||
= XTAH, 1
|
||||
|
||||
# The documentation doesn't match the firmware!
|
||||
> R_SARADC_SMPL, 9, 2
|
||||
= DIV1, 0
|
||||
= DIV2, 1
|
||||
= DIV4, 2
|
||||
= DIV8, 3
|
||||
|
||||
> W_SARADC_SMPL, 10, 2
|
||||
= DIV1, 0
|
||||
= DIV2, 1
|
||||
= DIV4, 2
|
||||
= DIV8, 3
|
||||
|
||||
> R_PLL, 11, 1
|
||||
= RCHF, 0
|
||||
= XTAH, 1
|
||||
|
||||
DIV_CLK_GATE = 0x0004
|
||||
> DIV_CLK_GATE, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
DEV_CLK_GATE = 0x0008
|
||||
> GPIOA, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> GPIOB, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> GPIOC, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> IIC0, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> IIC1, 5, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> UART0, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> UART1, 7, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> UART2, 8, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SPI0, 10, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SPI1, 11, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_BASE0, 12, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_BASE1, 13, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_BASE2, 14, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_PLUS0, 15, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_PLUS1, 16, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_BASE0, 17, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_BASE1, 18, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_PLUS0, 20, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_PLUS1, 21, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RTC, 22, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> IWDT, 23, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> WWDT, 24, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SARADC, 25, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CRC, 27, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> AES, 28, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
RC_FREQ_DELTA = 0x0078
|
||||
> RCLF_DELTA, 0, 10
|
||||
> RCLF_SIG, 10, 1
|
||||
> RCHF_DELTA, 11, 20
|
||||
> RCHF_SIG, 31, 1
|
||||
|
||||
VREF_VOLT_DELTA = 0x007C
|
||||
|
||||
CHIP_ID0 = 0x0080
|
||||
CHIP_ID1 = 0x0084
|
||||
CHIP_ID2 = 0x0088
|
||||
CHIP_ID3 = 0x008C
|
||||
|
||||
230
hardware/dp32g030/uart.def
Normal file
230
hardware/dp32g030/uart.def
Normal file
@ -0,0 +1,230 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[UART]
|
||||
$ = UART_Port_t
|
||||
|
||||
CTRL = 0x0000
|
||||
> UARTEN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXEN, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXEN, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXDMAEN, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXDMAEN, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> NINEBIT, 5, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PAREN, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
BAUD = 0x0004
|
||||
TDR = 0x0008
|
||||
RDR = 0x000C
|
||||
|
||||
IE = 0x0010
|
||||
> TXDONE, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PARITYE, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> STOPE, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXTO, 5, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXFIFO, 7, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO_OVF, 8, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> ABRD_OVF, 9, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
IF = 0x0014
|
||||
> TXDONE, 2, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> PARITYE, 3, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> STOPE, 4, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXTO, 5, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO, 6, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO, 7, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_OVF, 8, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> ABRD_OVF, 9, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_EMPTY, 10, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_FULL, 11, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_HFULL, 12, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO_EMPTY, 13, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO_FULL, 14, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO_HFULL, 15, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXBUSY, 16, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RF_LEVEL, 17, 3
|
||||
= 0_8_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
> TF_LEVEL, 20, 3
|
||||
= 0_8_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
FIFO = 0x0018
|
||||
> RF_LEVEL, 0, 3
|
||||
= 1_BYTE, 0
|
||||
= 2_BYTE, 1
|
||||
= 3_BYTE, 2
|
||||
= 4_BYTE, 3
|
||||
= 5_BYTE, 4
|
||||
= 6_BYTE, 5
|
||||
= 7_BYTE, 6
|
||||
= 8_BYTE, 7
|
||||
|
||||
> TF_LEVEL, 3, 3
|
||||
= 0_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
> RF_CLR, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TF_CLR, 7, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
FC = 0x001C
|
||||
> CTSEN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RTSEN, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CTSPOL, 2, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
> RTSPOL, 3, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
> CTS_SIGNAL, 4, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
> RTS_SIGNAL, 5, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
RXTO = 0x0020
|
||||
|
||||
[UART0]
|
||||
@ = 0x4006B000, 0x800, $UART
|
||||
|
||||
[UART1]
|
||||
@ = 0x4006B800, 0x800, $UART
|
||||
|
||||
[UART2]
|
||||
@ = 0x4006C000, 0x800, $UART
|
||||
|
||||
Reference in New Issue
Block a user