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132
hardware/dp32g030/saradc.def
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132
hardware/dp32g030/saradc.def
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# Copyright 2023 Dual Tachyon
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# https://github.com/DualTachyon
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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[SARADC]
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@ = 0x400BA000, 0x800
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CFG = 0x0000
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> CH_SEL, 0, 15
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> AVG, 16, 2
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= 1_SAMPLE, 0
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= 2_SAMPLE, 1
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= 4_SAMPLE, 2
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= 8_SAMPLE, 3
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> CONT, 18, 1
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= SINGLE, 0
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= CONTINUOUS, 1
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> SMPL_SETUP, 19, 3
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= 1_CYCLE, 0
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= 2_CYCLE, 1
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= 4_CYCLE, 2
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= 8_CYCLE, 3
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= 16_CYCLE, 4
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= 32_CYCLE, 5
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= 64_CYCLE, 6
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= 128_CYCLE, 7
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> MEM_MODE, 22, 1
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= FIFO, 0
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= CHANNEL, 1
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> SMPL_CLK, 23, 1
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= EXTERNAL, 0
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= INTERNAL, 1
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> SMPL_WIN, 24, 3
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= 1_CYCLE, 0
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= 3_CYCLE, 1
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= 5_CYCLE, 2
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= 7_CYCLE, 3
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= 9_CYCLE, 4
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= 11_CYCLE, 5
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= 13_CYCLE, 6
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= 15_CYCLE, 7
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> ADC_EN, 27, 1
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= DISABLE, 0
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= ENABLE, 1
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> ADC_TRIG, 28, 1
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= CPU, 0
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= EXTERNAL, 1
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> DMA_EN, 29, 1
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= DISABLE, 0
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= ENABLE, 1
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START = 0x0004
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> START, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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> SOFT_RESET, 2, 1
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= ASSERT, 0
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= DEASSERT, 1
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IE = 0x0008
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> CHx_EOC, 0, 16
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= NONE, 0x0000
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= ALL, 0xFFFF
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> FIFO_FULL, 16, 1
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= DISABLE, 0
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= ENABLE, 1
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> FIFO_HFULL, 17, 1
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= DISABLE, 0
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= ENABLE, 1
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IF = 0x000C
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> CHx_EOC, 0, 16
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> FIFO_FULL, 16, 1
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= NOT_SET, 0
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= SET, 1
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> FIFO_HFULL, 17, 1
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= NOT_SET, 0
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= SET, 1
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CH0 = 0x0010
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EXTTRIG_SEL = 0x00B0
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CALIB_OFFSET = 0x00F0
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> OFFSET, 0, 8
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> VALID, 16, 1
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= NO, 0
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= YES, 1
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CALIB_KD = 0x00F4
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> KD, 0, 8
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> VALID, 16, 1
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= NO, 0
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= YES, 1
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[ADC_CHx]
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$ = ADC_Channel_t
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STAT = 0x0000
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> EOC, 0, 1
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= NOT_COMPLETE, 0
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= COMPLETE, 1
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DATA = 0x0004
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> DATA, 0, 12
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> NUM, 12, 4
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