From 630c6ac196af265dc0c13a9efd283ab85c36757e Mon Sep 17 00:00:00 2001 From: OneOfEleven Date: Fri, 10 Nov 2023 13:36:02 +0000 Subject: [PATCH] . --- Makefile | 2 ++ board.c | 4 ++-- driver/backlight.c | 2 +- driver/uart.c | 12 ++++++------ .../Firmware/Examples/MCU-LINK/fsl_usart.c | 10 +++++----- firmware.bin | Bin 61184 -> 61184 bytes firmware.packed.bin | Bin 61202 -> 61202 bytes sram-overlay.c | 3 +-- sram-overlay.h | 1 + 9 files changed, 18 insertions(+), 16 deletions(-) diff --git a/Makefile b/Makefile index b907f2a..64689a2 100644 --- a/Makefile +++ b/Makefile @@ -258,6 +258,8 @@ endif CFLAGS = +CFLAGS += -DCPU_CLOCK_HZ=48000000 + ifeq ($(ENABLE_CLANG),0) #CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c11 -MMD CFLAGS += -Os -Werror -mcpu=cortex-m0 -freorder-blocks-algorithm=stc -std=c11 -MMD diff --git a/board.c b/board.c index 5d82198..296e211 100644 --- a/board.c +++ b/board.c @@ -51,8 +51,8 @@ FLASH_ConfigureTrimValues(); SYSTEM_ConfigureClocks(); - overlay_FLASH_MainClock = 48000000; - overlay_FLASH_ClockMultiplier = 48; + overlay_FLASH_MainClock = CPU_CLOCK_HZ; + overlay_FLASH_ClockMultiplier = CPU_CLOCK_HZ / 1000000; FLASH_Init(FLASH_READ_MODE_2_CYCLE); } diff --git a/driver/backlight.c b/driver/backlight.c index ba367f3..5d55849 100644 --- a/driver/backlight.c +++ b/driver/backlight.c @@ -28,7 +28,7 @@ void BACKLIGHT_init(void) { // 48MHz / 94 / 1024 ~ 500Hz const uint32_t PWM_FREQUENCY_HZ = 1000; - PWM_PLUS0_CLKSRC |= ((48000000 / 1024 / PWM_FREQUENCY_HZ) << 16); + PWM_PLUS0_CLKSRC |= ((CPU_CLOCK_HZ / 1024 / PWM_FREQUENCY_HZ) << 16); PWM_PLUS0_PERIOD = 1023; PORTCON_PORTB_SEL0 &= ~(PORTCON_PORTB_SEL0_B6_MASK); diff --git a/driver/uart.c b/driver/uart.c index eaca866..4193493 100644 --- a/driver/uart.c +++ b/driver/uart.c @@ -31,17 +31,17 @@ void UART_Init(void) uint32_t Frequency; UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE; - Delta = SYSCON_RC_FREQ_DELTA; - Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT; - Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT; - Frequency = Positive ? Frequency + 48000000U : 48000000U - Frequency; + Delta = SYSCON_RC_FREQ_DELTA; + Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT; + Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT; + Frequency = Positive ? Frequency + CPU_CLOCK_HZ : CPU_CLOCK_HZ - Frequency; UART1->BAUD = Frequency / 39053U; UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE; UART1->RXTO = 4; - UART1->FC = 0; + UART1->FC = 0; UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE; - UART1->IE = 0; + UART1->IE = 0; DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE; diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c index 2fdbbae..40d56a3 100644 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c +++ b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c @@ -5,7 +5,7 @@ * * SPDX-License-Identifier: BSD-3-Clause */ - + /* * Modified by Arm */ @@ -334,7 +334,7 @@ void USART_GetDefaultConfig(usart_config_t *config) /*! * brief Sets the USART instance baud rate. * - * This function configures the USART module baud rate. + * This function configures the USART module baud rate. * * USART_SetBaudRate(USART1, 115200U, 20000000U); * endcode @@ -363,12 +363,12 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src flexcomm_idx = FLEXCOMM_GetInstance(base); flexcomm_clock = CLOCK_GetFlexCommInputClock(flexcomm_idx); - if (flexcomm_clock != 48000000U) + if (flexcomm_clock != CPU_CLOCK_HZ) { /* FlexComm input clock must be 48000000 */ return kStatus_USART_BaudrateNotSupport; } - + /* Calculate fixed point divider (12 LSBs are fractional part) */ div = (uint32_t)(((uint64_t)flexcomm_clock << FRACT_BITS) / (uint64_t)baudrate_Bps); @@ -376,7 +376,7 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src { return kStatus_USART_BaudrateNotSupport; } - + br_div_best = 0U; if ((div & ((1 << FRACT_BITS) - 1U)) == 0U) { diff --git a/firmware.bin b/firmware.bin index 6f5af8f5141934bea4f41a69837962d0204dc7b9..9901c1ddff3e040480cb841ae982b2f70296c227 100644 GIT binary patch delta 79 zcmZp;$J}s_c?0iN_S7^}BXfh)%_3Ku*<_&{9ReEI+z&%8$KF~ delta 79 zcmZp;$J}s_c?0iNc4K4HM9Vb8%_3Ku*<_&{9Rsrv&7r*4FyzdHKoC`x#|A_1;qUZw=T22>r(>)p{DAK BEQtUB delta 95 zcmV-l0HFVp-UE`}1F!}l2YaW40a?9Xvkf2+wFl5=Fo*;3TC*h8g9aVQf-i&cr)O)) z^qw@9R&Ot)$NLYYDizy&3sqL$v&7r*4Fy$iHKxzAx#|A_1;zOWv@El|>r(>)U9Imi BELZ>l diff --git a/sram-overlay.c b/sram-overlay.c index 844351e..f65e30b 100644 --- a/sram-overlay.c +++ b/sram-overlay.c @@ -23,7 +23,7 @@ static volatile uint32_t *pFlash = 0; uint32_t overlay_FLASH_MainClock; uint32_t overlay_FLASH_ClockMultiplier; -uint32_t overlay_0x20000478; // Nothing is using this??? +//uint32_t overlay_0x20000478; // Nothing is using this??? void overlay_FLASH_RebootToBootloader(void) { @@ -86,7 +86,6 @@ void overlay_FLASH_Unlock(void) uint32_t overlay_FLASH_ReadByAHB(uint32_t Offset) { - return pFlash[(Offset & ~3U) / 4]; } diff --git a/sram-overlay.h b/sram-overlay.h index 8b6c7cc..37b0158 100644 --- a/sram-overlay.h +++ b/sram-overlay.h @@ -19,6 +19,7 @@ #include #include + #include "driver/flash.h" extern uint32_t overlay_FLASH_MainClock __attribute__((section(".srambss")));