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Dual watch count down constants

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OneOfEleven
2023-09-13 17:34:56 +01:00
parent fde690a74a
commit d95ba32be5
10 changed files with 119 additions and 71 deletions
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68
driver/bk4819-regs.h
View File

@@ -286,50 +286,50 @@ enum {
// REG 51
#define BK4819_REG_51_SHIFT_ENABLE_CxCSS 15
#define BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT 14
#define BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY 13
#define BK4819_REG_51_SHIFT_CxCSS_MODE 12
#define BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH 11
#define BK4819_REG_51_SHIFT_1050HZ_DETECTION 10
#define BK4819_REG_51_SHIFT_AUTO_CDCSS_BW 9
#define BK4819_REG_51_SHIFT_AUTO_CTCSS_BW 8
#define BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1 0
#define BK4819_REG_51_SHIFT_ENABLE_CxCSS 15
#define BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT 14
#define BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY 13
#define BK4819_REG_51_SHIFT_CxCSS_MODE 12
#define BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH 11
#define BK4819_REG_51_SHIFT_1050HZ_DETECTION 10
#define BK4819_REG_51_SHIFT_AUTO_CDCSS_BW 9
#define BK4819_REG_51_SHIFT_AUTO_CTCSS_BW 8
#define BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1 0
#define BK4819_REG_51_MASK_ENABLE_CxCSS (0x01U << BK4819_REG_51_SHIFT_ENABLE_CxCSS)
#define BK4819_REG_51_MASK_GPIO6_PIN2_INPUT (0x01U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT)
#define BK4819_REG_51_MASK_TX_CDCSS_POLARITY (0x01U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY)
#define BK4819_REG_51_MASK_CxCSS_MODE (0x01U << BK4819_REG_51_SHIFT_CxCSS_MODE)
#define BK4819_REG_51_MASK_CDCSS_BIT_WIDTH (0x01U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH)
#define BK4819_REG_51_MASK_1050HZ_DETECTION (0x01U << BK4819_REG_51_SHIFT_1050HZ_DETECTION)
#define BK4819_REG_51_MASK_AUTO_CDCSS_BW (0x01U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW)
#define BK4819_REG_51_MASK_AUTO_CTCSS_BW (0x01U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW)
#define BK4819_REG_51_MASK_CxCSS_TX_GAIN1 (0x7FU << BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1)
#define BK4819_REG_51_MASK_ENABLE_CxCSS (0x01U << BK4819_REG_51_SHIFT_ENABLE_CxCSS)
#define BK4819_REG_51_MASK_GPIO6_PIN2_INPUT (0x01U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT)
#define BK4819_REG_51_MASK_TX_CDCSS_POLARITY (0x01U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY)
#define BK4819_REG_51_MASK_CxCSS_MODE (0x01U << BK4819_REG_51_SHIFT_CxCSS_MODE)
#define BK4819_REG_51_MASK_CDCSS_BIT_WIDTH (0x01U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH)
#define BK4819_REG_51_MASK_1050HZ_DETECTION (0x01U << BK4819_REG_51_SHIFT_1050HZ_DETECTION)
#define BK4819_REG_51_MASK_AUTO_CDCSS_BW (0x01U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW)
#define BK4819_REG_51_MASK_AUTO_CTCSS_BW (0x01U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW)
#define BK4819_REG_51_MASK_CxCSS_TX_GAIN1 (0x7FU << BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1)
enum {
BK4819_REG_51_ENABLE_CxCSS = (1U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_DISABLE_CxCSS = (0U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_ENABLE_CxCSS = (1U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_DISABLE_CxCSS = (0U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_GPIO6_PIN2_INPUT = (1U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_GPIO6_PIN2_NORMAL = (0U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_GPIO6_PIN2_INPUT = (1U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_GPIO6_PIN2_NORMAL = (0U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_TX_CDCSS_NEGATIVE = (1U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_TX_CDCSS_POSITIVE = (0U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_TX_CDCSS_NEGATIVE = (1U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_TX_CDCSS_POSITIVE = (0U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_MODE_CTCSS = (1U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_MODE_CDCSS = (0U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_MODE_CTCSS = (1U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_MODE_CDCSS = (0U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_CDCSS_24_BIT = (1U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_CDCSS_23_BIT = (0U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_CDCSS_24_BIT = (1U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_CDCSS_23_BIT = (0U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_1050HZ_DETECTION = (1U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_1050HZ_NO_DETECTION = (0U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_1050HZ_DETECTION = (1U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_1050HZ_NO_DETECTION = (0U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_AUTO_CDCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CDCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CDCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CDCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
};
// REG 70

22
driver/bk4819.c
View File

@@ -604,6 +604,16 @@ void BK4819_TxOn_Beep(void)
void BK4819_ExitSubAu(void)
{
// REG_51 <15> 0 1 = Enable TxCTCSS/CDCSS 0 = Disable
// REG_51 <14> 0 1 = GPIO0Input for CDCSS 0 = Normal Mode.(for BK4819v3)
// REG_51 <13> 0 1 = Transmit negative CDCSS code 0 = Transmit positive CDCSScode
// REG_51 <12> 0 CTCSS/CDCSS mode selection 1 = CTCSS 0 = CDCSS
// REG_51 <11> 0 CDCSS 24/23bit selection 1 = 24bit 0 = 23bit
// REG_51 <10> 0 1050HzDetectionMode 1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz
// REG_51 <9> 0 Auto CDCSS Bw Mode 1 = Disable 0 = Enable.
// REG_51 <8> 0 Auto CTCSS Bw Mode 0 = Enable 1 = Disable
// REG_51 <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning 0 = min 127 = max
BK4819_WriteRegister(BK4819_REG_51, 0x0000);
}
@@ -853,6 +863,17 @@ void BK4819_EnableFrequencyScan(void)
void BK4819_SetScanFrequency(uint32_t Frequency)
{
BK4819_SetFrequency(Frequency);
// REG_51 <15> 0 1 = Enable TxCTCSS/CDCSS 0 = Disable
// REG_51 <14> 0 1 = GPIO0 Input for CDCSS 0 = Normal Mode.(for BK4819v3)
// REG_51 <13> 0 1 = Transmit negative CDCSS code 0 = Transmit positive CDCSScode
// REG_51 <12> 0 CTCSS/CDCSS mode selection 1 = CTCSS 0 = CDCSS
// REG_51 <11> 0 CDCSS 24/23bit selection 1 = 24bit 0 = 23bit
// REG_51 <10> 0 1050HzDetectionMode 1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz
// REG_51 <9> 0 Auto CDCSS Bw Mode 1 = Disable 0 = Enable.
// REG_51 <8> 0 Auto CTCSS Bw Mode 0 = Enable 1 = Disable
// REG_51 <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning 0 = min 127 = max
BK4819_WriteRegister(BK4819_REG_51, 0
| BK4819_REG_51_DISABLE_CxCSS
| BK4819_REG_51_GPIO6_PIN2_NORMAL
@@ -862,6 +883,7 @@ void BK4819_SetScanFrequency(uint32_t Frequency)
| BK4819_REG_51_1050HZ_NO_DETECTION
| BK4819_REG_51_AUTO_CDCSS_BW_DISABLE
| BK4819_REG_51_AUTO_CTCSS_BW_DISABLE);
BK4819_RX_TurnOn();
}