diff --git a/app/aircopy.c b/app/aircopy.c index 76a7e07..cf5e5e2 100644 --- a/app/aircopy.c +++ b/app/aircopy.c @@ -411,6 +411,7 @@ void AIRCOPY_process_fsk_rx_10ms(void) for (i = 0; i < 4; i++) { const uint16_t word = BK4819_ReadRegister(0x5F); + if (g_fsk_write_index < ARRAY_SIZE(g_fsk_buffer)) g_fsk_buffer[g_fsk_write_index++] = word; } diff --git a/app/app.c b/app/app.c index 860e675..b1fa1ce 100644 --- a/app/app.c +++ b/app/app.c @@ -1040,12 +1040,15 @@ void APP_process_radio_interrupts(void) #ifdef ENABLE_MDC1200 { const uint16_t rx_sync_flags = BK4819_ReadRegister(0x0B); + const uint16_t fsk_reg59 = BK4819_ReadRegister(0x59) & ~((1u << 15) | (1u << 14) | (1u << 12) | (1u << 11)); + const bool rx_sync_neg = (rx_sync_flags & (1u << 7)) ? true : false; const bool rx_sync_pos = (rx_sync_flags & (1u << 6)) ? true : false; const bool rx_sync = (interrupt_bits & BK4819_REG_02_FSK_RX_SYNC) ? true : false; const bool rx_finished = (interrupt_bits & BK4819_REG_02_FSK_RX_FINISHED) ? true : false; const bool rx_fifo_almost_full = (interrupt_bits & BK4819_REG_02_FSK_FIFO_ALMOST_FULL) ? true : false; + BK4819_set_GPIO_pin(BK4819_GPIO6_PIN2_GREEN, true); // LED on if (rx_sync_neg) @@ -1069,20 +1072,6 @@ void APP_process_radio_interrupts(void) #endif } - if (rx_fifo_almost_full) - { - #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) - UART_printf("fsk rx almost full\r\n"); - #endif - } - - if (rx_finished) - { - #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) - UART_printf("fsk rx finished\r\n"); - #endif - } - if (rx_fifo_almost_full) { uint8_t buffer[sizeof(mdc1200_sync_suc_xor) + 14]; @@ -1090,11 +1079,15 @@ void APP_process_radio_interrupts(void) uint8_t op; uint8_t arg; uint16_t unit_id; - const uint16_t fsk_reg59 = BK4819_ReadRegister(0x59) & ~((1u << 15) | (1u << 14) | (1u << 12) | (1u << 11)); + const unsigned int sync_size = (fsk_reg59 & (1u << 3)) ? 4 : 2; // const unsigned int size = 1 + ((BK4819_ReadRegister(0x5D) >> 8) & 0xffff); const unsigned int size = sizeof(buffer) - sync_size; + #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) + UART_printf("fsk rx almost full\r\n"); + #endif + // 40 C4 B0 32 BA F9 33 18 35 08 83 F6 0C C9 // 0100000011000100101100000011001010111010111110010011001100011000001101010000100010000011111101100000110011001001 @@ -1109,13 +1102,13 @@ void APP_process_radio_interrupts(void) // precede the data with the missing sync pattern for (i = 0; i < sync_size; i++) - buffer[k++] = mdc1200_sync_suc_xor[i] ^ (rx_sync_neg ? 0xff : 0); + buffer[k++] = mdc1200_sync_suc_xor[i] ^ (rx_sync_neg ? 0x00 : 0xFF); for (i = 0; i < (size / 2); i++) { const uint16_t word = BK4819_ReadRegister(0x5F); - buffer[k++] = (word >> 8) & 0xff; buffer[k++] = (word >> 0) & 0xff; + buffer[k++] = (word >> 8) & 0xff; } } @@ -1153,6 +1146,16 @@ void APP_process_radio_interrupts(void) } } + + if (rx_finished) + { + #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) + UART_printf("fsk rx finished\r\n"); + #endif + + BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); + BK4819_WriteRegister(0x59, (1u << 12) | fsk_reg59); + } } #endif } diff --git a/driver/bk4819.c b/driver/bk4819.c index ec109b3..6210f31 100644 --- a/driver/bk4819.c +++ b/driver/bk4819.c @@ -53,8 +53,8 @@ void BK4819_Init(void) BK4819_WriteRegister(0x37, 0x1D0F); BK4819_WriteRegister(0x36, 0x0022); - BK4819_DisableAGC(); -// BK4819_EnableAGC(); +// BK4819_DisableAGC(); + BK4819_EnableAGC(); BK4819_WriteRegister(0x19, 0x1041); // 0001 0000 0100 0001 <15> MIC AGC 1 = disable 0 = enable @@ -342,28 +342,34 @@ void BK4819_EnableAGC(void) // <2:0> 0b110 DC Filter Band Width for Rx (IF In). // 000=Bypass DC filter; - // default fix index too strong, set to min (011->100) - //BK4819_WriteRegister(0x7E, (1u << 15) | (4u << 12) | (5u << 3) | (6u << 0)); - BK4819_WriteRegister(0x7E, (0u << 15) | // 0 AGC fix mode (3u << 12) | // 3 AGC fix index (5u << 3) | // 5 DC Filter band width for Tx (MIC In) (6u << 0)); // 6 DC Filter band width for Rx (I.F In) - BK4819_WriteRegister(0x13, (3u << 8) | (5u << 5) | (3u << 3) | (6u << 0)); // 000000 11 101 11 110 - BK4819_WriteRegister(0x12, 0x037C); - BK4819_WriteRegister(0x11, 0x027B); - BK4819_WriteRegister(0x10, 0x007A); - BK4819_WriteRegister(0x14, 0x0018); -/* - // undocumented ? - BK4819_WriteRegister(0x49, 0x2A38); - BK4819_WriteRegister(0x7B, 0x318C); - BK4819_WriteRegister(0x7C, 0x595E); - BK4819_WriteRegister(0x20, 0x8DEF); -*/ - // fagci had the answer to why we weren't as sensitive! + // TBR: fagci has this listed as two values, agc_rssi and lna_peak_rssi + // This is why AGC appeared to do nothing as-is for Rx + // + // REG_62 + // + // <15:8> 0xFF AGC RSSI + // + // <7:0> 0xFF LNA Peak RSSI + // + // TBR: Using S9+30 (173) and S9 (143) as suggested values + BK4819_WriteRegister(0x62, (173u << 8) | (143u << 0)); + + // AGC auto-adjusts the following LNA values, no need to set them ourselves + //BK4819_WriteRegister(0x13, (3u << 8) | (5u << 5) | (3u << 3) | (6u << 0)); // 000000 11 101 11 110 + //BK4819_WriteRegister(0x12, 0x037B); // 000000 11 011 11 011 + //BK4819_WriteRegister(0x11, 0x027B); // 000000 10 011 11 011 + //BK4819_WriteRegister(0x10, 0x007A); // 000000 00 011 11 010 + //BK4819_WriteRegister(0x14, 0x0019); // 000000 00 000 11 001 + + BK4819_WriteRegister(0x49, 0x2A38); + BK4819_WriteRegister(0x7B, 0x8420); + for (unsigned int i = 0; i < 8; i++) BK4819_WriteRegister(0x06, ((i & 7u) << 13) | (0x4A << 7) | (0x36 << 0)); } @@ -2168,11 +2174,14 @@ void BK4819_reset_fsk(void) BK4819_WriteRegister(0x5B, ((uint16_t)mdc1200_sync_suc_xor[2] << 8) | (mdc1200_sync_suc_xor[3] << 0)); // disable CRC - BK4819_WriteRegister(0x5C, 0x5625 | (0u << 6)); - - // packet size .. 14 bytes - size of a single mdc1200 packet - BK4819_WriteRegister(0x5D, (((sizeof(mdc1200_sync_suc_xor) - 4 + 14) - 1) << 8)); + BK4819_WriteRegister(0x5C, 0x5625); + { // packet size .. 14 bytes - size of a single mdc1200 packet + uint16_t size = sizeof(mdc1200_sync_suc_xor) + 14; + size -= (fsk_reg59 & (1u << 3)) ? 4 : 2; + BK4819_WriteRegister(0x5D, ((size - 1) << 8)); + } + // clear FIFO's then enable RX BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); BK4819_WriteRegister(0x59, (1u << 12) | fsk_reg59); diff --git a/firmware.bin b/firmware.bin index 9f9fdc5..45b3054 100644 Binary files a/firmware.bin and b/firmware.bin differ diff --git a/firmware.packed.bin b/firmware.packed.bin index 649e4b0..d331c24 100644 Binary files a/firmware.packed.bin and b/firmware.packed.bin differ diff --git a/mdc1200.c b/mdc1200.c index ececba1..0283908 100644 --- a/mdc1200.c +++ b/mdc1200.c @@ -25,9 +25,13 @@ const uint8_t mdc1200_sync[5] = {0x07, 0x09, 0x2a, 0x44, 0x6f}; // 0000 0111 0000 1001 0010 1010 0100 0100 0110 1111 // // after successive bit xorring: +// // 0000 0100 1000 1101 1011 1111 0110 0110 0101 1000 // 0x048DBF6658 // +// 1111 1011 0111 0010 0100 0000 1001 1001 1010 0111 .. bit inverted +// 0xFB724099A7 +// uint8_t mdc1200_sync_suc_xor[sizeof(mdc1200_sync)]; /* @@ -487,9 +491,13 @@ bool MDC1200_process_rx( uint8_t *arg, uint16_t *unit_id) { - const uint8_t *buffer8 = (const uint8_t *)buffer; + const uint8_t *buffer8 = (const uint8_t *)buffer; unsigned int index; + // FB 72 40 99 A7 + // FB 72 40 99 A7 BF 3B 4F CD 45 06 CC D1 CC D1 CC D1 CC 2B + // FB 72 40 99 A7 BA 24 FC F8 43 05 CA D1 CC FF 1B FF 1B 2B + memset(&rx, 0, sizeof(rx)); for (index = 0; index < size; index++) @@ -498,71 +506,36 @@ bool MDC1200_process_rx( int bit; const uint8_t rx_byte = buffer8[index]; - + for (bit = 7; bit >= 0; bit--) { rx.prev_bit = rx.bit; - + rx.bit = (rx_byte >> bit) & 1u; - - if (rx.stage == 0) - { // scanning for the pre-amble - rx.xor_bit = rx.bit & 1u; - } - else - { - rx.xor_bit = (rx.xor_bit ^ rx.bit) & 1u; - if (rx.inverted_sync) - rx.xor_bit ^= 1u; - } - + + rx.xor_bit = (rx.xor_bit ^ rx.bit) & 1u; + if (rx.stage > 0 && rx.inverted_sync) + rx.xor_bit ^= 1u; + rx.shift_reg = (rx.shift_reg << 1) | (rx.xor_bit & 1u); rx.bit_count++; - + // ********* - + if (rx.stage == 0) - { // looking for pre-amble - if (rx.bit_count < 20 || (rx.shift_reg & 0xfffff) != 1u) - continue; - - rx.xor_bit = 1; - rx.stage = 1; - rx.bit_count = 1; - - //s.printf("%5u %2u %u pre-amble found", index, rx_bit_count, rx_packet_stage); - //Memo1->Lines->Add(s); - } - - if (rx.stage < 2) - { - //s.printf("%5u %3u %u ", index, rx_bit_count, rx_packet_stage); - //for (uint64_t mask = 1ull << ((sizeof(rx_shift_reg) * 8) - 1); mask != 0; mask >>= 1) - // s += (rx_shift_reg & mask) ? '#' : '.'; - //s += " "; - //for (int i = sizeof(rx_shift_reg) - 1; i >= 0; i--) - //{ - // String s2; - // s2.printf(" %02X", (uint8_t)(rx_shift_reg >> (i * 8))); - // s += s2; - //} - //Memo1->Lines->Add(s); - } - - if (rx.stage == 1) - { // looking for the 40-bit sync pattern, it follows the 24-bit pre-amble - + { // looking for the 40-bit sync pattern + const unsigned int sync_bit_ok_threshold = 32; - + if (rx.bit_count >= sync_bit_ok_threshold) { // 40-bit sync pattern uint64_t sync_nor = 0x07092a446fu; // normal uint64_t sync_inv = 0xffffffffffu ^ sync_nor; // bit inverted - + sync_nor ^= rx.shift_reg; sync_inv ^= rx.shift_reg; - + unsigned int nor_count = 0; unsigned int inv_count = 0; for (i = 40; i > 0; i--, sync_nor >>= 1, sync_inv >>= 1) @@ -572,95 +545,72 @@ bool MDC1200_process_rx( } nor_count = 40 - nor_count; inv_count = 40 - inv_count; - + if (nor_count >= sync_bit_ok_threshold || inv_count >= sync_bit_ok_threshold) { // good enough - + rx.inverted_sync = (inv_count > nor_count) ? true : false; - - //String s; - //s.printf("%5u %2u %u sync found %s %u bits ", - // index, - // rx_bit_count, - // rx_packet_stage, - // rx_inverted_sync ? "inv" : "nor", - // rx_inverted_sync ? inv_count : nor_count); - - //for (int i = 4; i >= 0; i--) - //{ - // String s2; - // uint8_t b = rx_shift_reg >> (8 * i); - // if (rx_inverted_sync) - // b ^= 0xff; - // s2.printf(" %02X", b); - // s += s2; - //} - //Memo1->Lines->Add(s); - - rx.data_index = 0; + rx.data_index = 0; rx.bit_count = 0; rx.stage++; + + #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) + UART_printf("mdc1200 rx sync %s\r\n", rx.inverted_sync ? "inv" : "nor"); + #endif } } - + continue; } - - // ********* - - if (rx.stage < 2) - continue; - + if (rx.bit_count < 8) continue; - + rx.bit_count = 0; - - // 55 55 55 55 55 55 55 07 09 2A 44 6F 94 9C 22 20 32 A4 1A 37 1E 3A 00 98 2C 84 - + + // 07 09 2A 44 6F 94 9C 22 20 32 A4 1A 37 1E 3A 00 98 2C 84 + rx.data[rx.data_index++] = rx.shift_reg & 0xff; // save the last 8 bits - + if (rx.data_index < (FEC_K * 2)) continue; - - // s.printf("%5u %3u %u %2u ", index, rx_bit_count, rx_packet_stage, rx_buffer.size()); - // for (i = 0; i < rx_data_index; i++) - // { - // String s2; - // const uint8_t b = rx_buffer[i]; - // s2.printf(" %02X", b); - // s += s2; - // } - // Memo1->Lines->Add(s); - + + #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) + UART_SendText("mdc1200 rx "); + for (i = 0; i < rx.data_index; i++) + UART_printf(" %02X", rx.data[i]); + UART_SendText("\r\n"); + #endif + if (!decode_data(rx.data)) { MDC1200_reset_rx(); + + #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) + UART_SendText("mdc1200 rx decode error\r\n"); + #endif + continue; } - + // extract the info from the packet *op = rx.data[0]; *arg = rx.data[1]; *unit_id = ((uint16_t)rx.data[3] << 8) | (rx.data[2] << 0); - - //s.printf("%5u %3u %u %2u decoded ", index, rx_bit_count, rx_packet_stage, rx_buffer.size()); - //for (i = 0; i < 14; i++) - //{ - // String s2; - // const uint8_t b = data[i]; - // s2.printf(" %02X", b); - // s += s2; - //} - //Memo1->Lines->Add(s); - + + #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) + UART_printf("mdc1200 rx op %02X arg %02X id %04X\r\n", *op, *arg, *unit_id); + #endif + // reset the detector MDC1200_reset_rx(); - + return true; } } - + + MDC1200_reset_rx(); + return false; } @@ -679,4 +629,6 @@ void mdc1200_init(void) { memcpy(mdc1200_sync_suc_xor, mdc1200_sync, sizeof(mdc1200_sync)); xor_modulation(mdc1200_sync_suc_xor, sizeof(mdc1200_sync_suc_xor)); + + MDC1200_reset_rx(); } diff --git a/ui/main.c b/ui/main.c index 60e2bdb..d59c0aa 100644 --- a/ui/main.c +++ b/ui/main.c @@ -853,25 +853,26 @@ void UI_DisplayMain(void) #ifdef ENABLE_TX_WHEN_AM if (state == VFO_STATE_NORMAL || state == VFO_STATE_ALARM) #else - if ((state == VFO_STATE_NORMAL || state == VFO_STATE_ALARM) && !g_current_vfo->am_mode) // not allowed to TX if in AM mode + if ((state == VFO_STATE_NORMAL || state == VFO_STATE_ALARM) && !g_eeprom.vfo_info[vfo_num].am_mode) // not allowed to TX if in AM mode #endif { - if (FREQUENCY_tx_freq_check(g_current_vfo->p_tx->frequency) == 0) - { // show the TX power + if (FREQUENCY_tx_freq_check(g_eeprom.vfo_info[vfo_num].p_tx->frequency) == 0) + { + // show the TX power const char pwr_list[] = "LMH"; const unsigned int i = g_eeprom.vfo_info[vfo_num].output_power; str[0] = (i < ARRAY_SIZE(pwr_list)) ? pwr_list[i] : '\0'; str[1] = '\0'; UI_PrintStringSmall(str, LCD_WIDTH + 46, 0, line + 1); - } - if (g_eeprom.vfo_info[vfo_num].freq_config_rx.frequency != g_eeprom.vfo_info[vfo_num].freq_config_tx.frequency) - { // show the TX offset symbol - const char dir_list[] = "\0+-"; - const unsigned int i = g_eeprom.vfo_info[vfo_num].tx_offset_freq_dir; - str[0] = (i < sizeof(dir_list)) ? dir_list[i] : '?'; - str[1] = '\0'; - UI_PrintStringSmall(str, LCD_WIDTH + 54, 0, line + 1); + if (g_eeprom.vfo_info[vfo_num].freq_config_rx.frequency != g_eeprom.vfo_info[vfo_num].freq_config_tx.frequency) + { // show the TX offset symbol + const char dir_list[] = "\0+-"; + const unsigned int i = g_eeprom.vfo_info[vfo_num].tx_offset_freq_dir; + str[0] = (i < sizeof(dir_list)) ? dir_list[i] : '?'; + str[1] = '\0'; + UI_PrintStringSmall(str, LCD_WIDTH + 54, 0, line + 1); + } } }