From f724b159c7d7d62006e466938abe8762fd4a1179 Mon Sep 17 00:00:00 2001 From: OneOfEleven Date: Fri, 10 Nov 2023 14:30:04 +0000 Subject: [PATCH] . --- Makefile | 4 +- bsp/dp32g030/pwmplus.h | 146 + .../CMSIS/Core/Template/ARMv8-M/main_s.c | 58 - .../CMSIS/Core/Template/ARMv8-M/tz_context.c | 200 - .../CoreValidation/Include/CV_Framework.h | 44 - .../CMSIS/CoreValidation/Include/CV_Report.h | 89 - .../CoreValidation/Include/CV_Typedefs.h | 58 - .../CMSIS/CoreValidation/Include/cmsis_cv.h | 135 - .../CMSIS_5/CMSIS/CoreValidation/LICENSE.txt | 201 - .../App/Bootloader_Cortex-M/App.clayer.yml | 14 - .../App/Bootloader_Cortex-M/bootloader.c | 84 - .../App/Validation_Cortex-A/App.clayer.yml | 48 - .../Layer/App/Validation_Cortex-A/main.c | 133 - .../App/Validation_Cortex-M/App.clayer.yml | 73 - .../Layer/App/Validation_Cortex-M/main.c | 143 - .../Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf | 67 - .../RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0 | 67 - .../Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld | 181 - 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.../CMSIS/Core_A/Include/cmsis_iccarm.h | 573 --- .../CMSIS_5/CMSIS/Core_A/Include/core_ca.h | 2940 ----------- .../CMSIS_5/CMSIS/Core_A/Include/irq_ctrl.h | 192 - .../CMSIS/Core_A/Source/irq_ctrl_gic.c | 433 -- .../CMSIS/DAP/Firmware/Config/DAP_config.h | 561 --- .../Examples/LPC-Link2/CMSIS_DAP.uvguix | 1878 ------- .../Examples/LPC-Link2/CMSIS_DAP.uvoptx | 554 --- .../Examples/LPC-Link2/CMSIS_DAP.uvprojx | 1208 ----- .../Firmware/Examples/LPC-Link2/DAP_config.h | 709 --- .../LPC-Link2_LPC4370_Cortex-M4.dbgconf | 43 - ...C-Link2_on-board_LPC4322_Cortex-M4.dbgconf | 43 - .../Examples/LPC-Link2/Objects/CMSIS_DAP.hex | 4356 ----------------- .../DAP/Firmware/Examples/LPC-Link2/README.md | 8 - .../Examples/LPC-Link2/RTE/CMSIS/RTX_Config.c | 63 - .../Examples/LPC-Link2/RTE/CMSIS/RTX_Config.h | 580 --- .../RTE/Device/LPC4322_Cortex-M4/RTE_Device.h | 2483 ---------- .../LPC4322_Cortex-M4/startup_LPC43xx.s | 333 -- .../Device/LPC4322_Cortex-M4/system_LPC43xx.c | 938 ---- .../RTE/Device/LPC4370_Cortex-M4/RTE_Device.h | 2483 ---------- .../LPC4370_Cortex-M4/startup_LPC43xx.s | 333 -- .../Device/LPC4370_Cortex-M4/system_LPC43xx.c | 938 ---- .../LPC-Link2/RTE/USB/USBD_Config_0.c | 206 - .../LPC-Link2/RTE/USB/USBD_Config_CDC_0.h | 364 -- .../RTE/USB/USBD_Config_CustomClass_0.h | 3771 -------------- .../LPC-Link2/USBD_User_CDC_ACM_UART_0.c | 381 -- .../LPC-Link2/USBD_User_CustomClass_0.c | 358 -- .../DAP/Firmware/Examples/LPC-Link2/main.c | 78 - .../Firmware/Examples/LPC-Link2/osObjects.h | 54 - .../DAP/Firmware/Examples/LPC-Link2/ser_num.c | 93 - .../DAP/Firmware/Examples/LPC-Link2/ser_num.h | 33 - .../DAP/Firmware/Examples/LPC-Link2/target.c | 35 - .../Examples/MCU-LINK/CMSIS_DAP.uvguix | 3619 -------------- .../Examples/MCU-LINK/CMSIS_DAP.uvoptx | 480 -- .../Examples/MCU-LINK/CMSIS_DAP.uvprojx | 955 ---- .../Firmware/Examples/MCU-LINK/DAP_config.h | 651 --- .../MCU-Link_LPC55S69JBD64_cm33_core0.dbgconf | 18 - .../Firmware/Examples/MCU-LINK/MCU-Link.mex | 743 --- .../Examples/MCU-LINK/Objects/CMSIS_DAP.hex | 4356 ----------------- .../DAP/Firmware/Examples/MCU-LINK/README.md | 13 - .../Examples/MCU-LINK/RTE/CMSIS/RTX_Config.c | 64 - .../Examples/MCU-LINK/RTE/CMSIS/RTX_Config.h | 580 --- .../LPC55S69_cm33_core0_flash.scf | 105 - .../LPC55S69_cm33_core0_flash_ns.scf | 107 - .../LPC55S69_cm33_core0_flash_s.scf | 116 - .../LPC55S69_cm33_core0_ram.scf | 105 - .../LPC55S69JBD64_cm33_core0/RTE_Device.h | 215 - .../startup_LPC55S69_cm33_core0.S | 801 --- .../Examples/MCU-LINK/RTE/USB/USBD_Config_0.c | 206 - .../MCU-LINK/RTE/USB/USBD_Config_CDC_0.h | 364 -- .../RTE/USB/USBD_Config_CustomClass_0.h | 3771 -------------- .../Examples/MCU-LINK/USBD1_LPC55xxx.c | 984 ---- .../MCU-LINK/USBD_User_CDC_ACM_UART_0.c | 381 -- .../MCU-LINK/USBD_User_CustomClass_0.c | 358 -- .../Firmware/Examples/MCU-LINK/USB_LPC55xxx.h | 70 - .../Examples/MCU-LINK/board/clock_config.c | 150 - .../Examples/MCU-LINK/board/clock_config.h | 62 - .../Examples/MCU-LINK/board/peripherals.c | 77 - .../Examples/MCU-LINK/board/peripherals.h | 33 - .../Examples/MCU-LINK/board/pin_mux.c | 337 -- .../Examples/MCU-LINK/board/pin_mux.h | 276 -- .../Firmware/Examples/MCU-LINK/fsl_usart.c | 1284 ----- .../DAP/Firmware/Examples/MCU-LINK/main.c | 96 - .../Firmware/Examples/MCU-LINK/osObjects.h | 54 - .../DAP/Firmware/Examples/MCU-LINK/ser_num.c | 86 - .../DAP/Firmware/Examples/MCU-LINK/ser_num.h | 33 - .../CMSIS_5/CMSIS/DAP/Firmware/Include/DAP.h | 367 -- .../CMSIS_5/CMSIS/DAP/Firmware/Source/DAP.c | 1816 ------- .../CMSIS/DAP/Firmware/Source/DAP_vendor.c | 100 - .../CMSIS/DAP/Firmware/Source/JTAG_DP.c | 370 -- .../CMSIS_5/CMSIS/DAP/Firmware/Source/SWO.c | 798 --- .../CMSIS_5/CMSIS/DAP/Firmware/Source/SW_DP.c | 286 -- .../CMSIS_5/CMSIS/DAP/Firmware/Source/UART.c | 652 --- .../DAP/Firmware/Template/CMSIS_DAP_v2.inf | 54 - .../Template/MDK5/USBD_User_CDC_ACM_UART_0.c | 381 -- .../Template/MDK5/USBD_User_CustomClass_0.c | 358 -- .../Firmware/Template/MDK5/USBD_User_HID_0.c | 246 - .../CMSIS/DAP/Firmware/Template/MDK5/main.c | 71 - .../DAP/Firmware/Template/MDK5/osObjects.h | 54 - .../DAP/Firmware/Validation/MDK5/README.md | 37 - .../MDK5/RTE/Device/ARMCM3/startup_ARMCM3.s | 262 - .../MDK5/RTE/Device/ARMCM3/system_ARMCM3.c | 68 - .../MDK5/RTE/_CMSIS_DAP/RTE_Components.h | 21 - .../Validation/MDK5/Validation.CMSIS_DAP.cprj | 45 - .../Validation/MDK5/Validation.uvguix | 1878 ------- .../Validation/MDK5/Validation.uvoptx | 248 - .../Validation/MDK5/Validation.uvprojx | 449 -- .../DAP/Firmware/Validation/MDK5/test.bat | 50 - .../CMSIS/DAP/Firmware/Validation/MDK5/test.c | 89 - .../DAP/Firmware/Validation/MDK5/test.ini | 430 -- .../CMSIS/Driver/DriverTemplates/Driver_CAN.c | 317 -- .../Driver/DriverTemplates/Driver_ETH_MAC.c | 231 - .../Driver/DriverTemplates/Driver_ETH_PHY.c | 128 - .../Driver/DriverTemplates/Driver_Flash.c | 144 - .../CMSIS/Driver/DriverTemplates/Driver_I2C.c | 150 - .../CMSIS/Driver/DriverTemplates/Driver_MCI.c | 225 - .../Driver/DriverTemplates/Driver_NAND.c | 190 - .../CMSIS/Driver/DriverTemplates/Driver_SAI.c | 128 - .../CMSIS/Driver/DriverTemplates/Driver_SPI.c | 150 - .../Driver/DriverTemplates/Driver_Storage.c | 118 - .../Driver/DriverTemplates/Driver_USART.c | 153 - .../Driver/DriverTemplates/Driver_USBD.c | 164 - .../Driver/DriverTemplates/Driver_USBH.c | 181 - .../Driver/DriverTemplates/Driver_WiFi.c | 213 - .../CMSIS_5/CMSIS/Driver/Include/Driver_CAN.h | 388 -- .../CMSIS/Driver/Include/Driver_Common.h | 69 - .../CMSIS_5/CMSIS/Driver/Include/Driver_ETH.h | 87 - .../CMSIS/Driver/Include/Driver_ETH_MAC.h | 310 -- .../CMSIS/Driver/Include/Driver_ETH_PHY.h | 143 - .../CMSIS/Driver/Include/Driver_Flash.h | 209 - .../CMSIS_5/CMSIS/Driver/Include/Driver_I2C.h | 223 - .../CMSIS_5/CMSIS/Driver/Include/Driver_MCI.h | 366 -- .../CMSIS/Driver/Include/Driver_NAND.h | 426 -- .../CMSIS_5/CMSIS/Driver/Include/Driver_SAI.h | 315 -- .../CMSIS_5/CMSIS/Driver/Include/Driver_SPI.h | 254 - .../CMSIS/Driver/Include/Driver_Storage.h | 434 -- .../CMSIS/Driver/Include/Driver_USART.h | 347 -- .../CMSIS_5/CMSIS/Driver/Include/Driver_USB.h | 92 - .../CMSIS/Driver/Include/Driver_USBD.h | 279 -- .../CMSIS/Driver/Include/Driver_USBH.h | 423 -- .../CMSIS/Driver/Include/Driver_WiFi.h | 666 --- .../CMSIS/Driver/VIO/Include/cmsis_vio.h | 175 - .../CMSIS_5/CMSIS/Driver/VIO/Source/vio.c | 337 -- .../CMSIS/Driver/VIO/Source/vio_memory.c | 208 - .../CMSIS_5/CMSIS/Driver/VIO/cmsis_vio.scvd | 78 - .../Device/ARM/ARMCA5/Config/mem_ARMCA5.h | 100 - .../Device/ARM/ARMCA5/Config/system_ARMCA5.h | 65 - .../Device/ARM/ARMCA5/Include/ARMCA5.h | 138 - .../Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct | 77 - .../ARM/ARMCA5/Source/AC5/startup_ARMCA5.c | 151 - .../Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct | 77 - .../ARM/ARMCA5/Source/AC6/startup_ARMCA5.c | 136 - .../Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld | 181 - .../Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct | 77 - .../ARM/ARMCA5/Source/GCC/startup_ARMCA5.c | 136 - .../Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf | 67 - .../ARM/ARMCA5/Source/IAR/startup_ARMCA5.s | 140 - .../Device/ARM/ARMCA5/Source/mmu_ARMCA5.c | 232 - .../Device/ARM/ARMCA5/Source/system_ARMCA5.c | 93 - .../Device/ARM/ARMCA7/Config/mem_ARMCA7.h | 100 - .../Device/ARM/ARMCA7/Config/system_ARMCA7.h | 65 - .../Device/ARM/ARMCA7/Include/ARMCA7.h | 135 - .../Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct | 77 - .../ARM/ARMCA7/Source/AC5/startup_ARMCA7.c | 151 - .../Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct | 77 - .../ARM/ARMCA7/Source/AC6/startup_ARMCA7.c | 136 - .../Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld | 181 - .../ARM/ARMCA7/Source/GCC/startup_ARMCA7.c | 136 - .../Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf | 67 - .../ARM/ARMCA7/Source/IAR/startup_ARMCA7.s | 140 - .../Device/ARM/ARMCA7/Source/mmu_ARMCA7.c | 232 - .../Device/ARM/ARMCA7/Source/system_ARMCA7.c | 93 - .../Device/ARM/ARMCA9/Config/mem_ARMCA9.h | 100 - .../Device/ARM/ARMCA9/Config/system_ARMCA9.h | 65 - .../Device/ARM/ARMCA9/Include/ARMCA9.h | 139 - .../Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct | 77 - .../ARM/ARMCA9/Source/AC5/startup_ARMCA9.c | 151 - .../Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct | 77 - .../ARM/ARMCA9/Source/AC6/startup_ARMCA9.c | 136 - .../Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld | 181 - .../ARM/ARMCA9/Source/GCC/startup_ARMCA9.c | 136 - .../Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf | 67 - .../ARM/ARMCA9/Source/IAR/startup_ARMCA9.s | 140 - .../Device/ARM/ARMCA9/Source/mmu_ARMCA9.c | 232 - .../Device/ARM/ARMCA9/Source/system_ARMCA9.c | 93 - .../ARM/ARMCM0/Source/IAR/startup_ARMCM0.s | 147 - .../ARM/ARMCM0plus/Include/ARMCM0plus.h | 127 - .../ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h | 127 - .../ARMCM0plus/Include/system_ARMCM0plus.h | 64 - .../ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct | 80 - .../ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct | 80 - .../Source/ARM/startup_ARMCM0plus.s | 168 - .../ARM/ARMCM0plus/Source/GCC/gcc_arm.ld | 296 -- .../Source/GCC/startup_ARMCM0plus.S | 181 - .../Source/IAR/startup_ARMCM0plus.s | 147 - .../ARMCM0plus/Source/startup_ARMCM0plus.c | 148 - .../ARM/ARMCM0plus/Source/system_ARMCM0plus.c | 65 - .../Device/ARM/ARMCM1/Include/ARMCM1.h | 128 - .../Device/ARM/ARMCM1/Include/system_ARMCM1.h | 64 - .../ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct | 80 - .../ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct | 80 - .../ARM/ARMCM1/Source/ARM/startup_ARMCM1.s | 168 - .../Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld | 296 -- .../ARM/ARMCM1/Source/GCC/startup_ARMCM1.S | 181 - .../ARM/ARMCM1/Source/IAR/startup_ARMCM1.s | 147 - .../Device/ARM/ARMCM1/Source/startup_ARMCM1.c | 146 - .../Device/ARM/ARMCM1/Source/system_ARMCM1.c | 56 - .../Device/ARM/ARMCM23/Debug/ARMv8MBL.dbgconf | 13 - .../Device/ARM/ARMCM23/Include/ARMCM23.h | 128 - .../Device/ARM/ARMCM23/Include/ARMCM23_TZ.h | 128 - .../Include/Template/partition_ARMCM23.h | 832 ---- .../ARM/ARMCM23/Include/system_ARMCM23.h | 64 - .../ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct | 123 - .../ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct | 123 - .../ARM/ARMCM23/Source/ARM/startup_ARMCM23.S | 155 - .../Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld | 316 -- .../ARM/ARMCM23/Source/GCC/startup_ARMCM23.S | 200 - .../ARM/ARMCM23/Source/IAR/startup_ARMCM23.s | 168 - .../ARM/ARMCM23/Source/startup_ARMCM23.c | 161 - .../ARM/ARMCM23/Source/system_ARMCM23.c | 80 - .../Device/ARM/ARMCM3/Include/ARMCM3.h | 127 - .../Device/ARM/ARMCM3/Include/system_ARMCM3.h | 64 - .../ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct | 80 - .../ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct | 80 - .../ARM/ARMCM3/Source/ARM/startup_ARMCM3.s | 172 - .../Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld | 296 -- .../ARM/ARMCM3/Source/GCC/startup_ARMCM3.S | 182 - .../ARM/ARMCM3/Source/IAR/startup_ARMCM3.s | 155 - .../Device/ARM/ARMCM3/Source/startup_ARMCM3.c | 150 - .../Device/ARM/ARMCM3/Source/system_ARMCM3.c | 65 - .../Device/ARM/ARMCM33/Include/ARMCM33.h | 131 - .../ARM/ARMCM33/Include/ARMCM33_DSP_FP.h | 131 - .../ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h | 131 - .../Device/ARM/ARMCM33/Include/ARMCM33_TZ.h | 131 - .../Include/Template/partition_ARMCM33.h | 1260 ----- .../ARM/ARMCM33/Include/system_ARMCM33.h | 64 - .../ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct | 123 - .../ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct | 123 - .../ARM/ARMCM33/Source/ARM/startup_ARMCM33.S | 159 - .../Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld | 316 -- .../ARM/ARMCM33/Source/GCC/startup_ARMCM33.S | 202 - .../ARM/ARMCM33/Source/IAR/startup_ARMCM33.s | 177 - .../ARM/ARMCM33/Source/startup_ARMCM33.c | 170 - .../ARM/ARMCM33/Source/system_ARMCM33.c | 97 - .../Device/ARM/ARMCM35P/Include/ARMCM35P.h | 131 - .../ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h | 131 - .../ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h | 131 - .../Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h | 131 - .../Include/Template/partition_ARMCM35P.h | 1260 ----- .../ARM/ARMCM35P/Include/system_ARMCM35P.h | 64 - .../ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct | 123 - .../ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct | 123 - .../ARMCM35P/Source/ARM/startup_ARMCM35P.S | 159 - .../Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld | 316 -- .../ARMCM35P/Source/GCC/startup_ARMCM35P.S | 202 - .../ARMCM35P/Source/IAR/startup_ARMCM35P.s | 177 - .../ARM/ARMCM35P/Source/startup_ARMCM35P.c | 170 - .../ARM/ARMCM35P/Source/system_ARMCM35P.c | 97 - .../Device/ARM/ARMCM4/Include/ARMCM4.h | 128 - .../Device/ARM/ARMCM4/Include/ARMCM4_FP.h | 128 - .../Device/ARM/ARMCM4/Include/system_ARMCM4.h | 64 - .../ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct | 80 - .../ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct | 80 - .../ARM/ARMCM4/Source/ARM/startup_ARMCM4.s | 172 - .../Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld | 296 -- .../ARM/ARMCM4/Source/GCC/startup_ARMCM4.S | 182 - .../ARM/ARMCM4/Source/IAR/startup_ARMCM4.s | 155 - .../Device/ARM/ARMCM4/Source/startup_ARMCM4.c | 152 - .../Device/ARM/ARMCM4/Source/system_ARMCM4.c | 81 - .../Device/ARM/ARMCM55/Include/ARMCM55.h | 137 - .../Include/Template/partition_ARMCM55.h | 1261 ----- .../ARM/ARMCM55/Include/system_ARMCM55.h | 64 - .../ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct | 123 - .../ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct | 123 - .../Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld | 316 -- .../ARM/ARMCM55/Source/startup_ARMCM55.c | 164 - .../ARM/ARMCM55/Source/system_ARMCM55.c | 107 - .../Device/ARM/ARMCM7/Include/ARMCM7.h | 133 - .../Device/ARM/ARMCM7/Include/ARMCM7_DP.h | 133 - .../Device/ARM/ARMCM7/Include/ARMCM7_SP.h | 133 - .../Device/ARM/ARMCM7/Include/system_ARMCM7.h | 64 - .../ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct | 80 - .../ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct | 80 - .../ARM/ARMCM7/Source/ARM/startup_ARMCM7.s | 172 - .../Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld | 296 -- .../ARM/ARMCM7/Source/GCC/startup_ARMCM7.S | 182 - .../ARM/ARMCM7/Source/IAR/startup_ARMCM7.s | 155 - .../Device/ARM/ARMCM7/Source/startup_ARMCM7.c | 154 - .../Device/ARM/ARMCM7/Source/system_ARMCM7.c | 83 - .../Device/ARM/ARMCM85/Include/ARMCM85.h | 135 - .../Include/Template/partition_ARMCM85.h | 1301 ----- .../ARM/ARMCM85/Include/system_ARMCM85.h | 63 - .../ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct | 130 - .../ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct | 130 - .../Device/ARM/ARMCM85/Source/GCC/gcc_arm.ld | 314 -- .../ARM/ARMCM85/Source/startup_ARMCM85.c | 164 - .../ARM/ARMCM85/Source/system_ARMCM85.c | 106 - .../Device/ARM/ARMSC000/Include/ARMSC000.h | 126 - .../ARM/ARMSC000/Include/system_ARMSC000.h | 64 - .../ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct | 76 - .../ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct | 76 - .../ARMSC000/Source/ARM/startup_ARMSC000.s | 168 - .../Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld | 296 -- .../ARMSC000/Source/GCC/startup_ARMSC000.S | 181 - .../ARMSC000/Source/IAR/startup_ARMSC000.s | 147 - .../ARM/ARMSC000/Source/startup_ARMSC000.c | 146 - .../ARM/ARMSC000/Source/system_ARMSC000.c | 56 - .../Device/ARM/ARMSC300/Include/ARMSC300.h | 126 - .../ARM/ARMSC300/Include/system_ARMSC300.h | 65 - .../ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct | 76 - .../ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct | 76 - .../ARMSC300/Source/ARM/startup_ARMSC300.s | 172 - .../Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld | 296 -- .../ARMSC300/Source/GCC/startup_ARMSC300.S | 182 - .../ARMSC300/Source/IAR/startup_ARMSC300.s | 155 - .../ARM/ARMSC300/Source/startup_ARMSC300.c | 150 - .../ARM/ARMSC300/Source/system_ARMSC300.c | 70 - .../Include/ARMv81MML_DSP_DP_MVE_FP.h | 134 - .../Include/Template/partition_ARMv81MML.h | 1261 ----- .../ARM/ARMv81MML/Include/system_ARMv81MML.h | 65 - .../ARMv81MML/Source/ARM/ARMv81MML_ac6.sct | 119 - .../ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct | 119 - .../ARM/ARMv81MML/Source/GCC/gcc_arm.ld | 316 -- .../ARM/ARMv81MML/Source/startup_ARMv81MML.c | 164 - .../ARM/ARMv81MML/Source/system_ARMv81MML.c | 93 - .../Device/ARM/ARMv8MBL/Include/ARMv8MBL.h | 127 - .../Include/Template/partition_ARMv8MBL.h | 1232 ----- .../ARM/ARMv8MBL/Include/system_ARMv8MBL.h | 65 - .../ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct | 119 - .../ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct | 119 - .../ARMv8MBL/Source/ARM/startup_ARMv8MBL.S | 155 - .../Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld | 316 -- .../ARMv8MBL/Source/GCC/startup_ARMv8MBL.S | 200 - .../ARMv8MBL/Source/IAR/startup_ARMv8MBL.s | 147 - .../ARM/ARMv8MBL/Source/startup_ARMv8MBL.c | 159 - .../ARM/ARMv8MBL/Source/system_ARMv8MBL.c | 74 - .../Device/ARM/ARMv8MML/Include/ARMv8MML.h | 132 - .../Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h | 133 - .../ARM/ARMv8MML/Include/ARMv8MML_DSP.h | 132 - .../ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h | 133 - .../ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h | 133 - .../Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h | 133 - .../Include/Template/partition_ARMv8MML.h | 1260 ----- .../ARM/ARMv8MML/Include/system_ARMv8MML.h | 65 - .../ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct | 119 - .../ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct | 119 - .../ARMv8MML/Source/ARM/startup_ARMv8MML.S | 159 - .../Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld | 316 -- .../ARMv8MML/Source/GCC/startup_ARMv8MML.S | 202 - .../ARMv8MML/Source/IAR/startup_ARMv8MML.s | 157 - .../ARM/ARMv8MML/Source/startup_ARMv8MML.c | 174 - .../ARM/ARMv8MML/Source/system_ARMv8MML.c | 98 - external/CMSIS_5/Device/ARM/SVD/ARMCM1.svd | 76 - external/CMSIS_5/Device/ARM/SVD/ARMCM23.svd | 103 - external/CMSIS_5/Device/ARM/SVD/ARMCM3.svd | 76 - external/CMSIS_5/Device/ARM/SVD/ARMCM33.svd | 103 - external/CMSIS_5/Device/ARM/SVD/ARMCM35P.svd | 103 - external/CMSIS_5/Device/ARM/SVD/ARMCM4.svd | 76 - external/CMSIS_5/Device/ARM/SVD/ARMCM55.svd | 107 - external/CMSIS_5/Device/ARM/SVD/ARMCM7.svd | 80 - external/CMSIS_5/Device/ARM/SVD/ARMCM85.svd | 105 - external/CMSIS_5/Device/ARM/SVD/ARMSC000.svd | 76 - external/CMSIS_5/Device/ARM/SVD/ARMSC300.svd | 76 - external/CMSIS_5/Device/ARM/SVD/ARMv8MBL.svd | 103 - external/CMSIS_5/Device/ARM/SVD/ARMv8MML.svd | 103 - .../Device/_Template_Flash/Abstract.txt | 32 - .../CMSIS_5/Device/_Template_Flash/FlashDev.c | 45 - .../CMSIS_5/Device/_Template_Flash/FlashOS.h | 77 - .../CMSIS_5/Device/_Template_Flash/FlashPrg.c | 118 - .../Device/_Template_Flash/NewDevice.uvguix | 1848 ------- .../Device/_Template_Flash/NewDevice.uvoptx | 232 - .../Device/_Template_Flash/NewDevice.uvprojx | 420 -- .../CMSIS_5/Device/_Template_Flash/Target.lin | 22 - .../Device/_Template_Vendor/ReadMe.txt | 71 - .../Vendor/Device/Include/Device.h | 230 - .../Include/Template/partition_Device.h | 1262 ----- .../Vendor/Device/Include/system_Device.h | 64 - .../Vendor/Device/Source/ARM/Device_ac5.sct | 79 - .../Vendor/Device/Source/ARM/Device_ac6.sct | 119 - .../Device/Source/ARM/startup_Device_ac5.s | 137 - .../Source/ARM/startup_Device_ac5_noSct.s | 164 - .../Device/Source/ARM/startup_Device_ac6.S | 151 - .../Vendor/Device/Source/GCC/gcc_arm.ld | 316 -- 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delete mode 100644 external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h delete mode 100644 external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h delete mode 100644 external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h delete mode 100644 external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/Device.sct delete mode 100644 external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c delete mode 100644 external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c delete mode 100644 external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c diff --git a/Makefile b/Makefile index 64689a2..2639be5 100644 --- a/Makefile +++ b/Makefile @@ -258,8 +258,6 @@ endif CFLAGS = -CFLAGS += -DCPU_CLOCK_HZ=48000000 - ifeq ($(ENABLE_CLANG),0) #CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c11 -MMD CFLAGS += -Os -Werror -mcpu=cortex-m0 -freorder-blocks-algorithm=stc -std=c11 -MMD @@ -282,6 +280,8 @@ endif # better to bust than add new bugs CFLAGS += -Wall -Wextra -Wpedantic +CFLAGS += -DCPU_CLOCK_HZ=48000000 + CFLAGS += -DPRINTF_INCLUDE_CONFIG_H CFLAGS += -DGIT_HASH=\"$(GIT_HASH)\" ifeq ($(ENABLE_SWD),1) diff --git a/bsp/dp32g030/pwmplus.h b/bsp/dp32g030/pwmplus.h new file mode 100644 index 0000000..3b74475 --- /dev/null +++ b/bsp/dp32g030/pwmplus.h @@ -0,0 +1,146 @@ +#ifndef HARDWARE_DP32G030_PWMPLUS_H +#define HARDWARE_DP32G030_PWMPLUS_H + +#define PWM_PLUS0_BASE_ADDR 0x400B4000U + +//--------------- + +#define PWMPLUS_CFG 0x00U + +#define PWMPLUS_CFG_COUNTER_EN_SHIFT 0U +#define PWMPLUS_CFG_COUNTER_EN_WIDTH 1U +#define PWMPLUS_CFG_COUNTER_EN_MASK (((1U << PWMPLUS_CFG_COUNTER_EN_WIDTH) - 1U) << PWMPLUS_CFG_COUNTER_EN_SHIFT) +#define PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE 1U +#define PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE (PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE << PWMPLUS_CFG_COUNTER_EN_SHIFT) + +#define PWMPLUS_CFG_CNT_TYPE_SHIFT 1U + +#define PWMPLUS_CFG_CNT_REP_SHIFT 2U +#define PWMPLUS_CFG_CNT_REP_WIDTH 1U +#define PWMPLUS_CFG_CNT_REP_VALUE_ENABLE 1U +#define PWMPLUS_CFG_CNT_REP_BITS_ENABLE (PWMPLUS_CFG_CNT_REP_VALUE_ENABLE << PWMPLUS_CFG_CNT_REP_SHIFT) + +#define PWMPLUS_CFG_OUT_MODE_SHIFT 3U +#define PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE 1U +#define PWMPLUS_CFG_OUT_MODE_BITS_ENABLE (PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE << PWMPLUS_CFG_OUT_MODE_SHIFT) + +#define PWMPLUS_CFG_AUTO_RELOAD_SHIFT 8U + +//--------------- + +#define PWMPLUS_GEN 0x04U + +#define PWMPLUS_GEN_CH0_OE_SHIFT 24U +#define PWMPLUS_GEN_CH0_OE_WIDTH 1U +#define PWMPLUS_GEN_CH0_OE_VALUE_ENABLE 1U +#define PWMPLUS_GEN_CH0_OE_BITS_ENABLE (PWMPLUS_GEN_CH0_OE_VALUE_ENABLE << PWMPLUS_GEN_CH0_OE_SHIFT) + +#define PWMPLUS_GEN_CH0_OUTINV_SHIFT 16U +#define PWMPLUS_GEN_CH0_OUTINV_WIDTH 1U +#define PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE 1U +#define PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE (PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE << PWMPLUS_GEN_CH0_OUTINV_SHIFT) + +#define PWMPLUS_GEN_CH0_START_SHIFT 8U +#define PWMPLUS_GEN_CH0_START_WIDTH 1U +#define PWMPLUS_GEN_CH0_START_VALUE_ENABLE 1U +#define PWMPLUS_GEN_CH0_START_BITS_ENABLE (PWMPLUS_GEN_CH0_START_VALUE_ENABLE << PWMPLUS_GEN_CH0_START_SHIFT) + +#define PWMPLUS_GEN_CH0_IDLE_SHIFT 0U +#define PWMPLUS_GEN_CH0_IDLE_WIDTH 1U +#define PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE 1U +#define PWMPLUS_GEN_CH0_IDLE_BITS_ENABLE (PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE << PWMPLUS_GEN_CH0_IDLE_SHIFT) + +//--------------- + +#define PWMPLUS_CLKSRC 0x08U +#define PWMPLUS_BRAKE_CFG 0x0CU +#define PWMPLUS_MASK_LEV 0x10U +#define PWMPLUS_PERIOD 0x1CU +#define PWMPLUS_CH0_COMP 0x20U +#define PWMPLUS_CH1_COMP 0x24U +#define PWMPLUS_CH2_COMP 0x28U +#define PWMPLUS_CH0_DT 0x30U +#define PWMPLUS_CH1_DT 0x34U +#define PWMPLUS_CH2_DT 0x38U +#define PWMPLUS_TRIG_COMP 0x40U +#define PWMPLUS_TRIG_CFG 0x44U +#define PWMPLUS_IE 0x60U +#define PWMPLUS_IF 0x64U +#define PWMPLUS_SWLOAD 0x84U +#define PWMPLUS_MASK_EN 0x88 +#define PWMPLUS_CNT_ST 0xE0 +#define PWMPLUS_BRAKE_ST 0xE4 + + + + + + + + + + + + + +#define PWM_PLUS0_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CFG) +#define PWM_PLUS0_CFG (*(volatile uint32_t *)PWM_PLUS0_CFG_ADDR) + +#define PWM_PLUS0_GEN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_GEN) +#define PWM_PLUS0_GEN (*(volatile uint32_t *)PWM_PLUS0_GEN_ADDR) + +#define PWM_PLUS0_CLKSRC_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CLKSRC) +#define PWM_PLUS0_CLKSRC (*(volatile uint32_t *)PWM_PLUS0_CLKSRC_ADDR) + +#define PWM_PLUS0_BRAKE_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_CFG) +#define PWM_PLUS0_BRAKE_CFG (*(volatile uint32_t *)PWM_PLUS0_BRAKE_CFG_ADDR) + +#define PWM_PLUS0_MASK_LEV_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_LEV) +#define PWM_PLUS0_MASK_LEV (*(volatile uint32_t *)PWM_PLUS0_MASK_LEV_ADDR) + +#define PWM_PLUS0_PERIOD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_PERIOD) +#define PWM_PLUS0_PERIOD (*(volatile uint32_t *)PWM_PLUS0_PERIOD_ADDR) + +#define PWM_PLUS0_CH0_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_COMP) +#define PWM_PLUS0_CH0_COMP (*(volatile uint32_t *)PWM_PLUS0_CH0_COMP_ADDR) + +#define PWM_PLUS0_CH1_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_COMP) +#define PWM_PLUS0_CH1_COMP (*(volatile uint32_t *)PWM_PLUS0_CH1_COMP_ADDR) + +#define PWM_PLUS0_CH2_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_COMP) +#define PWM_PLUS0_CH2_COMP (*(volatile uint32_t *)PWM_PLUS0_CH2_COMP_ADDR) + +#define PWM_PLUS0_CH0_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_DT) +#define PWM_PLUS0_CH0_DT (*(volatile uint32_t *)PWM_PLUS0_CH0_DT_ADDR) + +#define PWM_PLUS0_CH1_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_DT) +#define PWM_PLUS0_CH1_DT (*(volatile uint32_t *)PWM_PLUS0_CH1_DT_ADDR) + +#define PWM_PLUS0_CH2_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_DT) +#define PWM_PLUS0_CH2_DT (*(volatile uint32_t *)PWM_PLUS0_CH2_DT_ADDR) + +#define PWM_PLUS0_TRIG_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_COMP) +#define PWM_PLUS0_TRIG_COMP (*(volatile uint32_t *)PWM_PLUS0_TRIG_COMP_ADDR) + +#define PWM_PLUS0_TRIG_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_CFG) +#define PWM_PLUS0_TRIG_CFG (*(volatile uint32_t *)PWM_PLUS0_TRIG_CFG_ADDR) + +#define PWM_PLUS0_IE_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IE) +#define PWM_PLUS0_IE (*(volatile uint32_t *)PWM_PLUS0_IE_ADDR) + +#define PWM_PLUS0_IF_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IF) +#define PWM_PLUS0_IF (*(volatile uint32_t *)PWM_PLUS0_IF_ADDR) + +#define PWM_PLUS0_SWLOAD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_SWLOAD) +#define PWM_PLUS0_SWLOAD (*(volatile uint32_t *)PWM_PLUS0_SWLOAD_ADDR) + +#define PWM_PLUS0_MASK_EN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_EN) +#define PWM_PLUS0_MASK_EN (*(volatile uint32_t *)PWM_PLUS0_MASK_EN_ADDR) + +#define PWM_PLUS0_CNT_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CNT_ST) +#define PWM_PLUS0_CNT_ST (*(volatile uint32_t *)PWM_PLUS0_CNT_ST_ADDR) + +#define PWM_PLUS0_BRAKE_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_ST) +#define PWM_PLUS0_BRAKE_ST (*(volatile uint32_t *)PWM_PLUS0_BRAKE_ST_ADDR) + +#endif \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/main_s.c b/external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/main_s.c deleted file mode 100644 index 273607b..0000000 --- a/external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/main_s.c +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** - * @file main_s.c - * @brief Code template for secure main function - * @version V1.1.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2013-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Use CMSE intrinsics */ -#include - -#include "RTE_Components.h" -#include CMSIS_device_header - -/* TZ_START_NS: Start address of non-secure application */ -#ifndef TZ_START_NS -#define TZ_START_NS (0x200000U) -#endif - -/* typedef for non-secure callback functions */ -typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - -/* Secure main() */ -int main(void) { - funcptr_void NonSecure_ResetHandler; - - /* Add user setup code for secure part here*/ - - /* Set non-secure main stack (MSP_NS) */ - __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - - /* Get non-secure reset handler */ - NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - - /* Start non-secure state software application */ - NonSecure_ResetHandler(); - - /* Non-secure software does not return, this code is not executed */ - while (1) { - __NOP(); - } -} diff --git a/external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/tz_context.c b/external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/tz_context.c deleted file mode 100644 index e2e8294..0000000 --- a/external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/tz_context.c +++ /dev/null @@ -1,200 +0,0 @@ -/****************************************************************************** - * @file tz_context.c - * @brief Context Management for Armv8-M TrustZone - Sample implementation - * @version V1.1.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2016-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "tz_context.h" - -/// Number of process slots (threads may call secure library code) -#ifndef TZ_PROCESS_STACK_SLOTS -#define TZ_PROCESS_STACK_SLOTS 8U -#endif - -/// Stack size of the secure library code -#ifndef TZ_PROCESS_STACK_SIZE -#define TZ_PROCESS_STACK_SIZE 256U -#endif - -typedef struct { - uint32_t sp_top; // stack space top - uint32_t sp_limit; // stack space limit - uint32_t sp; // current stack pointer -} stack_info_t; - -static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; -static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; -static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; - - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -__attribute__((cmse_nonsecure_entry)) -uint32_t TZ_InitContextSystem_S (void) { - uint32_t n; - - if (__get_IPSR() == 0U) { - return 0U; // Thread Mode - } - - for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { - ProcessStackInfo[n].sp = 0U; - ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; - ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; - *((uint32_t *)ProcessStackMemory[n]) = n + 1U; - } - *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; - - ProcessStackFreeSlot = 0U; - - // Default process stack pointer and stack limit - __set_PSPLIM((uint32_t)ProcessStackMemory); - __set_PSP ((uint32_t)ProcessStackMemory); - - // Privileged Thread Mode using PSP - __set_CONTROL(0x02U); - - return 1U; // Success -} - - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -__attribute__((cmse_nonsecure_entry)) -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { - uint32_t slot; - - (void)module; // Ignore (fixed Stack size) - - if (__get_IPSR() == 0U) { - return 0U; // Thread Mode - } - - if (ProcessStackFreeSlot == 0xFFFFFFFFU) { - return 0U; // No slot available - } - - slot = ProcessStackFreeSlot; - ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); - - ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; - - return (slot + 1U); -} - - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -__attribute__((cmse_nonsecure_entry)) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { - uint32_t slot; - - if (__get_IPSR() == 0U) { - return 0U; // Thread Mode - } - - if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { - return 0U; // Invalid ID - } - - slot = id - 1U; - - if (ProcessStackInfo[slot].sp == 0U) { - return 0U; // Inactive slot - } - ProcessStackInfo[slot].sp = 0U; - - *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; - ProcessStackFreeSlot = slot; - - return 1U; // Success -} - - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -__attribute__((cmse_nonsecure_entry)) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { - uint32_t slot; - - if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { - return 0U; // Thread Mode or using Main Stack for threads - } - - if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { - return 0U; // Invalid ID - } - - slot = id - 1U; - - if (ProcessStackInfo[slot].sp == 0U) { - return 0U; // Inactive slot - } - - // Setup process stack pointer and stack limit - __set_PSPLIM(ProcessStackInfo[slot].sp_limit); - __set_PSP (ProcessStackInfo[slot].sp); - - return 1U; // Success -} - - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -__attribute__((cmse_nonsecure_entry)) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { - uint32_t slot; - uint32_t sp; - - if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { - return 0U; // Thread Mode or using Main Stack for threads - } - - if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { - return 0U; // Invalid ID - } - - slot = id - 1U; - - if (ProcessStackInfo[slot].sp == 0U) { - return 0U; // Inactive slot - } - - sp = __get_PSP(); - if ((sp < ProcessStackInfo[slot].sp_limit) || - (sp > ProcessStackInfo[slot].sp_top)) { - return 0U; // SP out of range - } - ProcessStackInfo[slot].sp = sp; - - // Default process stack pointer and stack limit - __set_PSPLIM((uint32_t)ProcessStackMemory); - __set_PSP ((uint32_t)ProcessStackMemory); - - return 1U; // Success -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Framework.h b/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Framework.h deleted file mode 100644 index 241f615..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Framework.h +++ /dev/null @@ -1,44 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_Framework.h - * Purpose: Framework header - *---------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __FRAMEWORK_H__ -#define __FRAMEWORK_H__ - -#include "CV_Typedefs.h" -#include "CV_Report.h" - -/*----------------------------------------------------------------------------- - * Test framework global definitions - *----------------------------------------------------------------------------*/ - -/* Test case definition macro */ -#define TCD(x, y) {x, #x, y} - -/* Test case description structure */ -typedef struct __TestCase { - void (*TestFunc)(void); /* Test function */ - const char *TFName; /* Test function name string */ - BOOL en; /* Test function enabled */ -} TEST_CASE; - -/* Test suite description structure */ -typedef struct __TestSuite { - const char *FileName; /* Test module file name */ - const char *Date; /* Compilation date */ - const char *Time; /* Compilation time */ - const char *ReportTitle; /* Title or name of module under test */ - void (*Init)(void); /* Init function callback */ - - uint32_t TCBaseNum; /* Base number for test case numbering */ - TEST_CASE *TC; /* Array of test cases */ - uint32_t NumOfTC; /* Number of test cases (sz of TC array)*/ - -} TEST_SUITE; - -/* Defined in user test module */ -extern TEST_SUITE ts; - -#endif /* __FRAMEWORK_H__ */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Report.h b/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Report.h deleted file mode 100644 index 7c34466..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Report.h +++ /dev/null @@ -1,89 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_Report.h - * Purpose: Report statistics and layout header - *---------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __REPORT_H__ -#define __REPORT_H__ - -#include "CV_Config.h" -#include "CV_Typedefs.h" - -/*----------------------------------------------------------------------------- - * Test report global definitions - *----------------------------------------------------------------------------*/ - -#define REP_TC_FAIL 0 -#define REP_TC_WARN 1 -#define REP_TC_PASS 2 -#define REP_TC_NOEX 3 - -/* Test case result definition */ -typedef enum { - PASSED = 0, - WARNING, - FAILED, - NOT_EXECUTED -} TC_RES; - -/* Assertion result info */ -typedef struct { - const char *module; /* Module name */ - uint32_t line; /* Assertion line */ -} AS_INFO; - -/* Test case callback interface definition */ -typedef struct { - BOOL (* Result) (TC_RES res); - BOOL (* Dbgi) (TC_RES res, const char *fn, uint32_t ln, char *desc); -} TC_ITF; - -/* Assert interface to the report */ -extern TC_ITF tcitf; - -/* Assertion result buffer */ -typedef struct { -AS_INFO passed[BUFFER_ASSERTIONS]; -AS_INFO failed[BUFFER_ASSERTIONS]; -AS_INFO warnings[BUFFER_ASSERTIONS]; -} AS_T_INFO; - -/* Assertion statistics */ -typedef struct { - uint32_t passed; /* Total assertions passed */ - uint32_t failed; /* Total assertions failed */ - uint32_t warnings; /* Total assertions warnings */ - AS_T_INFO info; /* Detailed assertion info */ -} AS_STAT; - -/* Test global statistics */ -typedef struct { - uint32_t tests; /* Total test cases count */ - uint32_t executed; /* Total test cases executed */ - uint32_t passed; /* Total test cases passed */ - uint32_t failed; /* Total test cases failed */ - uint32_t warnings; /* Total test cases warnings */ - AS_STAT assertions; /* Total assertions statistics */ -} TEST_REPORT; - -/* Test report interface */ -typedef struct { - BOOL (* Init) (void); - BOOL (* Open) (const char *title, const char *date, const char *time, const char *fn); - BOOL (* Close) (void); - BOOL (* Open_TC) (uint32_t num, const char *fn); - BOOL (* Close_TC) (void); -} REPORT_ITF; - -/* Test report statistics */ -extern TEST_REPORT test_report; - -/* Test report interface */ -extern REPORT_ITF ritf; - -/* Assertions and test results */ -extern TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc); -extern TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond); - -#endif /* __REPORT_H__ */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Typedefs.h b/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Typedefs.h deleted file mode 100644 index 20fe08e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Typedefs.h +++ /dev/null @@ -1,58 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_Typedefs.h - * Purpose: Test framework filetypes and structures description - *---------------------------------------------------------------------------- - * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __TYPEDEFS_H__ -#define __TYPEDEFS_H__ - -#include -#include -#include -#include - -typedef unsigned int BOOL; - -#ifndef __TRUE - #define __TRUE 1 -#endif -#ifndef __FALSE - #define __FALSE 0 -#endif - -#ifndef ENABLED - #define ENABLED 1 -#endif -#ifndef DISABLED - #define DISABLED 0 -#endif - -#ifndef NULL - #ifdef __cplusplus // EC++ - #define NULL 0 - #else - #define NULL ((void *) 0) - #endif -#endif - -#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0])) - -#if defined( __GNUC__ ) || defined ( __clang__ ) -static const int PATH_DELIMITER = '/'; -#else -static const int PATH_DELIMITER = '\\'; -#endif - -//lint -emacro(9016,__FILENAME__) allow pointer arithmetic for truncating filename -//lint -emacro(613,__FILENAME__) null pointer is checked -#define __FILENAME__ ((strrchr(__FILE__, PATH_DELIMITER) != NULL) ? (strrchr(__FILE__, PATH_DELIMITER) + 1) : __FILE__) - -/* Assertions and test results */ -#define SET_RESULT(res, desc) (void)__set_result(__FILENAME__, __LINE__, (res), (desc)); - -//lint -emacro(9031,ASSERT_TRUE) allow boolean condition as parameter -//lint -emacro(613,ASSERT_TRUE) null pointer is checked -#define ASSERT_TRUE(cond) (void)__assert_true (__FILENAME__, __LINE__, (cond) ? 1U : 0U) - -#endif /* __TYPEDEFS_H__ */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Include/cmsis_cv.h b/external/CMSIS_5/CMSIS/CoreValidation/Include/cmsis_cv.h deleted file mode 100644 index 26fedc9..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Include/cmsis_cv.h +++ /dev/null @@ -1,135 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: cmsis_cv.h - * Purpose: cmsis_cv header - *---------------------------------------------------------------------------- - * Copyright (c) 2017 - 2021 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __CMSIS_CV_H -#define __CMSIS_CV_H - -#include -#include "CV_Config.h" - -/* Expansion macro used to create CMSIS Driver references */ -#define EXPAND_SYMBOL(name, port) name##port -#define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port) - -// Simulator counter -#ifndef HW_PRESENT -extern uint32_t SIM_CYCCNT; -#endif - -// SVC interrupt callback -extern void (*TST_IRQHandler)(void); - -// Test main function -extern void cmsis_cv (void); -extern void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc); - -// Test cases -extern void TC_CoreInstr_NOP (void); -extern void TC_CoreInstr_SEV (void); -extern void TC_CoreInstr_BKPT (void); -extern void TC_CoreInstr_ISB (void); -extern void TC_CoreInstr_DSB (void); -extern void TC_CoreInstr_DMB (void); -extern void TC_CoreInstr_WFI (void); -extern void TC_CoreInstr_WFE (void); -extern void TC_CoreInstr_REV (void); -extern void TC_CoreInstr_REV16 (void); -extern void TC_CoreInstr_REVSH (void); -extern void TC_CoreInstr_ROR (void); -extern void TC_CoreInstr_RBIT (void); -extern void TC_CoreInstr_CLZ (void); -extern void TC_CoreInstr_SSAT (void); -extern void TC_CoreInstr_USAT (void); -extern void TC_CoreInstr_RRX (void); -extern void TC_CoreInstr_LoadStoreExclusive (void); -extern void TC_CoreInstr_LoadStoreUnpriv (void); -extern void TC_CoreInstr_LoadStoreAcquire (void); -extern void TC_CoreInstr_LoadStoreAcquireExclusive (void); -extern void TC_CoreInstr_UnalignedUint16 (void); -extern void TC_CoreInstr_UnalignedUint32 (void); - -extern void TC_CoreSimd_SatAddSub (void); -extern void TC_CoreSimd_ParSat16 (void); -extern void TC_CoreSimd_PackUnpack (void); -extern void TC_CoreSimd_ParSel (void); -extern void TC_CoreSimd_ParAddSub8 (void); -extern void TC_CoreSimd_AbsDif8 (void); -extern void TC_CoreSimd_ParAddSub16 (void); -extern void TC_CoreSimd_ParMul16 (void); -extern void TC_CoreSimd_Pack16 (void); -extern void TC_CoreSimd_MulAcc32 (void); - -#if defined(__CORTEX_M) - extern void TC_CoreFunc_EnDisIRQ (void); - extern void TC_CoreFunc_IRQPrio (void); - extern void TC_CoreFunc_EncDecIRQPrio (void); - extern void TC_CoreFunc_IRQVect (void); - extern void TC_CoreFunc_Control (void); - extern void TC_CoreFunc_IPSR (void); - extern void TC_CoreFunc_APSR (void); - extern void TC_CoreFunc_PSP (void); - extern void TC_CoreFunc_MSP (void); - extern void TC_CoreFunc_PSPLIM (void); - extern void TC_CoreFunc_PSPLIM_NS (void); - extern void TC_CoreFunc_MSPLIM (void); - extern void TC_CoreFunc_MSPLIM_NS (void); - extern void TC_CoreFunc_PRIMASK (void); - extern void TC_CoreFunc_FAULTMASK (void); - extern void TC_CoreFunc_BASEPRI (void); - extern void TC_CoreFunc_FPUType (void); - extern void TC_CoreFunc_FPSCR (void); -#elif defined(__CORTEX_A) - extern void TC_CoreAFunc_IRQ (void); - extern void TC_CoreAFunc_FaultIRQ (void); - extern void TC_CoreAFunc_FPSCR (void); - extern void TC_CoreAFunc_CPSR (void); - extern void TC_CoreAFunc_Mode (void); - extern void TC_CoreAFunc_SP (void); - extern void TC_CoreAFunc_SP_usr (void); - extern void TC_CoreAFunc_FPEXC (void); - extern void TC_CoreAFunc_ACTLR (void); - extern void TC_CoreAFunc_CPACR (void); - extern void TC_CoreAFunc_DFSR (void); - extern void TC_CoreAFunc_IFSR (void); - extern void TC_CoreAFunc_ISR (void); - extern void TC_CoreAFunc_CBAR (void); - extern void TC_CoreAFunc_TTBR0 (void); - extern void TC_CoreAFunc_DACR (void); - extern void TC_CoreAFunc_SCTLR (void); - extern void TC_CoreAFunc_ACTRL (void); - extern void TC_CoreAFunc_MPIDR (void); - extern void TC_CoreAFunc_VBAR (void); - extern void TC_CoreAFunc_MVBAR (void); - extern void TC_CoreAFunc_FPU_Enable (void); -#endif - -#if defined(__CORTEX_M) -extern void TC_MPU_SetClear (void); -extern void TC_MPU_Load (void); -#endif - -#if defined(__CORTEX_A) -extern void TC_GenTimer_CNTFRQ (void); -extern void TC_GenTimer_CNTP_TVAL (void); -extern void TC_GenTimer_CNTP_CTL (void); -extern void TC_GenTimer_CNTPCT(void); -extern void TC_GenTimer_CNTP_CVAL(void); -#endif - -#if defined(__CORTEX_M) -extern void TC_CML1Cache_EnDisableICache(void); -extern void TC_CML1Cache_EnDisableDCache(void); -extern void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void); -#elif defined(__CORTEX_A) -extern void TC_CAL1Cache_EnDisable(void); -extern void TC_CAL1Cache_EnDisableBTAC(void); -extern void TC_CAL1Cache_log2_up(void); -extern void TC_CAL1Cache_InvalidateDCacheAll(void); -extern void TC_CAL1Cache_CleanDCacheAll(void); -extern void TC_CAL1Cache_CleanInvalidateDCacheAll(void); -#endif - -#endif /* __CMSIS_CV_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/LICENSE.txt b/external/CMSIS_5/CMSIS/CoreValidation/LICENSE.txt deleted file mode 100644 index 8dada3e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/LICENSE.txt +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright {yyyy} {name of copyright owner} - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml deleted file mode 100644 index 49fcb6d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml +++ /dev/null @@ -1,14 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: App - # name: CMSIS-Core_Validation (Bootloader) - description: Validation of CMSIS-Core implementation (Bootloader part) - - # packs: - # - pack: ARM::CMSIS - - groups: - - group: Source Files - files: - - file: ./bootloader.c diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c deleted file mode 100644 index eb9b011..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 15. October 2016 - * $Revision: 1.1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Code template for secure main function - * - *---------------------------------------------------------------------------*/ - -#include -#include - -/* Use CMSE intrinsics */ -#include - -#include "RTE_Components.h" -#include CMSIS_device_header - -/* TZ_START_NS: Start address of non-secure application */ -#ifndef TZ_START_NS -#define TZ_START_NS (0x200000U) -#endif - -#if 1 -/* Dummy Non-secure callable (entry) function */ -__attribute__((cmse_nonsecure_entry)) int validationDummy(int x) { - return x; -} -#endif - -/* typedef for non-secure callback functions */ -typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - -/* Secure main() */ -int main(void) { - funcptr_void NonSecure_ResetHandler; - - /* Add user setup code for secure part here*/ - - /* Set non-secure main stack (MSP_NS) */ - __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - - /* Get non-secure reset handler */ - NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - - /* Start non-secure state software application */ - NonSecure_ResetHandler(); - - /* Non-secure software does not return, this code is not executed */ - while (1) { - __NOP(); - } -} - -#if defined(__CORTEX_M) -__NO_RETURN -extern void HardFault_Handler(void); -void HardFault_Handler(void) { - printf("Bootloader HardFault!\n"); - #ifdef __MICROLIB - for(;;) {} - #else - exit(1); - #endif -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/App.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/App.clayer.yml deleted file mode 100644 index e8fece9..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/App.clayer.yml +++ /dev/null @@ -1,48 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: App - # name: CMSIS-Core_Validation - description: Validation of CMSIS-Core implementation - - # packs: - # - pack: ARM::CMSIS - - define: - - PRINT_XML_REPORT: 1 - - add-path: - - ../../../Include - - ../../../Source/ConfigA - - misc: - - for-compiler: AC6 - C-CPP: - - -Wno-declaration-after-statement - - -Wno-covered-switch-default - - for-compiler: GCC - C-CPP: - - -Wno-declaration-after-statement - - -Wno-covered-switch-default - - groups: - - group: Documentation - files: - - file: ../../../README.md - - - group: Source Files - files: - - file: ./main.c - - - group: CMSIS-Core_Validation - files: - - file: ../../../Source/cmsis_cv.c - - file: ../../../Source/CV_CoreAFunc.c - - file: ../../../Source/CV_CoreInstr.c - - file: ../../../Source/CV_CAL1Cache.c -# - file: ../../../Source/ConfigA/mmu.c - - - group: Validation Framework - files: - - file: ../../../Source/CV_Framework.c - - file: ../../../Source/CV_Report.c diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/main.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/main.c deleted file mode 100644 index ce1e0e6..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/main.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include - -#include "RTE_Components.h" -#include CMSIS_device_header - -#ifdef RTE_Compiler_EventRecorder -#include "EventRecorder.h" -#endif - -#include "cmsis_cv.h" -#include "CV_Report.h" - -//lint -e970 allow using int for main - -int main (void) -{ - - // System Initialization - SystemCoreClockUpdate(); - -#ifdef RTE_Compiler_EventRecorder - // Initialize and start Event Recorder - (void)EventRecorderInitialize(EventRecordError, 1U); - (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU); -#endif - - cmsis_cv(); - - #ifdef __MICROLIB - for(;;) {} - #else - exit(0); - #endif -} - -#if defined(__CORTEX_A) -#include "irq_ctrl.h" - -#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ - (defined ( __GNUC__ )) - #define __IRQ __attribute__((interrupt("IRQ"))) -#elif defined ( __CC_ARM ) - #define __IRQ __irq -#elif defined ( __ICCARM__ ) - #define __IRQ __irq __arm -#else - #error "Unsupported compiler!" -#endif - - -__IRQ -void IRQ_Handler(void); -__IRQ -void IRQ_Handler(void) { - const IRQn_ID_t irqn = IRQ_GetActiveIRQ(); - IRQHandler_t const handler = IRQ_GetHandler(irqn); - if (handler != NULL) { - __enable_irq(); - handler(); - __disable_irq(); - } - IRQ_EndOfInterrupt(irqn); -} - -__IRQ __NO_RETURN -void Undef_Handler (void); -__IRQ __NO_RETURN -void Undef_Handler (void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!"); - exit(0); -} - -__IRQ -void SVC_Handler (void); -__IRQ -void SVC_Handler (void) { -} - -__IRQ __NO_RETURN -void PAbt_Handler (void); -__IRQ __NO_RETURN -void PAbt_Handler (void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!"); - exit(0); -} - -__IRQ __NO_RETURN -void DAbt_Handler (void); -__IRQ __NO_RETURN -void DAbt_Handler (void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!"); - exit(0); -} - -__IRQ -void FIQ_Handler (void); -__IRQ -void FIQ_Handler (void) { -} -#endif - -#if defined(__CORTEX_M) -__NO_RETURN -void HardFault_Handler(void); -__NO_RETURN -void HardFault_Handler(void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!"); - #ifdef __MICROLIB - for(;;) {} - #else - exit(0); - #endif -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml deleted file mode 100644 index e722ac5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml +++ /dev/null @@ -1,73 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: App - # name: CMSIS-Core_Validation - description: Validation of CMSIS-Core implementation - - # packs: - # - pack: ARM::CMSIS - - define: - - PRINT_XML_REPORT: 1 - - add-path: - - ../../../Include - - ../../../Source/Config - - misc: - - for-compiler: AC6 - C-CPP: - - -Wno-declaration-after-statement - - -Wno-covered-switch-default - - for-compiler: GCC - C-CPP: - - -Wno-declaration-after-statement - - -Wno-covered-switch-default - - groups: - - group: Documentation - files: - - file: ../../../README.md - - - group: Source Files - files: - - file: ./main.c - - - group: CMSIS-Core_Validation - files: - - file: ../../../Source/cmsis_cv.c - - file: ../../../Source/CV_CoreFunc.c - - file: ../../../Source/CV_CoreInstr.c - - file: ../../../Source/CV_CoreSimd.c - - file: ../../../Source/CV_CML1Cache.c - - file: ../../../Source/CV_MPU_ARMv7.c - for-context: - - +CM0 - - +CM0plus - - +CM3 - - +CM4 - - +CM4FP - - +CM7 - - +CM7SP - - +CM7DP - - file: ../../../Source/CV_MPU_ARMv8.c - for-context: - - +CM23 - - +CM23S - - +CM23NS - - +CM33 - - +CM33S - - +CM33NS - - +CM35P - - +CM35PS - - +CM35PNS - - +CM55S - - +CM55NS - - +CM85S - - +CM85NS - - - group: Validation Framework - files: - - file: ../../../Source/CV_Framework.c - - file: ../../../Source/CV_Report.c diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/main.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/main.c deleted file mode 100644 index 0d927ab..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/main.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include - -#include "RTE_Components.h" -#include CMSIS_device_header - -#ifdef RTE_Compiler_EventRecorder -#include "EventRecorder.h" -#endif - -#include "cmsis_cv.h" -#include "CV_Report.h" - -//lint -e970 allow using int for main - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include - - /* Dummy Non-secure callable (entry) function */ - __attribute__((cmse_nonsecure_entry)) int validationDummy(int x) { - return x; - } -#endif - -int main (void) -{ - - // System Initialization - SystemCoreClockUpdate(); - -#ifdef RTE_Compiler_EventRecorder - // Initialize and start Event Recorder - (void)EventRecorderInitialize(EventRecordError, 1U); - (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU); -#endif - - cmsis_cv(); - - #ifdef __MICROLIB - for(;;) {} - #else - exit(0); - #endif -} - -#if defined(__CORTEX_A) -#include "irq_ctrl.h" - -#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ - (defined ( __GNUC__ )) - #define __IRQ __attribute__((interrupt("IRQ"))) -#elif defined ( __CC_ARM ) - #define __IRQ __irq -#elif defined ( __ICCARM__ ) - #define __IRQ __irq __arm -#else - #error "Unsupported compiler!" -#endif - - -__IRQ -void IRQ_Handler(void); -__IRQ -void IRQ_Handler(void) { - const IRQn_ID_t irqn = IRQ_GetActiveIRQ(); - IRQHandler_t const handler = IRQ_GetHandler(irqn); - if (handler != NULL) { - __enable_irq(); - handler(); - __disable_irq(); - } - IRQ_EndOfInterrupt(irqn); -} - -__IRQ __NO_RETURN -void Undef_Handler (void); -__IRQ __NO_RETURN -void Undef_Handler (void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!"); - exit(0); -} - -__IRQ -void SVC_Handler (void); -__IRQ -void SVC_Handler (void) { -} - -__IRQ __NO_RETURN -void PAbt_Handler (void); -__IRQ __NO_RETURN -void PAbt_Handler (void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!"); - exit(0); -} - -__IRQ __NO_RETURN -void DAbt_Handler (void); -__IRQ __NO_RETURN -void DAbt_Handler (void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!"); - exit(0); -} - -__IRQ -void FIQ_Handler (void); -__IRQ -void FIQ_Handler (void) { -} -#endif - -#if defined(__CORTEX_M) -__NO_RETURN -void HardFault_Handler(void); -__NO_RETURN -void HardFault_Handler(void) { - cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!"); - #ifdef __MICROLIB - for(;;) {} - #else - exit(0); - #endif -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0 deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0 +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld deleted file mode 100644 index 8811727..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld +++ /dev/null @@ -1,181 +0,0 @@ -#include "mem_ARMCA5.h" - -MEMORY -{ - ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - - Image$$VECTORS$$Base = .; - * (RESET) - KEEP(*(.isr_vector)) - Image$$VECTORS$$Limit = .; - - *(SVC_TABLE) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - Image$$RO_DATA$$Base = .; - *(.rodata*) - Image$$RO_DATA$$Limit = .; - - KEEP(*(.eh_frame*)) - } > ROM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - __copy_table_end__ = .; - } > ROM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > ROM - - __etext = .; - - .ttb : - { - Image$$TTB$$ZI$$Base = .; - . += __TTB_SIZE; - Image$$TTB$$ZI$$Limit = .; - } > L_TTB - - .data : - { - Image$$RW_DATA$$Base = .; - __data_start__ = .; - *(vtable) - *(.data*) - Image$$RW_DATA$$Limit = .; - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - - .bss ALIGN(0x400): - { - Image$$ZI_DATA$$Base = .; - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; - __end__ = .; - end = __end__; - } > RAM AT > RAM - -#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) - .heap (NOLOAD): - { - . = ALIGN(8); - Image$$HEAP$$ZI$$Base = .; - . += __HEAP_SIZE; - Image$$HEAP$$ZI$$Limit = .; - __HeapLimit = .; - } > RAM -#endif - - .stack (NOLOAD): - { - . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; - . = ALIGN(8); - - __StackTop = .; - Image$$SYS_STACK$$ZI$$Base = .; - . += __STACK_SIZE; - Image$$SYS_STACK$$ZI$$Limit = .; - __stack = .; - - Image$$FIQ_STACK$$ZI$$Base = .; - . += __FIQ_STACK_SIZE; - Image$$FIQ_STACK$$ZI$$Limit = .; - - Image$$IRQ_STACK$$ZI$$Base = .; - . += __IRQ_STACK_SIZE; - Image$$IRQ_STACK$$ZI$$Limit = .; - - Image$$SVC_STACK$$ZI$$Base = .; - . += __SVC_STACK_SIZE; - Image$$SVC_STACK$$ZI$$Limit = .; - - Image$$ABT_STACK$$ZI$$Base = .; - . += __ABT_STACK_SIZE; - Image$$ABT_STACK$$ZI$$Limit = .; - - Image$$UND_STACK$$ZI$$Base = .; - . += __UND_STACK_SIZE; - Image$$UND_STACK$$ZI$$Limit = .; - - } > RAM -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.sct deleted file mode 100644 index 41e562c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA5.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mem_ARMCA5.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mem_ARMCA5.h deleted file mode 100644 index 9fe85c0..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mem_ARMCA5.h +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************//** - * @file mem_ARMCA5.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_ARMCA5_H -#define __MEM_ARMCA5_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// ROM Base Address <0x0-0xFFFFFFFF:0x100000> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x80000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- RAM Configuration ----------------------------------- -// RAM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// RAM Base Address <0x0-0xFFFFFFFF:0x100000> -// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// Data Sections -// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Exceptional Modes -// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// -// - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x80200000 -#define __RAM_SIZE 0x00200000 - -#define __RW_DATA_SIZE 0x00100000 -#define __ZI_DATA_SIZE 0x000F0000 - -#define __STACK_SIZE 0x00001000 -#define __HEAP_SIZE 0x00008000 - -#define __UND_STACK_SIZE 0x00000100 -#define __ABT_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned -// The TLB L2 entries are placed after the L1 in the MMU config -// TTB Base Address <0x0-0xFFFFFFFF:0x4000> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x80500000 -#define __TTB_SIZE 0x00005000 - -#endif /* __MEM_ARMCA5_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c deleted file mode 100644 index 58a9480..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************//** - * @file mmu_ARMCA5.c - * @brief MMU Configuration for ARM Cortex-A5 Device Series - * @version V1.2.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map - - Memory Type -0xffffffff |--------------------------| ------------ - | FLAG SYNC | Device Memory -0xfffff000 |--------------------------| ------------ - | Fault | Fault -0xfff00000 |--------------------------| ------------ - | | Normal - | | - | Daughterboard | - | memory | - | | -0x80505000 |--------------------------| ------------ - |TTB (L2 Sync Flags ) 4k | Normal -0x80504C00 |--------------------------| ------------ - |TTB (L2 Peripherals-B) 16k| Normal -0x80504800 |--------------------------| ------------ - |TTB (L2 Peripherals-A) 16k| Normal -0x80504400 |--------------------------| ------------ - |TTB (L2 Priv Periphs) 4k | Normal -0x80504000 |--------------------------| ------------ - | TTB (L1 Descriptors) | Normal -0x80500000 |--------------------------| ------------ - | Stack | Normal - |--------------------------| ------------ - | Heap | Normal -0x80400000 |--------------------------| ------------ - | ZI Data | Normal -0x80300000 |--------------------------| ------------ - | RW Data | Normal -0x80200000 |--------------------------| ------------ - | RO Data | Normal - |--------------------------| ------------ - | RO Code | USH Normal -0x80000000 |--------------------------| ------------ - | Daughterboard | Fault - | HSB AXI buses | -0x40000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x2c002000 |--------------------------| ------------ - | Private Address | Device Memory -0x2c000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x20000000 |--------------------------| ------------ - | Peripherals | Device Memory RW/RO - | | & Fault -0x00000000 |--------------------------| -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors should place all memory in domain 0 - -#include "ARMCA5.h" -#include "mem_ARMCA5.h" - -// TTB base address -#define TTB_BASE ((uint32_t*)__TTB_BASE) - -// L2 table pointers -//---------------------------------------- -#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core - // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. - // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. - -#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space -#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF -#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF -#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization - -//--------------------- PERIPHERALS ------------------- -#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) -#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) - -//--------------------- SYNC FLAGS -------------------- -#define FLAG_SYNC 0xFFFFF000 -#define F_SYNC_BASE 0xFFF00000 //1M aligned - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; - - //Create 4GB of faulting entries - MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); - - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Define Image - MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections - MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections - - //--------------------- PERIPHERALS ------------------- - MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW); - MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE , 16, Sect_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory - MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define private address space entry. - MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - // Define L2CC entry. Uncomment if PL310 is present - // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) - MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define synchronization space entry. - MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x1 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x01 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x0 (Inner WB WA) */ - __set_TTBR0(__TTB_BASE | 0x48); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c deleted file mode 100644 index 55c6029..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" -#elif defined ( __GNUC__ ) - "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" -#else - #error Unknown compiler. -#endif - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - "BL __main \n" -#elif defined ( __GNUC__ ) - "BL _start \n" -#else - #error Unknown compiler. -#endif - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1 deleted file mode 100644 index 1bdd541..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1 +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL __main \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s deleted file mode 100644 index 85babb9..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.s - * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA5 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(4) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0 deleted file mode 100644 index 85babb9..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0 +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.s - * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA5 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(4) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c deleted file mode 100644 index 5f599f6..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1 deleted file mode 100644 index 5f599f6..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1 +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h deleted file mode 100644 index 6a2a6da..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA5.h - * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA5_H -#define __SYSTEM_ARMCA5_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA5_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0 deleted file mode 100644 index 6a2a6da..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0 +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA5.h - * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA5_H -#define __SYSTEM_ARMCA5_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA5_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml deleted file mode 100644 index 354560a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml +++ /dev/null @@ -1,23 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup - - component: Device:IRQ Controller:GIC - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/model_config.txt deleted file mode 100644 index 7d9b5be..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/model_config.txt +++ /dev/null @@ -1,21 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cluster.cpu0.ase-present=0 # (bool , init-time) default = '1' : Set whether model has NEON support -cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false -cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true -cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] -cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] -cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] -cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] -cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation -cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0 deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0 +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.ld deleted file mode 100644 index 44ef88f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.ld +++ /dev/null @@ -1,181 +0,0 @@ -#include "mem_ARMCA7.h" - -MEMORY -{ - ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - - Image$$VECTORS$$Base = .; - * (RESET) - KEEP(*(.isr_vector)) - Image$$VECTORS$$Limit = .; - - *(SVC_TABLE) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - Image$$RO_DATA$$Base = .; - *(.rodata*) - Image$$RO_DATA$$Limit = .; - - KEEP(*(.eh_frame*)) - } > ROM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - __copy_table_end__ = .; - } > ROM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > ROM - - __etext = .; - - .ttb : - { - Image$$TTB$$ZI$$Base = .; - . += __TTB_SIZE; - Image$$TTB$$ZI$$Limit = .; - } > L_TTB - - .data : - { - Image$$RW_DATA$$Base = .; - __data_start__ = .; - *(vtable) - *(.data*) - Image$$RW_DATA$$Limit = .; - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - - .bss ALIGN(0x400): - { - Image$$ZI_DATA$$Base = .; - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; - __end__ = .; - end = __end__; - } > RAM AT > RAM - -#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) - .heap (NOLOAD): - { - . = ALIGN(8); - Image$$HEAP$$ZI$$Base = .; - . += __HEAP_SIZE; - Image$$HEAP$$ZI$$Limit = .; - __HeapLimit = .; - } > RAM -#endif - - .stack (NOLOAD): - { - . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; - . = ALIGN(8); - - __StackTop = .; - Image$$SYS_STACK$$ZI$$Base = .; - . += __STACK_SIZE; - Image$$SYS_STACK$$ZI$$Limit = .; - __stack = .; - - Image$$FIQ_STACK$$ZI$$Base = .; - . += __FIQ_STACK_SIZE; - Image$$FIQ_STACK$$ZI$$Limit = .; - - Image$$IRQ_STACK$$ZI$$Base = .; - . += __IRQ_STACK_SIZE; - Image$$IRQ_STACK$$ZI$$Limit = .; - - Image$$SVC_STACK$$ZI$$Base = .; - . += __SVC_STACK_SIZE; - Image$$SVC_STACK$$ZI$$Limit = .; - - Image$$ABT_STACK$$ZI$$Base = .; - . += __ABT_STACK_SIZE; - Image$$ABT_STACK$$ZI$$Limit = .; - - Image$$UND_STACK$$ZI$$Base = .; - . += __UND_STACK_SIZE; - Image$$UND_STACK$$ZI$$Limit = .; - - } > RAM -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.sct deleted file mode 100644 index d8f3716..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA7.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mem_ARMCA7.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mem_ARMCA7.h deleted file mode 100644 index 9590595..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mem_ARMCA7.h +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************//** - * @file mem_ARMCA7.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_ARMCA7_H -#define __MEM_ARMCA7_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// ROM Base Address <0x0-0xFFFFFFFF:0x100000> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x80000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- RAM Configuration ----------------------------------- -// RAM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// RAM Base Address <0x0-0xFFFFFFFF:0x100000> -// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// Data Sections -// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Exceptional Modes -// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// -// - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x80200000 -#define __RAM_SIZE 0x00200000 - -#define __RW_DATA_SIZE 0x00100000 -#define __ZI_DATA_SIZE 0x000F0000 - -#define __STACK_SIZE 0x00001000 -#define __HEAP_SIZE 0x00008000 - -#define __UND_STACK_SIZE 0x00000100 -#define __ABT_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned -// The TLB L2 entries are placed after the L1 in the MMU config -// TTB Base Address <0x0-0xFFFFFFFF:0x4000> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x80500000 -#define __TTB_SIZE 0x00005000 - -#endif /* __MEM_ARMCA7_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c deleted file mode 100644 index 26431f3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************//** - * @file mmu_ARMCA7.c - * @brief MMU Configuration for Arm Cortex-A7 Device Series - * @version V1.2.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map - - Memory Type -0xffffffff |--------------------------| ------------ - | FLAG SYNC | Device Memory -0xfffff000 |--------------------------| ------------ - | Fault | Fault -0xfff00000 |--------------------------| ------------ - | | Normal - | | - | Daughterboard | - | memory | - | | -0x80505000 |--------------------------| ------------ - |TTB (L2 Sync Flags ) 4k | Normal -0x80504C00 |--------------------------| ------------ - |TTB (L2 Peripherals-B) 16k| Normal -0x80504800 |--------------------------| ------------ - |TTB (L2 Peripherals-A) 16k| Normal -0x80504400 |--------------------------| ------------ - |TTB (L2 Priv Periphs) 4k | Normal -0x80504000 |--------------------------| ------------ - | TTB (L1 Descriptors) | Normal -0x80500000 |--------------------------| ------------ - | Stack | Normal - |--------------------------| ------------ - | Heap | Normal -0x80400000 |--------------------------| ------------ - | ZI Data | Normal -0x80300000 |--------------------------| ------------ - | RW Data | Normal -0x80200000 |--------------------------| ------------ - | RO Data | Normal - |--------------------------| ------------ - | RO Code | USH Normal -0x80000000 |--------------------------| ------------ - | Daughterboard | Fault - | HSB AXI buses | -0x40000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x2c002000 |--------------------------| ------------ - | Private Address | Device Memory -0x2c000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x20000000 |--------------------------| ------------ - | Peripherals | Device Memory RW/RO - | | & Fault -0x00000000 |--------------------------| -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors should place all memory in domain 0 - -#include "ARMCA7.h" -#include "mem_ARMCA7.h" - -// TTB base address -#define TTB_BASE ((uint32_t*)__TTB_BASE) - -// L2 table pointers -//---------------------------------------- -#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core - // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. - // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. - -#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space -#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF -#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF -#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization - -//--------------------- PERIPHERALS ------------------- -#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) -#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) - -//--------------------- SYNC FLAGS -------------------- -#define FLAG_SYNC 0xFFFFF000 -#define F_SYNC_BASE 0xFFF00000 //1M aligned - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; - - //Create 4GB of faulting entries - MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); - - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Define Image - MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections - MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections - - //--------------------- PERIPHERALS ------------------- - MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW); - MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE , 16, Sect_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory - MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define private address space entry. - MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - // Define L2CC entry. Uncomment if PL310 is present - // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) - MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define synchronization space entry. - MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x1 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x01 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x0 (Inner WB WA) */ - __set_TTBR0(__TTB_BASE | 0x48); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c deleted file mode 100644 index 7847189..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" -#elif defined ( __GNUC__ ) - "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" -#else - #error Unknown compiler. -#endif - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - "BL __main \n" -#elif defined ( __GNUC__ ) - "BL _start \n" -#else - #error Unknown compiler. -#endif - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1 deleted file mode 100644 index da8ae87..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1 +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL __main \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s deleted file mode 100644 index 6872e9e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.s - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA7 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(4) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0 deleted file mode 100644 index 6872e9e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0 +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.s - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA7 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(4) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c deleted file mode 100644 index 803ec49..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1 deleted file mode 100644 index 803ec49..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1 +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h deleted file mode 100644 index 0405aa3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA7.h - * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA7_H -#define __SYSTEM_ARMCA7_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA7_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0 deleted file mode 100644 index 0405aa3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0 +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA7.h - * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA7_H -#define __SYSTEM_ARMCA7_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA7_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml deleted file mode 100644 index 354560a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml +++ /dev/null @@ -1,23 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup - - component: Device:IRQ Controller:GIC - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/model_config.txt deleted file mode 100644 index 963ac52..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/model_config.txt +++ /dev/null @@ -1,22 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with VFP support -cluster.cpu0.ase-present=0 # (bool , init-time) default = '1' : Set whether CT model has been built with NEON support -cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false -cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true -cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] -cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] -cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] -cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] -cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cluster.l1_icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 I-cache has stateful implementation -cluster.l1_dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 D-cache has stateful implementation -cluster.l2_cache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L2 cache has stateful implementation -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0 deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0 +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.ld deleted file mode 100644 index 60b5b10..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.ld +++ /dev/null @@ -1,181 +0,0 @@ -#include "mem_ARMCA9.h" - -MEMORY -{ - ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - - Image$$VECTORS$$Base = .; - * (RESET) - KEEP(*(.isr_vector)) - Image$$VECTORS$$Limit = .; - - *(SVC_TABLE) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - Image$$RO_DATA$$Base = .; - *(.rodata*) - Image$$RO_DATA$$Limit = .; - - KEEP(*(.eh_frame*)) - } > ROM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - __copy_table_end__ = .; - } > ROM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > ROM - - __etext = .; - - .ttb : - { - Image$$TTB$$ZI$$Base = .; - . += __TTB_SIZE; - Image$$TTB$$ZI$$Limit = .; - } > L_TTB - - .data : - { - Image$$RW_DATA$$Base = .; - __data_start__ = .; - *(vtable) - *(.data*) - Image$$RW_DATA$$Limit = .; - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - - .bss ALIGN(0x400): - { - Image$$ZI_DATA$$Base = .; - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; - __end__ = .; - end = __end__; - } > RAM AT > RAM - -#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) - .heap (NOLOAD): - { - . = ALIGN(8); - Image$$HEAP$$ZI$$Base = .; - . += __HEAP_SIZE; - Image$$HEAP$$ZI$$Limit = .; - __HeapLimit = .; - } > RAM -#endif - - .stack (NOLOAD): - { - . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; - . = ALIGN(8); - - __StackTop = .; - Image$$SYS_STACK$$ZI$$Base = .; - . += __STACK_SIZE; - Image$$SYS_STACK$$ZI$$Limit = .; - __stack = .; - - Image$$FIQ_STACK$$ZI$$Base = .; - . += __FIQ_STACK_SIZE; - Image$$FIQ_STACK$$ZI$$Limit = .; - - Image$$IRQ_STACK$$ZI$$Base = .; - . += __IRQ_STACK_SIZE; - Image$$IRQ_STACK$$ZI$$Limit = .; - - Image$$SVC_STACK$$ZI$$Base = .; - . += __SVC_STACK_SIZE; - Image$$SVC_STACK$$ZI$$Limit = .; - - Image$$ABT_STACK$$ZI$$Base = .; - . += __ABT_STACK_SIZE; - Image$$ABT_STACK$$ZI$$Limit = .; - - Image$$UND_STACK$$ZI$$Base = .; - . += __UND_STACK_SIZE; - Image$$UND_STACK$$ZI$$Limit = .; - - } > RAM -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.sct deleted file mode 100644 index 3316f93..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA9.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mem_ARMCA9.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mem_ARMCA9.h deleted file mode 100644 index 3609d7f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mem_ARMCA9.h +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************//** - * @file mem_ARMCA9.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_ARMCA9_H -#define __MEM_ARMCA9_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// ROM Base Address <0x0-0xFFFFFFFF:0x100000> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x80000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- RAM Configuration ----------------------------------- -// RAM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// RAM Base Address <0x0-0xFFFFFFFF:0x100000> -// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// Data Sections -// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Exceptional Modes -// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// -// - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x80200000 -#define __RAM_SIZE 0x00200000 - -#define __RW_DATA_SIZE 0x00100000 -#define __ZI_DATA_SIZE 0x000F0000 - -#define __STACK_SIZE 0x00001000 -#define __HEAP_SIZE 0x00008000 - -#define __UND_STACK_SIZE 0x00000100 -#define __ABT_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned -// The TLB L2 entries are placed after the L1 in the MMU config -// TTB Base Address <0x0-0xFFFFFFFF:0x4000> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x80500000 -#define __TTB_SIZE 0x00005000 - -#endif /* __MEM_ARMCA9_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c deleted file mode 100644 index 1435eb9..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************//** - * @file mmu_ARMCA9.c - * @brief MMU Configuration for Arm Cortex-A9 Device Series - * @version V1.2.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map - - Memory Type -0xffffffff |--------------------------| ------------ - | FLAG SYNC | Device Memory -0xfffff000 |--------------------------| ------------ - | Fault | Fault -0xfff00000 |--------------------------| ------------ - | | Normal - | | - | Daughterboard | - | memory | - | | -0x80505000 |--------------------------| ------------ - |TTB (L2 Sync Flags ) 4k | Normal -0x80504C00 |--------------------------| ------------ - |TTB (L2 Peripherals-B) 16k| Normal -0x80504800 |--------------------------| ------------ - |TTB (L2 Peripherals-A) 16k| Normal -0x80504400 |--------------------------| ------------ - |TTB (L2 Priv Periphs) 4k | Normal -0x80504000 |--------------------------| ------------ - | TTB (L1 Descriptors) | Normal -0x80500000 |--------------------------| ------------ - | Stack | Normal - |--------------------------| ------------ - | Heap | Normal -0x80400000 |--------------------------| ------------ - | ZI Data | Normal -0x80300000 |--------------------------| ------------ - | RW Data | Normal -0x80200000 |--------------------------| ------------ - | RO Data | Normal - |--------------------------| ------------ - | RO Code | USH Normal -0x80000000 |--------------------------| ------------ - | Daughterboard | Fault - | HSB AXI buses | -0x40000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x2c002000 |--------------------------| ------------ - | Private Address | Device Memory -0x2c000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x20000000 |--------------------------| ------------ - | Peripherals | Device Memory RW/RO - | | & Fault -0x00000000 |--------------------------| -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors should place all memory in domain 0 - -#include "ARMCA9.h" -#include "mem_ARMCA9.h" - -// TTB base address -#define TTB_BASE ((uint32_t*)__TTB_BASE) - -// L2 table pointers -//---------------------------------------- -#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core - // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. - // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. - -#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space -#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF -#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF -#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization - -//--------------------- PERIPHERALS ------------------- -#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) -#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) - -//--------------------- SYNC FLAGS -------------------- -#define FLAG_SYNC 0xFFFFF000 -#define F_SYNC_BASE 0xFFF00000 //1M aligned - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; - - //Create 4GB of faulting entries - MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); - - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Define Image - MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections - MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections - - //--------------------- PERIPHERALS ------------------- - MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW); - MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE , 16, Sect_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory - MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define private address space entry. - MMU_TTPage4k (TTB_BASE, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - // Define L2CC entry. Uncomment if PL310 is present - // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) - MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define synchronization space entry. - MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x1 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x01 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x0 (Inner WB WA) */ - __set_TTBR0(__TTB_BASE | 0x48); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.c deleted file mode 100644 index 6278f11..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.c +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.c - * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" -#elif defined ( __GNUC__ ) - "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" -#else - #error Unknown compiler. -#endif - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - "BL __main \n" -#elif defined ( __GNUC__ ) - "BL _start \n" -#else - #error Unknown compiler. -#endif - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s deleted file mode 100644 index 5db9773..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.s - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA9 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(2) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0 deleted file mode 100644 index 5db9773..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0 +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.s - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA9 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(2) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.c deleted file mode 100644 index cdf9213..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.c +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA9.c - * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h deleted file mode 100644 index b60ce5a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA9.h - * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA9_H -#define __SYSTEM_ARMCA9_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA9_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0 deleted file mode 100644 index b60ce5a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0 +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA9.h - * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA9_H -#define __SYSTEM_ARMCA9_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA9_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml deleted file mode 100644 index 354560a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml +++ /dev/null @@ -1,23 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup - - component: Device:IRQ Controller:GIC - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/model_config.txt deleted file mode 100644 index 1c99c27..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/model_config.txt +++ /dev/null @@ -1,21 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cluster.cpu0.ase-present=0 # (bool , init-time) default = '1' : Set whether model has NEON support -cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false -cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true -cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] -cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] -cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] -cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] -cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation -cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct deleted file mode 100644 index 5300b01..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c deleted file mode 100644 index fb32110..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c +++ /dev/null @@ -1,146 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM0.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM0) - #include "ARMCM0.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 deleted file mode 100644 index fb32110..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 +++ /dev/null @@ -1,146 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM0.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM0) - #include "ARMCM0.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c deleted file mode 100644 index bf724ae..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM0.c - * @brief CMSIS Device System Source File for - * ARMCM0 Device - * @version V1.0.0 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM0.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd deleted file mode 100644 index 391dda4..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/model_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/model_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct deleted file mode 100644 index 0f499b2..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c deleted file mode 100644 index 76d1fa8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM0plus.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM0P) - #include "ARMCM0plus.h" -#elif defined (ARMCM0P_MPU) - #include "ARMCM0plus_MPU.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3 deleted file mode 100644 index 76d1fa8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3 +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM0plus.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM0P) - #include "ARMCM0plus.h" -#elif defined (ARMCM0P_MPU) - #include "ARMCM0plus_MPU.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c deleted file mode 100644 index 62658d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM0plus.c - * @brief CMSIS Device System Source File for - * ARMCM0plus Device - * @version V1.0.1 - * @date 05. September 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM0plus.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd deleted file mode 100644 index 391dda4..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/model_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/model_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct deleted file mode 100644 index d2a3815..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/gcc_arm.ld deleted file mode 100644 index 9886379..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option --section-start or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0 deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0 +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c deleted file mode 100644 index 3381c1f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM23.c - * @brief CMSIS Device System Source File for - * ARMCM23 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM23.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/model_config.txt deleted file mode 100644 index 4936cd3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/model_config.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct deleted file mode 100644 index 5646e84..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00200000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20200000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/gcc_arm.ld deleted file mode 100644 index 6945b28..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00200000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20200000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option --section-start or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/system_ARMCM23.c deleted file mode 100644 index 3381c1f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/system_ARMCM23.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM23.c - * @brief CMSIS Device System Source File for - * ARMCM23 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM23.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/model_config.txt deleted file mode 100644 index c4f4818..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/model_config.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct deleted file mode 100644 index c3f2cb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/gcc_arm.ld deleted file mode 100644 index b70792f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option --section-start or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h deleted file mode 100644 index a7a090e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h +++ /dev/null @@ -1,832 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM23.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 - * @version V5.3.1 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM23_H -#define PARTITION_ARMCM23_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - - -/* -// Setup behaviour of single SysTick -*/ -#define SCB_ICSR_INIT 0 - -/* -// in a single SysTick implementation, SysTick is -// <0=>Secure -// <1=>Non-Secure -// Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation -*/ -#define SCB_ICSR_STTNS_VAL 0 - -/* -// -*/ - - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) - SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | - ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); - #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM23_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/system_ARMCM23.c deleted file mode 100644 index 3381c1f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/system_ARMCM23.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM23.c - * @brief CMSIS Device System Source File for - * ARMCM23 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM23.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/model_config.txt deleted file mode 100644 index c4f4818..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/model_config.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct deleted file mode 100644 index c3f2cb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/gcc_arm.ld deleted file mode 100644 index b70792f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option --section-start or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h deleted file mode 100644 index d3402da..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h +++ /dev/null @@ -1,832 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM23.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 - * @version V5.3.1 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM23_H -#define PARTITION_ARMCM23_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - - -/* -// Setup behaviour of single SysTick -*/ -#define SCB_ICSR_INIT 0 - -/* -// in a single SysTick implementation, SysTick is -// <0=>Secure -// <1=>Non-Secure -// Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation -*/ -#define SCB_ICSR_STTNS_VAL 0 - -/* -// -*/ - - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x0000122B - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) - SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | - ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); - #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM23_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/system_ARMCM23.c deleted file mode 100644 index 3381c1f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/system_ARMCM23.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM23.c - * @brief CMSIS Device System Source File for - * ARMCM23 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM23.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/model_config.txt deleted file mode 100644 index c4f4818..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/model_config.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct deleted file mode 100644 index 4309a0b..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0 deleted file mode 100644 index dda75e3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0 +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c deleted file mode 100644 index b541573..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM3.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM3) - #include "ARMCM3.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3 deleted file mode 100644 index b541573..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3 +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM3.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM3) - #include "ARMCM3.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c deleted file mode 100644 index 3c5eda7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM3.c - * @brief CMSIS Device System Source File for - * ARMCM3 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1 deleted file mode 100644 index 3c5eda7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1 +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM3.c - * @brief CMSIS Device System Source File for - * ARMCM3 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd deleted file mode 100644 index 391dda4..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/model_config.txt deleted file mode 100644 index 5b61c6e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/model_config.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -armcortexm3ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -armcortexm3ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -armcortexm3ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -armcortexm3ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -armcortexm3ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -armcortexm3ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -armcortexm3ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -armcortexm3ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct deleted file mode 100644 index a62975f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0 deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/system_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/system_ARMCM33.c deleted file mode 100644 index 919b8bd..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/system_ARMCM33.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM33.c - * @brief CMSIS Device System Source File for - * ARMCM33 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/tiac_arm.cmd b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/tiac_arm.cmd deleted file mode 100644 index 391dda4..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/model_config.txt deleted file mode 100644 index 271fd6c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct deleted file mode 100644 index 94b99d5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00200000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20200000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld deleted file mode 100644 index 6058784..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00200000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20200000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c deleted file mode 100644 index 919b8bd..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM33.c - * @brief CMSIS Device System Source File for - * ARMCM33 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/model_config.txt deleted file mode 100644 index 656fbb5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct deleted file mode 100644 index ea28bfc..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld deleted file mode 100644 index f44186e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h deleted file mode 100644 index a7cb0d7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM33.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 - * @version V1.1.1 - * @date 12. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM33_H -#define PARTITION_ARMCM33_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM33_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c deleted file mode 100644 index 919b8bd..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM33.c - * @brief CMSIS Device System Source File for - * ARMCM33 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/model_config.txt deleted file mode 100644 index 656fbb5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct deleted file mode 100644 index ea28bfc..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld deleted file mode 100644 index f44186e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h deleted file mode 100644 index 2c09a0c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM33.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 - * @version V1.1.1 - * @date 12. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM33_H -#define PARTITION_ARMCM33_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x0000122B - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM33_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c deleted file mode 100644 index 919b8bd..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM33.c - * @brief CMSIS Device System Source File for - * ARMCM33 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/model_config.txt deleted file mode 100644 index 656fbb5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct deleted file mode 100644 index d06959f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0 deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/system_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/system_ARMCM35P.c deleted file mode 100644 index 2ccc84b..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/system_ARMCM35P.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM35P.c - * @brief CMSIS Device System Source File for - * ARMCM35P Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/model_config.txt deleted file mode 100644 index 271fd6c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct deleted file mode 100644 index 50bfe06..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00200000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20200000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld deleted file mode 100644 index 6058784..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00200000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20200000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c deleted file mode 100644 index 2ccc84b..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM35P.c - * @brief CMSIS Device System Source File for - * ARMCM35P Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/model_config.txt deleted file mode 100644 index 656fbb5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct deleted file mode 100644 index 96395c9..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld deleted file mode 100644 index f44186e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h deleted file mode 100644 index 299dd18..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM35P.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P - * @version V1.0.0 - * @date 03. September 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM35P_H -#define PARTITION_ARMCM35P_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM35P_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c deleted file mode 100644 index 2ccc84b..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM35P.c - * @brief CMSIS Device System Source File for - * ARMCM35P Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/model_config.txt deleted file mode 100644 index 656fbb5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct deleted file mode 100644 index 96395c9..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld deleted file mode 100644 index f44186e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h deleted file mode 100644 index 85d63e6..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM35P.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P - * @version V1.0.0 - * @date 03. September 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM35P_H -#define PARTITION_ARMCM35P_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x0000122B - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM35P_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c deleted file mode 100644 index 2ccc84b..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM35P.c - * @brief CMSIS Device System Source File for - * ARMCM35P Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/model_config.txt deleted file mode 100644 index 656fbb5..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/model_config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct deleted file mode 100644 index eb67b5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c deleted file mode 100644 index 2d7ca21..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c +++ /dev/null @@ -1,152 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM4.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3 deleted file mode 100644 index 2d7ca21..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3 +++ /dev/null @@ -1,152 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM4.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c deleted file mode 100644 index 9d983d2..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM4.c - * @brief CMSIS Device System Source File for - * ARMCM4 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd deleted file mode 100644 index 391dda4..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/model_config.txt deleted file mode 100644 index 8c69b9c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/model_config.txt +++ /dev/null @@ -1,14 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support -armcortexm4ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -armcortexm4ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -armcortexm4ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -armcortexm4ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct deleted file mode 100644 index eb67b5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c deleted file mode 100644 index 2d7ca21..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c +++ /dev/null @@ -1,152 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM4.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3 deleted file mode 100644 index 2d7ca21..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3 +++ /dev/null @@ -1,152 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM4.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/system_ARMCM4.c deleted file mode 100644 index 9d983d2..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/system_ARMCM4.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM4.c - * @brief CMSIS Device System Source File for - * ARMCM4 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/tiac_arm.cmd b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/tiac_arm.cmd deleted file mode 100644 index 391dda4..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/model_config.txt deleted file mode 100644 index 34dc907..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/model_config.txt +++ /dev/null @@ -1,14 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -armcortexm4ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -armcortexm4ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -armcortexm4ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -armcortexm4ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-heap_limit=0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-stack_base=0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-stack_limit=0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -armcortexm4ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct deleted file mode 100644 index d9e8ee1..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00200000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20200000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 deleted file mode 100644 index 970df5c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/gcc_arm.ld deleted file mode 100644 index 6058784..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00200000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20200000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c deleted file mode 100644 index 0557c5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM55.c - * @brief CMSIS-Core Device Startup File for Cortex-M55 Device - * @version V1.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 deleted file mode 100644 index 0557c5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM55.c - * @brief CMSIS-Core Device Startup File for Cortex-M55 Device - * @version V1.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c deleted file mode 100644 index d66624d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.c - * @brief CMSIS Device System Source File for - * ARMCM55 Device - * @version V1.1.0 - * @date 28. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM55.h" - #endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set low-power state for PDEPU */ - /* 0b00 | ON, PDEPU is not in low-power state */ - /* 0b01 | ON, but the clock is off */ - /* 0b10 | RET(ention) */ - /* 0b11 | OFF */ - - /* Clear ELPSTATE, value is 0b11 on Cold reset */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 deleted file mode 100644 index d66624d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.c - * @brief CMSIS Device System Source File for - * ARMCM55 Device - * @version V1.1.0 - * @date 28. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM55.h" - #endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set low-power state for PDEPU */ - /* 0b00 | ON, PDEPU is not in low-power state */ - /* 0b01 | ON, but the clock is off */ - /* 0b10 | RET(ention) */ - /* 0b11 | OFF */ - - /* Clear ELPSTATE, value is 0b11 on Cold reset */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/model_config.txt deleted file mode 100644 index c5bc897..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/model_config.txt +++ /dev/null @@ -1,29 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct deleted file mode 100644 index ab4ccad..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 deleted file mode 100644 index a369523..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/gcc_arm.ld deleted file mode 100644 index f44186e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/partition_ARMCM55.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/partition_ARMCM55.h deleted file mode 100644 index eabaf30..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/partition_ARMCM55.h +++ /dev/null @@ -1,1261 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM55.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 20. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM55_H -#define PARTITION_ARMCM55_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM55_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c deleted file mode 100644 index 0557c5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM55.c - * @brief CMSIS-Core Device Startup File for Cortex-M55 Device - * @version V1.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 deleted file mode 100644 index 0557c5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM55.c - * @brief CMSIS-Core Device Startup File for Cortex-M55 Device - * @version V1.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c deleted file mode 100644 index d66624d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.c - * @brief CMSIS Device System Source File for - * ARMCM55 Device - * @version V1.1.0 - * @date 28. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM55.h" - #endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set low-power state for PDEPU */ - /* 0b00 | ON, PDEPU is not in low-power state */ - /* 0b01 | ON, but the clock is off */ - /* 0b10 | RET(ention) */ - /* 0b11 | OFF */ - - /* Clear ELPSTATE, value is 0b11 on Cold reset */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 deleted file mode 100644 index d66624d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.c - * @brief CMSIS Device System Source File for - * ARMCM55 Device - * @version V1.1.0 - * @date 28. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM55.h" - #endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set low-power state for PDEPU */ - /* 0b00 | ON, PDEPU is not in low-power state */ - /* 0b01 | ON, but the clock is off */ - /* 0b10 | RET(ention) */ - /* 0b11 | OFF */ - - /* Clear ELPSTATE, value is 0b11 on Cold reset */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/model_config.txt deleted file mode 100644 index c5bc897..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/model_config.txt +++ /dev/null @@ -1,29 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct deleted file mode 100644 index ab4ccad..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 deleted file mode 100644 index a369523..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/gcc_arm.ld deleted file mode 100644 index f44186e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/partition_ARMCM55.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/partition_ARMCM55.h deleted file mode 100644 index f23a0f0..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/partition_ARMCM55.h +++ /dev/null @@ -1,1261 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM55.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 20. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM55_H -#define PARTITION_ARMCM55_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x0000122B - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM55_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c deleted file mode 100644 index 0557c5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM55.c - * @brief CMSIS-Core Device Startup File for Cortex-M55 Device - * @version V1.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 deleted file mode 100644 index 0557c5f..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM55.c - * @brief CMSIS-Core Device Startup File for Cortex-M55 Device - * @version V1.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c deleted file mode 100644 index d66624d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.c - * @brief CMSIS Device System Source File for - * ARMCM55 Device - * @version V1.1.0 - * @date 28. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM55.h" - #endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set low-power state for PDEPU */ - /* 0b00 | ON, PDEPU is not in low-power state */ - /* 0b01 | ON, but the clock is off */ - /* 0b10 | RET(ention) */ - /* 0b11 | OFF */ - - /* Clear ELPSTATE, value is 0b11 on Cold reset */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 deleted file mode 100644 index d66624d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.c - * @brief CMSIS Device System Source File for - * ARMCM55 Device - * @version V1.1.0 - * @date 28. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM55.h" - #endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set low-power state for PDEPU */ - /* 0b00 | ON, PDEPU is not in low-power state */ - /* 0b01 | ON, but the clock is off */ - /* 0b10 | RET(ention) */ - /* 0b11 | OFF */ - - /* Clear ELPSTATE, value is 0b11 on Cold reset */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/model_config.txt deleted file mode 100644 index c5bc897..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/model_config.txt +++ /dev/null @@ -1,29 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct deleted file mode 100644 index 3cba29e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c deleted file mode 100644 index 509cd33..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3 deleted file mode 100644 index 509cd33..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3 +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c deleted file mode 100644 index 75f9c18..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM7.c - * @brief CMSIS Device System Source File for - * ARMCM7 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt deleted file mode 100644 index da5f3de..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt +++ /dev/null @@ -1,14 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support -armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -armcortexm7ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -armcortexm7ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -armcortexm7ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-heap_limit=0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-stack_base=0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-stack_limit=0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct deleted file mode 100644 index 3cba29e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c deleted file mode 100644 index 509cd33..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3 deleted file mode 100644 index 509cd33..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3 +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/system_ARMCM7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/system_ARMCM7.c deleted file mode 100644 index 75f9c18..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/system_ARMCM7.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM7.c - * @brief CMSIS Device System Source File for - * ARMCM7 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/model_config.txt deleted file mode 100644 index acc5fac..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/model_config.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -armcortexm7ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -armcortexm7ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -armcortexm7ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-heap_limit=0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-stack_base=0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-stack_limit=0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -armcortexm7ct.DP_FLOAT=1 # (bool , init-time) default = '1' : Support 8-byte floats -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct deleted file mode 100644 index 3cba29e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c deleted file mode 100644 index 509cd33..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3 deleted file mode 100644 index 509cd33..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3 +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/system_ARMCM7.c deleted file mode 100644 index 75f9c18..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/system_ARMCM7.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM7.c - * @brief CMSIS Device System Source File for - * ARMCM7 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/model_config.txt deleted file mode 100644 index 9bad471..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/model_config.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -armcortexm7ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -armcortexm7ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -armcortexm7ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -armcortexm7ct.DP_FLOAT=0 # (bool , init-time) default = '1' : Support 8-byte floats -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct deleted file mode 100644 index 09bdba2..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct +++ /dev/null @@ -1,130 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00200000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20200000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0 deleted file mode 100644 index cf72c41..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0 +++ /dev/null @@ -1,126 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld deleted file mode 100644 index 73c34d3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00200000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20200000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 deleted file mode 100644 index 028ca8e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c deleted file mode 100644 index 067871d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM85.c - * @brief CMSIS Device Startup File for ARMCM85 Device - * @version V1.0.0 - * @date 07. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 deleted file mode 100644 index 067871d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM85.c - * @brief CMSIS Device Startup File for ARMCM85 Device - * @version V1.0.0 - * @date 07. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c deleted file mode 100644 index 7a16501..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.c - * @brief CMSIS Device System Source File for ARMCM85 Device - * @version V1.0.0 - * @date 30. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM85.h" - #endif -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 deleted file mode 100644 index 7a16501..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.c - * @brief CMSIS Device System Source File for ARMCM85 Device - * @version V1.0.0 - * @date 30. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM85.h" - #endif -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/model_config.txt deleted file mode 100644 index e602725..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/model_config.txt +++ /dev/null @@ -1,30 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.MVE=1 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included -cpu0.ID_ISAR5.PACBTI=1 # (int , init-time) default = '0x0' : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct deleted file mode 100644 index c8049ef..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct +++ /dev/null @@ -1,130 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 deleted file mode 100644 index 3eddea7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 +++ /dev/null @@ -1,126 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld deleted file mode 100644 index f4f12ca..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 deleted file mode 100644 index 028ca8e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h deleted file mode 100644 index a3d881a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h +++ /dev/null @@ -1,1301 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM85.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 07. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM85_H -#define PARTITION_ARMCM85_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM85_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 deleted file mode 100644 index a3d881a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 +++ /dev/null @@ -1,1301 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM85.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 07. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM85_H -#define PARTITION_ARMCM85_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM85_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c deleted file mode 100644 index 067871d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM85.c - * @brief CMSIS Device Startup File for ARMCM85 Device - * @version V1.0.0 - * @date 07. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 deleted file mode 100644 index 067871d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM85.c - * @brief CMSIS Device Startup File for ARMCM85 Device - * @version V1.0.0 - * @date 07. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c deleted file mode 100644 index 7a16501..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.c - * @brief CMSIS Device System Source File for ARMCM85 Device - * @version V1.0.0 - * @date 30. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM85.h" - #endif -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 deleted file mode 100644 index 7a16501..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.c - * @brief CMSIS Device System Source File for ARMCM85 Device - * @version V1.0.0 - * @date 30. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM85.h" - #endif -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/model_config.txt deleted file mode 100644 index e602725..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/model_config.txt +++ /dev/null @@ -1,30 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.MVE=1 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included -cpu0.ID_ISAR5.PACBTI=1 # (int , init-time) default = '0x0' : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct deleted file mode 100644 index c8049ef..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct +++ /dev/null @@ -1,130 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00200000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 deleted file mode 100644 index 3eddea7..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 +++ /dev/null @@ -1,126 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld deleted file mode 100644 index f4f12ca..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 deleted file mode 100644 index 028ca8e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h deleted file mode 100644 index 87c94c1..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h +++ /dev/null @@ -1,1301 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM85.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 07. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM85_H -#define PARTITION_ARMCM85_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x0000122B - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM85_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 deleted file mode 100644 index a3d881a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 +++ /dev/null @@ -1,1301 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM85.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 07. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM85_H -#define PARTITION_ARMCM85_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM85_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c deleted file mode 100644 index 067871d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM85.c - * @brief CMSIS Device Startup File for ARMCM85 Device - * @version V1.0.0 - * @date 07. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 deleted file mode 100644 index 067871d..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM85.c - * @brief CMSIS Device Startup File for ARMCM85 Device - * @version V1.0.0 - * @date 07. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c deleted file mode 100644 index 7a16501..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.c - * @brief CMSIS Device System Source File for ARMCM85 Device - * @version V1.0.0 - * @date 30. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM85.h" - #endif -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 deleted file mode 100644 index 7a16501..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.c - * @brief CMSIS Device System Source File for ARMCM85 Device - * @version V1.0.0 - * @date 30. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM85.h" - #endif -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/Target.clayer.yml b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/Target.clayer.yml deleted file mode 100644 index ee45512..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - misc: - - for-compiler: IAR - Link: [--config generic_cortex.icf] - - groups: - - group: VHT/FVP - files: - - file: ./model_config.txt diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/model_config.txt b/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/model_config.txt deleted file mode 100644 index e602725..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/model_config.txt +++ /dev/null @@ -1,30 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.MVE=1 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included -cpu0.ID_ISAR5.PACBTI=1 # (int , init-time) default = '0x0' : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI -cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -#---------------------------------------------------------------------------------------------- diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/Bootloader.cproject.yml b/external/CMSIS_5/CMSIS/CoreValidation/Project/Bootloader.cproject.yml deleted file mode 100644 index 3453694..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/Bootloader.cproject.yml +++ /dev/null @@ -1,117 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/cproject.schema.json - -project: - layers: - # App: CMSIS-Core Validation for Cortex-M (Bootloader part) - - layer: ../Layer/App/Bootloader_Cortex-M/App.clayer.yml - for-context: - - .AC6_low - - .AC6_mid - - .AC6_high - - .AC6_size - - .AC6_tiny - - .GCC_low - - .GCC_mid - - .GCC_high - - .GCC_size - - .GCC_tiny - - .IAR_low - - .IAR_mid - - .IAR_high - - .IAR_size - - .IAR_tiny - - #Target: CM23S - - layer: ../Layer/Target/CM23S_BL/Target.clayer.yml - for-context: - - .AC6_low+CM23S - - .AC6_mid+CM23S - - .AC6_high+CM23S - - .AC6_size+CM23S - - .AC6_tiny+CM23S - - .GCC_low+CM23S - - .GCC_mid+CM23S - - .GCC_high+CM23S - - .GCC_size+CM23S - - .GCC_tiny+CM23S - - .IAR_low+CM23S - - .IAR_mid+CM23S - - .IAR_high+CM23S - - .IAR_size+CM23S - - .IAR_tiny+CM23S - - #Target: CM33S - - layer: ../Layer/Target/CM33S_BL/Target.clayer.yml - for-context: - - .AC6_low+CM33S - - .AC6_mid+CM33S - - .AC6_high+CM33S - - .AC6_size+CM33S - - .AC6_tiny+CM33S - - .GCC_low+CM33S - - .GCC_mid+CM33S - - .GCC_high+CM33S - - .GCC_size+CM33S - - .GCC_tiny+CM33S - - .IAR_low+CM33S - - .IAR_mid+CM33S - - .IAR_high+CM33S - - .IAR_size+CM33S - - .IAR_tiny+CM33S - - #Target: CM35PS - - layer: ../Layer/Target/CM35PS_BL/Target.clayer.yml - for-context: - - .AC6_low+CM35PS - - .AC6_mid+CM35PS - - .AC6_high+CM35PS - - .AC6_size+CM35PS - - .AC6_tiny+CM35PS - - .GCC_low+CM35PS - - .GCC_mid+CM35PS - - .GCC_high+CM35PS - - .GCC_size+CM35PS - - .GCC_tiny+CM35PS - - .IAR_low+CM35PS - - .IAR_mid+CM35PS - - .IAR_high+CM35PS - - .IAR_size+CM35PS - - .IAR_tiny+CM35PS - - #Target: CM55S - - layer: ../Layer/Target/CM55S_BL/Target.clayer.yml - for-context: - - .AC6_low+CM55S - - .AC6_mid+CM55S - - .AC6_high+CM55S - - .AC6_size+CM55S - - .AC6_tiny+CM55S - - .GCC_low+CM55S - - .GCC_mid+CM55S - - .GCC_high+CM55S - - .GCC_size+CM55S - - .GCC_tiny+CM55S - - .IAR_low+CM55S - - .IAR_mid+CM55S - - .IAR_high+CM55S - - .IAR_size+CM55S - - .IAR_tiny+CM55S - - #Target: CM85S - - layer: ../Layer/Target/CM85S_BL/Target.clayer.yml - for-context: - - .AC6_low+CM85S - - .AC6_mid+CM85S - - .AC6_high+CM85S - - .AC6_size+CM85S - - .AC6_tiny+CM85S - - .GCC_low+CM85S - - .GCC_mid+CM85S - - .GCC_high+CM85S - - .GCC_size+CM85S - - .GCC_tiny+CM85S - - .IAR_low+CM85S - - .IAR_mid+CM85S - - .IAR_high+CM85S - - .IAR_size+CM85S - - .IAR_tiny+CM85S diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.cproject.yml b/external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.cproject.yml deleted file mode 100644 index 23e5b1a..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.cproject.yml +++ /dev/null @@ -1,491 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/cproject.schema.json - -project: - layers: - # App: CMSIS-Core Validation for Cortex-M - - layer: ../Layer/App/Validation_Cortex-M/App.clayer.yml - for-context: - - +CM0 - - +CM0plus - - +CM3 - - +CM4 - - +CM4FP - - +CM7 - - +CM7SP - - +CM7DP - - +CM23 - - +CM23S - - +CM23NS - - +CM33 - - +CM33S - - +CM33NS - - +CM35P - - +CM35PS - - +CM35PNS - - +CM55S - - +CM55NS - - +CM85S - - +CM85NS - - # App: CMSIS-Core Validation for Cortex-A - - layer: ../Layer/App/Validation_Cortex-A/App.clayer.yml - for-context: - - +CA5 - - +CA7 - - +CA9 - - #Target: CM0 - - layer: ../Layer/Target/CM0/Target.clayer.yml - for-context: - - .AC6_low+CM0 - - .AC6_mid+CM0 - - .AC6_high+CM0 - - .AC6_size+CM0 - - .AC6_tiny+CM0 - - .GCC_low+CM0 - - .GCC_mid+CM0 - - .GCC_high+CM0 - - .GCC_size+CM0 - - .GCC_tiny+CM0 - - .IAR_low+CM0 - - .IAR_mid+CM0 - - .IAR_high+CM0 - - .IAR_size+CM0 - - .IAR_tiny+CM0 - - #Target: CM0plus - - layer: ../Layer/Target/CM0plus/Target.clayer.yml - for-context: - - .AC6_low+CM0plus - - .AC6_mid+CM0plus - - .AC6_high+CM0plus - - .AC6_size+CM0plus - - .AC6_tiny+CM0plus - - .GCC_low+CM0plus - - .GCC_mid+CM0plus - - .GCC_high+CM0plus - - .GCC_size+CM0plus - - .GCC_tiny+CM0plus - - .IAR_low+CM0plus - - .IAR_mid+CM0plus - - .IAR_high+CM0plus - - .IAR_size+CM0plus - - .IAR_tiny+CM0plus - - #Target: CM3 - - layer: ../Layer/Target/CM3/Target.clayer.yml - for-context: - - .AC6_low+CM3 - - .AC6_mid+CM3 - - .AC6_high+CM3 - - .AC6_size+CM3 - - .AC6_tiny+CM3 - - .GCC_low+CM3 - - .GCC_mid+CM3 - - .GCC_high+CM3 - - .GCC_size+CM3 - - .GCC_tiny+CM3 - - .IAR_low+CM3 - - .IAR_mid+CM3 - - .IAR_high+CM3 - - .IAR_size+CM3 - - .IAR_tiny+CM3 - - #Target: CM4 - - layer: ../Layer/Target/CM4/Target.clayer.yml - for-context: - - .AC6_low+CM4 - - .AC6_mid+CM4 - - .AC6_high+CM4 - - .AC6_size+CM4 - - .AC6_tiny+CM4 - - .GCC_low+CM4 - - .GCC_mid+CM4 - - .GCC_high+CM4 - - .GCC_size+CM4 - - .GCC_tiny+CM4 - - .IAR_low+CM4 - - .IAR_mid+CM4 - - .IAR_high+CM4 - - .IAR_size+CM4 - - .IAR_tiny+CM4 - - #Target: CM4FP - - layer: ../Layer/Target/CM4FP/Target.clayer.yml - for-context: - - .AC6_low+CM4FP - - .AC6_mid+CM4FP - - .AC6_high+CM4FP - - .AC6_size+CM4FP - - .AC6_tiny+CM4FP - - .GCC_low+CM4FP - - .GCC_mid+CM4FP - - .GCC_high+CM4FP - - .GCC_size+CM4FP - - .GCC_tiny+CM4FP - - .IAR_low+CM4FP - - .IAR_mid+CM4FP - - .IAR_high+CM4FP - - .IAR_size+CM4FP - - .IAR_tiny+CM4FP - - #Target: CM7 - - layer: ../Layer/Target/CM7/Target.clayer.yml - for-context: - - .AC6_low+CM7 - - .AC6_mid+CM7 - - .AC6_high+CM7 - - .AC6_size+CM7 - - .AC6_tiny+CM7 - - .GCC_low+CM7 - - .GCC_mid+CM7 - - .GCC_high+CM7 - - .GCC_size+CM7 - - .GCC_tiny+CM7 - - .IAR_low+CM7 - - .IAR_mid+CM7 - - .IAR_high+CM7 - - .IAR_size+CM7 - - .IAR_tiny+CM7 - - #Target: CM7SP - - layer: ../Layer/Target/CM7SP/Target.clayer.yml - for-context: - - .AC6_low+CM7SP - - .AC6_mid+CM7SP - - .AC6_high+CM7SP - - .AC6_size+CM7SP - - .AC6_tiny+CM7SP - - .GCC_low+CM7SP - - .GCC_mid+CM7SP - - .GCC_high+CM7SP - - .GCC_size+CM7SP - - .GCC_tiny+CM7SP - - .IAR_low+CM7SP - - .IAR_mid+CM7SP - - .IAR_high+CM7SP - - .IAR_size+CM7SP - - .IAR_tiny+CM7SP - - #Target: CM7DP - - layer: ../Layer/Target/CM7DP/Target.clayer.yml - for-context: - - .AC6_low+CM7DP - - .AC6_mid+CM7DP - - .AC6_high+CM7DP - - .AC6_size+CM7DP - - .AC6_tiny+CM7DP - - .GCC_low+CM7DP - - .GCC_mid+CM7DP - - .GCC_high+CM7DP - - .GCC_size+CM7DP - - .GCC_tiny+CM7DP - - .IAR_low+CM7DP - - .IAR_mid+CM7DP - - .IAR_high+CM7DP - - .IAR_size+CM7DP - - .IAR_tiny+CM7DP - - #Target: CM23 - - layer: ../Layer/Target/CM23/Target.clayer.yml - for-context: - - .AC6_low+CM23 - - .AC6_mid+CM23 - - .AC6_high+CM23 - - .AC6_size+CM23 - - .AC6_tiny+CM23 - - .GCC_low+CM23 - - .GCC_mid+CM23 - - .GCC_high+CM23 - - .GCC_size+CM23 - - .GCC_tiny+CM23 - - .IAR_low+CM23 - - .IAR_mid+CM23 - - .IAR_high+CM23 - - .IAR_size+CM23 - - .IAR_tiny+CM23 - - #Target: CM23S - - layer: ../Layer/Target/CM23S/Target.clayer.yml - for-context: - - .AC6_low+CM23S - - .AC6_mid+CM23S - - .AC6_high+CM23S - - .AC6_size+CM23S - - .AC6_tiny+CM23S - - .GCC_low+CM23S - - .GCC_mid+CM23S - - .GCC_high+CM23S - - .GCC_size+CM23S - - .GCC_tiny+CM23S - - .IAR_low+CM23S - - .IAR_mid+CM23S - - .IAR_high+CM23S - - .IAR_size+CM23S - - .IAR_tiny+CM23S - - #Target: CM23NS - - layer: ../Layer/Target/CM23NS/Target.clayer.yml - for-context: - - .AC6_low+CM23NS - - .AC6_mid+CM23NS - - .AC6_high+CM23NS - - .AC6_size+CM23NS - - .AC6_tiny+CM23NS - - .GCC_low+CM23NS - - .GCC_mid+CM23NS - - .GCC_high+CM23NS - - .GCC_size+CM23NS - - .GCC_tiny+CM23NS - - .IAR_low+CM23NS - - .IAR_mid+CM23NS - - .IAR_high+CM23NS - - .IAR_size+CM23NS - - .IAR_tiny+CM23NS - - #Target: CM33 - - layer: ../Layer/Target/CM33/Target.clayer.yml - for-context: - - .AC6_low+CM33 - - .AC6_mid+CM33 - - .AC6_high+CM33 - - .AC6_size+CM33 - - .AC6_tiny+CM33 - - .GCC_low+CM33 - - .GCC_mid+CM33 - - .GCC_high+CM33 - - .GCC_size+CM33 - - .GCC_tiny+CM33 - - .IAR_low+CM33 - - .IAR_mid+CM33 - - .IAR_high+CM33 - - .IAR_size+CM33 - - .IAR_tiny+CM33 - - #Target: CM33S - - layer: ../Layer/Target/CM33S/Target.clayer.yml - for-context: - - .AC6_low+CM33S - - .AC6_mid+CM33S - - .AC6_high+CM33S - - .AC6_size+CM33S - - .AC6_tiny+CM33S - - .GCC_low+CM33S - - .GCC_mid+CM33S - - .GCC_high+CM33S - - .GCC_size+CM33S - - .GCC_tiny+CM33S - - .IAR_low+CM33S - - .IAR_mid+CM33S - - .IAR_high+CM33S - - .IAR_size+CM33S - - .IAR_tiny+CM33S - - #Target: CM33NS - - layer: ../Layer/Target/CM33NS/Target.clayer.yml - for-context: - - .AC6_low+CM33NS - - .AC6_mid+CM33NS - - .AC6_high+CM33NS - - .AC6_size+CM33NS - - .AC6_tiny+CM33NS - - .GCC_low+CM33NS - - .GCC_mid+CM33NS - - .GCC_high+CM33NS - - .GCC_size+CM33NS - - .GCC_tiny+CM33NS - - .IAR_low+CM33NS - - .IAR_mid+CM33NS - - .IAR_high+CM33NS - - .IAR_size+CM33NS - - .IAR_tiny+CM33NS - - #Target: CM35P - - layer: ../Layer/Target/CM35P/Target.clayer.yml - for-context: - - .AC6_low+CM35P - - .AC6_mid+CM35P - - .AC6_high+CM35P - - .AC6_size+CM35P - - .AC6_tiny+CM35P - - .GCC_low+CM35P - - .GCC_mid+CM35P - - .GCC_high+CM35P - - .GCC_size+CM35P - - .GCC_tiny+CM35P - - .IAR_low+CM35P - - .IAR_mid+CM35P - - .IAR_high+CM35P - - .IAR_size+CM35P - - .IAR_tiny+CM35P - - #Target: CM35PS - - layer: ../Layer/Target/CM35PS/Target.clayer.yml - for-context: - - .AC6_low+CM35PS - - .AC6_mid+CM35PS - - .AC6_high+CM35PS - - .AC6_size+CM35PS - - .AC6_tiny+CM35PS - - .GCC_low+CM35PS - - .GCC_mid+CM35PS - - .GCC_high+CM35PS - - .GCC_size+CM35PS - - .GCC_tiny+CM35PS - - .IAR_low+CM35PS - - .IAR_mid+CM35PS - - .IAR_high+CM35PS - - .IAR_size+CM35PS - - .IAR_tiny+CM35PS - - #Target: CM35PNS - - layer: ../Layer/Target/CM35PNS/Target.clayer.yml - for-context: - - .AC6_low+CM35PNS - - .AC6_mid+CM35PNS - - .AC6_high+CM35PNS - - .AC6_size+CM35PNS - - .AC6_tiny+CM35PNS - - .GCC_low+CM35PNS - - .GCC_mid+CM35PNS - - .GCC_high+CM35PNS - - .GCC_size+CM35PNS - - .GCC_tiny+CM35PNS - - .IAR_low+CM35PNS - - .IAR_mid+CM35PNS - - .IAR_high+CM35PNS - - .IAR_size+CM35PNS - - .IAR_tiny+CM35PNS - - #Target: CM55S - - layer: ../Layer/Target/CM55S/Target.clayer.yml - for-context: - - .AC6_low+CM55S - - .AC6_mid+CM55S - - .AC6_high+CM55S - - .AC6_size+CM55S - - .AC6_tiny+CM55S - - .GCC_low+CM55S - - .GCC_mid+CM55S - - .GCC_high+CM55S - - .GCC_size+CM55S - - .GCC_tiny+CM55S - - .IAR_low+CM55S - - .IAR_mid+CM55S - - .IAR_high+CM55S - - .IAR_size+CM55S - - .IAR_tiny+CM55S - - #Target: CM55NS - - layer: ../Layer/Target/CM55NS/Target.clayer.yml - for-context: - - .AC6_low+CM55NS - - .AC6_mid+CM55NS - - .AC6_high+CM55NS - - .AC6_size+CM55NS - - .AC6_tiny+CM55NS - - .GCC_low+CM55NS - - .GCC_mid+CM55NS - - .GCC_high+CM55NS - - .GCC_size+CM55NS - - .GCC_tiny+CM55NS - - .IAR_low+CM55NS - - .IAR_mid+CM55NS - - .IAR_high+CM55NS - - .IAR_size+CM55NS - - .IAR_tiny+CM55NS - - #Target: CM85S - - layer: ../Layer/Target/CM85S/Target.clayer.yml - for-context: - - .AC6_low+CM85S - - .AC6_mid+CM85S - - .AC6_high+CM85S - - .AC6_size+CM85S - - .AC6_tiny+CM85S - - .GCC_low+CM85S - - .GCC_mid+CM85S - - .GCC_high+CM85S - - .GCC_size+CM85S - - .GCC_tiny+CM85S - - .IAR_low+CM85S - - .IAR_mid+CM85S - - .IAR_high+CM85S - - .IAR_size+CM85S - - .IAR_tiny+CM85S - - #Target: CM85NS - - layer: ../Layer/Target/CM85NS/Target.clayer.yml - for-context: - - .AC6_low+CM85NS - - .AC6_mid+CM85NS - - .AC6_high+CM85NS - - .AC6_size+CM85NS - - .AC6_tiny+CM85NS - - .GCC_low+CM85NS - - .GCC_mid+CM85NS - - .GCC_high+CM85NS - - .GCC_size+CM85NS - - .GCC_tiny+CM85NS - - .IAR_low+CM85NS - - .IAR_mid+CM85NS - - .IAR_high+CM85NS - - .IAR_size+CM85NS - - .IAR_tiny+CM85NS - - #Target: CA5 - - layer: ../Layer/Target/CA5/Target.clayer.yml - for-context: - - .AC6_low+CA5 - - .AC6_mid+CA5 - - .AC6_high+CA5 - - .AC6_size+CA5 - - .AC6_tiny+CA5 - - .GCC_low+CA5 - - .GCC_mid+CA5 - - .GCC_high+CA5 - - .GCC_size+CA5 - - .GCC_tiny+CA5 - - .IAR_low+CA5 - - .IAR_mid+CA5 - - .IAR_high+CA5 - - .IAR_size+CA5 - - .IAR_tiny+CA5 - - #Target: CA7 - - layer: ../Layer/Target/CA7/Target.clayer.yml - for-context: - - .AC6_low+CA7 - - .AC6_mid+CA7 - - .AC6_high+CA7 - - .AC6_size+CA7 - - .AC6_tiny+CA7 - - .GCC_low+CA7 - - .GCC_mid+CA7 - - .GCC_high+CA7 - - .GCC_size+CA7 - - .GCC_tiny+CA7 - - .IAR_low+CA7 - - .IAR_mid+CA7 - - .IAR_high+CA7 - - .IAR_size+CA7 - - .IAR_tiny+CA7 - - #Target: CA9 - - layer: ../Layer/Target/CA9/Target.clayer.yml - for-context: - - .AC6_low+CA9 - - .AC6_mid+CA9 - - .AC6_high+CA9 - - .AC6_size+CA9 - - .AC6_tiny+CA9 - - .GCC_low+CA9 - - .GCC_mid+CA9 - - .GCC_high+CA9 - - .GCC_size+CA9 - - .GCC_tiny+CA9 - - .IAR_low+CA9 - - .IAR_mid+CA9 - - .IAR_high+CA9 - - .IAR_size+CA9 - - .IAR_tiny+CA9 diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.csolution.yml b/external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.csolution.yml deleted file mode 100644 index 373eed0..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.csolution.yml +++ /dev/null @@ -1,235 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/csolution.schema.json - -solution: - packs: - - pack: ARM::CMSIS - path: ../../../ - - misc: - - for-compiler: AC6 - C: [-std=c99, -gdwarf-4, -ffunction-sections] - Link: [--entry=Reset_Handler, --symbols, --map] - - for-compiler: GCC - C: [-std=gnu99, -gdwarf-2, -ffunction-sections, -fdata-sections] - Link: [--specs=nano.specs, --specs=rdimon.specs] - - for-compiler: IAR - Link: [--semihosting] - - target-types: - #CM0 - - type: CM0 - device: ARMCM0 - - #CM0plus - - type: CM0plus - device: ARMCM0P - - #CM3 - - type: CM3 - device: ARMCM3 - - #CM4 - - type: CM4 - device: ARMCM4 - - #CM4FP - - type: CM4FP - device: ARMCM4_FP - - #CM7 - - type: CM7 - device: ARMCM7 - - #CM7SP - - type: CM7SP - device: ARMCM7_SP - - #CM7DP - - type: CM7DP - device: ARMCM7_DP - - #CM23 - - type: CM23 - device: ARMCM23 - processor: - trustzone: off - - #CM23S - - type: CM23S - device: ARMCM23_TZ - processor: - trustzone: secure - - #CM23NS - - type: CM23NS - device: ARMCM23_TZ - processor: - trustzone: non-secure - - #CM33 - - type: CM33 - device: ARMCM33_DSP_FP - processor: - trustzone: off - - #CM33S - - type: CM33S - device: ARMCM33_DSP_FP_TZ - processor: - trustzone: secure - - #CM33NS - - type: CM33NS - device: ARMCM33_DSP_FP_TZ - processor: - trustzone: non-secure - - #CM35P - - type: CM35P - device: ARMCM35P_DSP_FP - processor: - trustzone: off - - #CM35PS - - type: CM35PS - device: ARMCM35P_DSP_FP_TZ - processor: - trustzone: secure - - #CM35PNS - - type: CM35PNS - device: ARMCM35P_DSP_FP_TZ - processor: - trustzone: non-secure - - #CM55S - - type: CM55S - device: ARMCM55 - processor: - trustzone: secure - - #CM55NS - - type: CM55NS - device: ARMCM55 - processor: - trustzone: non-secure - - #CM85S - - type: CM85S - device: ARMCM85 - processor: - trustzone: secure - - #CM85NS - - type: CM85NS - device: ARMCM85 - processor: - trustzone: non-secure - - #CA5 - - type: CA5 - device: ARMCA5 - - #CA7 - - type: CA7 - device: ARMCA7 - - #CA9 - - type: CA9 - device: ARMCA9 - - build-types: - #AC6_low, AC6_mid, AC6_high, AC6_size, AC6_OZ, - - type: AC6_low - compiler: AC6 - misc: - - for-compiler: AC6 - C: [-O1] - - type: AC6_mid - compiler: AC6 - misc: - - for-compiler: AC6 - C: [-O2] - - type: AC6_high - compiler: AC6 - misc: - - for-compiler: AC6 - C: [-O3] - - type: AC6_size - compiler: AC6 - misc: - - for-compiler: AC6 - C: [-Os] - - type: AC6_tiny - compiler: AC6 - misc: - - for-compiler: AC6 - C: [-Oz] - #GCC_low, GCC_mid, GCC_high, GCC_size, GCC_OZ, - - type: GCC_low - compiler: GCC - misc: - - for-compiler: GCC - C: [-O1] - - type: GCC_mid - compiler: GCC - misc: - - for-compiler: GCC - C: [-O2] - - type: GCC_high - compiler: GCC - misc: - - for-compiler: GCC - C: [-O3] - - type: GCC_size - compiler: GCC - misc: - - for-compiler: GCC - C: [-Os] - - type: GCC_tiny - compiler: GCC - misc: - - for-compiler: GCC - C: [-Ofast] - #IAR_low - - type: IAR_low - compiler: IAR - misc: - - for-compiler: IAR - C: [-Ol, --dlib_config DLib_Config_Full.h] - - type: IAR_mid - compiler: IAR - misc: - - for-compiler: IAR - C: [-Om, --dlib_config DLib_Config_Full.h] - - type: IAR_high - compiler: IAR - misc: - - for-compiler: IAR - C: [-Oh, --dlib_config DLib_Config_Full.h] - - type: IAR_size - compiler: IAR - misc: - - for-compiler: IAR - C: [-Ohz, --dlib_config DLib_Config_Full.h] - - type: IAR_tiny - compiler: IAR - misc: - - for-compiler: IAR - C: [-Ohs, --dlib_config DLib_Config_Full.h] - - projects: - - project: ./Validation.cproject.yml - - - project: ./Bootloader.cproject.yml - for-context: - - +CM23S - - +CM33S - - +CM35PS - - +CM55S - - +CM85S - - output-dirs: - cprjdir: ./$Project$.$BuildType$+$TargetType$ - intdir: ./$Project$.$BuildType$+$TargetType$/intdir - outdir: ./$Project$.$BuildType$+$TargetType$/outdir diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/avh.yml b/external/CMSIS_5/CMSIS/CoreValidation/Project/avh.yml deleted file mode 100644 index c958d09..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/avh.yml +++ /dev/null @@ -1,39 +0,0 @@ -name: "RTOS2 Validation" -workdir: ../../../ -backend: - aws: - ami-version: ~=1.3 - instance-type: t2.micro -upload: - - ARM.CMSIS.pdsc - - CMSIS/Core/**/* - - CMSIS/Core_A/**/* - - CMSIS/CoreValidation/**/* - - -:CMSIS/CoreValidation/Project/Core_Validation-*.zip - - -:CMSIS/CoreValidation/Project/Core_Validation-*.junit - - -:CMSIS/CoreValidation/Project/Validation.*/**/* - - -:CMSIS/CoreValidation/Project/Bootloader.*/**/* - - Device/ARM/**/* -steps: - - run: | - wget https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases/download/1.5.0/cmsis-toolbox.sh - chmod +x cmsis-toolbox.sh - sudo ./cmsis-toolbox.sh </dev/null)) - $(dirname $(which armcc 2>/dev/null)) - $(dirname $(which arm-none-eabi-gcc 2>/dev/null)) - - EOI - echo "cpackget : $(which cpackget)" - echo "csolution: $(which csolution)" - echo "cbuild : $(which cbuild)" - - run: | - pip install -r requirements.txt 2>&1 - - run: | - cd CMSIS/CoreValidation/Project - python build.py --verbose -c AC6 -c GCC -d "CM[047]*" -d "CM[23]3*" build run 2>&1 || echo "Something failed!" -download: - - CMSIS/CoreValidation/Project/Core_Validation-*.zip - - CMSIS/CoreValidation/Project/Core_Validation-*.junit diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/build.py b/external/CMSIS_5/CMSIS/CoreValidation/Project/build.py deleted file mode 100644 index 3259e4c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/build.py +++ /dev/null @@ -1,259 +0,0 @@ -#!/usr/bin/python -# -*- coding: utf-8 -*- - -import logging - -from datetime import datetime -from enum import Enum -from glob import glob, iglob -from pathlib import Path - -from lxml.etree import XMLSyntaxError -from zipfile import ZipFile - -from matrix_runner import main, matrix_axis, matrix_action, matrix_command, matrix_filter, \ - ConsoleReport, CropReport, TransformReport, JUnitReport - - -@matrix_axis("device", "d", "Device(s) to be considered.") -class DeviceAxis(Enum): - CM0 = ('Cortex-M0', 'CM0') - CM0plus = ('Cortex-M0plus', 'CM0plus') - CM3 = ('Cortex-M3', 'CM3') - CM4 = ('Cortex-M4', 'CM4') - CM4FP = ('Cortex-M4FP', 'CM4FP') - CM7 = ('Cortex-M7', 'CM7') - CM7SP = ('Cortex-M7SP', 'CM7SP') - CM7DP = ('Cortex-M7DP', 'CM7DP') - CM23 = ('Cortex-M23', 'CM23') - CM23S = ('Cortex-M23S', 'CM23S') - CM23NS = ('Cortex-M23NS', 'CM23NS') - CM33 = ('Cortex-M33', 'CM33') - CM33S = ('Cortex-M33S', 'CM33S') - CM33NS = ('Cortex-M33NS', 'CM33NS') - CM35P = ('Cortex-M35P', 'CM35P') - CM35PS = ('Cortex-M35PS', 'CM35PS') - CM35PNS = ('Cortex-M35PNS', 'CM35PNS') - CM55S = ('Cortex-M55S', 'CM55S') - CM55NS = ('Cortex-M55NS', 'CM55NS') - CM85S = ('Cortex-M85S', 'CM85S') - CM85NS = ('Cortex-M85NS', 'CM85NS') - CA5 = ('Cortex-A5', 'CA5') - CA7 = ('Cortex-A7', 'CA7') - CA9 = ('Cortex-A9', 'CA9') -# CA5NEON = ('Cortex-A5neon', 'CA5neon') -# CA7NEON = ('Cortex-A7neon', 'CA7neon') -# CA9NEON = ('Cortex-A9neon', 'CA9neon') - - def has_bl(self): - return self in [ - DeviceAxis.CM23NS, - DeviceAxis.CM33NS, - DeviceAxis.CM35PNS, - DeviceAxis.CM55NS, - DeviceAxis.CM85NS - ] - - @property - def bl_device(self): - bld = { - DeviceAxis.CM23NS: 'CM23S', - DeviceAxis.CM33NS: 'CM33S', - DeviceAxis.CM35PNS: 'CM35PS', - DeviceAxis.CM55NS: 'CM55S', - DeviceAxis.CM85NS: 'CM85S' - } - return bld[self] - - -@matrix_axis("compiler", "c", "Compiler(s) to be considered.") -class CompilerAxis(Enum): - AC6 = ('AC6') - AC6LTM = ('AC6LTM') - GCC = ('GCC') - IAR = ('IAR') - - @property - def image_ext(self): - ext = { - CompilerAxis.AC6: 'axf', - CompilerAxis.AC6LTM: 'axf', - CompilerAxis.GCC: 'elf', - CompilerAxis.IAR: 'elf' - } - return ext[self] - - -@matrix_axis("optimize", "o", "Optimization level(s) to be considered.") -class OptimizationAxis(Enum): - LOW = ('low', 'O1') - MID = ('mid', 'O2') - HIGH = ('high', 'Ofast') - SIZE = ('size', 'Os') - TINY = ('tiny', 'Oz') - - -MODEL_EXECUTABLE = { - DeviceAxis.CM0: ("VHT_MPS2_Cortex-M0", []), - DeviceAxis.CM0plus: ("VHT_MPS2_Cortex-M0plus", []), - DeviceAxis.CM3: ("VHT_MPS2_Cortex-M3", []), - DeviceAxis.CM4: ("VHT_MPS2_Cortex-M4", []), - DeviceAxis.CM4FP: ("VHT_MPS2_Cortex-M4", []), - DeviceAxis.CM7: ("VHT_MPS2_Cortex-M7", []), - DeviceAxis.CM7DP: ("VHT_MPS2_Cortex-M7", []), - DeviceAxis.CM7SP: ("VHT_MPS2_Cortex-M7", []), - DeviceAxis.CM23: ("VHT_MPS2_Cortex-M23", []), - DeviceAxis.CM23S: ("VHT_MPS2_Cortex-M23", []), - DeviceAxis.CM23NS: ("VHT_MPS2_Cortex-M23", []), - DeviceAxis.CM33: ("VHT_MPS2_Cortex-M33", []), - DeviceAxis.CM33S: ("VHT_MPS2_Cortex-M33", []), - DeviceAxis.CM33NS: ("VHT_MPS2_Cortex-M33", []), - DeviceAxis.CM35P: ("VHT_MPS2_Cortex-M35P", []), - DeviceAxis.CM35PS: ("VHT_MPS2_Cortex-M35P", []), - DeviceAxis.CM35PNS: ("VHT_MPS2_Cortex-M35P", []), - DeviceAxis.CM55S: ("VHT_MPS2_Cortex-M55", []), - DeviceAxis.CM55NS: ("VHT_MPS2_Cortex-M55", []), - DeviceAxis.CM85S: ("VHT_MPS2_Cortex-M85", []), - DeviceAxis.CM85NS: ("VHT_MPS2_Cortex-M85", []), - DeviceAxis.CA5: ("FVP_VE_Cortex-A5x1", []), - DeviceAxis.CA7: ("FVP_VE_Cortex-A7x1", []), - DeviceAxis.CA9: ("FVP_VE_Cortex-A9x1", []), -# DeviceAxis.CA5NEON: ("FVP_VE_Cortex-A5x1", []), -# DeviceAxis.CA7NEON: ("FVP_VE_Cortex-A7x1", []), -# DeviceAxis.CA9NEON: ("FVP_VE_Cortex-A9x1", []) -} - -def config_suffix(config, timestamp=True): - suffix = f"{config.compiler[0]}-{config.optimize[0]}-{config.device[1]}" - if timestamp: - suffix += f"-{datetime.now().strftime('%Y%m%d%H%M%S')}" - return suffix - - -def image_name(config): - return f"Validation" - - -def project_name(config): - return f"Validation.{config.compiler}_{config.optimize}+{config.device[1]}" - - -def bl_image_name(config): - return f"Bootloader" - - -def bl_project_name(config): - return f"Bootloader.{config.compiler}_{config.optimize}+{config.device.bl_device}" - - -def output_dir(config): - return "outdir" - - -def bl_output_dir(config): - return "outdir" - - -def model_config(config): - return f"../Layer/Target/{config.device[1]}/model_config.txt" - - -@matrix_action -def clean(config): - """Build the selected configurations using CMSIS-Build.""" - yield cbuild_clean(f"{project_name(config)}/{project_name(config)}.cprj") - - -@matrix_action -def build(config, results): - """Build the selected configurations using CMSIS-Build.""" - - if config.device.has_bl(): - logging.info("Compiling Bootloader...") - yield csolution(f"{bl_project_name(config)}") - yield cbuild(f"{bl_project_name(config)}/{bl_project_name(config)}.cprj") - - logging.info("Compiling Tests...") - - if config.compiler == CompilerAxis.GCC and config.device.match("CA*"): - ldfile = Path(f"{project_name(config)}/RTE/Device/ARM{config.device[1]}/ARM{config.device[1]}.ld") - infile = ldfile.replace(ldfile.with_suffix('.ld.in')) - yield preprocess(infile, ldfile) - - yield csolution(f"{project_name(config)}") - yield cbuild(f"{project_name(config)}/{project_name(config)}.cprj") - - if not all(r.success for r in results): - return - - file = f"Core_Validation-{config_suffix(config)}.zip" - logging.info(f"Archiving build output to {file}...") - with ZipFile(file, "w") as archive: - for content in iglob(f"{project_name(config)}/**/*", recursive=True): - if Path(content).is_file(): - archive.write(content) - - -@matrix_action -def extract(config): - """Extract the latest build archive.""" - archives = sorted(glob(f"RTOS2_Validation-{config_suffix(config, timestamp=False)}-*.zip"), reverse=True) - yield unzip(archives[0]) - - -@matrix_action -def run(config, results): - """Run the selected configurations.""" - logging.info("Running Core Validation on Arm model ...") - yield model_exec(config) - - try: - results[0].test_report.write(f"Core_Validation-{config_suffix(config)}.junit") - except RuntimeError as e: - if isinstance(e.__cause__, XMLSyntaxError): - logging.error("No valid test report found in model output!") - else: - logging.exception(e) - - -@matrix_command() -def cbuild_clean(project): - return ["cbuild", "-c", project] - - -@matrix_command() -def unzip(archive): - return ["bash", "-c", f"unzip {archive}"] - - -@matrix_command() -def preprocess(infile, outfile): - return ["arm-none-eabi-gcc", "-xc", "-E", infile, "-P", "-o", outfile] - -@matrix_command() -def csolution(project): - return ["csolution", "convert", "-s", "Validation.csolution.yml", "-c", project] - -@matrix_command() -def cbuild(project): - return ["cbuild", project] - - -@matrix_command(test_report=ConsoleReport() | - CropReport('<\?xml version="1.0"\?>', '') | - TransformReport('validation.xsl') | - JUnitReport(title=lambda title, result: f"{result.command.config.compiler}." - f"{result.command.config.optimize}." - f"{result.command.config.device}." - f"{title}")) -def model_exec(config): - cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 100, "-f", model_config(config)] - cmdline += MODEL_EXECUTABLE[config.device][1] - cmdline += ["-a", f"{project_name(config)}/{output_dir(config)}/{image_name(config)}.{config.compiler.image_ext}"] - if config.device.has_bl(): - cmdline += ["-a", f"{bl_project_name(config)}/{bl_output_dir(config)}/{bl_image_name(config)}.{config.compiler.image_ext}"] - return cmdline - - -if __name__ == "__main__": - main() diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/cpacklist.txt b/external/CMSIS_5/CMSIS/CoreValidation/Project/cpacklist.txt deleted file mode 100644 index 6740002..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/cpacklist.txt +++ /dev/null @@ -1 +0,0 @@ -ARM.CMSIS.5.9.0 diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/requirements.txt b/external/CMSIS_5/CMSIS/CoreValidation/Project/requirements.txt deleted file mode 100644 index d074321..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/requirements.txt +++ /dev/null @@ -1,6 +0,0 @@ -# -*- coding: utf-8 -*- -# -# Python requirements for build.py script -# -python-matrix-runner~=1.0 -lxml~=4.8 diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Project/validation.xsl b/external/CMSIS_5/CMSIS/CoreValidation/Project/validation.xsl deleted file mode 100644 index 4d0c2cc..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Project/validation.xsl +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - : - - - - - - - - - - - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/README.md b/external/CMSIS_5/CMSIS/CoreValidation/README.md deleted file mode 100644 index c8ae93b..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/README.md +++ /dev/null @@ -1,133 +0,0 @@ -# CMSIS-Core Validation - -This folder contains a test suite that validates CMSIS-Core implementations. It uses [**Fixed Virtual Platforms**](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms) to run tests to verify correct operation of the CMSIS-Core functionality on various Arm Cortex based processors. - -## Folder structure - -```txt - 📂 CoreValidation - ┣ 📂 Include Include files for test cases etc. - ┣ 📂 Layer Layers for creating the projects. - ┣ 📂 Project Solution and project files to build tests for various configurations. - â”— 📂 Source Test case source code. -``` - -## Test matrix - -Currently, the following build configurations are provided: - -1. Compiler - - Arm Compiler 6 (AC6) - - GNU Compiler (GCC) - - IAR Compiler (IAR) -2. Devices - - Cortex-M0 - - Cortex-M0+ - - Cortex-M3 - - Cortex-M4 - - w/o FPU - - with FPU - - Cortex-M7 - - w/o FPU - - with SP FPU - - with DP FPU - - Cortex-M23 - - w/o security extensions (TrustZone) - - in secure mode - - in non-secure mode - - Cortex-M33 (with FPU and DSP extensions) - - w/o security extensions (TrustZone) - - in secure mode - - in non-secure mode - - Cortex-M35P (with FPU and DSP extensions) - - w/o security extensions (TrustZone) - - in secure mode - - in non-secure mode - - Cortex-M55 (with FPU and DSP extensions) - - in secure mode - - in non-secure mode - - Cortex-M85 (with FPU and DSP extensions) - - in secure mode - - in non-secure mode - - Cortex-A5 - - w/o NEON extensions - - Cortex-A7 - - w/o NEON extensions - - Cortex-A9 - - w/o NEON extensions -3. Optimization Levels - - Low - - AC6: `-O1` - - GCC: `-O1` - - IAR: `-Ol` - - Mid - - AC6: `-O2` - - GCC: `-O2` - - IAR: `-Om` - - High - - AC6: `-O3` - - GCC: `-O3` - - IAR: `-Oh` - - Size - - AC6: `-Os` - - GCC: `-Os` - - IAR: `-Ohz` - - Tiny - - AC6: `-Oz` - - GCC: `-Ofast` - - IAR: `-Ohs` - -## Prerequisites - -The following tools are required to build and run the CoreValidation tests: - -- [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases) 1.3.0 or higher -- CMake -- Ninja build -- Arm Compiler 6 -- GNU Compiler -- IAR Compiler -- Python 3.8 or higher -- Arm Virtual Hardware Models - -The executables need to be present on the `PATH`. - -Install the Python packages required by `build.py`: - -```bash -CMSIS_5/CMSIS/CoreValidation/Project $ pip install -r requirements.txt -``` - -## Build and run - -To build and run the CoreValidation tests for one or more configurations use the following command line. -Select the ``, ``, and `optimize` level to `build` and `run` for. - -```bash -CMSIS_5/CMSIS/CoreValidation/Project $ ./build.py -c -d -o [build] [run] -``` - -For example, build and run the tests using GCC for Cortex-M3 with low optimization, execute: - -```bash -CMSIS_5/CMSIS/CoreValidation/Project $ ./build.py -c GCC -d CM3 -o low build run -[GCC][Cortex-M3][low](build:csolution) csolution convert -s Validation.csolution.yml -c Validation.GCC_low+CM3 -[GCC][Cortex-M3][low](build:csolution) csolution succeeded with exit code 0 -[GCC][Cortex-M3][low](build:cbuild) cbuild Validation.GCC_low+CM3/Validation.GCC_low+CM3.cprj -[GCC][Cortex-M3][low](build:cbuild) cbuild succeeded with exit code 0 -[GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf -[GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 succeeded with exit code 0 - -Matrix Summary -============== - -compiler device optimize build clean extract run ----------- --------- ---------- ------- ------- --------- ----- -GCC Cortex-M3 low success (skip) (skip) 35/35 -``` - -The full test report is written to `Core_Validation-GCC-low-CM3-.junit` file. - -## License - -[![License](https://img.shields.io/badge/License-Apache_2.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CAL1Cache.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CAL1Cache.c deleted file mode 100644 index 7d16f28..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CAL1Cache.c +++ /dev/null @@ -1,181 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_CAL1Cache.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CAL1Cache_EnDisable(void) { - - uint32_t orig = __get_SCTLR(); - - L1C_EnableCaches(); - - uint32_t sctlr = __get_SCTLR(); - ASSERT_TRUE((sctlr & SCTLR_I_Msk) == SCTLR_I_Msk); - ASSERT_TRUE((sctlr & SCTLR_C_Msk) == SCTLR_C_Msk); - - L1C_CleanDCacheAll(); - L1C_DisableCaches(); - - sctlr = __get_SCTLR(); - ASSERT_TRUE((sctlr & SCTLR_I_Msk) == 0U); - ASSERT_TRUE((sctlr & SCTLR_C_Msk) == 0U); - - __set_SCTLR(orig); - __ISB(); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CAL1Cache_EnDisableBTAC(void) { - uint32_t orig = __get_SCTLR(); - - L1C_EnableBTAC(); - - uint32_t sctlr = __get_SCTLR(); - ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk); - - L1C_DisableBTAC(); - - sctlr = __get_SCTLR(); -#if __CORTEX_A == 7 - // On Cortex-A7 SCTLR_Z is RAO/WI. - ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk); -#else - ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == 0U); -#endif - - __set_SCTLR(orig); - __ISB(); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CAL1Cache_log2_up(void) { - uint8_t log2 = __log2_up(0U); - ASSERT_TRUE(log2 == 0U); - - log2 = __log2_up(1U); - ASSERT_TRUE(log2 == 0U); - - log2 = __log2_up(2U); - ASSERT_TRUE(log2 == 1U); - - log2 = __log2_up(3U); - ASSERT_TRUE(log2 == 2U); - - log2 = __log2_up(4U); - ASSERT_TRUE(log2 == 2U); - - log2 = __log2_up(0x80000000U); - ASSERT_TRUE(log2 == 31U); - - log2 = __log2_up(0x80000001U); - ASSERT_TRUE(log2 == 32U); - - log2 = __log2_up(0xFFFFFFFFU); - ASSERT_TRUE(log2 == 32U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CAL1Cache_InvalidateDCacheAll(void) { - - /* setup */ - uint32_t orig = __get_SCTLR(); - volatile uint32_t value = 0x0815U; - - L1C_EnableCaches(); - - L1C_CleanDCacheAll(); - - /* test cached value gets lost */ - - // WHEN a value is written - value = 0x4711U; - - // ... and the cache is invalidated - L1C_InvalidateDCacheAll(); - - // ... and the cache is disabled - L1C_DisableCaches(); - - // THEN the new value has been lost - ASSERT_TRUE(value == 0x0815U); - - /* tear down */ - L1C_InvalidateDCacheAll(); - __set_SCTLR(orig); - __ISB(); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CAL1Cache_CleanDCacheAll(void) { - /* setup */ - uint32_t orig = __get_SCTLR(); - uint32_t value = 0x0815U; - - L1C_EnableCaches(); - - L1C_CleanDCacheAll(); - - /* test cached value is preserved */ - - // WHEN a value is written - value = 0x4711U; - - // ... and the cache is cleaned - L1C_CleanDCacheAll(); - - // ... and the cache is disabled - L1C_DisableCaches(); - - // THEN the new value is preserved - ASSERT_TRUE(value == 0x4711U); - - /* tear down */ - L1C_InvalidateDCacheAll(); - __set_SCTLR(orig); - __ISB(); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CAL1Cache_CleanInvalidateDCacheAll(void) { - /* setup */ - uint32_t orig = __get_SCTLR(); - uint32_t value = 0x0815U; - - L1C_EnableCaches(); - - L1C_CleanDCacheAll(); - - /* test cached value is preserved */ - - // WHEN a value is written - value = 0x4711U; - - // ... and the cache is cleaned/invalidated - L1C_CleanInvalidateDCacheAll(); - - // ... and the cache is disabled - L1C_DisableCaches(); - - // THEN the new value is preserved - ASSERT_TRUE(value == 0x4711U); - - /* tear down */ - L1C_InvalidateDCacheAll(); - __set_SCTLR(orig); - __ISB(); -} - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CML1Cache.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CML1Cache.c deleted file mode 100644 index 86d07d3..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CML1Cache.c +++ /dev/null @@ -1,56 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_CML1Cache.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2020 - 2021 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CML1Cache_EnDisableICache(void) { -#ifdef __ICACHE_PRESENT - SCB_EnableICache(); - - ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == SCB_CCR_IC_Msk); - - SCB_DisableICache(); - - ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == 0U); -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CML1Cache_EnDisableDCache(void) { -#ifdef __DCACHE_PRESENT - SCB_EnableDCache(); - - ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == SCB_CCR_DC_Msk); - - SCB_DisableDCache(); - - ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U); -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -#ifdef __DCACHE_PRESENT -static uint32_t TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[] = { 42U, 0U, 8U, 15U }; -#endif - -void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void) { -#ifdef __DCACHE_PRESENT - SCB_DisableDCache(); - SCB_CleanDCache_by_Addr(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values, sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values)/sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[0])); - ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U); -#endif -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreAFunc.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreAFunc.c deleted file mode 100644 index e130d5e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreAFunc.c +++ /dev/null @@ -1,284 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_CoreFunc.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_IRQ(void) { - uint32_t orig = __get_CPSR(); - - __enable_irq(); - uint32_t cpsr = __get_CPSR(); - ASSERT_TRUE((cpsr & CPSR_I_Msk) == 0U); - - __disable_irq(); - cpsr = __get_CPSR(); - ASSERT_TRUE((cpsr & CPSR_I_Msk) == CPSR_I_Msk); - - __set_CPSR(orig); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_FaultIRQ(void) { - uint32_t orig = __get_CPSR(); - - __enable_fault_irq(); - uint32_t cpsr = __get_CPSR(); - ASSERT_TRUE((cpsr & CPSR_F_Msk) == 0U); - - __disable_fault_irq(); - cpsr = __get_CPSR(); - ASSERT_TRUE((cpsr & CPSR_F_Msk) == CPSR_F_Msk); - - __set_CPSR(orig); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_FPSCR(void) { - - volatile float f1 = 47.11f; - volatile float f2 = 8.15f; - volatile float f3 = f1 / f2; - - uint32_t fpscr = __get_FPSCR(); - __set_FPSCR(fpscr); - - ASSERT_TRUE(fpscr == __get_FPSCR()); - ASSERT_TRUE((f3 < 5.781f) && (f3 > 5.780f)); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -#if defined(__CC_ARM) -#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn) -#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn) -#elif defined( __GNUC__ ) && defined(__thumb__) -#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) -#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) -#else -#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) -#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) -#endif - -void TC_CoreAFunc_CPSR(void) { - uint32_t result; - - uint32_t cpsr = __get_CPSR(); - __set_CPSR(cpsr & CPSR_M_Msk); - - // Check negative flag - int32_t Rm = 5; - int32_t Rn = 7; - __SUBS(Rm, Rm, Rn); - result = __get_CPSR(); - ASSERT_TRUE((result & CPSR_N_Msk) == CPSR_N_Msk); - - // Check zero and compare flag - Rm = 5; - __SUBS(Rm, Rm, Rm); - result = __get_CPSR(); - ASSERT_TRUE((result & CPSR_Z_Msk) == CPSR_Z_Msk); - ASSERT_TRUE((result & CPSR_C_Msk) == CPSR_C_Msk); - - // Check overflow flag - Rm = 5; - Rn = INT32_MAX; - __ADDS(Rm, Rm, Rn); - result = __get_CPSR(); - ASSERT_TRUE((result & CPSR_V_Msk) == CPSR_V_Msk); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_Mode(void) { - uint32_t mode = __get_mode(); - __set_mode(mode); - - ASSERT_TRUE(mode == __get_mode()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -static uint32_t TC_CoreAFunc_SP_orig; -static uint32_t TC_CoreAFunc_SP_sp; -static uint32_t TC_CoreAFunc_SP_result; - -void TC_CoreAFunc_SP(void) { - TC_CoreAFunc_SP_orig = __get_SP(); - - TC_CoreAFunc_SP_sp = TC_CoreAFunc_SP_orig + 0x12345678U; - __set_SP(TC_CoreAFunc_SP_sp); - TC_CoreAFunc_SP_result = __get_SP(); - - __set_SP(TC_CoreAFunc_SP_orig); - - ASSERT_TRUE(TC_CoreAFunc_SP_result == TC_CoreAFunc_SP_sp); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -static uint32_t TC_CoreAFunc_SP_usr_orig; -static uint32_t TC_CoreAFunc_SP_usr_sp; -static uint32_t TC_CoreAFunc_SP_usr_result; - -void TC_CoreAFunc_SP_usr(void) { - TC_CoreAFunc_SP_usr_orig = __get_SP_usr(); - - TC_CoreAFunc_SP_usr_sp = TC_CoreAFunc_SP_usr_orig + 0x12345678U; - __set_SP(TC_CoreAFunc_SP_usr_sp); - TC_CoreAFunc_SP_usr_result = __get_SP_usr(); - - __set_SP(TC_CoreAFunc_SP_usr_orig); - - ASSERT_TRUE(TC_CoreAFunc_SP_usr_result == TC_CoreAFunc_SP_usr_sp); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_FPEXC(void) { - uint32_t fpexc = __get_FPEXC(); - __set_FPEXC(fpexc); - - ASSERT_TRUE(fpexc == __get_FPEXC()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_ACTLR(void) { - uint32_t actlr = __get_ACTLR(); - __set_ACTLR(actlr); - - ASSERT_TRUE(actlr == __get_ACTLR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_CPACR(void) { - uint32_t cpacr = __get_CPACR(); - __set_CPACR(cpacr); - - ASSERT_TRUE(cpacr == __get_CPACR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_DFSR(void) { - uint32_t dfsr = __get_DFSR(); - __set_DFSR(dfsr); - - ASSERT_TRUE(dfsr == __get_DFSR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_IFSR(void) { - uint32_t ifsr = __get_IFSR(); - __set_IFSR(ifsr); - - ASSERT_TRUE(ifsr == __get_IFSR()); -} - -/*0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_ISR(void) { - uint32_t isr = __get_ISR(); - - ASSERT_TRUE(isr == __get_ISR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_CBAR(void) { - uint32_t cbar = __get_CBAR(); - - ASSERT_TRUE(cbar == __get_CBAR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_TTBR0(void) { - uint32_t ttbr0 = __get_TTBR0(); - __set_TTBR0(ttbr0); - - ASSERT_TRUE(ttbr0 == __get_TTBR0()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_DACR(void) { - uint32_t dacr = __get_DACR(); - __set_DACR(dacr); - - ASSERT_TRUE(dacr == __get_DACR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_SCTLR(void) { - uint32_t sctlr = __get_SCTLR(); - __set_SCTLR(sctlr); - - ASSERT_TRUE(sctlr == __get_SCTLR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_ACTRL(void) { - uint32_t actrl = __get_ACTRL(); - __set_ACTRL(actrl); - - ASSERT_TRUE(actrl == __get_ACTRL()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_MPIDR(void) { - uint32_t mpidr = __get_MPIDR(); - - ASSERT_TRUE(mpidr == __get_MPIDR()); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -static uint8_t vectorRAM[32U] __attribute__((aligned(32U))); - -void TC_CoreAFunc_VBAR(void) { - uint32_t vbar = __get_VBAR(); - - memcpy(vectorRAM, (void*)vbar, sizeof(vectorRAM)); - - __set_VBAR((uint32_t)vectorRAM); - ASSERT_TRUE(((uint32_t)vectorRAM) == __get_VBAR()); - - __set_VBAR(vbar); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_CoreAFunc_MVBAR(void) { - uint32_t mvbar = __get_MVBAR(); - - memcpy(vectorRAM, (void*)mvbar, sizeof(vectorRAM)); - - __set_MVBAR((uint32_t)vectorRAM); - ASSERT_TRUE(((uint32_t)vectorRAM) == __get_MVBAR()); - - __set_MVBAR(mvbar); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ - -void TC_CoreAFunc_FPU_Enable(void) { - uint32_t fpexc = __get_FPEXC(); - __set_FPEXC(fpexc & ~0x40000000u); // disable FPU - - uint32_t cp15; - __get_CP(15, 0, cp15, 1, 0, 2); - - cp15 &= ~0x00F00000u; - __set_CP(15, 0, cp15, 1, 0, 2); // disable FPU access - - __FPU_Enable(); - - __get_CP(15, 0, cp15, 1, 0, 2); - ASSERT_TRUE((cp15 & 0x00F00000u) == 0x00F00000u); - - fpexc = __get_FPEXC(); - ASSERT_TRUE((fpexc & 0x40000000u) == 0x40000000u); -} - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreFunc.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreFunc.c deleted file mode 100644 index fe98bbe..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreFunc.c +++ /dev/null @@ -1,723 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_CoreFunc.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 - 2023 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -static volatile uint32_t irqTaken = 0U; -#if defined(__CORTEX_M) && (__CORTEX_M > 0) -static volatile uint32_t irqActive = 0U; -#endif - -static void TC_CoreFunc_EnDisIRQIRQHandler(void) { - ++irqTaken; -#if defined(__CORTEX_M) && (__CORTEX_M > 0) - irqActive = NVIC_GetActive(Interrupt0_IRQn); -#endif -} - -static volatile uint32_t irqIPSR = 0U; -static volatile uint32_t irqXPSR = 0U; - -static void TC_CoreFunc_IPSR_IRQHandler(void) { - irqIPSR = __get_IPSR(); - irqXPSR = __get_xPSR(); -} - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_EnDisIRQ -\details -Check expected behavior of interrupt related control functions: -- __disable_irq() and __enable_irq() -- NVIC_EnableIRQ, NVIC_DisableIRQ, and NVIC_GetEnableIRQ -- NVIC_SetPendingIRQ, NVIC_ClearPendingIRQ, and NVIC_GetPendingIRQ -- NVIC_GetActive (not on Cortex-M0/M0+) -*/ -void TC_CoreFunc_EnDisIRQ (void) -{ - // Globally disable all interrupt servicing - __disable_irq(); - - // Enable the interrupt - NVIC_EnableIRQ(Interrupt0_IRQn); - ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) != 0U); - - // Clear its pending state - NVIC_ClearPendingIRQ(Interrupt0_IRQn); - ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U); - - // Register test interrupt handler. - TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler; - irqTaken = 0U; -#if defined(__CORTEX_M) && (__CORTEX_M > 0) - irqActive = UINT32_MAX; -#endif - - // Set the interrupt pending state - NVIC_SetPendingIRQ(Interrupt0_IRQn); - for(uint32_t i = 10U; i > 0U; --i) {__NOP();} - - // Interrupt is not taken - ASSERT_TRUE(irqTaken == 0U); - ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U); -#if defined(__CORTEX_M) && (__CORTEX_M > 0) - ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U); -#endif - - // Globally enable interrupt servicing - __enable_irq(); - - for(uint32_t i = 10U; i > 0U; --i) {__NOP();} - - // Interrupt was taken - ASSERT_TRUE(irqTaken == 1U); -#if defined(__CORTEX_M) && (__CORTEX_M > 0) - ASSERT_TRUE(irqActive != 0U); - ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U); -#endif - - // Interrupt it not pending anymore. - ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U); - - // Disable interrupt - NVIC_DisableIRQ(Interrupt0_IRQn); - ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) == 0U); - - // Set interrupt pending - NVIC_SetPendingIRQ(Interrupt0_IRQn); - for(uint32_t i = 10U; i > 0U; --i) {__NOP();} - - // Interrupt is not taken again - ASSERT_TRUE(irqTaken == 1U); - ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U); - - // Clear interrupt pending - NVIC_ClearPendingIRQ(Interrupt0_IRQn); - for(uint32_t i = 10U; i > 0U; --i) {__NOP();} - - // Interrupt it not pending anymore. - ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U); - - // Globally disable interrupt servicing - __disable_irq(); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_IRQPrio -\details -Check expected behavior of interrupt priority control functions: -- NVIC_SetPriority, NVIC_GetPriority -*/ -void TC_CoreFunc_IRQPrio (void) -{ - /* Test Exception Priority */ - uint32_t orig = NVIC_GetPriority(SVCall_IRQn); - - NVIC_SetPriority(SVCall_IRQn, orig+1U); - uint32_t prio = NVIC_GetPriority(SVCall_IRQn); - - ASSERT_TRUE(prio == orig+1U); - - NVIC_SetPriority(SVCall_IRQn, orig); - - /* Test Interrupt Priority */ - orig = NVIC_GetPriority(Interrupt0_IRQn); - - NVIC_SetPriority(Interrupt0_IRQn, orig+1U); - prio = NVIC_GetPriority(Interrupt0_IRQn); - - ASSERT_TRUE(prio == orig+1U); - - NVIC_SetPriority(Interrupt0_IRQn, orig); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** Helper function for TC_CoreFunc_EncDecIRQPrio -\details -The helper encodes and decodes the given priority configuration. -\param[in] prigroup The PRIGROUP setting to be considered for encoding/decoding. -\param[in] pre The preempt priority value. -\param[in] sub The subpriority value. -*/ -static void TC_CoreFunc_EncDecIRQPrio_Step(uint32_t prigroup, uint32_t pre, uint32_t sub) { - uint32_t prio = NVIC_EncodePriority(prigroup, pre, sub); - - uint32_t ret_pre = UINT32_MAX; - uint32_t ret_sub = UINT32_MAX; - - NVIC_DecodePriority(prio, prigroup, &ret_pre, &ret_sub); - - ASSERT_TRUE(ret_pre == pre); - ASSERT_TRUE(ret_sub == sub); -} - -/** -\brief Test case: TC_CoreFunc_EncDecIRQPrio -\details -Check expected behavior of interrupt priority encoding/decoding functions: -- NVIC_EncodePriority, NVIC_DecodePriority -*/ -void TC_CoreFunc_EncDecIRQPrio (void) -{ - /* Check only the valid range of PRIGROUP and preempt-/sub-priority values. */ - static const uint32_t priobits = (__NVIC_PRIO_BITS > 7U) ? 7U : __NVIC_PRIO_BITS; - for(uint32_t prigroup = 7U-priobits; prigroup<7U; prigroup++) { - for(uint32_t pre = 0U; pre<(128U>>prigroup); pre++) { - for(uint32_t sub = 0U; sub<(256U>>(8U-__NVIC_PRIO_BITS+7U-prigroup)); sub++) { - TC_CoreFunc_EncDecIRQPrio_Step(prigroup, pre, sub); - } - } - } -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_IRQVect -\details -Check expected behavior of interrupt vector relocation functions: -- NVIC_SetVector, NVIC_GetVector -*/ -void TC_CoreFunc_IRQVect(void) { -#if defined(__VTOR_PRESENT) && __VTOR_PRESENT - /* relocate vector table */ - extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - static VECTOR_TABLE_Type vectors[sizeof(__VECTOR_TABLE)/sizeof(__VECTOR_TABLE[0])] __ALIGNED(1024) __NO_INIT; - memcpy(vectors, __VECTOR_TABLE, sizeof(__VECTOR_TABLE)); - - const uint32_t orig_vtor = SCB->VTOR; - const uint32_t vtor = ((uint32_t)vectors) & SCB_VTOR_TBLOFF_Msk; - SCB->VTOR = vtor; - - ASSERT_TRUE(vtor == SCB->VTOR); - - /* check exception vectors */ - extern void HardFault_Handler(void); - extern void SVC_Handler(void); - extern void PendSV_Handler(void); - extern void SysTick_Handler(void); - - ASSERT_TRUE(NVIC_GetVector(HardFault_IRQn) == (uint32_t)HardFault_Handler); - ASSERT_TRUE(NVIC_GetVector(SVCall_IRQn) == (uint32_t)SVC_Handler); - ASSERT_TRUE(NVIC_GetVector(PendSV_IRQn) == (uint32_t)PendSV_Handler); - ASSERT_TRUE(NVIC_GetVector(SysTick_IRQn) == (uint32_t)SysTick_Handler); - - /* reconfigure WDT IRQ vector */ - extern void Interrupt0_Handler(void); - - const uint32_t wdtvec = NVIC_GetVector(Interrupt0_IRQn); - ASSERT_TRUE(wdtvec == (uint32_t)Interrupt0_Handler); - - NVIC_SetVector(Interrupt0_IRQn, wdtvec + 32U); - - ASSERT_TRUE(NVIC_GetVector(Interrupt0_IRQn) == (wdtvec + 32U)); - - /* restore vector table */ - SCB->VTOR = orig_vtor; -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_GetCtrl -\details -- Check if __set_CONTROL and __get_CONTROL() sets/gets control register -*/ -void TC_CoreFunc_Control (void) { - // don't use stack for this variables - static uint32_t orig; - static uint32_t ctrl; - static uint32_t result; - - orig = __get_CONTROL(); - ctrl = orig; - result = UINT32_MAX; - -#ifdef CONTROL_SPSEL_Msk - // SPSEL set to 0 (MSP) - ASSERT_TRUE((ctrl & CONTROL_SPSEL_Msk) == 0U); - - // SPSEL set to 1 (PSP) - ctrl |= CONTROL_SPSEL_Msk; - - // Move MSP to PSP - __set_PSP(__get_MSP()); -#endif - - __set_CONTROL(ctrl); - __ISB(); - - result = __get_CONTROL(); - - __set_CONTROL(orig); - __ISB(); - - ASSERT_TRUE(result == ctrl); - ASSERT_TRUE(__get_CONTROL() == orig); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_IPSR -\details -- Check if __get_IPSR intrinsic is available -- Check if __get_xPSR intrinsic is available -- Result differentiates between thread and exception modes -*/ -void TC_CoreFunc_IPSR (void) { - uint32_t result = __get_IPSR(); - ASSERT_TRUE(result == 0U); // Thread Mode - - result = __get_xPSR(); - ASSERT_TRUE((result & xPSR_ISR_Msk) == 0U); // Thread Mode - - TST_IRQHandler = TC_CoreFunc_IPSR_IRQHandler; - irqIPSR = 0U; - irqXPSR = 0U; - - NVIC_ClearPendingIRQ(Interrupt0_IRQn); - NVIC_EnableIRQ(Interrupt0_IRQn); - __enable_irq(); - - NVIC_SetPendingIRQ(Interrupt0_IRQn); - for(uint32_t i = 10U; i > 0U; --i) {__NOP();} - - __disable_irq(); - NVIC_DisableIRQ(Interrupt0_IRQn); - - ASSERT_TRUE(irqIPSR != 0U); // Exception Mode - ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ - -#if defined(__CC_ARM) -#define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn) -#define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn) -#elif defined( __GNUC__ ) && (!defined(__ti__)) && (!defined(__ARMCC_VERSION)) && (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) -#define SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") -#define ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") -#elif defined(_lint) -//lint -save -e(9026) allow function-like macro -#define SUBS(Rd, Rm, Rn) ((Rd) = (Rm) - (Rn)) -#define ADDS(Rd, Rm, Rn) ((Rd) = (Rm) + (Rn)) -//lint -restore -#else -#define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") -#define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") -#endif - -/** -\brief Test case: TC_CoreFunc_APSR -\details -- Check if __get_APSR intrinsic is available -- Check if __get_xPSR intrinsic is available -- Check negative, zero and overflow flags -*/ -void TC_CoreFunc_APSR (void) { - volatile uint32_t result; - //lint -esym(838, Rm) unused values - //lint -esym(438, Rm) unused values - - // Check negative flag - volatile int32_t Rm = 5; - volatile int32_t Rn = 7; - SUBS(Rm, Rm, Rn); - result = __get_APSR(); - ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk); - - Rm = 5; - Rn = 7; - SUBS(Rm, Rm, Rn); - result = __get_xPSR(); - ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk); - - // Check zero and compare flag - Rm = 5; - SUBS(Rm, Rm, Rm); - result = __get_APSR(); - ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk); - ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk); - - Rm = 5; - SUBS(Rm, Rm, Rm); - result = __get_xPSR(); - ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk); - ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk); - - // Check overflow flag - Rm = 5; - Rn = INT32_MAX; - ADDS(Rm, Rm, Rn); - result = __get_APSR(); - ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk); - - Rm = 5; - Rn = INT32_MAX; - ADDS(Rm, Rm, Rn); - result = __get_xPSR(); - ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_PSP -\details -- Check if __get_PSP and __set_PSP intrinsic can be used to manipulate process stack pointer. -*/ -void TC_CoreFunc_PSP (void) { - // don't use stack for this variables - static uint32_t orig; - static uint32_t psp; - static uint32_t result; - - orig = __get_PSP(); - - psp = orig + 0x12345678U; - __set_PSP(psp); - - result = __get_PSP(); - - __set_PSP(orig); - - ASSERT_TRUE(result == psp); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_MSP -\details -- Check if __get_MSP and __set_MSP intrinsic can be used to manipulate main stack pointer. -*/ -void TC_CoreFunc_MSP (void) { - // don't use stack for this variables - static uint32_t orig; - static uint32_t msp; - static uint32_t result; - static uint32_t ctrl; - - ctrl = __get_CONTROL(); - orig = __get_MSP(); - - __set_PSP(orig); - __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP - - msp = orig + 0x12345678U; - __set_MSP(msp); - - result = __get_MSP(); - - __set_MSP(orig); - - __set_CONTROL(ctrl); - - ASSERT_TRUE(result == msp); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_PSPLIM -\details -- Check if __get_PSPLIM and __set_PSPLIM intrinsic can be used to manipulate process stack pointer limit. -*/ -void TC_CoreFunc_PSPLIM (void) { -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - // don't use stack for this variables - static uint32_t orig; - static uint32_t psplim; - static uint32_t result; - - orig = __get_PSPLIM(); - - psplim = orig + 0x12345678U; - __set_PSPLIM(psplim); - - result = __get_PSPLIM(); - - __set_PSPLIM(orig); - -#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - ASSERT_TRUE(result == 0U); -#else - ASSERT_TRUE(result == psplim); -#endif - -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_PSPLIM_NS -\details -- Check if __TZ_get_PSPLIM_NS and __TZ_set_PSPLIM_NS intrinsic can be used to manipulate process stack pointer limit. -*/ -void TC_CoreFunc_PSPLIM_NS (void) { -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) - uint32_t orig; - uint32_t psplim; - uint32_t result; - - orig = __TZ_get_PSPLIM_NS(); - - psplim = orig + 0x12345678U; - __TZ_set_PSPLIM_NS(psplim); - - result = __TZ_get_PSPLIM_NS(); - - __TZ_set_PSPLIM_NS(orig); - -#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - ASSERT_TRUE(result == 0U); -#else - ASSERT_TRUE(result == psplim); -#endif -#endif - -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_MSPLIM -\details -- Check if __get_MSPLIM and __set_MSPLIM intrinsic can be used to manipulate main stack pointer limit. -*/ -void TC_CoreFunc_MSPLIM (void) { -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - // don't use stack for this variables - static uint32_t orig; - static uint32_t msplim; - static uint32_t result; - static uint32_t ctrl; - - ctrl = __get_CONTROL(); - __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP - - orig = __get_MSPLIM(); - - msplim = orig + 0x12345678U; - __set_MSPLIM(msplim); - - result = __get_MSPLIM(); - - __set_MSPLIM(orig); - - __set_CONTROL(ctrl); - -#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - ASSERT_TRUE(result == 0U); -#else - ASSERT_TRUE(result == msplim); -#endif - -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_MSPLIM_NS -\details -- Check if __TZ_get_MSPLIM_NS and __TZ_set_MSPLIM_NS intrinsic can be used to manipulate process stack pointer limit. -*/ -void TC_CoreFunc_MSPLIM_NS (void) { -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) - uint32_t orig; - uint32_t msplim; - uint32_t result; - - orig = __TZ_get_MSPLIM_NS(); - - msplim = orig + 0x12345678U; - __TZ_set_MSPLIM_NS(msplim); - - result = __TZ_get_MSPLIM_NS(); - - __TZ_set_MSPLIM_NS(orig); - -#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - ASSERT_TRUE(result == 0U); -#else - ASSERT_TRUE(result == msplim); -#endif -#endif - -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_PRIMASK -\details -- Check if __get_PRIMASK and __set_PRIMASK intrinsic can be used to manipulate PRIMASK. -- Check if __enable_irq and __disable_irq are reflected in PRIMASK. -*/ -void TC_CoreFunc_PRIMASK (void) { - uint32_t orig = __get_PRIMASK(); - - // toggle primask - uint32_t primask = (orig & ~0x01U) | (~orig & 0x01U); - - __set_PRIMASK(primask); - uint32_t result = __get_PRIMASK(); - ASSERT_TRUE(result == primask); - - __disable_irq(); - result = __get_PRIMASK(); - ASSERT_TRUE((result & 0x01U) == 1U); - - __enable_irq(); - result = __get_PRIMASK(); - ASSERT_TRUE((result & 0x01U) == 0U); - - __disable_irq(); - result = __get_PRIMASK(); - ASSERT_TRUE((result & 0x01U) == 1U); - - __set_PRIMASK(orig); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_FAULTMASK -\details -- Check if __get_FAULTMASK and __set_FAULTMASK intrinsic can be used to manipulate FAULTMASK. -- Check if __enable_fault_irq and __disable_fault_irq are reflected in FAULTMASK. -*/ -void TC_CoreFunc_FAULTMASK (void) { -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - - uint32_t orig = __get_FAULTMASK(); - - // toggle faultmask - uint32_t faultmask = (orig & ~0x01U) | (~orig & 0x01U); - - __set_FAULTMASK(faultmask); - uint32_t result = __get_FAULTMASK(); - ASSERT_TRUE(result == faultmask); - - __disable_fault_irq(); - result = __get_FAULTMASK(); - ASSERT_TRUE((result & 0x01U) == 1U); - - __enable_fault_irq(); - result = __get_FAULTMASK(); - ASSERT_TRUE((result & 0x01U) == 0U); - - __disable_fault_irq(); - result = __get_FAULTMASK(); - ASSERT_TRUE((result & 0x01U) == 1U); - - __set_FAULTMASK(orig); - -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_BASEPRI -\details -- Check if __get_BASEPRI and __set_BASEPRI intrinsic can be used to manipulate BASEPRI. -- Check if __set_BASEPRI_MAX intrinsic can be used to manipulate BASEPRI. -*/ -void TC_CoreFunc_BASEPRI(void) { -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - - uint32_t orig = __get_BASEPRI(); - - uint32_t basepri = ~orig & 0x80U; - __set_BASEPRI(basepri); - uint32_t result = __get_BASEPRI(); - - ASSERT_TRUE(result == basepri); - - __set_BASEPRI(orig); - - __set_BASEPRI_MAX(basepri); - result = __get_BASEPRI(); - - ASSERT_TRUE(result == basepri); - -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_FPUType -\details -Check SCB_GetFPUType returns information. -*/ -void TC_CoreFunc_FPUType(void) { - uint32_t fpuType = SCB_GetFPUType(); -#if defined(__FPU_PRESENT) && (__FPU_PRESENT != 0) - ASSERT_TRUE(fpuType > 0U); -#else - ASSERT_TRUE(fpuType == 0U); -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreFunc_FPSCR -\details -- Check if __get_FPSCR and __set_FPSCR intrinsics can be used -*/ -void TC_CoreFunc_FPSCR(void) { - uint32_t fpscr = __get_FPSCR(); - __ISB(); - __DSB(); - - __set_FPSCR(~fpscr); - __ISB(); - __DSB(); - - uint32_t result = __get_FPSCR(); - - __set_FPSCR(fpscr); - -#if (defined (__FPU_USED ) && (__FPU_USED == 1U)) - ASSERT_TRUE(result != fpscr); -#else - ASSERT_TRUE(result == 0U); -#endif -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreInstr.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreInstr.c deleted file mode 100644 index eaf49cd..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreInstr.c +++ /dev/null @@ -1,821 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_CoreInstr.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 - 2021 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -#if defined(__CORTEX_M) -#elif defined(__CORTEX_A) -#include "irq_ctrl.h" -#else -#error __CORTEX_M or __CORTEX_A must be defined! -#endif - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_NOP -\details -- Check if __NOP instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_NOP (void) { - __NOP(); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_SEV -\details -- Check if __SEV instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_SEV (void) { - __SEV(); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_BKPT -\details -- Check if __BKPT instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_BKPT (void) { - __BKPT(0xABU); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_ISB -\details -- Check if __ISB instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_ISB (void) { - __ISB(); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_DSB -\details -- Check if __DSB instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_DSB (void) { - __DSB(); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_DMB -\details -- Check if __DNB instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_DMB (void) { - __DMB(); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_WFI -\details -- Check if __WFI instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_WFI (void) { - __WFI(); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_WFE -\details -- Check if __WFE instrinsic is available -- No real assertion is deployed, just a compile time check. -*/ -void TC_CoreInstr_WFE (void) { - __WFE(); - ASSERT_TRUE(1U == 1U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_REV -\details -- Check if __REV instrinsic swaps all bytes in a word. -*/ -void TC_CoreInstr_REV (void) { - volatile uint32_t op1_u32; - volatile uint32_t res_u32; - - op1_u32 = 0x47110815U; - res_u32 = __REV(op1_u32); - ASSERT_TRUE(res_u32 == 0x15081147U); - - op1_u32 = 0x80000000U; - res_u32 = __REV(op1_u32); - ASSERT_TRUE(res_u32 == 0x00000080U); - - op1_u32 = 0x00000080U; - res_u32 = __REV(op1_u32); - ASSERT_TRUE(res_u32 == 0x80000000U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_REV16 -\details -- Check if __REV16 instrinsic swaps the bytes in both halfwords independendly. -*/ -void TC_CoreInstr_REV16(void) { - volatile uint32_t op1_u32; - volatile uint32_t res_u32; - - op1_u32 = 0x47110815U; - res_u32 = __REV16(op1_u32); - ASSERT_TRUE(res_u32 == 0x11471508U); - - op1_u32 = 0x00001234U; - res_u32 = __REV16(op1_u32); - ASSERT_TRUE(res_u32 == 0x00003412U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_REVSH -\details -- Check if __REVSH instrinsic swaps bytes in a signed halfword keeping the sign. -*/ -void TC_CoreInstr_REVSH(void) { - volatile int16_t value = 0U; - int16_t result = 0U; - - value = 0x4711; - result = __REVSH(value); - ASSERT_TRUE(result == 0x1147); - - value = (int16_t)0x8000; - result = __REVSH(value); - ASSERT_TRUE(result == 0x0080); - - value = 0x0080; - result = __REVSH(value); - ASSERT_TRUE(result == (int16_t)0x8000); - - value = -0x1234; - result = __REVSH(value); - ASSERT_TRUE(result == (int16_t)0xcced); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_RBIT -\details -- Check if __RBIT instrinsic revserses the bit order of arbitrary words. -*/ -void TC_CoreInstr_RBIT (void) { - volatile uint32_t value = 0U; - uint32_t result = 0U; - - value = 0xAAAAAAAAU; - result = __RBIT(value); - ASSERT_TRUE(result == 0x55555555U); - - value = 0x55555555U; - result = __RBIT(value); - ASSERT_TRUE(result == 0xAAAAAAAAU); - - value = 0x00000001U; - result = __RBIT(value); - ASSERT_TRUE(result == 0x80000000U); - - value = 0x80000000U; - result = __RBIT(value); - ASSERT_TRUE(result == 0x00000001U); - - value = 0xDEADBEEFU; - result = __RBIT(value); - ASSERT_TRUE(result == 0xF77DB57BU); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_ROR -\details -- Check if __ROR instrinsic moves all bits as expected. -*/ -void TC_CoreInstr_ROR(void) { - volatile uint32_t value = 0U; - uint32_t result = 0U; - - value = 0x00000001U; - result = __ROR(value, 1U); - ASSERT_TRUE(result == 0x80000000U); - - value = 0x80000000U; - result = __ROR(value, 1U); - ASSERT_TRUE(result == 0x40000000U); - - value = 0x40000000U; - result = __ROR(value, 30U); - ASSERT_TRUE(result == 0x00000001U); - - value = 0x00000001U; - result = __ROR(value, 32U); - ASSERT_TRUE(result == 0x00000001U); - - value = 0x08154711U; - result = __ROR(value, 8U); - ASSERT_TRUE(result == 0x11081547U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_CLZ -\details -- Check if __CLZ instrinsic counts leading zeros. -*/ -void TC_CoreInstr_CLZ (void) { - volatile uint32_t value = 0U; - uint32_t result = 0U; - - value = 0x00000000U; - result = __CLZ(value); - ASSERT_TRUE(result == 32); - - value = 0x00000001U; - result = __CLZ(value); - ASSERT_TRUE(result == 31); - - value = 0x40000000U; - result = __CLZ(value); - ASSERT_TRUE(result == 1); - - value = 0x80000000U; - result = __CLZ(value); - ASSERT_TRUE(result == 0); - - value = 0xFFFFFFFFU; - result = __CLZ(value); - ASSERT_TRUE(result == 0); - - value = 0x80000001U; - result = __CLZ(value); - ASSERT_TRUE(result == 0); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_SSAT -\details -- Check if __SSAT instrinsic saturates signed integer values. -*/ -void TC_CoreInstr_SSAT (void) { - volatile int32_t value = 0; - int32_t result = 0; - - value = INT32_MAX; - result = __SSAT(value, 32U); - ASSERT_TRUE(result == INT32_MAX); - - value = INT32_MAX; - result = __SSAT(value, 16U); - ASSERT_TRUE(result == INT16_MAX); - - value = INT32_MAX; - result = __SSAT(value, 8U); - ASSERT_TRUE(result == INT8_MAX); - - value = INT32_MAX; - result = __SSAT(value, 1U); - ASSERT_TRUE(result == 0); - - value = INT32_MIN; - result = __SSAT(value, 32U); - ASSERT_TRUE(result == INT32_MIN); - - value = INT32_MIN; - result = __SSAT(value, 16U); - ASSERT_TRUE(result == INT16_MIN); - - value = INT32_MIN; - result = __SSAT(value, 8U); - ASSERT_TRUE(result == INT8_MIN); - - value = INT32_MIN; - result = __SSAT(value, 1U); - ASSERT_TRUE(result == -1); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_USAT -\details -- Check if __USAT instrinsic saturates unsigned integer values. -*/ -void TC_CoreInstr_USAT (void) { - volatile int32_t value = 0U; - uint32_t result = 0U; - - value = INT32_MAX; - result = __USAT(value, 31U); - ASSERT_TRUE(result == (UINT32_MAX >> 1U)); - - value = INT32_MAX; - result = __USAT(value, 16U); - ASSERT_TRUE(result == UINT16_MAX); - - value = INT32_MAX; - result = __USAT(value, 8U); - ASSERT_TRUE(result == UINT8_MAX); - - value = INT32_MAX; - result = __USAT(value, 0U); - ASSERT_TRUE(result == 0U); - - value = INT32_MIN; - result = __USAT(value, 31U); - ASSERT_TRUE(result == 0U); - - value = INT32_MIN; - result = __USAT(value, 16U); - ASSERT_TRUE(result == 0U); - - value = INT32_MIN; - result = __USAT(value, 8U); - ASSERT_TRUE(result == 0U); - - value = INT32_MIN; - result = __USAT(value, 0U); - ASSERT_TRUE(result == 0U); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_CoreInstr_RRX -\details -- Check if __USAT instrinsic saturates unsigned integer values. -*/ -void TC_CoreInstr_RRX (void) { -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - - volatile uint32_t value = 0U; - volatile uint32_t result = 0U; - volatile xPSR_Type xPSR; - - value = 0x80000002; - xPSR.w = __get_xPSR(); - result = __RRX(value); - ASSERT_TRUE(result == (0x40000001 | (uint32_t)(xPSR.b.C << 31))); -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined(__CORTEX_A) ) ) - -/// Exclusive byte value -static volatile uint8_t TC_CoreInstr_LoadStoreExclusive_byte = 0x47U; - -/// Exclusive halfword value -static volatile uint16_t TC_CoreInstr_LoadStoreExclusive_hword = 0x0815U; - -/// Exclusive word value -static volatile uint32_t TC_CoreInstr_LoadStoreExclusive_word = 0x08154711U; - -/** -\brief Interrupt function for TC_CoreInstr_LoadStoreExclusive -\details -The interrupt manipulates all the global data -which disrupts the exclusive sequences in the test -*/ -static void TC_CoreInstr_LoadStoreExclusive_IRQHandler(void) { - - const uint8_t b = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); - __STREXB((uint8_t)~b, &TC_CoreInstr_LoadStoreExclusive_byte); - - const uint16_t hw = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); - __STREXH((uint16_t)~hw, &TC_CoreInstr_LoadStoreExclusive_hword); - - const uint32_t w = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); - __STREXW((uint32_t)~w, &TC_CoreInstr_LoadStoreExclusive_word); -} - -/** -\brief Helper function for TC_CoreInstr_LoadStoreExclusive to enable test interrupt. -\details -This helper function implements interrupt enabling according to target -architecture, i.e. Cortex-A or Cortex-M. -*/ -static void TC_CoreInstr_LoadStoreExclusive_IRQEnable(void) { -#if defined(__CORTEX_M) - TST_IRQHandler = TC_CoreInstr_LoadStoreExclusive_IRQHandler; - NVIC_EnableIRQ(Interrupt0_IRQn); -#elif defined(__CORTEX_A) - IRQ_SetHandler(SGI0_IRQn, TC_CoreInstr_LoadStoreExclusive_IRQHandler); - IRQ_Enable(SGI0_IRQn); -#else - #error __CORTEX_M or __CORTEX_A must be defined! -#endif - __enable_irq(); -} - -/** -\brief Helper function for TC_CoreInstr_LoadStoreExclusive to set test interrupt pending. -\details -This helper function implements set pending the test interrupt according to target -architecture, i.e. Cortex-A or Cortex-M. -*/ -static void TC_CoreInstr_LoadStoreExclusive_IRQPend(void) { -#if defined(__CORTEX_M) - NVIC_SetPendingIRQ(Interrupt0_IRQn); -#elif defined(__CORTEX_A) - IRQ_SetPending(SGI0_IRQn); -#else - #error __CORTEX_M or __CORTEX_A must be defined! -#endif - for(uint32_t i = 10U; i > 0U; --i) {} -} - -/** -\brief Helper function for TC_CoreInstr_LoadStoreExclusive to disable test interrupt. -\details -This helper function implements interrupt disabling according to target -architecture, i.e. Cortex-A or Cortex-M. -*/ -static void TC_CoreInstr_LoadStoreExclusive_IRQDisable(void) { - __disable_irq(); -#if defined(__CORTEX_M) - NVIC_DisableIRQ(Interrupt0_IRQn); - TST_IRQHandler = NULL; -#elif defined(__CORTEX_A) - IRQ_Disable(SGI0_IRQn); - IRQ_SetHandler(SGI0_IRQn, NULL); -#else - #error __CORTEX_M or __CORTEX_A must be defined! -#endif -} -#endif - -/** -\brief Test case: TC_CoreInstr_LoadStoreExclusive -\details -Checks exclusive load and store instructions: -- LDREXB, LDREXH, LDREXW -- STREXB, STREXH, STREXW -- CLREX -*/ -void TC_CoreInstr_LoadStoreExclusive (void) { -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined(__CORTEX_A) ) ) - uint8_t u8, u8Inv; - uint16_t u16, u16Inv; - uint32_t u32, u32Inv; - uint32_t result; - - /* 1. Test exclusives without interruption */ - u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); - ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte); - - result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte); - ASSERT_TRUE(result == 0U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8+1U); - - u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); - ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword); - - result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword); - ASSERT_TRUE(result == 0U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16+1U); - - u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); - ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word); - - result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word); - ASSERT_TRUE(result == 0U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32+1U); - - /* 2. Test exclusives with clear */ - u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); - ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte); - - __CLREX(); - - result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte); - ASSERT_TRUE(result == 1U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8); - - u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); - ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword); - - __CLREX(); - - result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword); - ASSERT_TRUE(result == 1U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16); - - u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); - ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word); - - __CLREX(); - - result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word); - ASSERT_TRUE(result == 1U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32); - - /* 3. Test exclusives with interruption */ - TC_CoreInstr_LoadStoreExclusive_IRQEnable(); - - u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); - ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte); - - TC_CoreInstr_LoadStoreExclusive_IRQPend(); - - result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte); - ASSERT_TRUE(result == 1U); - u8Inv = (uint8_t)~u8; - ASSERT_TRUE(u8Inv == TC_CoreInstr_LoadStoreExclusive_byte); - - u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); - ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword); - - TC_CoreInstr_LoadStoreExclusive_IRQPend(); - - result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword); - ASSERT_TRUE(result == 1U); - u16Inv = (uint16_t)~u16; - ASSERT_TRUE(u16Inv == TC_CoreInstr_LoadStoreExclusive_hword); - - u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); - ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word); - - TC_CoreInstr_LoadStoreExclusive_IRQPend(); - - result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word); - ASSERT_TRUE(result == 1U); - u32Inv = (uint32_t)~u32; - ASSERT_TRUE(u32Inv == TC_CoreInstr_LoadStoreExclusive_word); - - TC_CoreInstr_LoadStoreExclusive_IRQDisable(); -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/// byte value unprivileged access -static volatile uint8_t TC_CoreInstr_LoadStoreUnpriv_byte = 0x47U; - -/// halfword value unprivileged access -static volatile uint16_t TC_CoreInstr_LoadStoreUnpriv_hword = 0x0815U; - -/// word value unprivileged access -static volatile uint32_t TC_CoreInstr_LoadStoreUnpriv_word = 0x08154711U; -#endif - - -/** -\brief Test case: TC_CoreInstr_LoadStoreUnpriv -\details -Checks load/store unprivileged instructions: -- LDRBT, LDRHT, LDRT -- STRBT, STRHT, STRT -*/ -void TC_CoreInstr_LoadStoreUnpriv (void) { -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - uint8_t u8 = 0U; - uint16_t u16 = 0U; - uint32_t u32 = 0U; - - /* 1. Test without interruption */ - u8 = __LDRBT(&TC_CoreInstr_LoadStoreUnpriv_byte); - ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreUnpriv_byte); - - __STRBT(u8+1U, &TC_CoreInstr_LoadStoreUnpriv_byte); - ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_byte == u8+1U); - - u16 = __LDRHT(&TC_CoreInstr_LoadStoreUnpriv_hword); - ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreUnpriv_hword); - - __STRHT(u16+1U, &TC_CoreInstr_LoadStoreUnpriv_hword); - ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_hword == u16+1U); - - u32 = __LDRT(&TC_CoreInstr_LoadStoreUnpriv_word); - ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreUnpriv_word); - - __STRT(u32+1U, &TC_CoreInstr_LoadStoreUnpriv_word); - ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_word == u32+1U); -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/// byte value unprivileged access -static volatile uint8_t TC_CoreInstr_LoadStoreAcquire_byte = 0x47U; - -/// halfword value unprivileged access -static volatile uint16_t TC_CoreInstr_LoadStoreAcquire_hword = 0x0815U; - -/// word value unprivileged access -static volatile uint32_t TC_CoreInstr_LoadStoreAcquire_word = 0x08154711U; -#endif - - -/** -\brief Test case: TC_CoreInstr_LoadStoreAquire -\details -Checks Load-Acquire and Store-Release instructions: -- LDAB, LDAH, LDA -- STLB, STLH, STL -*/ -void TC_CoreInstr_LoadStoreAcquire (void) { -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - uint8_t u8 = 0U; - uint16_t u16 = 0U; - uint32_t u32 = 0U; - - /* 1. Test without interruption */ - u8 = __LDAB(&TC_CoreInstr_LoadStoreAcquire_byte); - ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquire_byte); - - __STLB(u8+1U, &TC_CoreInstr_LoadStoreAcquire_byte); - ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_byte == u8+1U); - - u16 = __LDAH(&TC_CoreInstr_LoadStoreAcquire_hword); - ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquire_hword); - - __STLH(u16+1U, &TC_CoreInstr_LoadStoreAcquire_hword); - ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_hword == u16+1U); - - u32 = __LDA(&TC_CoreInstr_LoadStoreAcquire_word); - ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquire_word); - - __STL(u32+1U, &TC_CoreInstr_LoadStoreAcquire_word); - ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_word == u32+1U); -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/// byte value unprivileged access -static volatile uint8_t TC_CoreInstr_LoadStoreAcquireExclusive_byte = 0x47U; - -/// halfword value unprivileged access -static volatile uint16_t TC_CoreInstr_LoadStoreAcquireExclusive_hword = 0x0815U; - -/// word value unprivileged access -static volatile uint32_t TC_CoreInstr_LoadStoreAcquireExclusive_word = 0x08154711U; -#endif - - -/** -\brief Test case: TC_CoreInstr_LoadStoreAquire -\details -Checks Load-Acquire and Store-Release exclusive instructions: -- LDAEXB, LDAEXH, LDAEX -- STLEXB, STLEXH, STLEX -*/ -void TC_CoreInstr_LoadStoreAcquireExclusive (void) { -#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - uint8_t u8 = 0U; - uint16_t u16 = 0U; - uint32_t u32 = 0U; - uint32_t result = 0U; - - /* 1. Test without interruption */ - u8 = __LDAEXB(&TC_CoreInstr_LoadStoreAcquireExclusive_byte); - ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquireExclusive_byte); - - result = __STLEXB(u8+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_byte); - ASSERT_TRUE(result == 0U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_byte == u8+1U); - - u16 = __LDAEXH(&TC_CoreInstr_LoadStoreAcquireExclusive_hword); - ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquireExclusive_hword); - - result = __STLEXH(u16+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_hword); - ASSERT_TRUE(result == 0U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_hword == u16+1U); - - u32 = __LDAEX(&TC_CoreInstr_LoadStoreAcquireExclusive_word); - ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquireExclusive_word); - - result = __STLEX(u32+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_word); - ASSERT_TRUE(result == 0U); - ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_word == u32+1U); -#endif -} - - -/** -\brief Test case: TC_CoreInstr_UnalignedUint16 -\details -Checks macro functions to access unaligned uint16_t values: -- __UNALIGNED_UINT16_READ -- __UNALIGNED_UINT16_WRITE -*/ -void TC_CoreInstr_UnalignedUint16(void) { - uint8_t buffer[3] = { 0U, 0U, 0U }; - uint16_t val; - - for(int i=0; i<2; i++) { - __UNALIGNED_UINT16_WRITE(&(buffer[i]), 0x4711U); - ASSERT_TRUE(buffer[i] == 0x11U); - ASSERT_TRUE(buffer[i+1] == 0x47U); - ASSERT_TRUE(buffer[(i+2)%3] == 0x00U); - - buffer[i] = 0x12U; - buffer[i+1] = 0x46U; - - val = __UNALIGNED_UINT16_READ(&(buffer[i])); - ASSERT_TRUE(val == 0x4612U); - - buffer[i] = 0x00U; - buffer[i+1] = 0x00U; - } -} - - -/** -\brief Test case: TC_CoreInstr_UnalignedUint32 -\details -Checks macro functions to access unaligned uint32_t values: -- __UNALIGNED_UINT32_READ -- __UNALIGNED_UINT32_WRITE -*/ -void TC_CoreInstr_UnalignedUint32(void) { - uint8_t buffer[7] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U }; - uint32_t val; - - for(int i=0; i<4; i++) { - __UNALIGNED_UINT32_WRITE(&(buffer[i]), 0x08154711UL); - ASSERT_TRUE(buffer[i+0] == 0x11U); - ASSERT_TRUE(buffer[i+1] == 0x47U); - ASSERT_TRUE(buffer[i+2] == 0x15U); - ASSERT_TRUE(buffer[i+3] == 0x08U); - ASSERT_TRUE(buffer[(i+4)%7] == 0x00U); - ASSERT_TRUE(buffer[(i+5)%7] == 0x00U); - ASSERT_TRUE(buffer[(i+6)%7] == 0x00U); - - buffer[i+0] = 0x12U; - buffer[i+1] = 0x46U; - buffer[i+2] = 0x14U; - buffer[i+3] = 0x09U; - - val = __UNALIGNED_UINT32_READ(&(buffer[i])); - ASSERT_TRUE(val == 0x09144612UL); - - buffer[i+0] = 0x00U; - buffer[i+1] = 0x00U; - buffer[i+2] = 0x00U; - buffer[i+3] = 0x00U; - } -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreSimd.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreSimd.c deleted file mode 100644 index 8068537..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreSimd.c +++ /dev/null @@ -1,713 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_CoreSimd.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2018 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/** -\brief Test case: TC_CoreSimd_SatAddSub -\details -- Check Saturating addition and subtraction: - __QADD - __QSUB -*/ -void TC_CoreSimd_SatAddSub (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile int32_t op1_s32, op2_s32; - volatile int32_t res_s32; - - /* --- __QADD Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80000003; - op2_s32 = (int32_t)0x00000004; - res_s32 = __QADD(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80000007); - - op1_s32 = (int32_t)0x80000000; - op2_s32 = (int32_t)0x80000002; - res_s32 = __QADD(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80000000); - - /* --- __QSUB Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80000003; - op2_s32 = (int32_t)0x00000004; - res_s32 = __QSUB(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80000000); - - op1_s32 = (int32_t)0x80000003; - op2_s32 = (int32_t)0x00000002; - res_s32 = __QSUB(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80000001); -#endif -} - -/** -\brief Test case: TC_CoreSimd_ParSat16 -\details -- Check Parallel 16-bit saturation: - __SSAT16 - __USAT16 -*/ -void TC_CoreSimd_ParSat16 (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile int32_t op1_s32; - volatile int32_t res_s32; - - /* --- __SSAT16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80030168; - res_s32 = __SSAT16(op1_s32, 8); - ASSERT_TRUE(res_s32 == (int32_t)0xFF80007F); - - /* --- __USAT16 Test ---------------------------------------------- */ - op1_s32 = 0x0030168; - res_s32 = __USAT16(op1_s32, 8); - ASSERT_TRUE(res_s32 == 0x000300FF); -#endif -} - -/** -\brief Test case: TC_CoreSimd_PackUnpack -\details -- Check Packing and unpacking: - __SXTB16 - __SXTB16_RORn - __SXTAB16 - __SXTAB16__RORn - __UXTB16 - __UXTAB16 -*/ -void TC_CoreSimd_PackUnpack (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile int32_t op1_s32, op2_s32; - volatile int32_t res_s32; - - /* --- __SXTB16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80830168; - res_s32 = __SXTB16(op1_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xFF830068); - - /* --- __SXTB16_ROR8 Test ----------------------------------------- */ - op1_s32 = (int32_t)0x80830168; - res_s32 = __SXTB16_RORn(op1_s32, 8); - ASSERT_TRUE(res_s32 == (int32_t)0xFF800001); - - /* --- __SXTB16_ROR16 Test ---------------------------------------- */ - op1_s32 = (int32_t)0x80830168; - res_s32 = __SXTB16_RORn(op1_s32, 16); - ASSERT_TRUE(res_s32 == (int32_t)0x68FF83); - - /* --- __SXTB16_ROR24 Test ---------------------------------------- */ - op1_s32 = (int32_t)0x80830168; - res_s32 = __SXTB16_RORn(op1_s32, 24); - ASSERT_TRUE(res_s32 == (int32_t)0x1FF80); - - /* --- __SXTAB16 Test --------------------------------------------- */ - op1_s32 = (int32_t)0x000D0008; - op2_s32 = (int32_t)0x80830168; - res_s32 = __SXTAB16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xFF900070); - - /* --- __SXTAB16__ROR8 Test --------------------------------------- */ - op1_s32 = (int32_t)0x000A000A; - op2_s32 = (int32_t)0x80830168; - res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8); - ASSERT_TRUE(res_s32 == (int32_t)0xFF8A000B); - - /* --- __SXTAB16__ROR8 Test --------------------------------------- */ - op1_s32 = (int32_t)0xFFF6FFF6; - op2_s32 = (int32_t)0x80830168; - res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8); - ASSERT_TRUE(res_s32 == (int32_t)0xFF76FFF7); - - /* --- __SXTAB16__ROR16 Test -------------------------------------- */ - op1_s32 = (int32_t)0xFFF60015; - op2_s32 = (int32_t)0x70880168; - res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 16); - ASSERT_TRUE(res_s32 == (int32_t)0x5EFF9D); - - /* --- __SXTAB16__ROR24 Test -------------------------------------- */ - op1_s32 = (int32_t)0xFFF60015; - op2_s32 = (int32_t)0x70880168; - res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 24); - ASSERT_TRUE(res_s32 == (int32_t)0xFFF70085); - - /* --- __UXTB16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80830168; - res_s32 = __UXTB16(op1_s32); - ASSERT_TRUE(res_s32 == 0x00830068); - - /* --- __UXTAB16 Test --------------------------------------------- */ - op1_s32 = 0x000D0008; - op2_s32 = (int32_t)0x80830168; - res_s32 = __UXTAB16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == 0x00900070); -#endif -} - -/** -\brief Test case: TC_CoreSimd_ParSel -\details -- Check Parallel selection: - __SEL -*/ -void TC_CoreSimd_ParSel (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile uint32_t res_u32; - - volatile int32_t op1_s32, op2_s32; - volatile int32_t res_s32; - - APSR_Type apsr; - xPSR_Type xpsr; - - /* --- __SEL Test ---------------------------------------------- */ - op1_s32 = 0x33221100; - op2_s32 = 0x77665544; - - res_s32 = __SADD8(0x80808080, 0x00000000); /* __sadd8 sets APSR.GE = 0x00 */ - res_u32 = __get_APSR(); - apsr.w = __get_APSR(); - ASSERT_TRUE( (res_u32 == apsr.w) ); - xpsr.w = __get_xPSR(); - ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); - res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x00 */ - ASSERT_TRUE( res_s32 == 0x77665544); - - res_s32 = __SADD8(0x80808000, 0x00000000); /* __sadd8 sets APSR.GE = 0x01 */ - res_u32 = __get_APSR(); - apsr.w = __get_APSR(); - ASSERT_TRUE( (res_u32 == apsr.w) ); - xpsr.w = __get_xPSR(); - ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); - res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x01 */ - ASSERT_TRUE(res_s32 == 0x77665500); - - res_s32 = __SADD8(0x80800080, 0x00000000); /* __sadd8 sets APSR.GE = 0x02 */ - res_u32 = __get_APSR(); - apsr.w = __get_APSR(); - ASSERT_TRUE( (res_u32 == apsr.w) ); - xpsr.w = __get_xPSR(); - ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); - res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x02 */ - ASSERT_TRUE(res_s32 == 0x77661144); -#endif -} - -/** -\brief Test case: TC_CoreSimd_ParAddSub8 -\details -- Check Parallel 8-bit addition and subtraction: - __SADD8 S Signed - __SSUB8 Q Signed Saturating - __SHADD8 SH Signed Halving - __SHSUB8 U Unsigned - __QADD8 UQ Unsigned Saturating - __QSUB8 UH Unsigned Halving - __UADD8 - __USUB8 - __UHADD8 - __UHSUB8 - __UQADD8 - __UQSUB8 -*/ -void TC_CoreSimd_ParAddSub8 (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile uint32_t op1_u32, op2_u32; - volatile uint32_t res_u32; - - volatile int32_t op1_s32, op2_s32; - volatile int32_t res_s32; - - /* --- __SADD8 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x87858381; - op2_s32 = (int32_t)0x08060402; - res_s32 = __SADD8(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x8F8B8783); - - /* --- __SSUB8 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x8F8B8783; - op2_s32 = (int32_t)0x08060402; - res_s32 = __SSUB8(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x87858381); - - /* --- __SHADD8 Test ---------------------------------------------- */ - op1_s32 = 0x07050302; - op2_s32 = 0x08060402; - res_s32 = __SHADD8(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == 0x07050302); - - /* --- __SHSUB8 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x8F8B8783; - op2_s32 = 0x08060402; - res_s32 = __SHSUB8(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xC3C2C1C0); - - /* --- __QADD8 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x8085837F; - op2_s32 = (int32_t)0xFF060402; - res_s32 = __QADD8(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x808B877F); - - /* --- __QSUB8 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x808B8783; - op2_s32 = (int32_t)0x08060402; - res_s32 = __QSUB8(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80858381); - - /* --- __UADD8 Test ---------------------------------------------- */ - op1_u32 = 0x07050301; - op2_u32 = 0x08060402; - res_u32 = __UADD8(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x0F0B0703); - - /* --- __USUB8 Test ---------------------------------------------- */ - op1_u32 = 0x0F0B0703; - op2_u32 = 0x08060402; - res_u32 = __USUB8(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x07050301); - - /* --- __UHADD8 Test ---------------------------------------------- */ - op1_u32 = 0x07050302; - op2_u32 = 0x08060402; - res_u32 = __UHADD8(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x07050302); - - /* --- __UHSUB8 Test ---------------------------------------------- */ - op1_u32 = 0x0F0B0703; - op2_u32 = 0x08060402; - res_u32 = __UHSUB8(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x03020100); - - /* --- __UQADD8 Test ---------------------------------------------- */ - op1_u32 = 0xFF050301; - op2_u32 = 0x08060402; - res_u32 = __UQADD8(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0xFF0B0703); - - /* --- __UQSUB8 Test ---------------------------------------------- */ - op1_u32 = 0x080B0702; - op2_u32 = 0x0F060408; - res_u32 = __UQSUB8(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x00050300); -#endif -} - -/** -\brief Test case: TC_CoreSimd_AbsDif8 -\details -- Check Sum of 8-bit absolute differences: - __USAD8 - __USADA8 -*/ -void TC_CoreSimd_AbsDif8 (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile uint32_t op1_u32, op2_u32, op3_u32; - volatile uint32_t res_u32; - - /* --- __USAD8 Test ---------------------------------------------- */ - op1_u32 = 0x87858381; - op2_u32 = 0x08060402; - res_u32 = __USAD8(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x000001FC); - - /* --- __USADA8 Test ---------------------------------------------- */ - op1_u32 = 0x87858381; - op2_u32 = 0x08060402; - op3_u32 = 0x00008000; - res_u32 = __USADA8(op1_u32, op2_u32, op3_u32); - ASSERT_TRUE(res_u32 == 0x000081FC); -#endif -} - -/** -\brief Test case: TC_CoreSimd_ParAddSub16 -\details -- Check Parallel 16-bit addition and subtraction: - __SADD16 - __SSUB16 - __SASX - __SSAX - __SHADD16 - __SHSUB16 - __SHASX - __SHSAX - __QADD16 - __QSUB16 - __QASX - __QSAX - __UADD16 - __USUB16 - __UASX - __USAX - __UHADD16 - __UHSUB16 - __UHASX - __UHSAX - __UQSUB16 - __UQADD16 - __UQASX - __UQSAX -*/ -void TC_CoreSimd_ParAddSub16 (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile uint32_t op1_u32, op2_u32; - volatile uint32_t res_u32; - - volatile int32_t op1_s32, op2_s32; - volatile int32_t res_s32; - - /* --- __SADD16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80038001; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SADD16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80078003); - - /* --- __SSUB16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80078003; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SSUB16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80038001); - - /* --- __SASX Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80078003; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SASX(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80097FFF); - - /* --- __SSAX Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80038007; - op2_s32 = (int32_t)0x00020004; - res_s32 = __SSAX(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x7FFF8009); - - /* --- __SHADD16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80038001; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SHADD16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xC003C001); - - /* --- __SHSUB16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80078003; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SHSUB16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xC001C000); - - /* --- __SHASX Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80078003; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SHASX(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xC004BFFF); - - /* --- __SHSAX Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80038007; - op2_s32 = (int32_t)0x00020004; - res_s32 = __SHSAX(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xBFFFC004); - - /* --- __QADD16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80038000; - op2_s32 = (int32_t)0x00048002; - res_s32 = __QADD16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80078000); - - /* --- __QSUB16 Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80038003; - op2_s32 = (int32_t)0x00040002; - res_s32 = __QSUB16(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80008001); - - /* --- __QASX Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80078003; - op2_s32 = (int32_t)0x00040002; - res_s32 = __QASX(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80098000); - - /* --- __QSAX Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x80038007; - op2_s32 = (int32_t)0x00020004; - res_s32 = __QSAX(op1_s32, op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x80008009); - - /* --- __UADD16 Test ---------------------------------------------- */ - op1_u32 = 0x00010002; - op2_u32 = 0x00020004; - res_u32 = __UADD16(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x00030006); - - /* --- __USUB16 Test ---------------------------------------------- */ - op1_u32 = 0x00030006; - op2_u32 = 0x00020004; - res_u32 = __USUB16(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x00010002); - - /* --- __UASX Test ---------------------------------------------- */ - op1_u32 = 0x80078003; - op2_u32 = 0x00040002; - res_u32 = __UASX(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x80097FFF); - - /* --- __USAX Test ---------------------------------------------- */ - op1_u32 = 0x80038007; - op2_u32 = 0x00020004; - res_u32 = __USAX(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x7FFF8009); - - /* --- __UHADD16 Test ---------------------------------------------- */ - op1_u32 = 0x00010002; - op2_u32 = 0x00020004; - res_u32 = __UHADD16(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x00010003); - - /* --- __UHSUB16 Test ---------------------------------------------- */ - op1_u32 = 0x00030006; - op2_u32 = 0x00020004; - res_u32 = __UHSUB16(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x00000001); - - /* --- __UHASX Test ---------------------------------------------- */ - op1_u32 = 0x80078003; - op2_u32 = 0x00040002; - res_u32 = __UHASX(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x40043FFF); - - /* --- __UHSAX Test ---------------------------------------------- */ - op1_u32 = 0x80038007; - op2_u32 = 0x00020004; - res_u32 = __UHSAX(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x3FFF4004); - - /* --- __UQADD16 Test ---------------------------------------------- */ - op1_u32 = 0xFFFE0002; - op2_u32 = 0x00020004; - res_u32 = __UQADD16(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0xFFFF0006); - - /* --- __UQSUB16 Test ---------------------------------------------- */ - op1_u32 = 0x00020006; - op2_u32 = 0x00030004; - res_u32 = __UQSUB16(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x00000002); - - /* --- __UQASX Test ---------------------------------------------- */ - op1_u32 = 0xFFF80003; - op2_u32 = 0x00040009; - res_u32 = __UQASX(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0xFFFF0000); - - /* --- __UQSAX Test ---------------------------------------------- */ - op1_u32 = 0x0003FFF8; - op2_u32 = 0x00090004; - res_u32 = __UQSAX(op1_u32, op2_u32); - ASSERT_TRUE(res_u32 == 0x0000FFFF); -#endif -} - -/** -\brief Test case: TC_CoreSimd_ParMul16 -\details -- Check Parallel 16-bit multiplication: - __SMLAD - __SMLADX - __SMLALD - __SMLALDX - __SMLSD - __SMLSDX - __SMLSLD - __SMLSLDX - __SMUAD - __SMUADX - __SMUSD - __SMUSDX -*/ -void TC_CoreSimd_ParMul16 (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile int32_t op1_s32, op2_s32, op3_s32; - volatile int32_t res_s32; - - volatile int64_t op1_s64; - volatile int64_t res_s64; - - /* --- __SMLAD Test ---------------------------------------------- */ - op1_s32 = 0x00030002; - op2_s32 = 0x00050004; - op3_s32 = 0x20000000; - res_s32 = __SMLAD(op1_s32, op2_s32, op3_s32); - ASSERT_TRUE(res_s32 == 0x20000017); - - /* --- __SMLADX Test ---------------------------------------------- */ - op1_s32 = 0x00030002; - op2_s32 = 0x00050004; - op3_s32 = 0x00000800; - res_s32 = __SMLADX(op1_s32, op2_s32, op3_s32); - ASSERT_TRUE(res_s32 == 0x00000816); - - /* --- __SMLALD Test ---------------------------------------------- */ - op1_s32 = 0x00030002; - op2_s32 = 0x00050004; - op1_s64 = 0x00000000200000000LL; - res_s64 = __SMLALD(op1_s32, op2_s32, op1_s64); - ASSERT_TRUE(res_s64 == 0x0000000200000017LL); - - /* --- __SMLALDX Test ---------------------------------------------- */ - op1_s32 = 0x00030002; - op2_s32 = 0x00050004; - op1_s64 = 0x00000000200000000LL; - res_s64 = __SMLALDX(op1_s32, op2_s32, op1_s64); - ASSERT_TRUE(res_s64 == 0x0000000200000016LL); - - /* --- __SMLSD Test ---------------------------------------------- */ - op1_s32 = 0x00030006; - op2_s32 = 0x00050004; - op3_s32 = 0x00000800; - res_s32 = __SMLSD(op1_s32, op2_s32, op3_s32); - ASSERT_TRUE(res_s32 == 0x00000809); - - /* --- __SMLSDX Test ---------------------------------------------- */ - op1_s32 = 0x00030002; - op2_s32 = 0x00050004; - op3_s32 = 0x00000800; - res_s32 = __SMLSDX(op1_s32, op2_s32, op3_s32); - ASSERT_TRUE(res_s32 == 0x000007FE); - - /* --- __SMLSLD Test ---------------------------------------------- */ - op1_s32 = 0x00030006; - op2_s32 = 0x00050004; - op1_s64 = 0x00000000200000000LL; - res_s64 = __SMLSLD(op1_s32, op2_s32, op1_s64); - ASSERT_TRUE(res_s64 == 0x0000000200000009LL); - - /* --- __SMLSLDX Test ---------------------------------------------- */ - op1_s32 = 0x00030006; - op2_s32 = 0x00050004; - op1_s64 = 0x00000000200000000LL; - res_s64 = __SMLSLDX(op1_s32, op2_s32, op1_s64); - ASSERT_TRUE(res_s64 == 0x0000000200000012LL); - - /* --- __SMUAD Test ---------------------------------------------- */ - op1_s32 = 0x00030001; - op2_s32 = 0x00040002; - res_s32 = __SMUAD(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == 0x0000000E); - - op1_s32 = (int32_t)0xFFFDFFFF; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SMUAD(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF2); - - /* --- __SMUADX Test ---------------------------------------------- */ - op1_s32 = 0x00030001; - op2_s32 = 0x00040002; - res_s32 = __SMUADX(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == 0x0000000A); - - op1_s32 = (int32_t)0xFFFDFFFF; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SMUADX(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6); - - /* --- __SMUSD Test ---------------------------------------------- */ - op1_s32 = (int32_t)0x00030001; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SMUSD(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6); - - op1_s32 = (int32_t)0xFFFDFFFF; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SMUSD(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == 0x0000000A); - - /* --- __SMUSDX Test ---------------------------------------------- */ - op1_s32 = 0x00030001; - op2_s32 = 0x00040002; - res_s32 = __SMUSDX(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFFE); - - op1_s32 = (int32_t)0xFFFDFFFF; - op2_s32 = (int32_t)0x00040002; - res_s32 = __SMUSDX(op1_s32,op2_s32); - ASSERT_TRUE(res_s32 == (int32_t)0x00000002); -#endif -} - -/** -\brief Test case: TC_CoreSimd_Part9 -\details -- Check Packing Halfword: - __PKHBT - __PKHTB -*/ -void TC_CoreSimd_Pack16 (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile uint32_t op1_u32, op2_u32; - volatile uint32_t res_u32; - - /* --- __PKHBT Test ---------------------------------------------- */ - op1_u32 = 0x00000111; - op2_u32 = 0x22200000; - res_u32 = __PKHBT(op1_u32, op2_u32, 0); - ASSERT_TRUE(res_u32 == 0x22200111); - - op1_u32 = 0x00000111; - op2_u32 = 0x22200000; - res_u32 = __PKHBT(op1_u32, op2_u32, 4); - ASSERT_TRUE(res_u32 == 0x22000111); - - /* --- __PKHTB Test ---------------------------------------------- */ - op1_u32 = 0x11100000; - op2_u32 = 0x00000222; - res_u32 = __PKHTB(op1_u32, op2_u32, 0); - ASSERT_TRUE(res_u32 == 0x11100222); - - op1_u32 = 0x11100000; - op2_u32 = 0x00000222; - res_u32 = __PKHTB(op1_u32, op2_u32, 4); - ASSERT_TRUE(res_u32 == 0x11100022); -#endif -} - -/** -\brief Test case: TC_CoreSimd_MulAcc32 -\details -- Check Signed Most Significant Word Multiply Accumulate: - __SMMLA -*/ -void TC_CoreSimd_MulAcc32 (void) { -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) - volatile int32_t op1_s32, op2_s32, op3_s32; - volatile int32_t res_s32; - - /* --- __SMMLA Test ---------------------------------------------- */ - op1_s32 = 0x00000200; - op2_s32 = 0x00000004; - op3_s32 = 0x00000100; - res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32); - ASSERT_TRUE(res_s32 == 0x00000100); - - op1_s32 = 0x40000000; - op2_s32 = 0x00000010; - op3_s32 = 0x00000300; - res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32); - ASSERT_TRUE(res_s32 == 0x00000304); -#endif -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Framework.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Framework.c deleted file mode 100644 index 112c828..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Framework.c +++ /dev/null @@ -1,104 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: cv_framework.c - * Purpose: Test framework entry point - *---------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/* Prototypes */ -void ts_cmsis_cv(void); -void closeDebug(void); - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\defgroup framework_funcs Framework Functions -\brief Functions in the Framework software component -\details - -@{ -*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Close the debug session. -\details -Debug session dead end - debug script should close session here. -*/ -void closeDebug(void) { - __NOP(); - // Test completed -} - - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ - -/** -\brief This is CORE Validation test suite. -\details -Program flow: - -# Test report statistics is initialized - -# Test report headers are written to the standard output - -# All defined test cases are executed: - - Test case statistics is initialized - - Test case report header is written to the standard output - - Test case is executed - - Test case results are written to the standard output - - Test case report footer is written to the standard output - - Test case is closed - -# Test report footer is written to the standard output - -# Debug session ends in dead loop -*/ -void ts_cmsis_cv () { - const char *fn; - uint32_t tc, no; - (void)ritf.Init (); /* Init test report */ - (void)ritf.Open (ts.ReportTitle, /* Write test report title */ - ts.Date, /* Write compilation date */ - ts.Time, /* Write compilation time */ - ts.FileName); /* Write module file name */ - - /* Execute all test cases */ - for (tc = 0; tc < ts.NumOfTC; tc++) { - no = ts.TCBaseNum+tc; /* Test case number */ - fn = ts.TC[tc].TFName; /* Test function name string */ - (void)ritf.Open_TC (no, fn); /* Open test case #(Base + TC) */ - if (ts.TC[tc].en != 0U) { - ts.TC[tc].TestFunc(); /* Execute test case if enabled */ - } - (void)ritf.Close_TC (); /* Close test case */ - } - (void)ritf.Close (); /* Close test report */ - - closeDebug(); /* Close debug session */ -} - -/** -\brief This is the entry point of the test framework. -\details -Program flow: - -# Hardware is first initialized if Init callback function is provided - -# Main thread is initialized -*/ -void cmsis_cv (void) { - - /* Init test suite */ - if (ts.Init != NULL) { - ts.Init(); /* Init hardware */ - } - - ts_cmsis_cv(); -} - -void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc) { - (void)__set_result(fn, ln, FAILED, desc); - (void)ritf.Close_TC(); - (void)ritf.Close(); - closeDebug(); -} - -/** -@} -*/ -// end of group framework_funcs diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_GenTimer.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_GenTimer.c deleted file mode 100644 index df1e7f2..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_GenTimer.c +++ /dev/null @@ -1,70 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_GenTimer.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_GenTimer_CNTFRQ(void) { - const uint32_t cntfrq1 = __get_CNTFRQ(); - __set_CNTFRQ(cntfrq1 + 1U); - const uint32_t cntfrq2 = __get_CNTFRQ(); - - ASSERT_TRUE((cntfrq1 + 1U) == cntfrq2); - - __set_CNTFRQ(cntfrq1); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_GenTimer_CNTP_TVAL(void) { - const uint32_t cntp_tval1 = __get_CNTP_TVAL(); - __set_CNTP_TVAL(cntp_tval1 + 1U); - const uint32_t cntp_tval2 = __get_CNTP_TVAL(); - - ASSERT_TRUE((cntp_tval2 - cntp_tval1) >= 1ULL); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_GenTimer_CNTP_CTL(void) { - static const uint32_t CNTP_CTL_ENABLE = 0x01U; - const uint32_t cntp_ctl = __get_CNTP_CTL(); - const uint32_t cntp_ctl_toggled = (cntp_ctl & (~CNTP_CTL_ENABLE)) | ((~cntp_ctl) & CNTP_CTL_ENABLE); - __set_CNTP_CTL(cntp_ctl_toggled); - - const uint32_t cntp_ctl_new = __get_CNTP_CTL(); - - ASSERT_TRUE((cntp_ctl_toggled & CNTP_CTL_ENABLE) == (cntp_ctl_new & CNTP_CTL_ENABLE)); - - __set_CNTP_CTL(cntp_ctl); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_GenTimer_CNTPCT(void) { - const uint64_t cntpct1 = __get_CNTPCT(); - for(int i=0; i<10; i++); - const uint64_t cntpct2 = __get_CNTPCT(); - - ASSERT_TRUE((cntpct2 - cntpct1) <= 120ULL); -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -void TC_GenTimer_CNTP_CVAL(void) { - const uint64_t cntp_cval1 = __get_CNTP_CVAL(); - __set_CNTP_CVAL(cntp_cval1 + 1ULL); - const uint64_t cntp_cval2 = __get_CNTP_CVAL(); - - ASSERT_TRUE((cntp_cval2 - cntp_cval1) >= 1ULL); -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c deleted file mode 100644 index 4c4933c..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c +++ /dev/null @@ -1,121 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_MPU_ARMv7.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -#if defined(__MPU_PRESENT) && __MPU_PRESENT -static void ClearMpu(void) { - for(uint32_t i = 0U; i < 8U; ++i) { - MPU->RNR = i; - MPU->RBAR = 0U; - MPU->RASR = 0U; - } -} -#endif - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_MPU_SetClear -\details -- Check if ARM_MPU_Load correctly loads MPU table to registers. -*/ -void TC_MPU_SetClear(void) -{ -#if defined(__MPU_PRESENT) && __MPU_PRESENT - static const ARM_MPU_Region_t table[] = { - { .RBAR = 0U, .RASR = 0U }, - { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) }, - { .RBAR = 0x50000000U, .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) } - }; - - #define ASSERT_MPU_REGION(rnr, region) \ - MPU->RNR = rnr; \ - ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (region.RBAR & MPU_RBAR_ADDR_Msk)); \ - ASSERT_TRUE(MPU->RASR == region.RASR) - - ClearMpu(); - - ARM_MPU_SetRegion(table[1].RBAR, table[1].RASR); - - ASSERT_MPU_REGION(1U, table[0]); - ASSERT_MPU_REGION(2U, table[1]); - ASSERT_MPU_REGION(3U, table[0]); - - ARM_MPU_SetRegionEx(5U, table[2].RBAR, table[2].RASR); - - ASSERT_MPU_REGION(4U, table[0]); - ASSERT_MPU_REGION(5U, table[2]); - ASSERT_MPU_REGION(6U, table[0]); - - ARM_MPU_ClrRegion(5U); - - MPU->RNR = 5U; - ASSERT_TRUE((MPU->RASR & MPU_RASR_ENABLE_Msk) == 0U); - - #undef ASSERT_MPU_REGION -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_MPU_Load -\details -- Check if ARM_MPU_Load correctly loads MPU table to registers. -*/ -void TC_MPU_Load(void) -{ -#if defined(__MPU_PRESENT) && __MPU_PRESENT - static const ARM_MPU_Region_t table[] = { - { .RBAR = ARM_MPU_RBAR(0U, 0x10000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB) }, - { .RBAR = ARM_MPU_RBAR(1U, 0x20000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) }, - { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) }, - { .RBAR = ARM_MPU_RBAR(3U, 0x40000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB) }, - { .RBAR = ARM_MPU_RBAR(4U, 0x50000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB) }, - { .RBAR = ARM_MPU_RBAR(5U, 0x60000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_16MB) }, - { .RBAR = ARM_MPU_RBAR(6U, 0x70000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_8MB) }, - { .RBAR = ARM_MPU_RBAR(7U, 0x80000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4MB) } - }; - - #define ASSERT_MPU_REGION(rnr, table) \ - MPU->RNR = rnr; \ - ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (table[rnr].RBAR & MPU_RBAR_ADDR_Msk)); \ - ASSERT_TRUE(MPU->RASR == table[rnr].RASR) - - ClearMpu(); - - ARM_MPU_Load(&(table[0]), 1U); - - ASSERT_MPU_REGION(0U, table); - - ARM_MPU_Load(&(table[1]), 5U); - - ASSERT_MPU_REGION(0U, table); - ASSERT_MPU_REGION(1U, table); - ASSERT_MPU_REGION(2U, table); - ASSERT_MPU_REGION(3U, table); - ASSERT_MPU_REGION(4U, table); - ASSERT_MPU_REGION(5U, table); - - ARM_MPU_Load(&(table[6]), 2U); - - ASSERT_MPU_REGION(5U, table); - ASSERT_MPU_REGION(6U, table); - ASSERT_MPU_REGION(7U, table); - - #undef ASSERT_MPU_REGION -#endif -} - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c deleted file mode 100644 index f1c8190..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c +++ /dev/null @@ -1,113 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_MPU_ARMv7.c - * Purpose: CMSIS CORE validation tests implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include "CV_Framework.h" -#include "cmsis_cv.h" - -/*----------------------------------------------------------------------------- - * Test implementation - *----------------------------------------------------------------------------*/ - -#if defined(__MPU_PRESENT) && __MPU_PRESENT -static void ClearMpu(void) { - for(uint32_t i = 0U; i < 8U; ++i) { - MPU->RNR = i; - MPU->RBAR = 0U; - MPU->RLAR = 0U; - } -} -#endif - -/*----------------------------------------------------------------------------- - * Test cases - *----------------------------------------------------------------------------*/ - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_MPU_SetClear -\details -- Check if ARM_MPU_Load correctly loads MPU table to registers. -*/ -void TC_MPU_SetClear(void) -{ -#if defined(__MPU_PRESENT) && __MPU_PRESENT - static const ARM_MPU_Region_t table[] = { - { .RBAR = 0U, .RLAR = 0U }, - { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) } - }; - - #define ASSERT_MPU_REGION(rnr, region) \ - MPU->RNR = rnr; \ - ASSERT_TRUE(MPU->RBAR == region.RBAR); \ - ASSERT_TRUE(MPU->RLAR == region.RLAR) - - ClearMpu(); - - ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR); - - ASSERT_MPU_REGION(1U, table[0]); - ASSERT_MPU_REGION(2U, table[1]); - ASSERT_MPU_REGION(3U, table[0]); - - ARM_MPU_ClrRegion(2U); - - MPU->RNR = 2U; - ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U); - - #undef ASSERT_MPU_REGION -#endif -} - -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ -/** -\brief Test case: TC_MPU_Load -\details -- Check if ARM_MPU_Load correctly loads MPU table to registers. -*/ -void TC_MPU_Load(void) -{ -#if defined(__MPU_PRESENT) && __MPU_PRESENT - static const ARM_MPU_Region_t table[] = { - { .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) }, - { .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) }, - { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) }, - { .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) }, - { .RBAR = ARM_MPU_RBAR(0x50000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x54000000U, 0U) }, - { .RBAR = ARM_MPU_RBAR(0x60000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x63000000U, 0U) }, - { .RBAR = ARM_MPU_RBAR(0x70000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x72000000U, 0U) }, - { .RBAR = ARM_MPU_RBAR(0x80000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x31000000U, 0U) } - }; - - #define ASSERT_MPU_REGION(rnr, table) \ - MPU->RNR = rnr; \ - ASSERT_TRUE(MPU->RBAR == table[rnr].RBAR); \ - ASSERT_TRUE(MPU->RLAR == table[rnr].RLAR) - - ClearMpu(); - - ARM_MPU_Load(0U, &(table[0]), 1U); - - ASSERT_MPU_REGION(0U, table); - - ARM_MPU_Load(1U, &(table[1]), 5U); - - ASSERT_MPU_REGION(0U, table); - ASSERT_MPU_REGION(1U, table); - ASSERT_MPU_REGION(2U, table); - ASSERT_MPU_REGION(3U, table); - ASSERT_MPU_REGION(4U, table); - ASSERT_MPU_REGION(5U, table); - - ARM_MPU_Load(6U, &(table[6]), 2U); - - ASSERT_MPU_REGION(5U, table); - ASSERT_MPU_REGION(6U, table); - ASSERT_MPU_REGION(7U, table); - - #undef ASSERT_MPU_REGION -#endif -} diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Report.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Report.c deleted file mode 100644 index 3fa2d23..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Report.c +++ /dev/null @@ -1,393 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: cv_report.c - * Purpose: Report statistics and layout implementation - *----------------------------------------------------------------------------- - * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#include "CV_Report.h" -#include -#include - -TEST_REPORT test_report; -static AS_STAT current_assertions; /* Current test case assertions statistics */ -#define TAS (&test_report.assertions) /* Total assertions */ -#define CAS (¤t_assertions) /* Current assertions */ - -#ifdef DISABLE_SEMIHOSTING -#if defined (__CC_ARM) - #pragma import __use_no_semihosting -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - __ASM(".global __use_no_semihosting"); -#endif -#define PRINT(x) -#define FLUSH() -void _sys_exit(int return_code) {} -#else -#define PRINT(x) MsgPrint x -#define FLUSH() MsgFlush() -#endif // DISABLE_SEMIHOSTING - -static uint8_t Passed[] = "PASSED"; -static uint8_t Warning[] = "WARNING"; -static uint8_t Failed[] = "FAILED"; -static uint8_t NotExe[] = "NOT EXECUTED"; - - -/*----------------------------------------------------------------------------- - * Test report function prototypes - *----------------------------------------------------------------------------*/ -static BOOL tr_Init (void); -static BOOL tc_Init (void); -static uint8_t *tr_Eval (void); -static uint8_t *tc_Eval (void); -static BOOL StatCount (TC_RES res); - -/*----------------------------------------------------------------------------- - * Printer function prototypes - *----------------------------------------------------------------------------*/ -static void MsgPrint (const char *msg, ...); -static void MsgFlush (void); - - -/*----------------------------------------------------------------------------- - * Assert interface function prototypes - *----------------------------------------------------------------------------*/ -static BOOL As_File_Result (TC_RES res); -static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc); - -TC_ITF tcitf = { - As_File_Result, - As_File_Dbgi, -}; - - -/*----------------------------------------------------------------------------- - * Test report interface function prototypes - *----------------------------------------------------------------------------*/ -BOOL tr_File_Init (void); -BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn); -BOOL tr_File_Close (void); -BOOL tc_File_Open (uint32_t num, const char *fn); -BOOL tc_File_Close (void); - -REPORT_ITF ritf = { - tr_File_Init, - tr_File_Open, - tr_File_Close, - tc_File_Open, - tc_File_Close -}; - - -/*----------------------------------------------------------------------------- - * Init test report - *----------------------------------------------------------------------------*/ -BOOL tr_File_Init (void) { - return (tr_Init()); -} - - -/*----------------------------------------------------------------------------- - * Open test report - *----------------------------------------------------------------------------*/ -#if (PRINT_XML_REPORT==1) -BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn) { - PRINT(("\n")); - PRINT(("\n")); - PRINT(("\n")); - PRINT(("\n")); - PRINT(("%s\n", title)); - PRINT(("%s\n", date)); - PRINT(("\n", time)); - PRINT(("%s\n", fn)); - PRINT(("\n")); -#else -BOOL tr_File_Open (const char *title, const char *date, const char *time, const char __attribute__((unused)) *fn) { - PRINT(("%s %s %s \n\n", title, date, time)); -#endif - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Open test case - *----------------------------------------------------------------------------*/ -BOOL tc_File_Open (uint32_t num, const char *fn) { - (void)tc_Init (); -#if (PRINT_XML_REPORT==1) - PRINT(("\n")); - PRINT(("%d\n", num)); - PRINT(("%s\n", fn)); - PRINT(("")); - PRINT(("")); - PRINT(("\n")); -#else - PRINT(("TEST %02d: %-42s ", num, fn)); -#endif - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Close test case - *----------------------------------------------------------------------------*/ -BOOL tc_File_Close (void) { - uint8_t *res = tc_Eval(); -#if (PRINT_XML_REPORT==1) - PRINT(("\n")); - PRINT(("%s\n", res)); - PRINT(("\n")); -#else - if ((res==Passed)||(res==NotExe)) { - PRINT(("%s\n", res)); - } else { - PRINT(("\n")); - } -#endif - FLUSH(); - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Close test report - *----------------------------------------------------------------------------*/ -BOOL tr_File_Close (void) { -#if (PRINT_XML_REPORT==1) - PRINT(("\n")); - PRINT(("\n")); - PRINT(("%d\n", test_report.tests)); - PRINT(("%d\n", test_report.executed)); - PRINT(("%d\n", test_report.passed)); - PRINT(("%d\n", test_report.failed)); - PRINT(("%d\n", test_report.warnings)); - PRINT(("%s\n", tr_Eval())); - PRINT(("\n")); - PRINT(("\n")); - PRINT(("\n")); -#else - PRINT(("\nTest Summary: %d Tests, %d Executed, %d Passed, %d Failed, %d Warnings.\n", - test_report.tests, - test_report.executed, - test_report.passed, - test_report.failed, - test_report.warnings)); - PRINT(("Test Result: %s\n", tr_Eval())); -#endif - FLUSH(); - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Assertion result counter - *----------------------------------------------------------------------------*/ -static BOOL As_File_Result (TC_RES res) { - return (StatCount (res)); -} - - -/*----------------------------------------------------------------------------- - * Set debug information state - *----------------------------------------------------------------------------*/ -#if (PRINT_XML_REPORT==1) -static BOOL As_File_Dbgi (TC_RES __attribute__((unused)) res, const char *fn, uint32_t ln, char *desc) { - PRINT(("\n")); - if (desc!=NULL) PRINT(("%s\n", desc)); - PRINT(("%s\n", fn)); - PRINT(("%d\n", ln)); - PRINT(("\n")); -#else -static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc) { - PRINT(("\n %s (%d)", fn, ln)); - if (res==WARNING){ PRINT((" [WARNING]")); } - if (res==FAILED) { PRINT((" [FAILED]")); } - if (desc!=NULL) { PRINT((" %s", desc)); } -#endif - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Init test report - *----------------------------------------------------------------------------*/ -static BOOL tr_Init (void) { - TAS->passed = 0; - TAS->failed = 0; - TAS->warnings = 0; - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Init test case - *----------------------------------------------------------------------------*/ -static BOOL tc_Init (void) { - CAS->passed = 0; - CAS->failed = 0; - CAS->warnings = 0; - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Evaluate test report results - *----------------------------------------------------------------------------*/ -static uint8_t *tr_Eval (void) { - if (test_report.failed > 0U) { - /* Test fails if any test case failed */ - return (Failed); - } - else if (test_report.warnings > 0U) { - /* Test warns if any test case warnings */ - return (Warning); - } - else if (test_report.passed > 0U) { - /* Test passes if at least one test case passed */ - return (Passed); - } - else { - /* No test cases were executed */ - return (NotExe); - } -} - - -/*----------------------------------------------------------------------------- - * Evaluate test case results - *----------------------------------------------------------------------------*/ -static uint8_t *tc_Eval (void) { - test_report.tests++; - test_report.executed++; - - if (CAS->failed > 0U) { - /* Test case fails if any failed assertion recorded */ - test_report.failed++; - return Failed; - } - else if (CAS->warnings > 0U) { - /* Test case warns if any warnings assertion recorded */ - test_report.warnings++; - return Warning; - } - else if (CAS->passed > 0U) { - /* Test case passes if at least one assertion passed */ - test_report.passed++; - return Passed; - } - else { - /* Assert was not invoked - nothing to evaluate */ - test_report.executed--; - return NotExe; - } -} - - -/*----------------------------------------------------------------------------- - * Statistics result counter - *----------------------------------------------------------------------------*/ -static BOOL StatCount (TC_RES res) { - switch (res) { - case PASSED: - CAS->passed++; - TAS->passed++; - break; - - case WARNING: - CAS->warnings++; - TAS->warnings++; - break; - - case FAILED: - CAS->failed++; - TAS->failed++; - break; - - case NOT_EXECUTED: - return (__FALSE); - - default: - break; - } - return (__TRUE); -} - - -/*----------------------------------------------------------------------------- - * Set result - *----------------------------------------------------------------------------*/ -TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc) { - - // save assertion result - switch (res) { - case PASSED: - if (TAS->passed < BUFFER_ASSERTIONS) { - test_report.assertions.info.passed[TAS->passed].module = fn; - test_report.assertions.info.passed[TAS->passed].line = ln; - } - break; - case FAILED: - if (TAS->failed < BUFFER_ASSERTIONS) { - test_report.assertions.info.failed[TAS->failed].module = fn; - test_report.assertions.info.failed[TAS->failed].line = ln; - } - break; - case WARNING: - if (TAS->warnings < BUFFER_ASSERTIONS) { - test_report.assertions.info.warnings[TAS->warnings].module = fn; - test_report.assertions.info.warnings[TAS->warnings].line = ln; - } - break; - case NOT_EXECUTED: - break; - - default: - break; - } - - // set debug info (if the test case didn't pass) - if (res != PASSED) { (void)tcitf.Dbgi (res, fn, ln, desc); } - // set result - (void)tcitf.Result (res); - return (res); -} - -/*----------------------------------------------------------------------------- - * Assert true - *----------------------------------------------------------------------------*/ -TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond) { - TC_RES res = FAILED; - if (cond != 0U) { res = PASSED; } - (void)__set_result(fn, ln, res, NULL); - return (res); -} - -#ifndef DISABLE_SEMIHOSTING -/*----------------------------------------------------------------------------- - * MsgFlush: Flush the standard output - *----------------------------------------------------------------------------*/ -static void MsgFlush(void) { - (void)fflush(stdout); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wformat-nonliteral" -#endif -/*----------------------------------------------------------------------------- - * MsgPrint: Print a message to the standard output - *----------------------------------------------------------------------------*/ -static void MsgPrint (const char *msg, ...) { - va_list args; - va_start(args, msg); - vprintf(msg, args); - va_end(args); -} -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang diagnostic pop -#endif -#endif // DISABLE_SEMIHOSTING - -/*----------------------------------------------------------------------------- - * End of file - *----------------------------------------------------------------------------*/ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config.h deleted file mode 100644 index f8054b0..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config.h +++ /dev/null @@ -1,158 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_Config.h - * Purpose: CV Config header - *---------------------------------------------------------------------------- - * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __CV_CONFIG_H -#define __CV_CONFIG_H - -#include "RTE_Components.h" -#include CMSIS_device_header - -#define RTE_CV_COREINSTR 1 -#define RTE_CV_COREFUNC 1 -#define RTE_CV_CORESIMD 1 -#define RTE_CV_MPUFUNC (__MPU_PRESENT) -#if defined __ICACHE_PRESENT || defined __DCACHE_PRESENT -#define RTE_CV_L1CACHE (__ICACHE_PRESENT || __DCACHE_PRESENT) -#endif - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Common Test Settings -// Print Output Format <0=> Plain Text <1=> XML -// Set the test results output format to plain text or XML -#ifndef PRINT_XML_REPORT -#define PRINT_XML_REPORT 1 -#endif -// Buffer size for assertions results -// Set the buffer size for assertions results buffer -#define BUFFER_ASSERTIONS 128U -// - -// Disable Test Cases -// Uncheck to disable an individual test case -// TC_CoreInstr_NOP -#define TC_COREINSTR_NOP_EN 1 -// TC_CoreInstr_SEV -#define TC_COREINSTR_SEV_EN 1 -// TC_CoreInstr_BKPT -#define TC_COREINSTR_BKPT_EN 1 -// TC_CoreInstr_ISB -#define TC_COREINSTR_ISB_EN 1 -// TC_CoreInstr_DSB -#define TC_COREINSTR_DSB_EN 1 -// TC_CoreInstr_DMB -#define TC_COREINSTR_DMB_EN 1 -// TC_CoreInstr_WFI -#define TC_COREINSTR_WFI_EN 0 -// TC_CoreInstr_WFE -#define TC_COREINSTR_WFE_EN 0 - -// TC_CoreInstr_REV -#define TC_COREINSTR_REV_EN 1 -// TC_CoreInstr_REV16 -#define TC_COREINSTR_REV16_EN 1 -// TC_CoreInstr_REVSH -#define TC_COREINSTR_REVSH_EN 1 -// TC_CoreInstr_ROR -#define TC_COREINSTR_ROR_EN 1 -// TC_CoreInstr_RBIT -#define TC_COREINSTR_RBIT_EN 1 -// TC_CoreInstr_CLZ -#define TC_COREINSTR_CLZ_EN 1 -// TC_CoreInstr_SSAT -#define TC_COREINSTR_SSAT_EN 1 -// TC_CoreInstr_USAT -#define TC_COREINSTR_USAT_EN 1 -// TC_CoreInstr_RRX -#define TC_COREINSTR_RRX_EN 1 -// TC_CoreInstr_LoadStoreExlusive -#define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1 -// TC_CoreInstr_LoadStoreUnpriv -#define TC_COREINSTR_LOADSTOREUNPRIV_EN 1 -// TC_CoreInstr_LoadStoreAcquire -#define TC_COREINSTR_LOADSTOREACQUIRE_EN 1 -// TC_CoreInstr_LoadStoreAcquireExclusive -#define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1 -// TC_CoreInstr_UnalignedUint16 -#define TC_COREINSTR_UNALIGNEDUINT16_EN 1 -// TC_CoreInstr_UnalignedUint32 -#define TC_COREINSTR_UNALIGNEDUINT32_EN 1 - -// TC_CoreSimd_SatAddSub -#define TC_CORESIMD_SATADDSUB_EN 1 -// TC_CoreSimd_ParSat16 -#define TC_CORESIMD_PARSAT16_EN 1 -// TC_CoreSimd_PackUnpack -#define TC_CORESIMD_PACKUNPACK_EN 1 -// TC_CoreSimd_ParSel -#define TC_CORESIMD_PARSEL_EN 1 -// TC_CoreSimd_ParAddSub8 -#define TC_CORESIMD_PARADDSUB8_EN 1 -// TC_CoreSimd_AbsDif8 -#define TC_CORESIMD_ABSDIF8_EN 1 -// TC_CoreSimd_ParAddSub16 -#define TC_CORESIMD_PARADDSUB16_EN 1 -// TC_CoreSimd_ParMul16 -#define TC_CORESIMD_PARMUL16_EN 1 -// TC_CoreSimd_Pack16 -#define TC_CORESIMD_PACK16_EN 1 -// TC_CoreSimd_MulAcc32 -#define TC_CORESIMD_MULACC32_EN 1 - -// TC_CoreFunc_EnDisIRQ -#define TC_COREFUNC_ENDISIRQ_EN 1 -// TC_CoreFunc_IRQPrio -#define TC_COREFUNC_IRQPRIO_EN 1 -// TC_CoreFunc_EncDecIRQPrio -#define TC_COREFUNC_ENCDECIRQPRIO_EN 1 -// TC_CoreFunc_IRQVect -#define TC_COREFUNC_IRQVECT_EN 1 -// TC_CoreFunc_Control -#define TC_COREFUNC_CONTROL_EN 1 -// TC_CoreFunc_IPSR -#define TC_COREFUNC_IPSR_EN 1 -// TC_CoreFunc_APSR -#define TC_COREFUNC_APSR_EN 1 -// TC_CoreFunc_PSP -#define TC_COREFUNC_PSP_EN 1 -// TC_CoreFunc_MSP -#define TC_COREFUNC_MSP_EN 1 - -// TC_CoreFunc_PSPLIM -#define TC_COREFUNC_PSPLIM_EN 1 -// TC_CoreFunc_PSPLIM_NS -#define TC_COREFUNC_PSPLIM_NS_EN 1 -// TC_CoreFunc_MSPLIM -#define TC_COREFUNC_MSPLIM_EN 1 -// TC_CoreFunc_MSPLIM_NS -#define TC_COREFUNC_MSPLIM_NS_EN 1 -// TC_CoreFunc_PRIMASK -#define TC_COREFUNC_PRIMASK_EN 1 -// TC_CoreFunc_FAULTMASK -#define TC_COREFUNC_FAULTMASK_EN 1 -// TC_CoreFunc_BASEPRI -#define TC_COREFUNC_BASEPRI_EN 1 -// TC_CoreFunc_FPUType -#define TC_COREFUNC_FPUTYPE_EN 1 -// TC_CoreFunc_FPSCR -#define TC_COREFUNC_FPSCR_EN 1 - -// TC_MPU_SetClear -#define TC_MPU_SETCLEAR_EN 1 -// TC_MPU_Load -#define TC_MPU_LOAD_EN 1 - -// TC_CML1Cache_EnDisableICache -#define TC_CML1CACHE_ENDISABLE_ICACHE 1 -// TC_CML1Cache_EnDisableDCache -#define TC_CML1CACHE_ENDISABLE_DCACHE 1 -// TC_CML1Cache_CleanDCacheByAddrWhileDisabled -#define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1 - -// - -#endif /* __CV_CONFIG_H */ - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config_template.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config_template.h deleted file mode 100644 index 60444de..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config_template.h +++ /dev/null @@ -1,146 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_Config.h - * Purpose: CV Config header - *---------------------------------------------------------------------------- - * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __CV_CONFIG_H -#define __CV_CONFIG_H - -#include "RTE_Components.h" -#include CMSIS_device_header - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Common Test Settings -// Print Output Format <0=> Plain Text <1=> XML -// Set the test results output format to plain text or XML -#ifndef PRINT_XML_REPORT -#define PRINT_XML_REPORT 1 -#endif -// Buffer size for assertions results -// Set the buffer size for assertions results buffer -#define BUFFER_ASSERTIONS 128U -// - -// Disable Test Cases -// Uncheck to disable an individual test case -// TC_CoreInstr_NOP -#define TC_COREINSTR_NOP_EN 1 -// TC_CoreInstr_SEV -#define TC_COREINSTR_SEV_EN 1 -// TC_CoreInstr_BKPT -#define TC_COREINSTR_BKPT_EN 1 -// TC_CoreInstr_ISB -#define TC_COREINSTR_ISB_EN 1 -// TC_CoreInstr_DSB -#define TC_COREINSTR_DSB_EN 1 -// TC_CoreInstr_DMB -#define TC_COREINSTR_DMB_EN 1 -// TC_CoreInstr_WFI -#define TC_COREINSTR_WFI_EN 0 -// TC_CoreInstr_WFE -#define TC_COREINSTR_WFE_EN 0 - -// TC_CoreInstr_REV -#define TC_COREINSTR_REV_EN 1 -// TC_CoreInstr_REV16 -#define TC_COREINSTR_REV16_EN 1 -// TC_CoreInstr_REVSH -#define TC_COREINSTR_REVSH_EN 1 -// TC_CoreInstr_ROR -#define TC_COREINSTR_ROR_EN 1 -// TC_CoreInstr_RBIT -#define TC_COREINSTR_RBIT_EN 1 -// TC_CoreInstr_CLZ -#define TC_COREINSTR_CLZ_EN 1 -// TC_CoreInstr_SSAT -#define TC_COREINSTR_SSAT_EN 1 -// TC_CoreInstr_USAT -#define TC_COREINSTR_USAT_EN 1 -// TC_CoreInstr_RRX -#define TC_COREINSTR_RRX_EN 1 -// TC_CoreInstr_LoadStoreExlusive -#define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1 -// TC_CoreInstr_LoadStoreUnpriv -#define TC_COREINSTR_LOADSTOREUNPRIV_EN 1 -// TC_CoreInstr_LoadStoreAcquire -#define TC_COREINSTR_LOADSTOREACQUIRE_EN 1 -// TC_CoreInstr_LoadStoreAcquireExclusive -#define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1 - -// TC_CoreSimd_SatAddSub -#define TC_CORESIMD_SATADDSUB_EN 1 -// TC_CoreSimd_ParSat16 -#define TC_CORESIMD_PARSAT16_EN 1 -// TC_CoreSimd_PackUnpack -#define TC_CORESIMD_PACKUNPACK_EN 1 -// TC_CoreSimd_ParSel -#define TC_CORESIMD_PARSEL_EN 1 -// TC_CoreSimd_ParAddSub8 -#define TC_CORESIMD_PARADDSUB8_EN 1 -// TC_CoreSimd_AbsDif8 -#define TC_CORESIMD_ABSDIF8_EN 1 -// TC_CoreSimd_ParAddSub16 -#define TC_CORESIMD_PARADDSUB16_EN 1 -// TC_CoreSimd_ParMul16 -#define TC_CORESIMD_PARMUL16_EN 1 -// TC_CoreSimd_Pack16 -#define TC_CORESIMD_PACK16_EN 1 -// TC_CoreSimd_MulAcc32 -#define TC_CORESIMD_MULACC32_EN 1 - -// TC_CoreFunc_EnDisIRQ -#define TC_COREFUNC_ENDISIRQ_EN 1 -// TC_CoreFunc_IRQPrio -#define TC_COREFUNC_IRQPRIO_EN 1 -// TC_CoreFunc_EncDecIRQPrio -#define TC_COREFUNC_ENCDECIRQPRIO_EN 1 -// TC_CoreFunc_IRQVect -#define TC_COREFUNC_IRQVECT_EN 1 -// TC_CoreFunc_Control -#define TC_COREFUNC_CONTROL_EN 1 -// TC_CoreFunc_IPSR -#define TC_COREFUNC_IPSR_EN 1 -// TC_CoreFunc_APSR -#define TC_COREFUNC_APSR_EN 1 -// TC_CoreFunc_PSP -#define TC_COREFUNC_PSP_EN 1 -// TC_CoreFunc_MSP -#define TC_COREFUNC_MSP_EN 1 - -// TC_CoreFunc_PSPLIM -#define TC_COREFUNC_PSPLIM_EN 1 -// TC_CoreFunc_PSPLIM_NS -#define TC_COREFUNC_PSPLIM_NS_EN 1 -// TC_CoreFunc_MSPLIM -#define TC_COREFUNC_MSPLIM_EN 1 -// TC_CoreFunc_MSPLIM_NS -#define TC_COREFUNC_MSPLIM_NS_EN 1 -// TC_CoreFunc_PRIMASK -#define TC_COREFUNC_PRIMASK_EN 1 -// TC_CoreFunc_FAULTMASK -#define TC_COREFUNC_FAULTMASK_EN 1 -// TC_CoreFunc_BASEPRI -#define TC_COREFUNC_BASEPRI_EN 1 -// TC_CoreFunc_FPUType -#define TC_COREFUNC_FPUTYPE_EN 1 -// TC_CoreFunc_FPSCR -#define TC_COREFUNC_FPSCR_EN 1 - -// TC_MPU_SetClear -#define TC_MPU_SETCLEAR_EN 1 -// TC_MPU_Load -#define TC_MPU_LOAD_EN 1 - -// TC_CML1Cache_EnDisableICache -#define TC_CML1CACHE_ENDISABLE_ICACHE 1 -// TC_CML1Cache_EnDisableDCache -#define TC_CML1CACHE_ENDISABLE_DCACHE 1 -// TC_CML1Cache_CleanDCacheByAddrWhileDisabled -#define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1 - -// - -#endif /* __CV_CONFIG_H */ - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM23.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM23.h deleted file mode 100644 index a7a090e..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM23.h +++ /dev/null @@ -1,832 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM23.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 - * @version V5.3.1 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM23_H -#define PARTITION_ARMCM23_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - - -/* -// Setup behaviour of single SysTick -*/ -#define SCB_ICSR_INIT 0 - -/* -// in a single SysTick implementation, SysTick is -// <0=>Secure -// <1=>Non-Secure -// Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation -*/ -#define SCB_ICSR_STTNS_VAL 0 - -/* -// -*/ - - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) - SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | - ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); - #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM23_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM33.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM33.h deleted file mode 100644 index be43760..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM33.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM33.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 - * @version V5.3.1 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM33_H -#define PARTITION_ARMCM33_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM33_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM35P.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM35P.h deleted file mode 100644 index 9e11ebf..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM35P.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM35P.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P - * @version V5.4.1 - * @date 03. September 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM35P_H -#define PARTITION_ARMCM35P_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM35P_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM55.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM55.h deleted file mode 100644 index eabaf30..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM55.h +++ /dev/null @@ -1,1261 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM55.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 20. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM55_H -#define PARTITION_ARMCM55_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM55_H */ diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h deleted file mode 100644 index 1995481..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h +++ /dev/null @@ -1,124 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_Config.h - * Purpose: CV Config header - *---------------------------------------------------------------------------- - * Copyright (c) 2017 - 2021 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __CV_CONFIG_H -#define __CV_CONFIG_H - -#include "RTE_Components.h" -#include CMSIS_device_header - -#define RTE_CV_COREINSTR 1 -#define RTE_CV_COREFUNC 1 -#define RTE_CV_L1CACHE 1 - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Common Test Settings -// Print Output Format <0=> Plain Text <1=> XML -// Set the test results output format to plain text or XML -#ifndef PRINT_XML_REPORT -#define PRINT_XML_REPORT 1 -#endif -// Buffer size for assertions results -// Set the buffer size for assertions results buffer -#define BUFFER_ASSERTIONS 128U -// - -// Disable Test Cases -// Uncheck to disable an individual test case -// TC_CoreInstr_NOP -#define TC_COREINSTR_NOP_EN 1 -// TC_CoreInstr_REV -#define TC_COREINSTR_REV_EN 1 -// TC_CoreInstr_REV16 -#define TC_COREINSTR_REV16_EN 1 -// TC_CoreInstr_REVSH -#define TC_COREINSTR_REVSH_EN 1 -// TC_CoreInstr_ROR -#define TC_COREINSTR_ROR_EN 1 -// TC_CoreInstr_RBIT -#define TC_COREINSTR_RBIT_EN 1 -// TC_CoreInstr_CLZ -#define TC_COREINSTR_CLZ_EN 1 -// TC_CoreInstr_Exclusives -#define TC_COREINSTR_EXCLUSIVES_EN 1 -// TC_CoreInstr_SSAT -#define TC_COREINSTR_SSAT_EN 1 -// TC_CoreInstr_USAT -#define TC_COREINSTR_USAT_EN 1 - -// TC_CoreAFunc_IRQ -#define TC_COREAFUNC_IRQ 1 -// TC_CoreAFunc_FaultIRQ -#define TC_COREAFUNC_FAULTIRQ 1 -// TC_CoreAFunc_FPSCR -#define TC_COREAFUNC_FPSCR 1 -// TC_CoreAFunc_CPSR -#define TC_COREAFUNC_CPSR 1 -// TC_CoreAFunc_Mode -#define TC_COREAFUNC_MODE 1 -// TC_CoreAFunc_SP -#define TC_COREAFUNC_SP 1 -// TC_CoreAFunc_SP_usr -#define TC_COREAFUNC_SP_USR 1 -// TC_CoreAFunc_FPEXC -#define TC_COREAFUNC_FPEXC 1 -// TC_CoreAFunc_ACTLR -#define TC_COREAFUNC_ACTLR 1 -// TC_CoreAFunc_CPACR -#define TC_COREAFUNC_CPACR 1 -// TC_CoreAFunc_DFSR -#define TC_COREAFUNC_DFSR 1 -// TC_CoreAFunc_IFSR -#define TC_COREAFUNC_IFSR 1 -// TC_CoreAFunc_ISR -#define TC_COREAFUNC_ISR 1 -// TC_CoreAFunc_CBAR -#define TC_COREAFUNC_CBAR 1 -// TC_CoreAFunc_TTBR0 -#define TC_COREAFUNC_TTBR0 1 -// TC_CoreAFunc_DACR -#define TC_COREAFUNC_DACR 1 -// TC_CoreAFunc_SCTLR -#define TC_COREAFUNC_SCTLR 1 -// TC_CoreAFunc_ACTRL -#define TC_COREAFUNC_ACTRL 1 -// TC_CoreAFunc_MPIDR -#define TC_COREAFUNC_MPIDR 1 -// TC_CoreAFunc_VBAR -#define TC_COREAFUNC_VBAR 1 -// TC_CoreAFunc_MVBAR -#define TC_COREAFUNC_MVBAR 1 -// TC_CoreAFunc_FPU_Enable -#define TC_COREAFUNC_FPU_ENABLE 1 - -// TC_GenTimer_CNTFRQ -#define TC_GENTIMER_CNTFRQ 1 -// TC_GenTimer_CNTP_TVAL -#define TC_GENTIMER_CNTP_TVAL 1 -// TC_GenTimer_CNTP_CTL -#define TC_GENTIMER_CNTP_CTL 1 -// TC_GenTimer_CNTPCT -#define TC_GENTIMER_CNTPCT 1 -// TC_GenTimer_CNTP_CVAL -#define TC_GENTIMER_CNTP_CVAL 1 - -// TC_CAL1Cache_EnDisable -#define TC_CAL1CACHE_ENDISABLE 1 -// TC_CAL1Cache_EnDisableBTAC -#define TC_CAL1CACHE_ENDISABLEBTAC 1 -// TC_CAL1Cache_log2_up -#define TC_CAL1CACHE_LOG2_UP 1 -// TC_CAL1Cache_InvalidateDCacheAll -#define TC_CAL1CACHE_INVALIDATEDCACHEALL 1 -// TC_CAL1Cache_CleanDCacheAll -#define TC_CAL1CACHE_CLEANDCACHEALL 1 -// TC_CAL1Cache_CleanInvalidateDCacheAll -#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1 -// - -#endif /* __CV_CONFIG_H */ - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config_template.h b/external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config_template.h deleted file mode 100644 index d2e0532..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config_template.h +++ /dev/null @@ -1,120 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: CV_Config.h - * Purpose: CV Config header - *---------------------------------------------------------------------------- - * Copyright (c) 2017 - 2021 ARM Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#ifndef __CV_CONFIG_H -#define __CV_CONFIG_H - -#include "RTE_Components.h" -#include CMSIS_device_header - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Common Test Settings -// Print Output Format <0=> Plain Text <1=> XML -// Set the test results output format to plain text or XML -#ifndef PRINT_XML_REPORT -#define PRINT_XML_REPORT 0 -#endif -// Buffer size for assertions results -// Set the buffer size for assertions results buffer -#define BUFFER_ASSERTIONS 128U -// - -// Disable Test Cases -// Uncheck to disable an individual test case -// TC_CoreInstr_NOP -#define TC_COREINSTR_NOP_EN 1 -// TC_CoreInstr_REV -#define TC_COREINSTR_REV_EN 1 -// TC_CoreInstr_REV16 -#define TC_COREINSTR_REV16_EN 1 -// TC_CoreInstr_REVSH -#define TC_COREINSTR_REVSH_EN 1 -// TC_CoreInstr_ROR -#define TC_COREINSTR_ROR_EN 1 -// TC_CoreInstr_RBIT -#define TC_COREINSTR_RBIT_EN 1 -// TC_CoreInstr_CLZ -#define TC_COREINSTR_CLZ_EN 1 -// TC_CoreInstr_Exclusives -#define TC_COREINSTR_EXCLUSIVES_EN 1 -// TC_CoreInstr_SSAT -#define TC_COREINSTR_SSAT_EN 1 -// TC_CoreInstr_USAT -#define TC_COREINSTR_USAT_EN 1 - -// TC_CoreAFunc_IRQ -#define TC_COREAFUNC_IRQ 1 -// TC_CoreAFunc_FaultIRQ -#define TC_COREAFUNC_FAULTIRQ 1 -// TC_CoreAFunc_FPSCR -#define TC_COREAFUNC_FPSCR 1 -// TC_CoreAFunc_CPSR -#define TC_COREAFUNC_CPSR 1 -// TC_CoreAFunc_Mode -#define TC_COREAFUNC_MODE 1 -// TC_CoreAFunc_SP -#define TC_COREAFUNC_SP 1 -// TC_CoreAFunc_SP_usr -#define TC_COREAFUNC_SP_USR 1 -// TC_CoreAFunc_FPEXC -#define TC_COREAFUNC_FPEXC 1 -// TC_CoreAFunc_ACTLR -#define TC_COREAFUNC_ACTLR 1 -// TC_CoreAFunc_CPACR -#define TC_COREAFUNC_CPACR 1 -// TC_CoreAFunc_DFSR -#define TC_COREAFUNC_DFSR 1 -// TC_CoreAFunc_IFSR -#define TC_COREAFUNC_IFSR 1 -// TC_CoreAFunc_ISR -#define TC_COREAFUNC_ISR 1 -// TC_CoreAFunc_CBAR -#define TC_COREAFUNC_CBAR 1 -// TC_CoreAFunc_TTBR0 -#define TC_COREAFUNC_TTBR0 1 -// TC_CoreAFunc_DACR -#define TC_COREAFUNC_DACR 1 -// TC_CoreAFunc_SCTLR -#define TC_COREAFUNC_SCTLR 1 -// TC_CoreAFunc_ACTRL -#define TC_COREAFUNC_ACTRL 1 -// TC_CoreAFunc_MPIDR -#define TC_COREAFUNC_MPIDR 1 -// TC_CoreAFunc_VBAR -#define TC_COREAFUNC_VBAR 1 -// TC_CoreAFunc_MVBAR -#define TC_COREAFUNC_MVBAR 1 -// TC_CoreAFunc_FPU_Enable -#define TC_COREAFUNC_FPU_ENABLE 1 - -// TC_GenTimer_CNTFRQ -#define TC_GENTIMER_CNTFRQ 1 -// TC_GenTimer_CNTP_TVAL -#define TC_GENTIMER_CNTP_TVAL 1 -// TC_GenTimer_CNTP_CTL -#define TC_GENTIMER_CNTP_CTL 1 -// TC_GenTimer_CNTPCT -#define TC_GENTIMER_CNTPCT 1 -// TC_GenTimer_CNTP_CVAL -#define TC_GENTIMER_CNTP_CVAL 1 - -// TC_CAL1Cache_EnDisable -#define TC_CAL1CACHE_ENDISABLE 1 -// TC_CAL1Cache_EnDisableBTAC -#define TC_CAL1CACHE_ENDISABLEBTAC 1 -// TC_CAL1Cache_log2_up -#define TC_CAL1CACHE_LOG2_UP 1 -// TC_CAL1Cache_InvalidateDCacheAll -#define TC_CAL1CACHE_INVALIDATEDCACHEALL 1 -// TC_CAL1Cache_CleanDCacheAll -#define TC_CAL1CACHE_CLEANDCACHEALL 1 -// TC_CAL1Cache_CleanInvalidateDCacheAll -#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1 -// - -#endif /* __CV_CONFIG_H */ - diff --git a/external/CMSIS_5/CMSIS/CoreValidation/Source/cmsis_cv.c b/external/CMSIS_5/CMSIS/CoreValidation/Source/cmsis_cv.c deleted file mode 100644 index 226d5cf..0000000 --- a/external/CMSIS_5/CMSIS/CoreValidation/Source/cmsis_cv.c +++ /dev/null @@ -1,189 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: cmsis_cv.c - * Purpose: Driver validation test cases entry point - *---------------------------------------------------------------------------- - * Copyright (c) 2017 - 2021 Arm Limited. All rights reserved. - *----------------------------------------------------------------------------*/ -#include "cmsis_cv.h" -#include "RTE_Components.h" -#include "CV_Framework.h" -#include "CV_Config.h" - -/*----------------------------------------------------------------------------- - * Prototypes - *----------------------------------------------------------------------------*/ - -void Interrupt0_Handler(void); - -/*----------------------------------------------------------------------------- - * Variables declarations - *----------------------------------------------------------------------------*/ - -void (*TST_IRQHandler)(void); - -void Interrupt0_Handler(void) { - if (TST_IRQHandler != NULL) TST_IRQHandler(); -} - -/*----------------------------------------------------------------------------- - * Init test suite - *----------------------------------------------------------------------------*/ -static void TS_Init (void) { - TST_IRQHandler = NULL; - -#ifdef RTE_CV_MEASURETICKS - StartCortexCycleCounter(); -#endif -} - -/*----------------------------------------------------------------------------- - * Test cases list - *----------------------------------------------------------------------------*/ -static TEST_CASE TC_LIST[] = { -#if defined(RTE_CV_COREINSTR) && RTE_CV_COREINSTR - #if defined(__CORTEX_M) - TCD ( TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ), - TCD ( TC_CoreInstr_WFI, TC_COREINSTR_WFI_EN ), - TCD ( TC_CoreInstr_WFE, TC_COREINSTR_WFE_EN ), - TCD ( TC_CoreInstr_SEV, TC_COREINSTR_SEV_EN ), - TCD ( TC_CoreInstr_BKPT, TC_COREINSTR_BKPT_EN ), - TCD ( TC_CoreInstr_ISB, TC_COREINSTR_ISB_EN ), - TCD ( TC_CoreInstr_DSB, TC_COREINSTR_DSB_EN ), - TCD ( TC_CoreInstr_DMB, TC_COREINSTR_DMB_EN ), - TCD ( TC_CoreInstr_REV, TC_COREINSTR_REV_EN ), - TCD ( TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ), - TCD ( TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ), - TCD ( TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ), - TCD ( TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ), - TCD ( TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ), - TCD ( TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ), - TCD ( TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ), - TCD ( TC_CoreInstr_RRX, TC_COREINSTR_RRX_EN ), - TCD ( TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_LOADSTOREEXCLUSIVE_EN ), - TCD ( TC_CoreInstr_LoadStoreUnpriv, TC_COREINSTR_LOADSTOREUNPRIV_EN ), - TCD ( TC_CoreInstr_LoadStoreAcquire, TC_COREINSTR_LOADSTOREACQUIRE_EN ), - TCD ( TC_CoreInstr_LoadStoreAcquireExclusive, TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN ), - TCD ( TC_CoreInstr_UnalignedUint16, TC_COREINSTR_UNALIGNEDUINT16_EN ), - TCD ( TC_CoreInstr_UnalignedUint32, TC_COREINSTR_UNALIGNEDUINT32_EN ), - - #elif defined(__CORTEX_A) - TCD (TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ), - TCD (TC_CoreInstr_REV, TC_COREINSTR_REV_EN ), - TCD (TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ), - TCD (TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ), - TCD (TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ), - TCD (TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ), - TCD (TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ), - TCD (TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ), - TCD (TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ), - TCD (TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_EXCLUSIVES_EN ), - #endif -#endif /* RTE_CV_COREINSTR */ - -#if defined (RTE_CV_CORESIMD) && RTE_CV_CORESIMD - TCD ( TC_CoreSimd_SatAddSub, TC_CORESIMD_SATADDSUB_EN ), - TCD ( TC_CoreSimd_ParSat16, TC_CORESIMD_PARSAT16_EN ), - TCD ( TC_CoreSimd_PackUnpack, TC_CORESIMD_PACKUNPACK_EN ), - TCD ( TC_CoreSimd_ParSel, TC_CORESIMD_PARSEL_EN ), - TCD ( TC_CoreSimd_ParAddSub8, TC_CORESIMD_PARADDSUB8_EN ), - TCD ( TC_CoreSimd_AbsDif8, TC_CORESIMD_ABSDIF8_EN ), - TCD ( TC_CoreSimd_ParAddSub16, TC_CORESIMD_PARADDSUB16_EN ), - TCD ( TC_CoreSimd_ParMul16, TC_CORESIMD_PARMUL16_EN ), - TCD ( TC_CoreSimd_Pack16, TC_CORESIMD_PACK16_EN ), - TCD ( TC_CoreSimd_MulAcc32, TC_CORESIMD_MULACC32_EN ), -#endif /* RTE_CV_CORESIMD */ - -#if defined(RTE_CV_COREFUNC) && RTE_CV_COREFUNC - #if defined(__CORTEX_M) - TCD ( TC_CoreFunc_EnDisIRQ, TC_COREFUNC_ENDISIRQ_EN ), - TCD ( TC_CoreFunc_IRQPrio, TC_COREFUNC_IRQPRIO_EN ), - TCD ( TC_CoreFunc_EncDecIRQPrio, TC_COREFUNC_ENCDECIRQPRIO_EN ), - TCD ( TC_CoreFunc_IRQVect, TC_COREFUNC_IRQVECT_EN ), - TCD ( TC_CoreFunc_Control, TC_COREFUNC_CONTROL_EN ), - TCD ( TC_CoreFunc_IPSR, TC_COREFUNC_IPSR_EN ), - TCD ( TC_CoreFunc_APSR, TC_COREFUNC_APSR_EN ), - TCD ( TC_CoreFunc_PSP, TC_COREFUNC_PSP_EN ), - TCD ( TC_CoreFunc_MSP, TC_COREFUNC_MSP_EN ), - TCD ( TC_CoreFunc_PSPLIM, TC_COREFUNC_PSPLIM_EN ), - TCD ( TC_CoreFunc_PSPLIM_NS, TC_COREFUNC_PSPLIM_NS_EN ), - TCD ( TC_CoreFunc_MSPLIM, TC_COREFUNC_MSPLIM_EN ), - TCD ( TC_CoreFunc_MSPLIM_NS, TC_COREFUNC_MSPLIM_NS_EN ), - TCD ( TC_CoreFunc_PRIMASK, TC_COREFUNC_PRIMASK_EN ), - TCD ( TC_CoreFunc_FAULTMASK, TC_COREFUNC_FAULTMASK_EN ), - TCD ( TC_CoreFunc_BASEPRI, TC_COREFUNC_BASEPRI_EN ), - TCD ( TC_CoreFunc_FPUType, TC_COREFUNC_FPUTYPE_EN ), - TCD ( TC_CoreFunc_FPSCR, TC_COREFUNC_FPSCR_EN ), - - #elif defined(__CORTEX_A) - TCD ( TC_CoreAFunc_IRQ, TC_COREAFUNC_IRQ ), - TCD ( TC_CoreAFunc_FaultIRQ, TC_COREAFUNC_FAULTIRQ ), - TCD ( TC_CoreAFunc_FPSCR, TC_COREAFUNC_FPSCR ), - TCD ( TC_CoreAFunc_CPSR, TC_COREAFUNC_CPSR ), - TCD ( TC_CoreAFunc_Mode, TC_COREAFUNC_MODE ), - TCD ( TC_CoreAFunc_SP, TC_COREAFUNC_SP ), - TCD ( TC_CoreAFunc_SP_usr, TC_COREAFUNC_SP_USR ), - TCD ( TC_CoreAFunc_FPEXC, TC_COREAFUNC_FPEXC ), - TCD ( TC_CoreAFunc_ACTLR, TC_COREAFUNC_ACTLR ), - TCD ( TC_CoreAFunc_CPACR, TC_COREAFUNC_CPACR ), - TCD ( TC_CoreAFunc_DFSR, TC_COREAFUNC_DFSR ), - TCD ( TC_CoreAFunc_IFSR, TC_COREAFUNC_IFSR ), - TCD ( TC_CoreAFunc_ISR, TC_COREAFUNC_ISR ), - TCD ( TC_CoreAFunc_CBAR, TC_COREAFUNC_CBAR ), - TCD ( TC_CoreAFunc_TTBR0, TC_COREAFUNC_TTBR0 ), - TCD ( TC_CoreAFunc_DACR, TC_COREAFUNC_DACR ), - TCD ( TC_CoreAFunc_SCTLR, TC_COREAFUNC_SCTLR ), - TCD ( TC_CoreAFunc_ACTRL, TC_COREAFUNC_ACTRL ), - TCD ( TC_CoreAFunc_MPIDR, TC_COREAFUNC_MPIDR ), - TCD ( TC_CoreAFunc_VBAR, TC_COREAFUNC_VBAR ), - TCD ( TC_CoreAFunc_MVBAR, TC_COREAFUNC_MVBAR ), - TCD ( TC_CoreAFunc_FPU_Enable, TC_COREAFUNC_FPU_ENABLE ), - #endif -#endif /* RTE_CV_COREFUNC */ - -#if defined(RTE_CV_MPUFUNC) && RTE_CV_MPUFUNC - TCD ( TC_MPU_SetClear, TC_MPU_SETCLEAR_EN ), - TCD ( TC_MPU_Load, TC_MPU_LOAD_EN ), -#endif /* RTE_CV_MPUFUNC */ - -#if defined(RTE_CV_GENTIMER) && RTE_CV_GENTIMER - TCD ( TC_GenTimer_CNTFRQ, TC_GENTIMER_CNTFRQ ), - TCD ( TC_GenTimer_CNTP_TVAL, TC_GENTIMER_CNTP_TVAL ), - TCD ( TC_GenTimer_CNTP_CTL, TC_GENTIMER_CNTP_CTL ), - TCD ( TC_GenTimer_CNTPCT, TC_GENTIMER_CNTPCT ), - TCD ( TC_GenTimer_CNTP_CVAL, TC_GENTIMER_CNTP_CVAL ), -#endif /* RTE_CV_GENTIMER */ - -#if defined(RTE_CV_L1CACHE) && RTE_CV_L1CACHE - #if defined(__CORTEX_M) - TCD ( TC_CML1Cache_EnDisableICache, TC_CML1CACHE_ENDISABLE_ICACHE ), - TCD ( TC_CML1Cache_EnDisableDCache, TC_CML1CACHE_ENDISABLE_DCACHE ), - TCD ( TC_CML1Cache_CleanDCacheByAddrWhileDisabled, TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED), - #elif defined(__CORTEX_A) - TCD ( TC_CAL1Cache_EnDisable, TC_CAL1CACHE_ENDISABLE ), - TCD ( TC_CAL1Cache_EnDisableBTAC, TC_CAL1CACHE_ENDISABLEBTAC ), - TCD ( TC_CAL1Cache_log2_up, TC_CAL1CACHE_LOG2_UP ), - TCD ( TC_CAL1Cache_InvalidateDCacheAll, TC_CAL1CACHE_INVALIDATEDCACHEALL ), - TCD ( TC_CAL1Cache_CleanDCacheAll, TC_CAL1CACHE_CLEANDCACHEALL ), - TCD ( TC_CAL1Cache_CleanInvalidateDCacheAll, TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL ), - #endif -#endif /* RTE_CV_L1CACHE */ -}; - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wdate-time" -#endif -/*----------------------------------------------------------------------------- - * Test suite description - *----------------------------------------------------------------------------*/ -TEST_SUITE ts = { - __FILE__, __DATE__, __TIME__, - "CMSIS-CORE Test Suite", - TS_Init, - 1, - TC_LIST, - ARRAY_SIZE (TC_LIST), -}; -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang diagnostic pop -#endif diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armcc.h b/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armcc.h deleted file mode 100644 index 66a03f8..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armcc.h +++ /dev/null @@ -1,605 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V1.0.6 - * @date 13. November 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) - #define __ARM_ARCH_7A__ 1 -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __FORCEINLINE - #define __FORCEINLINE __forceinline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ########################## Core Instruction Access ######################### */ -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - -/* ########################### Core Function Access ########################### */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(void); */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - -/** - \brief Get FPSCR (Floating Point Status/Control) - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - -/** - \brief Set FPSCR (Floating Point Status/Control) - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -/** \brief Get CPSR (Current Program Status Register) - \return CPSR Register value - */ -__STATIC_INLINE uint32_t __get_CPSR(void) -{ - register uint32_t __regCPSR __ASM("cpsr"); - return(__regCPSR); -} - - -/** \brief Set CPSR (Current Program Status Register) - \param [in] cpsr CPSR value to set - */ -__STATIC_INLINE void __set_CPSR(uint32_t cpsr) -{ - register uint32_t __regCPSR __ASM("cpsr"); - __regCPSR = cpsr; -} - -/** \brief Get Mode - \return Processor Mode - */ -__STATIC_INLINE uint32_t __get_mode(void) -{ - return (__get_CPSR() & 0x1FU); -} - -/** \brief Set Mode - \param [in] mode Mode value to set - */ -__STATIC_INLINE __ASM void __set_mode(uint32_t mode) -{ - MOV r1, lr - MSR CPSR_C, r0 - BX r1 -} - -/** \brief Get Stack Pointer - \return Stack Pointer - */ -__STATIC_INLINE __ASM uint32_t __get_SP(void) -{ - MOV r0, sp - BX lr -} - -/** \brief Set Stack Pointer - \param [in] stack Stack Pointer value to set - */ -__STATIC_INLINE __ASM void __set_SP(uint32_t stack) -{ - MOV sp, r0 - BX lr -} - - -/** \brief Get USR/SYS Stack Pointer - \return USR/SYSStack Pointer - */ -__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) -{ - ARM - PRESERVE8 - - MRS R1, CPSR - CPS #0x1F ;no effect in USR mode - MOV R0, SP - MSR CPSR_c, R1 ;no effect in USR mode - ISB - BX LR -} - -/** \brief Set USR/SYS Stack Pointer - \param [in] topOfProcStack USR/SYS Stack Pointer value to set - */ -__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) -{ - ARM - PRESERVE8 - - MRS R1, CPSR - CPS #0x1F ;no effect in USR mode - MOV SP, R0 - MSR CPSR_c, R1 ;no effect in USR mode - ISB - BX LR -} - -/** \brief Get FPEXC (Floating Point Exception Control Register) - \return Floating Point Exception Control Register value - */ -__STATIC_INLINE uint32_t __get_FPEXC(void) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpexc __ASM("fpexc"); - return(__regfpexc); -#else - return(0); -#endif -} - -/** \brief Set FPEXC (Floating Point Exception Control Register) - \param [in] fpexc Floating Point Exception Control value to set - */ -__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpexc __ASM("fpexc"); - __regfpexc = (fpexc); -#endif -} - -/* - * Include common core functions to access Coprocessor 15 registers - */ - -#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) -#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) -#define __get_CP64(cp, op1, Rt, CRm) \ - do { \ - uint32_t ltmp, htmp; \ - __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ - (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ - } while(0) - -#define __set_CP64(cp, op1, Rt, CRm) \ - do { \ - const uint64_t tmp = (Rt); \ - const uint32_t ltmp = (uint32_t)(tmp); \ - const uint32_t htmp = (uint32_t)(tmp >> 32U); \ - __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ - } while(0) - -#include "cmsis_cp15.h" - -/** \brief Enable Floating Point Unit - - Critical section, called from undef handler, so systick is disabled - */ -__STATIC_INLINE __ASM void __FPU_Enable(void) -{ - ARM - - //Permit access to VFP/NEON, registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - ISB - - //Enable VFP/NEON - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP/NEON registers to 0 - MOV R2,#0 - - //Initialise D16 registers to 0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - - IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 - //Initialise D32 registers to 0 - VMOV D16,R2,R2 - VMOV D17,R2,R2 - VMOV D18,R2,R2 - VMOV D19,R2,R2 - VMOV D20,R2,R2 - VMOV D21,R2,R2 - VMOV D22,R2,R2 - VMOV D23,R2,R2 - VMOV D24,R2,R2 - VMOV D25,R2,R2 - VMOV D26,R2,R2 - VMOV D27,R2,R2 - VMOV D28,R2,R2 - VMOV D29,R2,R2 - VMOV D30,R2,R2 - VMOV D31,R2,R2 - ENDIF - - //Initialise FPSCR to a known state - VMRS R1,FPSCR - LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R1,R1,R2 - VMSR FPSCR,R1 - - BX LR -} - -#endif /* __CMSIS_ARMCC_H */ diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armclang.h b/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armclang.h deleted file mode 100644 index 2d5be0f..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armclang.h +++ /dev/null @@ -1,644 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.2.2 - * @date 13. November 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __FORCEINLINE - #define __FORCEINLINE __attribute__((always_inline)) -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ########################## Core Instruction Access ######################### */ -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -#define __SADD8 __builtin_arm_sadd8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD8 __builtin_arm_qadd8 -#define __QSUB8 __builtin_arm_qsub8 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __SXTB16 __builtin_arm_sxtb16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSDX __builtin_arm_smlsdx -#define __USAT16 __builtin_arm_usat16 -#define __SSUB8 __builtin_arm_ssub8 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 - - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ - -/* ########################### Core Function Access ########################### */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr - -/** \brief Get CPSR Register - \return CPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CPSR(void) -{ - uint32_t result; - __ASM volatile("MRS %0, cpsr" : "=r" (result) ); - return(result); -} - -/** \brief Set CPSR Register - \param [in] cpsr CPSR value to set - */ -__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) -{ - __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); -} - -/** \brief Get Mode - \return Processor Mode - */ -__STATIC_FORCEINLINE uint32_t __get_mode(void) -{ - return (__get_CPSR() & 0x1FU); -} - -/** \brief Set Mode - \param [in] mode Mode value to set - */ -__STATIC_FORCEINLINE void __set_mode(uint32_t mode) -{ - __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); -} - -/** \brief Get Stack Pointer - \return Stack Pointer value - */ -__STATIC_FORCEINLINE uint32_t __get_SP(void) -{ - uint32_t result; - __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); - return result; -} - -/** \brief Set Stack Pointer - \param [in] stack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_SP(uint32_t stack) -{ - __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); -} - -/** \brief Get USR/SYS Stack Pointer - \return USR/SYS Stack Pointer value - */ -__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) -{ - uint32_t cpsr; - uint32_t result; - __ASM volatile( - "MRS %0, cpsr \n" - "CPS #0x1F \n" // no effect in USR mode - "MOV %1, sp \n" - "MSR cpsr_c, %0 \n" // no effect in USR mode - "ISB" : "=r"(cpsr), "=r"(result) : : "memory" - ); - return result; -} - -/** \brief Set USR/SYS Stack Pointer - \param [in] topOfProcStack USR/SYS Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) -{ - uint32_t cpsr; - __ASM volatile( - "MRS %0, cpsr \n" - "CPS #0x1F \n" // no effect in USR mode - "MOV sp, %1 \n" - "MSR cpsr_c, %0 \n" // no effect in USR mode - "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" - ); -} - -/** \brief Get FPEXC - \return Floating Point Exception Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) -{ -#if (__FPU_PRESENT == 1) - uint32_t result; - __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); - return(result); -#else - return(0); -#endif -} - -/** \brief Set FPEXC - \param [in] fpexc Floating Point Exception Control value to set - */ -__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) -{ -#if (__FPU_PRESENT == 1) - __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); -#endif -} - -/* - * Include common core functions to access Coprocessor 15 registers - */ - -#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) -#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) -#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) -#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) - -#include "cmsis_cp15.h" - -/** \brief Enable Floating Point Unit - - Critical section, called from undef handler, so systick is disabled - */ -__STATIC_INLINE void __FPU_Enable(void) -{ - __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR - " MRC p15,0,R1,c1,c0,2 \n" - " ORR R1,R1,#0x00F00000 \n" - " MCR p15,0,R1,c1,c0,2 \n" - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - " ISB \n" - - //Enable VFP/NEON - " VMRS R1,FPEXC \n" - " ORR R1,R1,#0x40000000 \n" - " VMSR FPEXC,R1 \n" - - //Initialise VFP/NEON registers to 0 - " MOV R2,#0 \n" - - //Initialise D16 registers to 0 - " VMOV D0, R2,R2 \n" - " VMOV D1, R2,R2 \n" - " VMOV D2, R2,R2 \n" - " VMOV D3, R2,R2 \n" - " VMOV D4, R2,R2 \n" - " VMOV D5, R2,R2 \n" - " VMOV D6, R2,R2 \n" - " VMOV D7, R2,R2 \n" - " VMOV D8, R2,R2 \n" - " VMOV D9, R2,R2 \n" - " VMOV D10,R2,R2 \n" - " VMOV D11,R2,R2 \n" - " VMOV D12,R2,R2 \n" - " VMOV D13,R2,R2 \n" - " VMOV D14,R2,R2 \n" - " VMOV D15,R2,R2 \n" - -#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) - //Initialise D32 registers to 0 - " VMOV D16,R2,R2 \n" - " VMOV D17,R2,R2 \n" - " VMOV D18,R2,R2 \n" - " VMOV D19,R2,R2 \n" - " VMOV D20,R2,R2 \n" - " VMOV D21,R2,R2 \n" - " VMOV D22,R2,R2 \n" - " VMOV D23,R2,R2 \n" - " VMOV D24,R2,R2 \n" - " VMOV D25,R2,R2 \n" - " VMOV D26,R2,R2 \n" - " VMOV D27,R2,R2 \n" - " VMOV D28,R2,R2 \n" - " VMOV D29,R2,R2 \n" - " VMOV D30,R2,R2 \n" - " VMOV D31,R2,R2 \n" -#endif - - //Initialise FPSCR to a known state - " VMRS R1,FPSCR \n" - " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R1,R1,R2 \n" - " VMSR FPSCR,R1 " - : : : "cc", "r1", "r2" - ); -} - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_compiler.h b/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_compiler.h deleted file mode 100644 index 3adf602..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_compiler.h +++ /dev/null @@ -1,245 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.3 - * @date 13. November 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef CMSIS_DEPRECATED - #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. - #define CMSIS_DEPRECATED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_cp15.h b/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_cp15.h deleted file mode 100644 index 9d53001..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_cp15.h +++ /dev/null @@ -1,523 +0,0 @@ -/**************************************************************************//** - * @file cmsis_cp15.h - * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.2 - * @date 19. December 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_CP15_H -#define __CMSIS_CP15_H - -/** \brief Get ACTLR - \return Auxiliary Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 1, 0, 1); - return(result); -} - -/** \brief Set ACTLR - \param [in] actlr Auxiliary Control value to set - */ -__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) -{ - __set_CP(15, 0, actlr, 1, 0, 1); -} - -/** \brief Get CPACR - \return Coprocessor Access Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_CPACR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 1, 0, 2); - return result; -} - -/** \brief Set CPACR - \param [in] cpacr Coprocessor Access Control value to set - */ -__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) -{ - __set_CP(15, 0, cpacr, 1, 0, 2); -} - -/** \brief Get DFSR - \return Data Fault Status Register value - */ -__STATIC_FORCEINLINE uint32_t __get_DFSR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 5, 0, 0); - return result; -} - -/** \brief Set DFSR - \param [in] dfsr Data Fault Status value to set - */ -__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) -{ - __set_CP(15, 0, dfsr, 5, 0, 0); -} - -/** \brief Get IFSR - \return Instruction Fault Status Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IFSR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 5, 0, 1); - return result; -} - -/** \brief Set IFSR - \param [in] ifsr Instruction Fault Status value to set - */ -__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) -{ - __set_CP(15, 0, ifsr, 5, 0, 1); -} - -/** \brief Get ISR - \return Interrupt Status Register value - */ -__STATIC_FORCEINLINE uint32_t __get_ISR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 12, 1, 0); - return result; -} - -/** \brief Get CBAR - \return Configuration Base Address register value - */ -__STATIC_FORCEINLINE uint32_t __get_CBAR(void) -{ - uint32_t result; - __get_CP(15, 4, result, 15, 0, 0); - return result; -} - -/** \brief Get TTBR0 - - This function returns the value of the Translation Table Base Register 0. - - \return Translation Table Base Register 0 value - */ -__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) -{ - uint32_t result; - __get_CP(15, 0, result, 2, 0, 0); - return result; -} - -/** \brief Set TTBR0 - - This function assigns the given value to the Translation Table Base Register 0. - - \param [in] ttbr0 Translation Table Base Register 0 value to set - */ -__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) -{ - __set_CP(15, 0, ttbr0, 2, 0, 0); -} - -/** \brief Get DACR - - This function returns the value of the Domain Access Control Register. - - \return Domain Access Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_DACR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 3, 0, 0); - return result; -} - -/** \brief Set DACR - - This function assigns the given value to the Domain Access Control Register. - - \param [in] dacr Domain Access Control Register value to set - */ -__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) -{ - __set_CP(15, 0, dacr, 3, 0, 0); -} - -/** \brief Set SCTLR - - This function assigns the given value to the System Control Register. - - \param [in] sctlr System Control Register value to set - */ -__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) -{ - __set_CP(15, 0, sctlr, 1, 0, 0); -} - -/** \brief Get SCTLR - \return System Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 1, 0, 0); - return result; -} - -/** \brief Set ACTRL - \param [in] actrl Auxiliary Control Register value to set - */ -__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) -{ - __set_CP(15, 0, actrl, 1, 0, 1); -} - -/** \brief Get ACTRL - \return Auxiliary Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) -{ - uint32_t result; - __get_CP(15, 0, result, 1, 0, 1); - return result; -} - -/** \brief Get MPIDR - - This function returns the value of the Multiprocessor Affinity Register. - - \return Multiprocessor Affinity Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 0, 0, 5); - return result; -} - -/** \brief Get VBAR - - This function returns the value of the Vector Base Address Register. - - \return Vector Base Address Register - */ -__STATIC_FORCEINLINE uint32_t __get_VBAR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 12, 0, 0); - return result; -} - -/** \brief Set VBAR - - This function assigns the given value to the Vector Base Address Register. - - \param [in] vbar Vector Base Address Register value to set - */ -__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) -{ - __set_CP(15, 0, vbar, 12, 0, 0); -} - -/** \brief Get MVBAR - - This function returns the value of the Monitor Vector Base Address Register. - - \return Monitor Vector Base Address Register - */ -__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) -{ - uint32_t result; - __get_CP(15, 0, result, 12, 0, 1); - return result; -} - -/** \brief Set MVBAR - - This function assigns the given value to the Monitor Vector Base Address Register. - - \param [in] mvbar Monitor Vector Base Address Register value to set - */ -__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) -{ - __set_CP(15, 0, mvbar, 12, 0, 1); -} - -#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ - defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ - defined(DOXYGEN) - -/** \brief Set CNTFRQ - - This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). - - \param [in] value CNTFRQ Register value to set -*/ -__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) -{ - __set_CP(15, 0, value, 14, 0, 0); -} - -/** \brief Get CNTFRQ - - This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). - - \return CNTFRQ Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) -{ - uint32_t result; - __get_CP(15, 0, result, 14, 0 , 0); - return result; -} - -/** \brief Set CNTP_TVAL - - This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). - - \param [in] value CNTP_TVAL Register value to set -*/ -__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) -{ - __set_CP(15, 0, value, 14, 2, 0); -} - -/** \brief Get CNTP_TVAL - - This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). - - \return CNTP_TVAL Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) -{ - uint32_t result; - __get_CP(15, 0, result, 14, 2, 0); - return result; -} - -/** \brief Get CNTPCT - - This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). - - \return CNTPCT Register value - */ -__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) -{ - uint64_t result; - __get_CP64(15, 0, result, 14); - return result; -} - -/** \brief Set CNTP_CVAL - - This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). - - \param [in] value CNTP_CVAL Register value to set -*/ -__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) -{ - __set_CP64(15, 2, value, 14); -} - -/** \brief Get CNTP_CVAL - - This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). - - \return CNTP_CVAL Register value - */ -__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) -{ - uint64_t result; - __get_CP64(15, 2, result, 14); - return result; -} - -/** \brief Set CNTP_CTL - - This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). - - \param [in] value CNTP_CTL Register value to set -*/ -__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) -{ - __set_CP(15, 0, value, 14, 2, 1); -} - -/** \brief Get CNTP_CTL register - \return CNTP_CTL Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) -{ - uint32_t result; - __get_CP(15, 0, result, 14, 2, 1); - return result; -} - -#endif - -/** \brief Set TLBIALL - - TLB Invalidate All - */ -__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) -{ - __set_CP(15, 0, value, 8, 7, 0); -} - -/** \brief Set BPIALL. - - Branch Predictor Invalidate All - */ -__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) -{ - __set_CP(15, 0, value, 7, 5, 6); -} - -/** \brief Set ICIALLU - - Instruction Cache Invalidate All - */ -__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) -{ - __set_CP(15, 0, value, 7, 5, 0); -} - -/** \brief Set ICIMVAC - - Instruction Cache Invalidate - */ -__STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value) -{ - __set_CP(15, 0, value, 7, 5, 1); -} - -/** \brief Set DCCMVAC - - Data cache clean - */ -__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) -{ - __set_CP(15, 0, value, 7, 10, 1); -} - -/** \brief Set DCIMVAC - - Data cache invalidate - */ -__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) -{ - __set_CP(15, 0, value, 7, 6, 1); -} - -/** \brief Set DCCIMVAC - - Data cache clean and invalidate - */ -__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) -{ - __set_CP(15, 0, value, 7, 14, 1); -} - -/** \brief Set CSSELR - */ -__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) -{ -// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); - __set_CP(15, 2, value, 0, 0, 0); -} - -/** \brief Get CSSELR - \return CSSELR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) -{ - uint32_t result; -// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); - __get_CP(15, 2, result, 0, 0, 0); - return result; -} - -/** \brief Set CCSIDR - \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. - */ -CMSIS_DEPRECATED -__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) -{ - __set_CSSELR(value); -} - -/** \brief Get CCSIDR - \return CCSIDR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) -{ - uint32_t result; -// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); - __get_CP(15, 1, result, 0, 0, 0); - return result; -} - -/** \brief Get CLIDR - \return CLIDR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) -{ - uint32_t result; -// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); - __get_CP(15, 1, result, 0, 0, 1); - return result; -} - -/** \brief Set DCISW - */ -__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) -{ -// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") - __set_CP(15, 0, value, 7, 6, 2); -} - -/** \brief Set DCCSW - */ -__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) -{ -// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") - __set_CP(15, 0, value, 7, 10, 2); -} - -/** \brief Set DCCISW - */ -__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) -{ -// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") - __set_CP(15, 0, value, 7, 14, 2); -} - -#endif diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_gcc.h b/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_gcc.h deleted file mode 100644 index ef5145b..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_gcc.h +++ /dev/null @@ -1,966 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V1.3.3 - * @date 13. November 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __FORCEINLINE - #define __FORCEINLINE __attribute__((always_inline)) -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : "=r" (result) : "r" (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value)); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_get_fpscr) - // Re-enable using built-in when GCC has been fixed - // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); - #else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); - #endif - #else - return(0U); - #endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_set_fpscr) - // Re-enable using built-in when GCC has been fixed - // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); - #else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); - #endif - #else - (void)fpscr; - #endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*@} end of group CMSIS_SIMD_intrinsics */ - - - -/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/** \brief Get CPSR Register - \return CPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CPSR(void) -{ - uint32_t result; - __ASM volatile("MRS %0, cpsr" : "=r" (result) ); - return(result); -} - -/** \brief Set CPSR Register - \param [in] cpsr CPSR value to set - */ -__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) -{ - __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); -} - -/** \brief Get Mode - \return Processor Mode - */ -__STATIC_FORCEINLINE uint32_t __get_mode(void) -{ - return (__get_CPSR() & 0x1FU); -} - -/** \brief Set Mode - \param [in] mode Mode value to set - */ -__STATIC_FORCEINLINE void __set_mode(uint32_t mode) -{ - __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); -} - -/** \brief Get Stack Pointer - \return Stack Pointer value - */ -__STATIC_FORCEINLINE uint32_t __get_SP(void) -{ - uint32_t result; - __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); - return result; -} - -/** \brief Set Stack Pointer - \param [in] stack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_SP(uint32_t stack) -{ - __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); -} - -/** \brief Get USR/SYS Stack Pointer - \return USR/SYS Stack Pointer value - */ -__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) -{ - uint32_t cpsr = __get_CPSR(); - uint32_t result; - __ASM volatile( - "CPS #0x1F \n" - "MOV %0, sp " : "=r"(result) : : "memory" - ); - __set_CPSR(cpsr); - __ISB(); - return result; -} - -/** \brief Set USR/SYS Stack Pointer - \param [in] topOfProcStack USR/SYS Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) -{ - uint32_t cpsr = __get_CPSR(); - __ASM volatile( - "CPS #0x1F \n" - "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" - ); - __set_CPSR(cpsr); - __ISB(); -} - -/** \brief Get FPEXC - \return Floating Point Exception Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) -{ -#if (__FPU_PRESENT == 1) - uint32_t result; - __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); - return(result); -#else - return(0); -#endif -} - -/** \brief Set FPEXC - \param [in] fpexc Floating Point Exception Control value to set - */ -__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) -{ -#if (__FPU_PRESENT == 1) - __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); -#endif -} - -/* - * Include common core functions to access Coprocessor 15 registers - */ - -#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) -#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) -#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) -#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) - -#include "cmsis_cp15.h" - -/** \brief Enable Floating Point Unit - - Critical section, called from undef handler, so systick is disabled - */ -__STATIC_INLINE void __FPU_Enable(void) -{ - __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR - " MRC p15,0,R1,c1,c0,2 \n" - " ORR R1,R1,#0x00F00000 \n" - " MCR p15,0,R1,c1,c0,2 \n" - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - " ISB \n" - - //Enable VFP/NEON - " VMRS R1,FPEXC \n" - " ORR R1,R1,#0x40000000 \n" - " VMSR FPEXC,R1 \n" - - //Initialise VFP/NEON registers to 0 - " MOV R2,#0 \n" - - //Initialise D16 registers to 0 - " VMOV D0, R2,R2 \n" - " VMOV D1, R2,R2 \n" - " VMOV D2, R2,R2 \n" - " VMOV D3, R2,R2 \n" - " VMOV D4, R2,R2 \n" - " VMOV D5, R2,R2 \n" - " VMOV D6, R2,R2 \n" - " VMOV D7, R2,R2 \n" - " VMOV D8, R2,R2 \n" - " VMOV D9, R2,R2 \n" - " VMOV D10,R2,R2 \n" - " VMOV D11,R2,R2 \n" - " VMOV D12,R2,R2 \n" - " VMOV D13,R2,R2 \n" - " VMOV D14,R2,R2 \n" - " VMOV D15,R2,R2 \n" - -#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) - //Initialise D32 registers to 0 - " VMOV D16,R2,R2 \n" - " VMOV D17,R2,R2 \n" - " VMOV D18,R2,R2 \n" - " VMOV D19,R2,R2 \n" - " VMOV D20,R2,R2 \n" - " VMOV D21,R2,R2 \n" - " VMOV D22,R2,R2 \n" - " VMOV D23,R2,R2 \n" - " VMOV D24,R2,R2 \n" - " VMOV D25,R2,R2 \n" - " VMOV D26,R2,R2 \n" - " VMOV D27,R2,R2 \n" - " VMOV D28,R2,R2 \n" - " VMOV D29,R2,R2 \n" - " VMOV D30,R2,R2 \n" - " VMOV D31,R2,R2 \n" -#endif - - //Initialise FPSCR to a known state - " VMRS R1,FPSCR \n" - " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R1,R1,R2 \n" - " VMSR FPSCR,R1 " - : : : "cc", "r1", "r2" - ); -} - -/*@} end of group CMSIS_Core_intrinsics */ - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_iccarm.h b/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_iccarm.h deleted file mode 100644 index 10f1f92..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/cmsis_iccarm.h +++ /dev/null @@ -1,573 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.8 - * @date 13. November 2022 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2018 IAR Systems -// Copyright (c) 2018-2019 Arm Limited -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#pragma language=extended - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_7A__ -/* Macro already defined */ -#else - #if defined(__ARM7A__) - #define __ARM_ARCH_7A__ 1 - #endif -#endif - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif - -#ifndef __UNALIGNED_UINT16_READ - #pragma language=save - #pragma language=extended - __IAR_FT uint16_t __iar_uint16_read(void const *ptr) - { - return *(__packed uint16_t*)(ptr); - } - #pragma language=restore - #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE - #pragma language=save - #pragma language=extended - __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) - { - *(__packed uint16_t*)(ptr) = val;; - } - #pragma language=restore - #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ - #pragma language=save - #pragma language=extended - __IAR_FT uint32_t __iar_uint32_read(void const *ptr) - { - return *(__packed uint32_t*)(ptr); - } - #pragma language=restore - #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE - #pragma language=save - #pragma language=extended - __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) - { - *(__packed uint32_t*)(ptr) = val;; - } - #pragma language=restore - #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#if 0 -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma language=save - #pragma language=extended - __packed struct __iar_u32 { uint32_t v; }; - #pragma language=restore - #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_CPSR() (__arm_rsr("CPSR")) - #define __get_mode() (__get_CPSR() & 0x1FU) - - #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) - #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) - - - #define __get_FPEXC() (__arm_rsr("FPEXC")) - #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) - - #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ - ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) - - #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ - (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) - - #define __get_CP64(cp, op1, Rt, CRm) \ - __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) - - #define __set_CP64(cp, op1, Rt, CRm) \ - __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) - - #include "cmsis_cp15.h" - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #define __SSAT __iar_builtin_SSAT - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #define __USAT __iar_builtin_USAT - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) - #define __get_FPSCR() (0) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - __IAR_FT void __set_mode(uint32_t mode) - { - __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); - } - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); - return(result); - } - - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - __IAR_FT uint32_t __get_FPEXC(void) - { - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) - uint32_t result; - __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); - return(result); - #else - return(0); - #endif - } - - __IAR_FT void __set_FPEXC(uint32_t fpexc) - { - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) - __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); - #endif - } - - - #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ - __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) - #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ - __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) - #define __get_CP64(cp, op1, Rt, CRm) \ - __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) - #define __set_CP64(cp, op1, Rt, CRm) \ - __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) - - #include "cmsis_cp15.h" - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - - -__IAR_FT uint32_t __get_SP_usr(void) -{ - uint32_t cpsr; - uint32_t result; - __ASM volatile( - "MRS %0, cpsr \n" - "CPS #0x1F \n" // no effect in USR mode - "MOV %1, sp \n" - "MSR cpsr_c, %2 \n" // no effect in USR mode - "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" - ); - return result; -} - -__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) -{ - uint32_t cpsr; - __ASM volatile( - "MRS %0, cpsr \n" - "CPS #0x1F \n" // no effect in USR mode - "MOV sp, %1 \n" - "MSR cpsr_c, %2 \n" // no effect in USR mode - "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" - ); -} - -#define __get_mode() (__get_CPSR() & 0x1FU) - -__STATIC_INLINE -void __FPU_Enable(void) -{ - __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR - " MRC p15,0,R1,c1,c0,2 \n" - " ORR R1,R1,#0x00F00000 \n" - " MCR p15,0,R1,c1,c0,2 \n" - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - " ISB \n" - - //Enable VFP/NEON - " VMRS R1,FPEXC \n" - " ORR R1,R1,#0x40000000 \n" - " VMSR FPEXC,R1 \n" - - //Initialise VFP/NEON registers to 0 - " MOV R2,#0 \n" - - //Initialise D16 registers to 0 - " VMOV D0, R2,R2 \n" - " VMOV D1, R2,R2 \n" - " VMOV D2, R2,R2 \n" - " VMOV D3, R2,R2 \n" - " VMOV D4, R2,R2 \n" - " VMOV D5, R2,R2 \n" - " VMOV D6, R2,R2 \n" - " VMOV D7, R2,R2 \n" - " VMOV D8, R2,R2 \n" - " VMOV D9, R2,R2 \n" - " VMOV D10,R2,R2 \n" - " VMOV D11,R2,R2 \n" - " VMOV D12,R2,R2 \n" - " VMOV D13,R2,R2 \n" - " VMOV D14,R2,R2 \n" - " VMOV D15,R2,R2 \n" - -#ifdef __ARM_ADVANCED_SIMD__ - //Initialise D32 registers to 0 - " VMOV D16,R2,R2 \n" - " VMOV D17,R2,R2 \n" - " VMOV D18,R2,R2 \n" - " VMOV D19,R2,R2 \n" - " VMOV D20,R2,R2 \n" - " VMOV D21,R2,R2 \n" - " VMOV D22,R2,R2 \n" - " VMOV D23,R2,R2 \n" - " VMOV D24,R2,R2 \n" - " VMOV D25,R2,R2 \n" - " VMOV D26,R2,R2 \n" - " VMOV D27,R2,R2 \n" - " VMOV D28,R2,R2 \n" - " VMOV D29,R2,R2 \n" - " VMOV D30,R2,R2 \n" - " VMOV D31,R2,R2 \n" -#endif - - //Initialise FPSCR to a known state - " VMRS R1,FPSCR \n" - " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R1,R1,R2 \n" - " VMSR FPSCR,R1 \n" - : : : "cc", "r1", "r2" - ); -} - - - -#undef __IAR_FT -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/core_ca.h b/external/CMSIS_5/CMSIS/Core_A/Include/core_ca.h deleted file mode 100644 index 12a1a6d..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/core_ca.h +++ /dev/null @@ -1,2940 +0,0 @@ -/**************************************************************************//** - * @file core_ca.h - * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File - * @version V1.0.8 - * @date 23. March 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CA_H_GENERIC -#define __CORE_CA_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ - -/* CMSIS CA definitions */ -#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ -#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ -#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ - __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ - -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CA_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CA_H_DEPENDANT -#define __CORE_CA_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - - /* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CA_REV - #define __CA_REV 0x0000U - #warning "__CA_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __GIC_PRESENT - #define __GIC_PRESENT 1U - #warning "__GIC_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __TIM_PRESENT - #define __TIM_PRESENT 1U - #warning "__TIM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __L2C_PRESENT - #define __L2C_PRESENT 0U - #warning "__L2C_PRESENT not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< \brief Defines 'read only' permissions */ -#else - #define __I volatile const /*!< \brief Defines 'read only' permissions */ -#endif -#define __O volatile /*!< \brief Defines 'write only' permissions */ -#define __IO volatile /*!< \brief Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ -#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ -#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ -#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas - - /******************************************************************************* - * Register Abstraction - Core Register contain: - - CPSR - - CP15 Registers - - L2C-310 Cache Controller - - Generic Interrupt Controller Distributor - - Generic Interrupt Controller Interface - ******************************************************************************/ - -/* Core Register CPSR */ -typedef union -{ - struct - { - uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ - uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ - uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ - uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ - uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ - uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ - uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ - uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ - RESERVED(0:4, uint32_t) - uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ - uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ - uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ - } b; /*!< \brief Structure used for bit access */ - uint32_t w; /*!< \brief Type used for word access */ -} CPSR_Type; - - - -/* CPSR Register Definitions */ -#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ -#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ - -#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ -#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ - -#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ -#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ - -#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ -#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ - -#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ -#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ - -#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ -#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ - -#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ -#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ - -#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ -#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ - -#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ -#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ - -#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ -#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ - -#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ -#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ - -#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ -#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ - -#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ -#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ - -#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ -#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ - -#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ -#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ - -#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ -#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ -#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ -#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ -#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ -#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ -#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ -#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ -#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ - -/* CP15 Register SCTLR */ -typedef union -{ - struct - { - uint32_t M:1; /*!< \brief bit: 0 MMU enable */ - uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ - uint32_t C:1; /*!< \brief bit: 2 Cache enable */ - RESERVED(0:2, uint32_t) - uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ - RESERVED(1:1, uint32_t) - uint32_t B:1; /*!< \brief bit: 7 Endianness model */ - RESERVED(2:2, uint32_t) - uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ - uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ - uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ - uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ - uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ - RESERVED(3:2, uint32_t) - uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ - RESERVED(4:1, uint32_t) - uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ - uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ - uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ - uint32_t U:1; /*!< \brief bit: 22 Alignment model */ - RESERVED(5:1, uint32_t) - uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ - uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ - RESERVED(6:1, uint32_t) - uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ - uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ - uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ - uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ - RESERVED(7:1, uint32_t) - } b; /*!< \brief Structure used for bit access */ - uint32_t w; /*!< \brief Type used for word access */ -} SCTLR_Type; - -#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ -#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ - -#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ -#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ - -#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ -#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ - -#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ -#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ - -#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ -#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ - -#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ -#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ - -#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ -#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ - -#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ -#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ - -#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ -#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ - -#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ -#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ - -#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ -#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ - -#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ -#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ - -#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ -#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ - -#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ -#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ - -#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ -#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ - -#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ -#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ - -#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ -#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ - -#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ -#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ - -#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ -#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ - -#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ -#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ - -#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ -#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ - -/* CP15 Register ACTLR */ -typedef union -{ -#if __CORTEX_A == 5 || defined(DOXYGEN) - /** \brief Structure used for bit access on Cortex-A5 */ - struct - { - uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ - RESERVED(0:5, uint32_t) - uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ - uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ - RESERVED(1:2, uint32_t) - uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ - uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ - uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ - uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ - uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ - uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ - uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ - RESERVED(3:9, uint32_t) - uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ - RESERVED(7:3, uint32_t) - } b; -#endif -#if __CORTEX_A == 7 || defined(DOXYGEN) - /** \brief Structure used for bit access on Cortex-A7 */ - struct - { - RESERVED(0:6, uint32_t) - uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ - RESERVED(1:3, uint32_t) - uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ - uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ - uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ - uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ - uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ - RESERVED(3:12, uint32_t) - uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ - RESERVED(7:3, uint32_t) - } b; -#endif -#if __CORTEX_A == 9 || defined(DOXYGEN) - /** \brief Structure used for bit access on Cortex-A9 */ - struct - { - uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ - RESERVED(0:1, uint32_t) - uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ - uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ - RESERVED(1:2, uint32_t) - uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ - uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ - uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ - uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ - RESERVED(7:22, uint32_t) - } b; -#endif - uint32_t w; /*!< \brief Type used for word access */ -} ACTLR_Type; - -#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ -#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ - -#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ -#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ - -#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ -#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ - -#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ -#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ - -#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ -#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ - -#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ -#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ - -#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ -#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ - -#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ -#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ - -#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ -#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ - -#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ -#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ - -#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ -#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ - -#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ -#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ - -#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ -#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ - -#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ -#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ - -#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ -#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ - -#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ -#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ - -#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ -#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ - -#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ -#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ - -#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ -#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ - -/* CP15 Register CPACR */ -typedef union -{ - struct - { - uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ - uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ - uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ - uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ - uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ - uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ - uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ - uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ - uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ - uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ - uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ - uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ - uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ - uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ - uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ - RESERVED(0:1, uint32_t) - uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ - uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ - } b; /*!< \brief Structure used for bit access */ - uint32_t w; /*!< \brief Type used for word access */ -} CPACR_Type; - -#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ -#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ - -#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ -#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ - -#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ -#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ - -#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ -#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ - -#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ -#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ -#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ - -/* CP15 Register DFSR */ -typedef union -{ - struct - { - uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ - uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ - RESERVED(0:1, uint32_t) - uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ - uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ - uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ - uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ - uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ - RESERVED(1:18, uint32_t) - } s; /*!< \brief Structure used for bit access in short format */ - struct - { - uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ - RESERVED(0:3, uint32_t) - uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ - RESERVED(1:1, uint32_t) - uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ - uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ - uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ - RESERVED(2:18, uint32_t) - } l; /*!< \brief Structure used for bit access in long format */ - uint32_t w; /*!< \brief Type used for word access */ -} DFSR_Type; - -#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ -#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ - -#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ -#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ - -#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ -#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ - -#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ -#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ - -#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ -#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ - -#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ -#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ - -#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ -#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ - -#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ -#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ - -/* CP15 Register IFSR */ -typedef union -{ - struct - { - uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ - RESERVED(0:5, uint32_t) - uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ - uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ - RESERVED(1:1, uint32_t) - uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ - RESERVED(2:19, uint32_t) - } s; /*!< \brief Structure used for bit access in short format */ - struct - { - uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ - RESERVED(0:3, uint32_t) - uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ - RESERVED(1:2, uint32_t) - uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ - RESERVED(2:19, uint32_t) - } l; /*!< \brief Structure used for bit access in long format */ - uint32_t w; /*!< \brief Type used for word access */ -} IFSR_Type; - -#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ -#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ - -#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ -#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ - -#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ -#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ - -#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ -#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ - -#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ -#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ - -/* CP15 Register ISR */ -typedef union -{ - struct - { - RESERVED(0:6, uint32_t) - uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ - uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ - uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ - RESERVED(1:23, uint32_t) - } b; /*!< \brief Structure used for bit access */ - uint32_t w; /*!< \brief Type used for word access */ -} ISR_Type; - -#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ -#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ - -#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ -#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ - -#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ -#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ - -/* DACR Register */ -#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ -#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ -#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ -#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ -#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param [in] field Name of the register bit field. - \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param [in] field Name of the register bit field. - \param [in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - - -/** - \brief Union type to access the L2C_310 Cache Controller. -*/ -#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) -typedef struct -{ - __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ - __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ - RESERVED(0[0x3e], uint32_t) - __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ - __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ - RESERVED(1[0x3e], uint32_t) - __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ - __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ - __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ - RESERVED(2[0x2], uint32_t) - __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ - __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ - __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ - __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ - RESERVED(3[0x143], uint32_t) - __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ - RESERVED(4[0xf], uint32_t) - __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ - RESERVED(6[2], uint32_t) - __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ - RESERVED(5[0xc], uint32_t) - __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ - RESERVED(7[1], uint32_t) - __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ - __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ - RESERVED(8[0xc], uint32_t) - __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ - RESERVED(9[1], uint32_t) - __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ - __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ - RESERVED(10[0x40], uint32_t) - __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ - __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ - __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ - __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ - __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ - __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ - __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ - __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ - __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ - __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ - __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ - __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ - __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ - __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ - __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ - __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ - RESERVED(11[0x4], uint32_t) - __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ - __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ - RESERVED(12[0xaa], uint32_t) - __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ - __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ - RESERVED(13[0xce], uint32_t) - __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ -} L2C_310_TypeDef; - -#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ -#endif - -#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) - -/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) -*/ -typedef struct -{ - __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ - __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ - RESERVED(0, uint32_t) - __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ - RESERVED(1[11], uint32_t) - __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ - RESERVED(2, uint32_t) - __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ - RESERVED(3, uint32_t) - __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ - RESERVED(4, uint32_t) - __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ - RESERVED(5[9], uint32_t) - __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ - __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ - __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ - __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ - __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ - __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ - __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ - __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ - RESERVED(6, uint32_t) - __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ - RESERVED(7, uint32_t) - __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ - __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ - RESERVED(8[32], uint32_t) - __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ - __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ - RESERVED(9[3], uint32_t) - __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ - __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ - RESERVED(10[5236], uint32_t) - __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ -} GICDistributor_Type; - -#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ - -/* GICDistributor CTLR Register */ -#define GICDistributor_CTLR_EnableGrp0_Pos 0U /*!< GICDistributor CTLR: EnableGrp0 Position */ -#define GICDistributor_CTLR_EnableGrp0_Msk (0x1U /*<< GICDistributor_CTLR_EnableGrp0_Pos*/) /*!< GICDistributor CTLR: EnableGrp0 Mask */ -#define GICDistributor_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)) & GICDistributor_CTLR_EnableGrp0_Msk) - -#define GICDistributor_CTLR_EnableGrp1_Pos 1U /*!< GICDistributor CTLR: EnableGrp1 Position */ -#define GICDistributor_CTLR_EnableGrp1_Msk (0x1U << GICDistributor_CTLR_EnableGrp1_Pos) /*!< GICDistributor CTLR: EnableGrp1 Mask */ -#define GICDistributor_CTLR_EnableGrp1(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk) - -#define GICDistributor_CTLR_ARE_Pos 4U /*!< GICDistributor CTLR: ARE Position */ -#define GICDistributor_CTLR_ARE_Msk (0x1U << GICDistributor_CTLR_ARE_Pos) /*!< GICDistributor CTLR: ARE Mask */ -#define GICDistributor_CTLR_ARE(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk) - -#define GICDistributor_CTLR_DC_Pos 6U /*!< GICDistributor CTLR: DC Position */ -#define GICDistributor_CTLR_DC_Msk (0x1U << GICDistributor_CTLR_DC_Pos) /*!< GICDistributor CTLR: DC Mask */ -#define GICDistributor_CTLR_DC(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk) - -#define GICDistributor_CTLR_EINWF_Pos 7U /*!< GICDistributor CTLR: EINWF Position */ -#define GICDistributor_CTLR_EINWF_Msk (0x1U << GICDistributor_CTLR_EINWF_Pos) /*!< GICDistributor CTLR: EINWF Mask */ -#define GICDistributor_CTLR_EINWF(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk) - -#define GICDistributor_CTLR_RWP_Pos 31U /*!< GICDistributor CTLR: RWP Position */ -#define GICDistributor_CTLR_RWP_Msk (0x1U << GICDistributor_CTLR_RWP_Pos) /*!< GICDistributor CTLR: RWP Mask */ -#define GICDistributor_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk) - -/* GICDistributor TYPER Register */ -#define GICDistributor_TYPER_ITLinesNumber_Pos 0U /*!< GICDistributor TYPER: ITLinesNumber Position */ -#define GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/) /*!< GICDistributor TYPER: ITLinesNumber Mask */ -#define GICDistributor_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)) & GICDistributor_CTLR_ITLinesNumber_Msk) - -#define GICDistributor_TYPER_CPUNumber_Pos 5U /*!< GICDistributor TYPER: CPUNumber Position */ -#define GICDistributor_TYPER_CPUNumber_Msk (0x7U << GICDistributor_TYPER_CPUNumber_Pos) /*!< GICDistributor TYPER: CPUNumber Mask */ -#define GICDistributor_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk) - -#define GICDistributor_TYPER_SecurityExtn_Pos 10U /*!< GICDistributor TYPER: SecurityExtn Position */ -#define GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos) /*!< GICDistributor TYPER: SecurityExtn Mask */ -#define GICDistributor_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk) - -#define GICDistributor_TYPER_LSPI_Pos 11U /*!< GICDistributor TYPER: LSPI Position */ -#define GICDistributor_TYPER_LSPI_Msk (0x1FU << GICDistributor_TYPER_LSPI_Pos) /*!< GICDistributor TYPER: LSPI Mask */ -#define GICDistributor_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk) - -/* GICDistributor IIDR Register */ -#define GICDistributor_IIDR_Implementer_Pos 0U /*!< GICDistributor IIDR: Implementer Position */ -#define GICDistributor_IIDR_Implementer_Msk (0xFFFU /*<< GICDistributor_IIDR_Implementer_Pos*/) /*!< GICDistributor IIDR: Implementer Mask */ -#define GICDistributor_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_IIDR_Implementer_Pos*/)) & GICDistributor_IIDR_Implementer_Msk) - -#define GICDistributor_IIDR_Revision_Pos 12U /*!< GICDistributor IIDR: Revision Position */ -#define GICDistributor_IIDR_Revision_Msk (0xFU << GICDistributor_IIDR_Revision_Pos) /*!< GICDistributor IIDR: Revision Mask */ -#define GICDistributor_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk) - -#define GICDistributor_IIDR_Variant_Pos 16U /*!< GICDistributor IIDR: Variant Position */ -#define GICDistributor_IIDR_Variant_Msk (0xFU << GICDistributor_IIDR_Variant_Pos) /*!< GICDistributor IIDR: Variant Mask */ -#define GICDistributor_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk) - -#define GICDistributor_IIDR_ProductID_Pos 24U /*!< GICDistributor IIDR: ProductID Position */ -#define GICDistributor_IIDR_ProductID_Msk (0xFFU << GICDistributor_IIDR_ProductID_Pos) /*!< GICDistributor IIDR: ProductID Mask */ -#define GICDistributor_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk) - -/* GICDistributor STATUSR Register */ -#define GICDistributor_STATUSR_RRD_Pos 0U /*!< GICDistributor STATUSR: RRD Position */ -#define GICDistributor_STATUSR_RRD_Msk (0x1U /*<< GICDistributor_STATUSR_RRD_Pos*/) /*!< GICDistributor STATUSR: RRD Mask */ -#define GICDistributor_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_STATUSR_RRD_Pos*/)) & GICDistributor_STATUSR_RRD_Msk) - -#define GICDistributor_STATUSR_WRD_Pos 1U /*!< GICDistributor STATUSR: WRD Position */ -#define GICDistributor_STATUSR_WRD_Msk (0x1U << GICDistributor_STATUSR_WRD_Pos) /*!< GICDistributor STATUSR: WRD Mask */ -#define GICDistributor_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk) - -#define GICDistributor_STATUSR_RWOD_Pos 2U /*!< GICDistributor STATUSR: RWOD Position */ -#define GICDistributor_STATUSR_RWOD_Msk (0x1U << GICDistributor_STATUSR_RWOD_Pos) /*!< GICDistributor STATUSR: RWOD Mask */ -#define GICDistributor_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk) - -#define GICDistributor_STATUSR_WROD_Pos 3U /*!< GICDistributor STATUSR: WROD Position */ -#define GICDistributor_STATUSR_WROD_Msk (0x1U << GICDistributor_STATUSR_WROD_Pos) /*!< GICDistributor STATUSR: WROD Mask */ -#define GICDistributor_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk) - -/* GICDistributor SETSPI_NSR Register */ -#define GICDistributor_SETSPI_NSR_INTID_Pos 0U /*!< GICDistributor SETSPI_NSR: INTID Position */ -#define GICDistributor_SETSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/) /*!< GICDistributor SETSPI_NSR: INTID Mask */ -#define GICDistributor_SETSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)) & GICDistributor_SETSPI_NSR_INTID_Msk) - -/* GICDistributor CLRSPI_NSR Register */ -#define GICDistributor_CLRSPI_NSR_INTID_Pos 0U /*!< GICDistributor CLRSPI_NSR: INTID Position */ -#define GICDistributor_CLRSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/) /*!< GICDistributor CLRSPI_NSR: INTID Mask */ -#define GICDistributor_CLRSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)) & GICDistributor_CLRSPI_NSR_INTID_Msk) - -/* GICDistributor SETSPI_SR Register */ -#define GICDistributor_SETSPI_SR_INTID_Pos 0U /*!< GICDistributor SETSPI_SR: INTID Position */ -#define GICDistributor_SETSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_SR_INTID_Pos*/) /*!< GICDistributor SETSPI_SR: INTID Mask */ -#define GICDistributor_SETSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)) & GICDistributor_SETSPI_SR_INTID_Msk) - -/* GICDistributor CLRSPI_SR Register */ -#define GICDistributor_CLRSPI_SR_INTID_Pos 0U /*!< GICDistributor CLRSPI_SR: INTID Position */ -#define GICDistributor_CLRSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/) /*!< GICDistributor CLRSPI_SR: INTID Mask */ -#define GICDistributor_CLRSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)) & GICDistributor_CLRSPI_SR_INTID_Msk) - -/* GICDistributor ITARGETSR Register */ -#define GICDistributor_ITARGETSR_CPU0_Pos 0U /*!< GICDistributor ITARGETSR: CPU0 Position */ -#define GICDistributor_ITARGETSR_CPU0_Msk (0x1U /*<< GICDistributor_ITARGETSR_CPU0_Pos*/) /*!< GICDistributor ITARGETSR: CPU0 Mask */ -#define GICDistributor_ITARGETSR_CPU0(x) (((uint8_t)(((uint8_t)(x)) /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)) & GICDistributor_ITARGETSR_CPU0_Msk) - -#define GICDistributor_ITARGETSR_CPU1_Pos 1U /*!< GICDistributor ITARGETSR: CPU1 Position */ -#define GICDistributor_ITARGETSR_CPU1_Msk (0x1U << GICDistributor_ITARGETSR_CPU1_Pos) /*!< GICDistributor ITARGETSR: CPU1 Mask */ -#define GICDistributor_ITARGETSR_CPU1(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk) - -#define GICDistributor_ITARGETSR_CPU2_Pos 2U /*!< GICDistributor ITARGETSR: CPU2 Position */ -#define GICDistributor_ITARGETSR_CPU2_Msk (0x1U << GICDistributor_ITARGETSR_CPU2_Pos) /*!< GICDistributor ITARGETSR: CPU2 Mask */ -#define GICDistributor_ITARGETSR_CPU2(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk) - -#define GICDistributor_ITARGETSR_CPU3_Pos 3U /*!< GICDistributor ITARGETSR: CPU3 Position */ -#define GICDistributor_ITARGETSR_CPU3_Msk (0x1U << GICDistributor_ITARGETSR_CPU3_Pos) /*!< GICDistributor ITARGETSR: CPU3 Mask */ -#define GICDistributor_ITARGETSR_CPU3(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk) - -#define GICDistributor_ITARGETSR_CPU4_Pos 4U /*!< GICDistributor ITARGETSR: CPU4 Position */ -#define GICDistributor_ITARGETSR_CPU4_Msk (0x1U << GICDistributor_ITARGETSR_CPU4_Pos) /*!< GICDistributor ITARGETSR: CPU4 Mask */ -#define GICDistributor_ITARGETSR_CPU4(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk) - -#define GICDistributor_ITARGETSR_CPU5_Pos 5U /*!< GICDistributor ITARGETSR: CPU5 Position */ -#define GICDistributor_ITARGETSR_CPU5_Msk (0x1U << GICDistributor_ITARGETSR_CPU5_Pos) /*!< GICDistributor ITARGETSR: CPU5 Mask */ -#define GICDistributor_ITARGETSR_CPU5(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk) - -#define GICDistributor_ITARGETSR_CPU6_Pos 6U /*!< GICDistributor ITARGETSR: CPU6 Position */ -#define GICDistributor_ITARGETSR_CPU6_Msk (0x1U << GICDistributor_ITARGETSR_CPU6_Pos) /*!< GICDistributor ITARGETSR: CPU6 Mask */ -#define GICDistributor_ITARGETSR_CPU6(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk) - -#define GICDistributor_ITARGETSR_CPU7_Pos 7U /*!< GICDistributor ITARGETSR: CPU7 Position */ -#define GICDistributor_ITARGETSR_CPU7_Msk (0x1U << GICDistributor_ITARGETSR_CPU7_Pos) /*!< GICDistributor ITARGETSR: CPU7 Mask */ -#define GICDistributor_ITARGETSR_CPU7(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk) - -/* GICDistributor SGIR Register */ -#define GICDistributor_SGIR_INTID_Pos 0U /*!< GICDistributor SGIR: INTID Position */ -#define GICDistributor_SGIR_INTID_Msk (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/) /*!< GICDistributor SGIR: INTID Mask */ -#define GICDistributor_SGIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk) - -#define GICDistributor_SGIR_NSATT_Pos 15U /*!< GICDistributor SGIR: NSATT Position */ -#define GICDistributor_SGIR_NSATT_Msk (0x1U << GICDistributor_SGIR_NSATT_Pos) /*!< GICDistributor SGIR: NSATT Mask */ -#define GICDistributor_SGIR_NSATT(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk) - -#define GICDistributor_SGIR_CPUTargetList_Pos 16U /*!< GICDistributor SGIR: CPUTargetList Position */ -#define GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos) /*!< GICDistributor SGIR: CPUTargetList Mask */ -#define GICDistributor_SGIR_CPUTargetList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk) - -#define GICDistributor_SGIR_TargetFilterList_Pos 24U /*!< GICDistributor SGIR: TargetFilterList Position */ -#define GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos) /*!< GICDistributor SGIR: TargetFilterList Mask */ -#define GICDistributor_SGIR_TargetFilterList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk) - -/* GICDistributor IROUTER Register */ -#define GICDistributor_IROUTER_Aff0_Pos 0UL /*!< GICDistributor IROUTER: Aff0 Position */ -#define GICDistributor_IROUTER_Aff0_Msk (0xFFUL /*<< GICDistributor_IROUTER_Aff0_Pos*/) /*!< GICDistributor IROUTER: Aff0 Mask */ -#define GICDistributor_IROUTER_Aff0(x) (((uint64_t)(((uint64_t)(x)) /*<< GICDistributor_IROUTER_Aff0_Pos*/)) & GICDistributor_IROUTER_Aff0_Msk) - -#define GICDistributor_IROUTER_Aff1_Pos 8UL /*!< GICDistributor IROUTER: Aff1 Position */ -#define GICDistributor_IROUTER_Aff1_Msk (0xFFUL << GICDistributor_IROUTER_Aff1_Pos) /*!< GICDistributor IROUTER: Aff1 Mask */ -#define GICDistributor_IROUTER_Aff1(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk) - -#define GICDistributor_IROUTER_Aff2_Pos 16UL /*!< GICDistributor IROUTER: Aff2 Position */ -#define GICDistributor_IROUTER_Aff2_Msk (0xFFUL << GICDistributor_IROUTER_Aff2_Pos) /*!< GICDistributor IROUTER: Aff2 Mask */ -#define GICDistributor_IROUTER_Aff2(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk) - -#define GICDistributor_IROUTER_IRM_Pos 31UL /*!< GICDistributor IROUTER: IRM Position */ -#define GICDistributor_IROUTER_IRM_Msk (0xFFUL << GICDistributor_IROUTER_IRM_Pos) /*!< GICDistributor IROUTER: IRM Mask */ -#define GICDistributor_IROUTER_IRM(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk) - -#define GICDistributor_IROUTER_Aff3_Pos 32UL /*!< GICDistributor IROUTER: Aff3 Position */ -#define GICDistributor_IROUTER_Aff3_Msk (0xFFUL << GICDistributor_IROUTER_Aff3_Pos) /*!< GICDistributor IROUTER: Aff3 Mask */ -#define GICDistributor_IROUTER_Aff3(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk) - - - -/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) -*/ -typedef struct -{ - __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ - __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ - __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ - __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ - __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ - __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ - __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ - __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ - __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ - __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ - __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ - __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ - RESERVED(1[40], uint32_t) - __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ - __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ - RESERVED(2[3], uint32_t) - __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ - RESERVED(3[960], uint32_t) - __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ -} GICInterface_Type; - -#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ - -/* GICInterface CTLR Register */ -#define GICInterface_CTLR_Enable_Pos 0U /*!< PTIM CTLR: Enable Position */ -#define GICInterface_CTLR_Enable_Msk (0x1U /*<< GICInterface_CTLR_Enable_Pos*/) /*!< PTIM CTLR: Enable Mask */ -#define GICInterface_CTLR_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_CTLR_Enable_Pos*/)) & GICInterface_CTLR_Enable_Msk) - -/* GICInterface PMR Register */ -#define GICInterface_PMR_Priority_Pos 0U /*!< PTIM PMR: Priority Position */ -#define GICInterface_PMR_Priority_Msk (0xFFU /*<< GICInterface_PMR_Priority_Pos*/) /*!< PTIM PMR: Priority Mask */ -#define GICInterface_PMR_Priority(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_PMR_Priority_Pos*/)) & GICInterface_PMR_Priority_Msk) - -/* GICInterface BPR Register */ -#define GICInterface_BPR_Binary_Point_Pos 0U /*!< PTIM BPR: Binary_Point Position */ -#define GICInterface_BPR_Binary_Point_Msk (0x7U /*<< GICInterface_BPR_Binary_Point_Pos*/) /*!< PTIM BPR: Binary_Point Mask */ -#define GICInterface_BPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_BPR_Binary_Point_Pos*/)) & GICInterface_BPR_Binary_Point_Msk) - -/* GICInterface IAR Register */ -#define GICInterface_IAR_INTID_Pos 0U /*!< PTIM IAR: INTID Position */ -#define GICInterface_IAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_IAR_INTID_Pos*/) /*!< PTIM IAR: INTID Mask */ -#define GICInterface_IAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IAR_INTID_Pos*/)) & GICInterface_IAR_INTID_Msk) - -/* GICInterface EOIR Register */ -#define GICInterface_EOIR_INTID_Pos 0U /*!< PTIM EOIR: INTID Position */ -#define GICInterface_EOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_EOIR_INTID_Pos*/) /*!< PTIM EOIR: INTID Mask */ -#define GICInterface_EOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_EOIR_INTID_Pos*/)) & GICInterface_EOIR_INTID_Msk) - -/* GICInterface RPR Register */ -#define GICInterface_RPR_INTID_Pos 0U /*!< PTIM RPR: INTID Position */ -#define GICInterface_RPR_INTID_Msk (0xFFU /*<< GICInterface_RPR_INTID_Pos*/) /*!< PTIM RPR: INTID Mask */ -#define GICInterface_RPR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_RPR_INTID_Pos*/)) & GICInterface_RPR_INTID_Msk) - -/* GICInterface HPPIR Register */ -#define GICInterface_HPPIR_INTID_Pos 0U /*!< PTIM HPPIR: INTID Position */ -#define GICInterface_HPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/) /*!< PTIM HPPIR: INTID Mask */ -#define GICInterface_HPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk) - -/* GICInterface ABPR Register */ -#define GICInterface_ABPR_Binary_Point_Pos 0U /*!< PTIM ABPR: Binary_Point Position */ -#define GICInterface_ABPR_Binary_Point_Msk (0x7U /*<< GICInterface_ABPR_Binary_Point_Pos*/) /*!< PTIM ABPR: Binary_Point Mask */ -#define GICInterface_ABPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_ABPR_Binary_Point_Pos*/)) & GICInterface_ABPR_Binary_Point_Msk) - -/* GICInterface AIAR Register */ -#define GICInterface_AIAR_INTID_Pos 0U /*!< PTIM AIAR: INTID Position */ -#define GICInterface_AIAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AIAR_INTID_Pos*/) /*!< PTIM AIAR: INTID Mask */ -#define GICInterface_AIAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AIAR_INTID_Pos*/)) & GICInterface_AIAR_INTID_Msk) - -/* GICInterface AEOIR Register */ -#define GICInterface_AEOIR_INTID_Pos 0U /*!< PTIM AEOIR: INTID Position */ -#define GICInterface_AEOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AEOIR_INTID_Pos*/) /*!< PTIM AEOIR: INTID Mask */ -#define GICInterface_AEOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AEOIR_INTID_Pos*/)) & GICInterface_AEOIR_INTID_Msk) - -/* GICInterface AHPPIR Register */ -#define GICInterface_AHPPIR_INTID_Pos 0U /*!< PTIM AHPPIR: INTID Position */ -#define GICInterface_AHPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AHPPIR_INTID_Pos*/) /*!< PTIM AHPPIR: INTID Mask */ -#define GICInterface_AHPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AHPPIR_INTID_Pos*/)) & GICInterface_AHPPIR_INTID_Msk) - -/* GICInterface STATUSR Register */ -#define GICInterface_STATUSR_RRD_Pos 0U /*!< GICInterface STATUSR: RRD Position */ -#define GICInterface_STATUSR_RRD_Msk (0x1U /*<< GICInterface_STATUSR_RRD_Pos*/) /*!< GICInterface STATUSR: RRD Mask */ -#define GICInterface_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_STATUSR_RRD_Pos*/)) & GICInterface_STATUSR_RRD_Msk) - -#define GICInterface_STATUSR_WRD_Pos 1U /*!< GICInterface STATUSR: WRD Position */ -#define GICInterface_STATUSR_WRD_Msk (0x1U << GICInterface_STATUSR_WRD_Pos) /*!< GICInterface STATUSR: WRD Mask */ -#define GICInterface_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk) - -#define GICInterface_STATUSR_RWOD_Pos 2U /*!< GICInterface STATUSR: RWOD Position */ -#define GICInterface_STATUSR_RWOD_Msk (0x1U << GICInterface_STATUSR_RWOD_Pos) /*!< GICInterface STATUSR: RWOD Mask */ -#define GICInterface_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk) - -#define GICInterface_STATUSR_WROD_Pos 3U /*!< GICInterface STATUSR: WROD Position */ -#define GICInterface_STATUSR_WROD_Msk (0x1U << GICInterface_STATUSR_WROD_Pos) /*!< GICInterface STATUSR: WROD Mask */ -#define GICInterface_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk) - -#define GICInterface_STATUSR_ASV_Pos 4U /*!< GICInterface STATUSR: ASV Position */ -#define GICInterface_STATUSR_ASV_Msk (0x1U << GICInterface_STATUSR_ASV_Pos) /*!< GICInterface STATUSR: ASV Mask */ -#define GICInterface_STATUSR_ASV(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk) - -/* GICInterface IIDR Register */ -#define GICInterface_IIDR_Implementer_Pos 0U /*!< GICInterface IIDR: Implementer Position */ -#define GICInterface_IIDR_Implementer_Msk (0xFFFU /*<< GICInterface_IIDR_Implementer_Pos*/) /*!< GICInterface IIDR: Implementer Mask */ -#define GICInterface_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IIDR_Implementer_Pos*/)) & GICInterface_IIDR_Implementer_Msk) - -#define GICInterface_IIDR_Revision_Pos 12U /*!< GICInterface IIDR: Revision Position */ -#define GICInterface_IIDR_Revision_Msk (0xFU << GICInterface_IIDR_Revision_Pos) /*!< GICInterface IIDR: Revision Mask */ -#define GICInterface_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk) - -#define GICInterface_IIDR_Arch_version_Pos 16U /*!< GICInterface IIDR: Arch_version Position */ -#define GICInterface_IIDR_Arch_version_Msk (0xFU << GICInterface_IIDR_Arch_version_Pos) /*!< GICInterface IIDR: Arch_version Mask */ -#define GICInterface_IIDR_Arch_version(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk) - -#define GICInterface_IIDR_ProductID_Pos 20U /*!< GICInterface IIDR: ProductID Position */ -#define GICInterface_IIDR_ProductID_Msk (0xFFFU << GICInterface_IIDR_ProductID_Pos) /*!< GICInterface IIDR: ProductID Mask */ -#define GICInterface_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk) - -/* GICInterface DIR Register */ -#define GICInterface_DIR_INTID_Pos 0U /*!< PTIM DIR: INTID Position */ -#define GICInterface_DIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/) /*!< PTIM DIR: INTID Mask */ -#define GICInterface_DIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk) -#endif /* (__GIC_PRESENT == 1U) || defined(DOXYGEN) */ - -#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) -#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) -/** \brief Structure type to access the Private Timer -*/ -typedef struct -{ - __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register - __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register - __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register - __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register - RESERVED(0[4], uint32_t) - __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register - __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register - __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register - __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register - __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register - __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register -} Timer_Type; -#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ - -/* PTIM Control Register */ -#define PTIM_CONTROL_Enable_Pos 0U /*!< PTIM CONTROL: Enable Position */ -#define PTIM_CONTROL_Enable_Msk (0x1U /*<< PTIM_CONTROL_Enable_Pos*/) /*!< PTIM CONTROL: Enable Mask */ -#define PTIM_CONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_CONTROL_Enable_Pos*/)) & PTIM_CONTROL_Enable_Msk) - -#define PTIM_CONTROL_AutoReload_Pos 1U /*!< PTIM CONTROL: Auto Reload Position */ -#define PTIM_CONTROL_AutoReload_Msk (0x1U << PTIM_CONTROL_AutoReload_Pos) /*!< PTIM CONTROL: Auto Reload Mask */ -#define PTIM_CONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk) - -#define PTIM_CONTROL_IRQenable_Pos 2U /*!< PTIM CONTROL: IRQ Enabel Position */ -#define PTIM_CONTROL_IRQenable_Msk (0x1U << PTIM_CONTROL_IRQenable_Pos) /*!< PTIM CONTROL: IRQ Enabel Mask */ -#define PTIM_CONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk) - -#define PTIM_CONTROL_Prescaler_Pos 8U /*!< PTIM CONTROL: Prescaler Position */ -#define PTIM_CONTROL_Prescaler_Msk (0xFFU << PTIM_CONTROL_Prescaler_Pos) /*!< PTIM CONTROL: Prescaler Mask */ -#define PTIM_CONTROL_Prescaler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk) - -/* WCONTROL Watchdog Control Register */ -#define PTIM_WCONTROL_Enable_Pos 0U /*!< PTIM WCONTROL: Enable Position */ -#define PTIM_WCONTROL_Enable_Msk (0x1U /*<< PTIM_WCONTROL_Enable_Pos*/) /*!< PTIM WCONTROL: Enable Mask */ -#define PTIM_WCONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WCONTROL_Enable_Pos*/)) & PTIM_WCONTROL_Enable_Msk) - -#define PTIM_WCONTROL_AutoReload_Pos 1U /*!< PTIM WCONTROL: Auto Reload Position */ -#define PTIM_WCONTROL_AutoReload_Msk (0x1U << PTIM_WCONTROL_AutoReload_Pos) /*!< PTIM WCONTROL: Auto Reload Mask */ -#define PTIM_WCONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk) - -#define PTIM_WCONTROL_IRQenable_Pos 2U /*!< PTIM WCONTROL: IRQ Enable Position */ -#define PTIM_WCONTROL_IRQenable_Msk (0x1U << PTIM_WCONTROL_IRQenable_Pos) /*!< PTIM WCONTROL: IRQ Enable Mask */ -#define PTIM_WCONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk) - -#define PTIM_WCONTROL_Mode_Pos 3U /*!< PTIM WCONTROL: Watchdog Mode Position */ -#define PTIM_WCONTROL_Mode_Msk (0x1U << PTIM_WCONTROL_Mode_Pos) /*!< PTIM WCONTROL: Watchdog Mode Mask */ -#define PTIM_WCONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk) - -#define PTIM_WCONTROL_Presacler_Pos 8U /*!< PTIM WCONTROL: Prescaler Position */ -#define PTIM_WCONTROL_Presacler_Msk (0xFFU << PTIM_WCONTROL_Presacler_Pos) /*!< PTIM WCONTROL: Prescaler Mask */ -#define PTIM_WCONTROL_Presacler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk) - -/* WISR Watchdog Interrupt Status Register */ -#define PTIM_WISR_EventFlag_Pos 0U /*!< PTIM WISR: Event Flag Position */ -#define PTIM_WISR_EventFlag_Msk (0x1U /*<< PTIM_WISR_EventFlag_Pos*/) /*!< PTIM WISR: Event Flag Mask */ -#define PTIM_WISR_EventFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WISR_EventFlag_Pos*/)) & PTIM_WISR_EventFlag_Msk) - -/* WRESET Watchdog Reset Status */ -#define PTIM_WRESET_ResetFlag_Pos 0U /*!< PTIM WRESET: Reset Flag Position */ -#define PTIM_WRESET_ResetFlag_Msk (0x1U /*<< PTIM_WRESET_ResetFlag_Pos*/) /*!< PTIM WRESET: Reset Flag Mask */ -#define PTIM_WRESET_ResetFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WRESET_ResetFlag_Pos*/)) & PTIM_WRESET_ResetFlag_Msk) - -#endif /* ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) */ -#endif /* (__TIM_PRESENT == 1U) || defined(DOXYGEN) */ - - /******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - L1 Cache Functions - - L2C-310 Cache Controller Functions - - PL1 Timer Functions - - GIC Functions - - MMU Functions - ******************************************************************************/ - -/* ########################## L1 Cache functions ################################# */ - -/** \brief Enable Caches by setting I and C bits in SCTLR register. -*/ -__STATIC_FORCEINLINE void L1C_EnableCaches(void) { - __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); - __ISB(); -} - -/** \brief Disable Caches by clearing I and C bits in SCTLR register. -*/ -__STATIC_FORCEINLINE void L1C_DisableCaches(void) { - __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); - __ISB(); -} - -/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. -*/ -__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { - __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); - __ISB(); -} - -/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. -*/ -__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { - __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); - __ISB(); -} - -/** \brief Invalidate entire branch predictor array -*/ -__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { - __set_BPIALL(0); - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new state -} - -/** \brief Clean instruction cache line by address. -* \param [in] va Pointer to instructions to clear the cache for. -*/ -__STATIC_FORCEINLINE void L1C_InvalidateICacheMVA(void *va) { - __set_ICIMVAC((uint32_t)va); - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new I cache state -} - -/** \brief Invalidate the whole instruction cache -*/ -__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { - __set_ICIALLU(0); - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new I cache state -} - -/** \brief Clean data cache line by address. -* \param [in] va Pointer to data to clear the cache for. -*/ -__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { - __set_DCCMVAC((uint32_t)va); - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Invalidate data cache line by address. -* \param [in] va Pointer to data to invalidate the cache for. -*/ -__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { - __set_DCIMVAC((uint32_t)va); - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Clean and Invalidate data cache by address. -* \param [in] va Pointer to data to invalidate the cache for. -*/ -__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { - __set_DCCIMVAC((uint32_t)va); - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Calculate log2 rounded up -* - log(0) => 0 -* - log(1) => 0 -* - log(2) => 1 -* - log(3) => 2 -* - log(4) => 2 -* - log(5) => 3 -* : : -* - log(16) => 4 -* - log(32) => 5 -* : : -* \param [in] n input value parameter -* \return log2(n) -*/ -__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) -{ - if (n < 2U) { - return 0U; - } - uint8_t log = 0U; - uint32_t t = n; - while(t > 1U) - { - log++; - t >>= 1U; - } - if (n & 1U) { log++; } - return log; -} - -/** \brief Apply cache maintenance to given cache level. -* \param [in] level cache level to be maintained -* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean -*/ -__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) -{ - uint32_t Dummy; - uint32_t ccsidr; - uint32_t num_sets; - uint32_t num_ways; - uint32_t shift_way; - uint32_t log2_linesize; - int32_t log2_num_ways; - - Dummy = level << 1U; - /* set csselr, select ccsidr register */ - __set_CSSELR(Dummy); - /* get current ccsidr register */ - ccsidr = __get_CCSIDR(); - num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; - num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; - log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; - log2_num_ways = __log2_up(num_ways); - if ((log2_num_ways < 0) || (log2_num_ways > 32)) { - return; // FATAL ERROR - } - shift_way = 32U - (uint32_t)log2_num_ways; - for(int32_t way = num_ways-1; way >= 0; way--) - { - for(int32_t set = num_sets-1; set >= 0; set--) - { - Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); - switch (maint) - { - case 0U: __set_DCISW(Dummy); break; - case 1U: __set_DCCSW(Dummy); break; - default: __set_DCCISW(Dummy); break; - } - } - } - __DMB(); -} - -/** \brief Clean and Invalidate the entire data or unified cache -* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency -* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean -*/ -__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { - uint32_t clidr; - uint32_t cache_type; - clidr = __get_CLIDR(); - for(uint32_t i = 0U; i<7U; i++) - { - cache_type = (clidr >> i*3U) & 0x7UL; - if ((cache_type >= 2U) && (cache_type <= 4U)) - { - __L1C_MaintainDCacheSetWay(i, op); - } - } -} - -/** \brief Clean and Invalidate the entire data or unified cache -* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency -* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean -* \deprecated Use generic L1C_CleanInvalidateCache instead. -*/ -CMSIS_DEPRECATED -__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { - L1C_CleanInvalidateCache(op); -} - -/** \brief Invalidate the whole data cache. -*/ -__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { - L1C_CleanInvalidateCache(0); -} - -/** \brief Clean the whole data cache. - */ -__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { - L1C_CleanInvalidateCache(1); -} - -/** \brief Clean and invalidate the whole data cache. - */ -__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { - L1C_CleanInvalidateCache(2); -} - -/* ########################## L2 Cache functions ################################# */ -#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) -/** \brief Cache Sync operation by writing CACHE_SYNC register. -*/ -__STATIC_INLINE void L2C_Sync(void) -{ - L2C_310->CACHE_SYNC = 0x0; -} - -/** \brief Read cache controller cache ID from CACHE_ID register. - * \return L2C_310_TypeDef::CACHE_ID - */ -__STATIC_INLINE int L2C_GetID (void) -{ - return L2C_310->CACHE_ID; -} - -/** \brief Read cache controller cache type from CACHE_TYPE register. -* \return L2C_310_TypeDef::CACHE_TYPE -*/ -__STATIC_INLINE int L2C_GetType (void) -{ - return L2C_310->CACHE_TYPE; -} - -/** \brief Invalidate all cache by way -*/ -__STATIC_INLINE void L2C_InvAllByWay (void) -{ - unsigned int assoc; - - if (L2C_310->AUX_CNT & (1U << 16U)) { - assoc = 16U; - } else { - assoc = 8U; - } - - L2C_310->INV_WAY = (1U << assoc) - 1U; - while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate - - L2C_Sync(); -} - -/** \brief Clean and Invalidate all cache by way -*/ -__STATIC_INLINE void L2C_CleanInvAllByWay (void) -{ - unsigned int assoc; - - if (L2C_310->AUX_CNT & (1U << 16U)) { - assoc = 16U; - } else { - assoc = 8U; - } - - L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; - while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate - - L2C_Sync(); -} - -/** \brief Enable Level 2 Cache -*/ -__STATIC_INLINE void L2C_Enable(void) -{ - L2C_310->CONTROL = 0; - L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; - L2C_310->DEBUG_CONTROL = 0; - L2C_310->DATA_LOCK_0_WAY = 0; - L2C_310->CACHE_SYNC = 0; - L2C_310->CONTROL = 0x01; - L2C_Sync(); -} - -/** \brief Disable Level 2 Cache -*/ -__STATIC_INLINE void L2C_Disable(void) -{ - L2C_310->CONTROL = 0x00; - L2C_Sync(); -} - -/** \brief Invalidate cache by physical address -* \param [in] pa Pointer to data to invalidate cache for. -*/ -__STATIC_INLINE void L2C_InvPa (void *pa) -{ - L2C_310->INV_LINE_PA = (unsigned int)pa; - L2C_Sync(); -} - -/** \brief Clean cache by physical address -* \param [in] pa Pointer to data to invalidate cache for. -*/ -__STATIC_INLINE void L2C_CleanPa (void *pa) -{ - L2C_310->CLEAN_LINE_PA = (unsigned int)pa; - L2C_Sync(); -} - -/** \brief Clean and invalidate cache by physical address -* \param [in] pa Pointer to data to invalidate cache for. -*/ -__STATIC_INLINE void L2C_CleanInvPa (void *pa) -{ - L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; - L2C_Sync(); -} -#endif - -/* ########################## GIC functions ###################################### */ -#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) - -/** \brief Enable the interrupt distributor using the GIC's CTLR register. -*/ -__STATIC_INLINE void GIC_EnableDistributor(void) -{ - GICDistributor->CTLR |= 1U; -} - -/** \brief Disable the interrupt distributor using the GIC's CTLR register. -*/ -__STATIC_INLINE void GIC_DisableDistributor(void) -{ - GICDistributor->CTLR &=~1U; -} - -/** \brief Read the GIC's TYPER register. -* \return GICDistributor_Type::TYPER -*/ -__STATIC_INLINE uint32_t GIC_DistributorInfo(void) -{ - return (GICDistributor->TYPER); -} - -/** \brief Reads the GIC's IIDR register. -* \return GICDistributor_Type::IIDR -*/ -__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) -{ - return (GICDistributor->IIDR); -} - -/** \brief Sets the GIC's ITARGETSR register for the given interrupt. -* \param [in] IRQn Interrupt to be configured. -* \param [in] cpu_target CPU interfaces to assign this interrupt to. -*/ -__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) -{ - uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); - GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); -} - -/** \brief Read the GIC's ITARGETSR register. -* \param [in] IRQn Interrupt to acquire the configuration for. -* \return GICDistributor_Type::ITARGETSR -*/ -__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) -{ - return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; -} - -/** \brief Enable the CPU's interrupt interface. -*/ -__STATIC_INLINE void GIC_EnableInterface(void) -{ - GICInterface->CTLR |= 1U; //enable interface -} - -/** \brief Disable the CPU's interrupt interface. -*/ -__STATIC_INLINE void GIC_DisableInterface(void) -{ - GICInterface->CTLR &=~1U; //disable distributor -} - -/** \brief Read the CPU's IAR register. -* \return GICInterface_Type::IAR -*/ -__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) -{ - return (IRQn_Type)(GICInterface->IAR); -} - -/** \brief Writes the given interrupt number to the CPU's EOIR register. -* \param [in] IRQn The interrupt to be signaled as finished. -*/ -__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) -{ - GICInterface->EOIR = IRQn; -} - -/** \brief Enables the given interrupt using GIC's ISENABLER register. -* \param [in] IRQn The interrupt to be enabled. -*/ -__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); -} - -/** \brief Get interrupt enable status using GIC's ISENABLER register. -* \param [in] IRQn The interrupt to be queried. -* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. -*/ -__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) -{ - return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; -} - -/** \brief Disables the given interrupt using GIC's ICENABLER register. -* \param [in] IRQn The interrupt to be disabled. -*/ -__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); -} - -/** \brief Get interrupt pending status from GIC's ISPENDR register. -* \param [in] IRQn The interrupt to be queried. -* \return 0 - interrupt is not pending, 1 - interrupt is pendig. -*/ -__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) -{ - uint32_t pend; - - if (IRQn >= 16U) { - pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; - } else { - // INTID 0-15 Software Generated Interrupt - pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; - // No CPU identification offered - if (pend != 0U) { - pend = 1U; - } else { - pend = 0U; - } - } - - return (pend); -} - -/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. -* \param [in] IRQn The interrupt to be enabled. -*/ -__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if (IRQn >= 16U) { - GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); - } else { - // INTID 0-15 Software Generated Interrupt - // Forward the interrupt to the CPU interface that requested it - GICDistributor->SGIR = (IRQn | 0x02000000U); - } -} - -/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. -* \param [in] IRQn The interrupt to be enabled. -*/ -__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if (IRQn >= 16U) { - GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); - } else { - // INTID 0-15 Software Generated Interrupt - GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); - } -} - -/** \brief Sets the interrupt configuration using GIC's ICFGR register. -* \param [in] IRQn The interrupt to be configured. -* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) -* Bit 1: 0 - level sensitive, 1 - edge triggered -*/ -__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) -{ - uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; /* read current register content */ - uint32_t shift = (IRQn % 16U) << 1U; /* calculate shift value */ - - int_config &= 3U; /* only 2 bits are valid */ - icfgr &= (~(3U << shift)); /* clear bits to change */ - icfgr |= ( int_config << shift); /* set new configuration */ - - GICDistributor->ICFGR[IRQn / 16U] = icfgr; /* write new register content */ -} - -/** \brief Get the interrupt configuration from the GIC's ICFGR register. -* \param [in] IRQn Interrupt to acquire the configuration for. -* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) -* Bit 1: 0 - level sensitive, 1 - edge triggered -*/ -__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) -{ - return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); -} - -/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. -* \param [in] IRQn The interrupt to be configured. -* \param [in] priority The priority for the interrupt, lower values denote higher priorities. -*/ -__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); - GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); -} - -/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. -* \param [in] IRQn The interrupt to be queried. -*/ -__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) -{ - return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; -} - -/** \brief Set the interrupt priority mask using CPU's PMR register. -* \param [in] priority Priority mask to be set. -*/ -__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) -{ - GICInterface->PMR = priority & 0xFFUL; //set priority mask -} - -/** \brief Read the current interrupt priority mask from CPU's PMR register. -* \result GICInterface_Type::PMR -*/ -__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) -{ - return GICInterface->PMR; -} - -/** \brief Configures the group priority and subpriority split point using CPU's BPR register. -* \param [in] binary_point Amount of bits used as subpriority. -*/ -__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) -{ - GICInterface->BPR = binary_point & 7U; //set binary point -} - -/** \brief Read the current group priority and subpriority split point from CPU's BPR register. -* \return GICInterface_Type::BPR -*/ -__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) -{ - return GICInterface->BPR; -} - -/** \brief Get the status for a given interrupt. -* \param [in] IRQn The interrupt to get status for. -* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active -*/ -__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) -{ - uint32_t pending, active; - - active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; - pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; - - return ((active<<1U) | pending); -} - -/** \brief Generate a software interrupt using GIC's SGIR register. -* \param [in] IRQn Software interrupt to be generated. -* \param [in] target_list List of CPUs the software interrupt should be forwarded to. -* \param [in] filter_list Filter to be applied to determine interrupt receivers. -*/ -__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) -{ - GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); -} - -/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. -* \return GICInterface_Type::HPPIR -*/ -__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) -{ - return GICInterface->HPPIR; -} - -/** \brief Provides information about the implementer and revision of the CPU interface. -* \return GICInterface_Type::IIDR -*/ -__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) -{ - return GICInterface->IIDR; -} - -/** \brief Set the interrupt group from the GIC's IGROUPR register. -* \param [in] IRQn The interrupt to be queried. -* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 -*/ -__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) -{ - uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; - uint32_t shift = (IRQn % 32U); - - igroupr &= (~(1U << shift)); - igroupr |= ( (group & 1U) << shift); - - GICDistributor->IGROUPR[IRQn / 32U] = igroupr; -} -#define GIC_SetSecurity GIC_SetGroup - -/** \brief Get the interrupt group from the GIC's IGROUPR register. -* \param [in] IRQn The interrupt to be queried. -* \return 0 - Group 0, 1 - Group 1 -*/ -__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) -{ - return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; -} -#define GIC_GetSecurity GIC_GetGroup - -/** \brief Initialize the interrupt distributor. -*/ -__STATIC_INLINE void GIC_DistInit(void) -{ - uint32_t i; - uint32_t num_irq = 0U; - uint32_t priority_field; - - //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableDistributor(); - //Get the maximum number of interrupts that the GIC supports - num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an IPRIORITYR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0U, 0xFFU); - priority_field = GIC_GetPriority((IRQn_Type)0U); - - for (i = 32U; i < num_irq; i++) - { - //Disable the SPI interrupt - GIC_DisableIRQ((IRQn_Type)i); - //Set level-sensitive (and N-N model) - GIC_SetConfiguration((IRQn_Type)i, 0U); - //Set priority - GIC_SetPriority((IRQn_Type)i, priority_field/2U); - //Set target list to CPU0 - GIC_SetTarget((IRQn_Type)i, 1U); - } - //Enable distributor - GIC_EnableDistributor(); -} - -/** \brief Initialize the CPU's interrupt interface -*/ -__STATIC_INLINE void GIC_CPUInterfaceInit(void) -{ - uint32_t i; - uint32_t priority_field; - - //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableInterface(); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an IPRIORITYR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0U, 0xFFU); - priority_field = GIC_GetPriority((IRQn_Type)0U); - - //SGI and PPI - for (i = 0U; i < 32U; i++) - { - if(i > 15U) { - //Set level-sensitive (and N-N model) for PPI - GIC_SetConfiguration((IRQn_Type)i, 0U); - } - //Disable SGI and PPI interrupts - GIC_DisableIRQ((IRQn_Type)i); - //Set priority - GIC_SetPriority((IRQn_Type)i, priority_field/2U); - } - //Enable interface - GIC_EnableInterface(); - //Set binary point to 0 - GIC_SetBinaryPoint(0U); - //Set priority mask - GIC_SetInterfacePriorityMask(0xFFU); -} - -/** \brief Initialize and enable the GIC -*/ -__STATIC_INLINE void GIC_Enable(void) -{ - GIC_DistInit(); - GIC_CPUInterfaceInit(); //per CPU -} -#endif - -/* ########################## Generic Timer functions ############################ */ -#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) - -/* PL1 Physical Timer */ -#if (__CORTEX_A == 7U) || defined(DOXYGEN) - -/** \brief Physical Timer Control register */ -typedef union -{ - struct - { - uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ - uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ - uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ - RESERVED(0:29, uint32_t) - } b; /*!< \brief Structure used for bit access */ - uint32_t w; /*!< \brief Type used for word access */ -} CNTP_CTL_Type; - -/** \brief Configures the frequency the timer shall run at. -* \param [in] value The timer frequency in Hz. -*/ -__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) -{ - __set_CNTFRQ(value); - __ISB(); -} - -/** \brief Sets the reset value of the timer. -* \param [in] value The value the timer is loaded with. -*/ -__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) -{ - __set_CNTP_TVAL(value); - __ISB(); -} - -/** \brief Get the current counter value. -* \return Current counter value. -*/ -__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) -{ - return(__get_CNTP_TVAL()); -} - -/** \brief Get the current physical counter value. -* \return Current physical counter value. -*/ -__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) -{ - return(__get_CNTPCT()); -} - -/** \brief Set the physical compare value. -* \param [in] value New physical timer compare value. -*/ -__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) -{ - __set_CNTP_CVAL(value); - __ISB(); -} - -/** \brief Get the physical compare value. -* \return Physical compare value. -*/ -__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) -{ - return(__get_CNTP_CVAL()); -} - -/** \brief Configure the timer by setting the control value. -* \param [in] value New timer control value. -*/ -__STATIC_INLINE void PL1_SetControl(uint32_t value) -{ - __set_CNTP_CTL(value); - __ISB(); -} - -/** \brief Get the control value. -* \return Control value. -*/ -__STATIC_INLINE uint32_t PL1_GetControl(void) -{ - return(__get_CNTP_CTL()); -} -#endif - -/* Private Timer */ -#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) -/** \brief Set the load value to timers LOAD register. -* \param [in] value The load value to be set. -*/ -__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) -{ - PTIM->LOAD = value; -} - -/** \brief Get the load value from timers LOAD register. -* \return Timer_Type::LOAD -*/ -__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) -{ - return(PTIM->LOAD); -} - -/** \brief Set current counter value from its COUNTER register. -*/ -__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) -{ - PTIM->COUNTER = value; -} - -/** \brief Get current counter value from timers COUNTER register. -* \result Timer_Type::COUNTER -*/ -__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) -{ - return(PTIM->COUNTER); -} - -/** \brief Configure the timer using its CONTROL register. -* \param [in] value The new configuration value to be set. -*/ -__STATIC_INLINE void PTIM_SetControl(uint32_t value) -{ - PTIM->CONTROL = value; -} - -/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. -* \return Timer_Type::CONTROL -*/ -__STATIC_INLINE uint32_t PTIM_GetControl(void) -{ - return(PTIM->CONTROL); -} - -/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. -* \return 0 - flag is not set, 1- flag is set -*/ -__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) -{ - return (PTIM->ISR & 1UL); -} - -/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. -*/ -__STATIC_INLINE void PTIM_ClearEventFlag(void) -{ - PTIM->ISR = 1; -} -#endif -#endif - -/* ########################## MMU functions ###################################### */ - -#define SECTION_DESCRIPTOR (0x2) -#define SECTION_MASK (0xFFFFFFFC) - -#define SECTION_TEXCB_MASK (0xFFFF8FF3) -#define SECTION_B_SHIFT (2) -#define SECTION_C_SHIFT (3) -#define SECTION_TEX0_SHIFT (12) -#define SECTION_TEX1_SHIFT (13) -#define SECTION_TEX2_SHIFT (14) - -#define SECTION_XN_MASK (0xFFFFFFEF) -#define SECTION_XN_SHIFT (4) - -#define SECTION_DOMAIN_MASK (0xFFFFFE1F) -#define SECTION_DOMAIN_SHIFT (5) - -#define SECTION_P_MASK (0xFFFFFDFF) -#define SECTION_P_SHIFT (9) - -#define SECTION_AP_MASK (0xFFFF73FF) -#define SECTION_AP_SHIFT (10) -#define SECTION_AP2_SHIFT (15) - -#define SECTION_S_MASK (0xFFFEFFFF) -#define SECTION_S_SHIFT (16) - -#define SECTION_NG_MASK (0xFFFDFFFF) -#define SECTION_NG_SHIFT (17) - -#define SECTION_NS_MASK (0xFFF7FFFF) -#define SECTION_NS_SHIFT (19) - -#define PAGE_L1_DESCRIPTOR (0x1) -#define PAGE_L1_MASK (0xFFFFFFFC) - -#define PAGE_L2_4K_DESC (0x2) -#define PAGE_L2_4K_MASK (0xFFFFFFFD) - -#define PAGE_L2_64K_DESC (0x1) -#define PAGE_L2_64K_MASK (0xFFFFFFFC) - -#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) -#define PAGE_4K_B_SHIFT (2) -#define PAGE_4K_C_SHIFT (3) -#define PAGE_4K_TEX0_SHIFT (6) -#define PAGE_4K_TEX1_SHIFT (7) -#define PAGE_4K_TEX2_SHIFT (8) - -#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) -#define PAGE_64K_B_SHIFT (2) -#define PAGE_64K_C_SHIFT (3) -#define PAGE_64K_TEX0_SHIFT (12) -#define PAGE_64K_TEX1_SHIFT (13) -#define PAGE_64K_TEX2_SHIFT (14) - -#define PAGE_TEXCB_MASK (0xFFFF8FF3) -#define PAGE_B_SHIFT (2) -#define PAGE_C_SHIFT (3) -#define PAGE_TEX_SHIFT (12) - -#define PAGE_XN_4K_MASK (0xFFFFFFFE) -#define PAGE_XN_4K_SHIFT (0) -#define PAGE_XN_64K_MASK (0xFFFF7FFF) -#define PAGE_XN_64K_SHIFT (15) - -#define PAGE_DOMAIN_MASK (0xFFFFFE1F) -#define PAGE_DOMAIN_SHIFT (5) - -#define PAGE_P_MASK (0xFFFFFDFF) -#define PAGE_P_SHIFT (9) - -#define PAGE_AP_MASK (0xFFFFFDCF) -#define PAGE_AP_SHIFT (4) -#define PAGE_AP2_SHIFT (9) - -#define PAGE_S_MASK (0xFFFFFBFF) -#define PAGE_S_SHIFT (10) - -#define PAGE_NG_MASK (0xFFFFF7FF) -#define PAGE_NG_SHIFT (11) - -#define PAGE_NS_MASK (0xFFFFFFF7) -#define PAGE_NS_SHIFT (3) - -#define OFFSET_1M (0x00100000) -#define OFFSET_64K (0x00010000) -#define OFFSET_4K (0x00001000) - -#define DESCRIPTOR_FAULT (0x00000000) - -/* Attributes enumerations */ - -/* Region size attributes */ -typedef enum -{ - SECTION, - PAGE_4k, - PAGE_64k, -} mmu_region_size_Type; - -/* Region type attributes */ -typedef enum -{ - NORMAL, - DEVICE, - SHARED_DEVICE, - NON_SHARED_DEVICE, - STRONGLY_ORDERED -} mmu_memory_Type; - -/* Region cacheability attributes */ -typedef enum -{ - NON_CACHEABLE, - WB_WA, - WT, - WB_NO_WA, -} mmu_cacheability_Type; - -/* Region parity check attributes */ -typedef enum -{ - ECC_DISABLED, - ECC_ENABLED, -} mmu_ecc_check_Type; - -/* Region execution attributes */ -typedef enum -{ - EXECUTE, - NON_EXECUTE, -} mmu_execute_Type; - -/* Region global attributes */ -typedef enum -{ - GLOBAL, - NON_GLOBAL, -} mmu_global_Type; - -/* Region shareability attributes */ -typedef enum -{ - NON_SHARED, - SHARED, -} mmu_shared_Type; - -/* Region security attributes */ -typedef enum -{ - SECURE, - NON_SECURE, -} mmu_secure_Type; - -/* Region access attributes */ -typedef enum -{ - NO_ACCESS, - RW, - READ, -} mmu_access_Type; - -/* Memory Region definition */ -typedef struct RegionStruct { - mmu_region_size_Type rg_t; - mmu_memory_Type mem_t; - uint8_t domain; - mmu_cacheability_Type inner_norm_t; - mmu_cacheability_Type outer_norm_t; - mmu_ecc_check_Type e_t; - mmu_execute_Type xn_t; - mmu_global_Type g_t; - mmu_secure_Type sec_t; - mmu_access_Type priv_t; - mmu_access_Type user_t; - mmu_shared_Type sh_t; - -} mmu_region_attributes_Type; - -//Following macros define the descriptors and attributes -//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 -#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); - -//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 -#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); - -//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 -#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); - -//Sect_Normal_RO. Sect_Normal_Cod, but not executable -#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); - -//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable -#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); -//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 -#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); - -//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 -#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); - -//Sect_Device_RW. Sect_Device_RO, but writeable -#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - MMU_GetSectionDescriptor(&descriptor_l1, region); -//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 -#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); - -//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 -#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); - -/** \brief Set section execution-never attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. - - \return 0 -*/ -__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) -{ - *descriptor_l1 &= SECTION_XN_MASK; - *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); - return 0; -} - -/** \brief Set section domain - - \param [out] descriptor_l1 L1 descriptor. - \param [in] domain Section domain - - \return 0 -*/ -__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) -{ - *descriptor_l1 &= SECTION_DOMAIN_MASK; - *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); - return 0; -} - -/** \brief Set section parity check - - \param [out] descriptor_l1 L1 descriptor. - \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED - - \return 0 -*/ -__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) -{ - *descriptor_l1 &= SECTION_P_MASK; - *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); - return 0; -} - -/** \brief Set section access privileges - - \param [out] descriptor_l1 L1 descriptor. - \param [in] user User Level Access: NO_ACCESS, RW, READ - \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ - \param [in] afe Access flag enable - - \return 0 -*/ -__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) -{ - uint32_t ap = 0; - - if (afe == 0) { //full access - if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } - else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == READ)) { ap = 0x2; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x7; } - } - - else { //Simplified access - if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x7; } - } - - *descriptor_l1 &= SECTION_AP_MASK; - *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; - *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; - - return 0; -} - -/** \brief Set section shareability - - \param [out] descriptor_l1 L1 descriptor. - \param [in] s_bit Section shareability: NON_SHARED, SHARED - - \return 0 -*/ -__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) -{ - *descriptor_l1 &= SECTION_S_MASK; - *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); - return 0; -} - -/** \brief Set section Global attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL - - \return 0 -*/ -__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) -{ - *descriptor_l1 &= SECTION_NG_MASK; - *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); - return 0; -} - -/** \brief Set section Security attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] s_bit Section Security attribute: SECURE, NON_SECURE - - \return 0 -*/ -__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) -{ - *descriptor_l1 &= SECTION_NS_MASK; - *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); - return 0; -} - -/* Page 4k or 64k */ -/** \brief Set 4k/64k page execution-never attribute - - \param [out] descriptor_l2 L2 descriptor. - \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. - \param [in] page Page size: PAGE_4k, PAGE_64k, - - \return 0 -*/ -__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) -{ - if (page == PAGE_4k) - { - *descriptor_l2 &= PAGE_XN_4K_MASK; - *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); - } - else - { - *descriptor_l2 &= PAGE_XN_64K_MASK; - *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); - } - return 0; -} - -/** \brief Set 4k/64k page domain - - \param [out] descriptor_l1 L1 descriptor. - \param [in] domain Page domain - - \return 0 -*/ -__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) -{ - *descriptor_l1 &= PAGE_DOMAIN_MASK; - *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page parity check - - \param [out] descriptor_l1 L1 descriptor. - \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED - - \return 0 -*/ -__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) -{ - *descriptor_l1 &= SECTION_P_MASK; - *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page access privileges - - \param [out] descriptor_l2 L2 descriptor. - \param [in] user User Level Access: NO_ACCESS, RW, READ - \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ - \param [in] afe Access flag enable - - \return 0 -*/ -__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) -{ - uint32_t ap = 0; - - if (afe == 0) { //full access - if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } - else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == READ)) { ap = 0x2; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x6; } - } - - else { //Simplified access - if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x7; } - } - - *descriptor_l2 &= PAGE_AP_MASK; - *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; - *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; - - return 0; -} - -/** \brief Set 4k/64k page shareability - - \param [out] descriptor_l2 L2 descriptor. - \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED - - \return 0 -*/ -__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) -{ - *descriptor_l2 &= PAGE_S_MASK; - *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page Global attribute - - \param [out] descriptor_l2 L2 descriptor. - \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL - - \return 0 -*/ -__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) -{ - *descriptor_l2 &= PAGE_NG_MASK; - *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page Security attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE - - \return 0 -*/ -__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) -{ - *descriptor_l1 &= PAGE_NS_MASK; - *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); - return 0; -} - -/** \brief Set Section memory attributes - - \param [out] descriptor_l1 L1 descriptor. - \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED - \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - - \return 0 -*/ -__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) -{ - *descriptor_l1 &= SECTION_TEXCB_MASK; - - if (STRONGLY_ORDERED == mem) - { - return 0; - } - else if (SHARED_DEVICE == mem) - { - *descriptor_l1 |= (1 << SECTION_B_SHIFT); - } - else if (NON_SHARED_DEVICE == mem) - { - *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); - } - else if (NORMAL == mem) - { - *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; - switch(inner) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l1 |= (1 << SECTION_B_SHIFT); - break; - case WT: - *descriptor_l1 |= 1 << SECTION_C_SHIFT; - break; - case WB_NO_WA: - *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); - break; - } - switch(outer) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); - break; - case WT: - *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; - break; - case WB_NO_WA: - *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); - break; - } - } - return 0; -} - -/** \brief Set 4k/64k page memory attributes - - \param [out] descriptor_l2 L2 descriptor. - \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED - \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - \param [in] page Page size - - \return 0 -*/ -__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) -{ - *descriptor_l2 &= PAGE_4K_TEXCB_MASK; - - if (page == PAGE_64k) - { - //same as section - MMU_MemorySection(descriptor_l2, mem, outer, inner); - } - else - { - if (STRONGLY_ORDERED == mem) - { - return 0; - } - else if (SHARED_DEVICE == mem) - { - *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); - } - else if (NON_SHARED_DEVICE == mem) - { - *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); - } - else if (NORMAL == mem) - { - *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; - switch(inner) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); - break; - case WT: - *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; - break; - case WB_NO_WA: - *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); - break; - } - switch(outer) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); - break; - case WT: - *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; - break; - case WB_NO_WA: - *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); - break; - } - } - } - - return 0; -} - -/** \brief Create a L1 section descriptor - - \param [out] descriptor L1 descriptor - \param [in] reg Section attributes - - \return 0 -*/ -__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) -{ - *descriptor = 0; - - MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); - MMU_XNSection(descriptor,reg.xn_t); - MMU_DomainSection(descriptor, reg.domain); - MMU_PSection(descriptor, reg.e_t); - MMU_APSection(descriptor, reg.user_t, reg.priv_t, 1); - MMU_SharedSection(descriptor,reg.sh_t); - MMU_GlobalSection(descriptor,reg.g_t); - MMU_SecureSection(descriptor,reg.sec_t); - *descriptor &= SECTION_MASK; - *descriptor |= SECTION_DESCRIPTOR; - - return 0; -} - - -/** \brief Create a L1 and L2 4k/64k page descriptor - - \param [out] descriptor L1 descriptor - \param [out] descriptor2 L2 descriptor - \param [in] reg 4k/64k page attributes - - \return 0 -*/ -__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) -{ - *descriptor = 0; - *descriptor2 = 0; - - switch (reg.rg_t) - { - case PAGE_4k: - MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); - MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); - MMU_DomainPage(descriptor, reg.domain); - MMU_PPage(descriptor, reg.e_t); - MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); - MMU_SharedPage(descriptor2,reg.sh_t); - MMU_GlobalPage(descriptor2,reg.g_t); - MMU_SecurePage(descriptor,reg.sec_t); - *descriptor &= PAGE_L1_MASK; - *descriptor |= PAGE_L1_DESCRIPTOR; - *descriptor2 &= PAGE_L2_4K_MASK; - *descriptor2 |= PAGE_L2_4K_DESC; - break; - - case PAGE_64k: - MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); - MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); - MMU_DomainPage(descriptor, reg.domain); - MMU_PPage(descriptor, reg.e_t); - MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); - MMU_SharedPage(descriptor2,reg.sh_t); - MMU_GlobalPage(descriptor2,reg.g_t); - MMU_SecurePage(descriptor,reg.sec_t); - *descriptor &= PAGE_L1_MASK; - *descriptor |= PAGE_L1_DESCRIPTOR; - *descriptor2 &= PAGE_L2_64K_MASK; - *descriptor2 |= PAGE_L2_64K_DESC; - break; - - case SECTION: - //error - break; - } - - return 0; -} - -/** \brief Create a 1MB Section - - \param [in] ttb Translation table base address - \param [in] base_address Section base address - \param [in] count Number of sections to create - \param [in] descriptor_l1 L1 descriptor (region attributes) - -*/ -__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) -{ - uint32_t offset; - uint32_t entry; - uint32_t i; - - offset = base_address >> 20; - entry = (base_address & 0xFFF00000) | descriptor_l1; - - //4 bytes aligned - ttb = ttb + offset; - - for (i = 0; i < count; i++ ) - { - //4 bytes aligned - *ttb++ = entry; - entry += OFFSET_1M; - } -} - -/** \brief Create a 4k page entry - - \param [in] ttb L1 table base address - \param [in] base_address 4k base address - \param [in] count Number of 4k pages to create - \param [in] descriptor_l1 L1 descriptor (region attributes) - \param [in] ttb_l2 L2 table base address - \param [in] descriptor_l2 L2 descriptor (region attributes) - -*/ -__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) -{ - - uint32_t offset, offset2; - uint32_t entry, entry2; - uint32_t i; - - offset = base_address >> 20; - entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; - - //4 bytes aligned - ttb += offset; - //create l1_entry - *ttb = entry; - - offset2 = (base_address & 0xff000) >> 12; - ttb_l2 += offset2; - entry2 = (base_address & 0xFFFFF000) | descriptor_l2; - for (i = 0; i < count; i++ ) - { - //4 bytes aligned - *ttb_l2++ = entry2; - entry2 += OFFSET_4K; - } -} - -/** \brief Create a 64k page entry - - \param [in] ttb L1 table base address - \param [in] base_address 64k base address - \param [in] count Number of 64k pages to create - \param [in] descriptor_l1 L1 descriptor (region attributes) - \param [in] ttb_l2 L2 table base address - \param [in] descriptor_l2 L2 descriptor (region attributes) - -*/ -__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) -{ - uint32_t offset, offset2; - uint32_t entry, entry2; - uint32_t i,j; - - - offset = base_address >> 20; - entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; - - //4 bytes aligned - ttb += offset; - //create l1_entry - *ttb = entry; - - offset2 = (base_address & 0xff000) >> 12; - ttb_l2 += offset2; - entry2 = (base_address & 0xFFFF0000) | descriptor_l2; - for (i = 0; i < count; i++ ) - { - //create 16 entries - for (j = 0; j < 16; j++) - { - //4 bytes aligned - *ttb_l2++ = entry2; - } - entry2 += OFFSET_64K; - } -} - -/** \brief Enable MMU -*/ -__STATIC_INLINE void MMU_Enable(void) -{ - // Set M bit 0 to enable the MMU - // Set AFE bit to enable simplified access permissions model - // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking - __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); - __ISB(); -} - -/** \brief Disable MMU -*/ -__STATIC_INLINE void MMU_Disable(void) -{ - // Clear M bit 0 to disable the MMU - __set_SCTLR( __get_SCTLR() & ~1); - __ISB(); -} - -/** \brief Invalidate entire unified TLB -*/ - -__STATIC_INLINE void MMU_InvalidateTLB(void) -{ - __set_TLBIALL(0); - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new state -} - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CA_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/external/CMSIS_5/CMSIS/Core_A/Include/irq_ctrl.h b/external/CMSIS_5/CMSIS/Core_A/Include/irq_ctrl.h deleted file mode 100644 index 1ca29a2..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Include/irq_ctrl.h +++ /dev/null @@ -1,192 +0,0 @@ -/**************************************************************************//** - * @file irq_ctrl.h - * @brief Interrupt Controller API header file - * @version V1.1.0 - * @date 03. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2017-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef IRQ_CTRL_H_ -#define IRQ_CTRL_H_ - -#include - -#ifndef IRQHANDLER_T -#define IRQHANDLER_T -/// Interrupt handler data type -typedef void (*IRQHandler_t) (void); -#endif - -#ifndef IRQN_ID_T -#define IRQN_ID_T -/// Interrupt ID number data type -typedef int32_t IRQn_ID_t; -#endif - -/* Interrupt mode bit-masks */ -#define IRQ_MODE_TRIG_Pos (0U) -#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) -#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt -#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt -#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt -#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt -#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt -#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt -#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt - -#define IRQ_MODE_TYPE_Pos (3U) -#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) -#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line -#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line - -#define IRQ_MODE_DOMAIN_Pos (4U) -#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) -#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain -#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain - -#define IRQ_MODE_CPU_Pos (5U) -#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) -#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs -#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 -#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 -#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 -#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 -#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 -#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 -#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 -#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 - -// Encoding in some early GIC implementations -#define IRQ_MODE_MODEL_Pos (13U) -#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) -#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model -#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model - -#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error - -/* Interrupt priority bit-masks */ -#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask -#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error - -/// Initialize interrupt controller. -/// \return 0 on success, -1 on error. -int32_t IRQ_Initialize (void); - -/// Register interrupt handler. -/// \param[in] irqn interrupt ID number -/// \param[in] handler interrupt handler function address -/// \return 0 on success, -1 on error. -int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); - -/// Get the registered interrupt handler. -/// \param[in] irqn interrupt ID number -/// \return registered interrupt handler function address. -IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); - -/// Enable interrupt. -/// \param[in] irqn interrupt ID number -/// \return 0 on success, -1 on error. -int32_t IRQ_Enable (IRQn_ID_t irqn); - -/// Disable interrupt. -/// \param[in] irqn interrupt ID number -/// \return 0 on success, -1 on error. -int32_t IRQ_Disable (IRQn_ID_t irqn); - -/// Get interrupt enable state. -/// \param[in] irqn interrupt ID number -/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. -uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); - -/// Configure interrupt request mode. -/// \param[in] irqn interrupt ID number -/// \param[in] mode mode configuration -/// \return 0 on success, -1 on error. -int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); - -/// Get interrupt mode configuration. -/// \param[in] irqn interrupt ID number -/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. -uint32_t IRQ_GetMode (IRQn_ID_t irqn); - -/// Get ID number of current interrupt request (IRQ). -/// \return interrupt ID number. -IRQn_ID_t IRQ_GetActiveIRQ (void); - -/// Get ID number of current fast interrupt request (FIQ). -/// \return interrupt ID number. -IRQn_ID_t IRQ_GetActiveFIQ (void); - -/// Signal end of interrupt processing. -/// \param[in] irqn interrupt ID number -/// \return 0 on success, -1 on error. -int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); - -/// Set interrupt pending flag. -/// \param[in] irqn interrupt ID number -/// \return 0 on success, -1 on error. -int32_t IRQ_SetPending (IRQn_ID_t irqn); - -/// Get interrupt pending flag. -/// \param[in] irqn interrupt ID number -/// \return 0 - interrupt is not pending, 1 - interrupt is pending. -uint32_t IRQ_GetPending (IRQn_ID_t irqn); - -/// Clear interrupt pending flag. -/// \param[in] irqn interrupt ID number -/// \return 0 on success, -1 on error. -int32_t IRQ_ClearPending (IRQn_ID_t irqn); - -/// Set interrupt priority value. -/// \param[in] irqn interrupt ID number -/// \param[in] priority interrupt priority value -/// \return 0 on success, -1 on error. -int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); - -/// Get interrupt priority. -/// \param[in] irqn interrupt ID number -/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. -uint32_t IRQ_GetPriority (IRQn_ID_t irqn); - -/// Set priority masking threshold. -/// \param[in] priority priority masking threshold value -/// \return 0 on success, -1 on error. -int32_t IRQ_SetPriorityMask (uint32_t priority); - -/// Get priority masking threshold -/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. -uint32_t IRQ_GetPriorityMask (void); - -/// Set priority grouping field split point -/// \param[in] bits number of MSB bits included in the group priority field comparison -/// \return 0 on success, -1 on error. -int32_t IRQ_SetPriorityGroupBits (uint32_t bits); - -/// Get priority grouping field split point -/// \return current number of MSB bits included in the group priority field comparison with -/// optional IRQ_PRIORITY_ERROR bit set. -uint32_t IRQ_GetPriorityGroupBits (void); - -#endif // IRQ_CTRL_H_ diff --git a/external/CMSIS_5/CMSIS/Core_A/Source/irq_ctrl_gic.c b/external/CMSIS_5/CMSIS/Core_A/Source/irq_ctrl_gic.c deleted file mode 100644 index fa7765f..0000000 --- a/external/CMSIS_5/CMSIS/Core_A/Source/irq_ctrl_gic.c +++ /dev/null @@ -1,433 +0,0 @@ -/**************************************************************************//** - * @file irq_ctrl_gic.c - * @brief Interrupt controller handling implementation for GIC - * @version V1.2.0 - * @date 30. October 2022 - ******************************************************************************/ -/* - * Copyright (c) 2017-2022 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#include "RTE_Components.h" -#include CMSIS_device_header - -#include "irq_ctrl.h" - -#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) - -/// Number of implemented interrupt lines -#ifndef IRQ_GIC_LINE_COUNT -#define IRQ_GIC_LINE_COUNT (1020U) -#endif - -#ifndef IRQ_GIC_EXTERN_IRQ_TABLE -static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; -#else -extern IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT]; -#endif -static uint32_t IRQ_ID0; - -/// Initialize interrupt controller. -__WEAK int32_t IRQ_Initialize (void) { - #ifndef IRQ_GIC_EXTERN_IRQ_TABLE - uint32_t i; - - for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { - IRQTable[i] = (IRQHandler_t)NULL; - } - GIC_Enable(); - #endif - return (0); -} - - -/// Register interrupt handler. -__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { - int32_t status; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - IRQTable[irqn] = handler; - status = 0; - } else { - status = -1; - } - - return (status); -} - -/// The Interrupt Handler. -__WEAK void IRQ_Handler (void) { - IRQn_Type irqn = GIC_AcknowledgePending (); - if (irqn < (IRQn_Type)IRQ_GIC_LINE_COUNT) { - IRQTable[irqn](); - } - GIC_EndInterrupt (irqn); -} - - -/// Get the registered interrupt handler. -__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { - IRQHandler_t h; - - // Ignore CPUID field (software generated interrupts) - irqn &= 0x3FFU; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - h = IRQTable[irqn]; - } else { - h = (IRQHandler_t)0; - } - - return (h); -} - - -/// Enable interrupt. -__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { - int32_t status; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - GIC_EnableIRQ ((IRQn_Type)irqn); - status = 0; - } else { - status = -1; - } - - return (status); -} - - -/// Disable interrupt. -__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { - int32_t status; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - GIC_DisableIRQ ((IRQn_Type)irqn); - status = 0; - } else { - status = -1; - } - - return (status); -} - - -/// Get interrupt enable state. -__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { - uint32_t enable; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - enable = GIC_GetEnableIRQ((IRQn_Type)irqn); - } else { - enable = 0U; - } - - return (enable); -} - - -/// Configure interrupt request mode. -__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { - uint32_t val; - uint8_t cfg; - uint8_t secure; - uint8_t cpu; - int32_t status = 0; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - // Check triggering mode - val = (mode & IRQ_MODE_TRIG_Msk); - - if (val == IRQ_MODE_TRIG_LEVEL) { - cfg = 0x00U; - } else if (val == IRQ_MODE_TRIG_EDGE) { - cfg = 0x02U; - } else { - cfg = 0x00U; - status = -1; - } - - val = (mode & IRQ_MODE_MODEL_Msk); - if (val == IRQ_MODE_MODEL_1N) { - cfg |= 1; // 1-N model - } - - // Check interrupt type - val = mode & IRQ_MODE_TYPE_Msk; - - if (val != IRQ_MODE_TYPE_IRQ) { - status = -1; - } - - // Check interrupt domain - val = mode & IRQ_MODE_DOMAIN_Msk; - - if (val == IRQ_MODE_DOMAIN_NONSECURE) { - secure = 0U; - } else { - // Check security extensions support - val = GIC_DistributorInfo() & (1UL << 10U); - - if (val != 0U) { - // Security extensions are supported - secure = 1U; - } else { - secure = 0U; - status = -1; - } - } - - // Check interrupt CPU targets - val = mode & IRQ_MODE_CPU_Msk; - - if (val == IRQ_MODE_CPU_ALL) { - cpu = 0xFFU; - } else { - cpu = (uint8_t)(val >> IRQ_MODE_CPU_Pos); - } - - // Apply configuration if no mode error - if (status == 0) { - GIC_SetConfiguration((IRQn_Type)irqn, cfg); - GIC_SetTarget ((IRQn_Type)irqn, cpu); - - if (secure != 0U) { - GIC_SetGroup ((IRQn_Type)irqn, secure); - } - } - } - - return (status); -} - - -/// Get interrupt mode configuration. -__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { - uint32_t mode; - uint32_t val; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - mode = IRQ_MODE_TYPE_IRQ; - - // Get trigger mode - val = GIC_GetConfiguration((IRQn_Type)irqn); - - if ((val & 2U) != 0U) { - // Corresponding interrupt is edge triggered - mode |= IRQ_MODE_TRIG_EDGE; - } else { - // Corresponding interrupt is level triggered - mode |= IRQ_MODE_TRIG_LEVEL; - } - - if (val & 1U) { - mode |= IRQ_MODE_MODEL_1N; - } - // Get interrupt CPU targets - mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; - - } else { - mode = IRQ_MODE_ERROR; - } - - return (mode); -} - - -/// Get ID number of current interrupt request (IRQ). -__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { - IRQn_ID_t irqn; - uint32_t prio; - - /* Dummy read to avoid GIC 390 errata 801120 */ - GIC_GetHighPendingIRQ(); - - irqn = GIC_AcknowledgePending(); - - __DSB(); - - /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ - /* The following workaround code is for a single-core system. It would be */ - /* different in a multi-core system. */ - /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ - /* so unlock it, otherwise service the interrupt as normal. */ - /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ - /* so will not occur here. */ - - if ((irqn == 0) || (irqn >= 0x3FE)) { - /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ - prio = GIC_GetPriority((IRQn_Type)0); - GIC_SetPriority ((IRQn_Type)0, prio); - - __DSB(); - - if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { - /* If the ID is 0, is active and has not been seen before */ - IRQ_ID0 = 1U; - } - /* End of Workaround GIC 390 errata 733075 */ - } - - return (irqn); -} - - -/// Get ID number of current fast interrupt request (FIQ). -__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { - return ((IRQn_ID_t)-1); -} - - -/// Signal end of interrupt processing. -__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { - int32_t status; - IRQn_Type irq = (IRQn_Type)irqn; - - irqn &= 0x3FFU; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - GIC_EndInterrupt (irq); - - if (irqn == 0) { - IRQ_ID0 = 0U; - } - - status = 0; - } else { - status = -1; - } - - return (status); -} - - -/// Set interrupt pending flag. -__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { - int32_t status; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - GIC_SetPendingIRQ ((IRQn_Type)irqn); - status = 0; - } else { - status = -1; - } - - return (status); -} - -/// Get interrupt pending flag. -__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { - uint32_t pending; - - if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); - } else { - pending = 0U; - } - - return (pending & 1U); -} - - -/// Clear interrupt pending flag. -__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { - int32_t status; - - if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - GIC_ClearPendingIRQ ((IRQn_Type)irqn); - status = 0; - } else { - status = -1; - } - - return (status); -} - - -/// Set interrupt priority value. -__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { - int32_t status; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - GIC_SetPriority ((IRQn_Type)irqn, priority); - status = 0; - } else { - status = -1; - } - - return (status); -} - - -/// Get interrupt priority. -__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { - uint32_t priority; - - if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - priority = GIC_GetPriority ((IRQn_Type)irqn); - } else { - priority = IRQ_PRIORITY_ERROR; - } - - return (priority); -} - - -/// Set priority masking threshold. -__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { - GIC_SetInterfacePriorityMask (priority); - return (0); -} - - -/// Get priority masking threshold -__WEAK uint32_t IRQ_GetPriorityMask (void) { - return GIC_GetInterfacePriorityMask(); -} - - -/// Set priority grouping field split point -__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { - int32_t status; - - if (bits == IRQ_PRIORITY_Msk) { - bits = 7U; - } - - if (bits < 8U) { - GIC_SetBinaryPoint (7U - bits); - status = 0; - } else { - status = -1; - } - - return (status); -} - - -/// Get priority grouping field split point -__WEAK uint32_t IRQ_GetPriorityGroupBits (void) { - uint32_t bp; - - bp = GIC_GetBinaryPoint() & 0x07U; - - return (7U - bp); -} - -#endif diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Config/DAP_config.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Config/DAP_config.h deleted file mode 100644 index 5e62cf4..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Config/DAP_config.h +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright (c) 2013-2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 16. June 2021 - * $Revision: V2.1.0 - * - * Project: CMSIS-DAP Configuration - * Title: DAP_config.h CMSIS-DAP Configuration File (Template) - * - *---------------------------------------------------------------------------*/ - -#ifndef __DAP_CONFIG_H__ -#define __DAP_CONFIG_H__ - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information -\ingroup DAP_ConfigIO_gr -@{ -Provides definitions about the hardware and configuration of the Debug Unit. - -This information includes: - - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. - - Debug Unit Identification strings (Vendor, Product, Serial Number). - - Debug Unit communication packet size. - - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - - Optional information about a connected Target Device (for Evaluation Boards). -*/ - -#ifdef _RTE_ -#include "RTE_Components.h" -#include CMSIS_device_header -#else -#include "device.h" // Debug Unit Cortex-M Processor Header File -#endif - -/// Processor Clock of the Cortex-M MCU used in the Debug Unit. -/// This value is used to calculate the SWD/JTAG clock speed. -#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz. - -/// Number of processor cycles for I/O Port write operations. -/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O -/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses -/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// required. -#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. - -/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. - -/// Indicate that JTAG communication mode is available at the Debug Port. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. - -/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. -/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. -#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. - -/// Default communication mode on the Debug Access Port. -/// Used for the command \ref DAP_Connect when Port Default mode is selected. -#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. - -/// Default communication speed on the Debug Access Port for SWD and JTAG mode. -/// Used to initialize the default SWD/JTAG clock frequency. -/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. -#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. - -/// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimize the communication performance with the -/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, -/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. -#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes. - -/// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimize the communication performance with the -/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the -/// setting can be reduced (valid range is 1 .. 255). -#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered. - -/// Indicate that UART Serial Wire Output (SWO) trace is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available. - -/// USART Driver instance number for the UART SWO. -#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). - -/// Maximum SWO UART Baudrate. -#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. - -/// Indicate that Manchester Serial Wire Output (SWO) trace is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. - -/// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). - -/// SWO Streaming Trace. -#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. - -/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. -#define TIMESTAMP_CLOCK 100000000U ///< Timestamp clock in Hz (0 = timestamps not supported). - -/// Indicate that UART Communication Port is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available. - -/// USART Driver instance number for the UART Communication Port. -#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). - -/// UART Receive Buffer Size. -#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). - -/// UART Transmit Buffer Size. -#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). - -/// Indicate that UART Communication via USB COM Port is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. - -/// Debug Unit is connected to fixed Target Device. -/// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings -/// are stored and may be used by the debugger or IDE to configure device parameters. -#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; - -#define TARGET_DEVICE_VENDOR "Arm" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device -#define TARGET_BOARD_VENDOR "Arm" ///< String indicating the Board Vendor -#define TARGET_BOARD_NAME "Arm board" ///< String indicating the Board Name - -#if TARGET_FIXED != 0 -#include -static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR; -static const char TargetDeviceName [] = TARGET_DEVICE_NAME; -static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR; -static const char TargetBoardName [] = TARGET_BOARD_NAME; -#endif - -/** Get Vendor Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { - (void)str; - return (0U); -} - -/** Get Product Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { - (void)str; - return (0U); -} - -/** Get Serial Number string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { - (void)str; - return (0U); -} - -/** Get Target Device Vendor string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceVendor); - len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Device Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceName); - len = (uint8_t)(strlen(TargetDeviceName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Board Vendor string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardVendor); - len = (uint8_t)(strlen(TargetBoardVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Board Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardName); - len = (uint8_t)(strlen(TargetBoardName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Product Firmware Version string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { - (void)str; - return (0U); -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access -\ingroup DAP_ConfigIO_gr -@{ - -Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode -and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug -interface of a device. The following I/O Pins are provided: - -JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode ----------------------------- | -------------------- | --------------------------------------------- -TCK: Test Clock | SWCLK: Clock | Output Push/Pull -TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) -TDI: Test Data Input | | Output Push/Pull -TDO: Test Data Output | | Input -nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor -nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor - - -DAP Hardware I/O Pin Access Functions -------------------------------------- -The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to -these I/O Pins. - -For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. -This functions are provided to achieve faster I/O that is possible with some advanced GPIO -peripherals that can independently write/read a single I/O pin without affecting any other pins -of the same I/O port. The following SWDIO I/O Pin functions are provided: - - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. - - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. - - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. - - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. -*/ - - -// Configure DAP I/O pins ------------------------------ - -/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. -Configures the DAP Hardware I/O pins for JTAG mode: - - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. - - TDO to input mode. -*/ -__STATIC_INLINE void PORT_JTAG_SETUP (void) { - ; -} - -/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. -Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - - SWCLK, SWDIO, nRESET to output mode and set to default high level. - - TDI, nTRST to HighZ mode (pins are unused in SWD mode). -*/ -__STATIC_INLINE void PORT_SWD_SETUP (void) { - ; -} - -/** Disable JTAG/SWD I/O Pins. -Disables the DAP Hardware I/O pins which configures: - - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. -*/ -__STATIC_INLINE void PORT_OFF (void) { - ; -} - - -// SWCLK/TCK I/O pin ------------------------------------- - -/** SWCLK/TCK I/O pin: Get Input. -\return Current status of the SWCLK/TCK DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { - return (0U); -} - -/** SWCLK/TCK I/O pin: Set Output to High. -Set the SWCLK/TCK DAP hardware I/O pin to high level. -*/ -__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { - ; -} - -/** SWCLK/TCK I/O pin: Set Output to Low. -Set the SWCLK/TCK DAP hardware I/O pin to low level. -*/ -__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { - ; -} - - -// SWDIO/TMS Pin I/O -------------------------------------- - -/** SWDIO/TMS I/O pin: Get Input. -\return Current status of the SWDIO/TMS DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { - return (0U); -} - -/** SWDIO/TMS I/O pin: Set Output to High. -Set the SWDIO/TMS DAP hardware I/O pin to high level. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { - ; -} - -/** SWDIO/TMS I/O pin: Set Output to Low. -Set the SWDIO/TMS DAP hardware I/O pin to low level. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { - ; -} - -/** SWDIO I/O pin: Get Input (used in SWD mode only). -\return Current status of the SWDIO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { - return (0U); -} - -/** SWDIO I/O pin: Set Output (used in SWD mode only). -\param bit Output value for the SWDIO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { - ; -} - -/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). -Configure the SWDIO DAP hardware I/O pin to output mode. This function is -called prior \ref PIN_SWDIO_OUT function calls. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { - ; -} - -/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). -Configure the SWDIO DAP hardware I/O pin to input mode. This function is -called prior \ref PIN_SWDIO_IN function calls. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { - ; -} - - -// TDI Pin I/O --------------------------------------------- - -/** TDI I/O pin: Get Input. -\return Current status of the TDI DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { - return (0U); -} - -/** TDI I/O pin: Set Output. -\param bit Output value for the TDI DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { - ; -} - - -// TDO Pin I/O --------------------------------------------- - -/** TDO I/O pin: Get Input. -\return Current status of the TDO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { - return (0U); -} - - -// nTRST Pin I/O ------------------------------------------- - -/** nTRST I/O pin: Get Input. -\return Current status of the nTRST DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { - return (0U); -} - -/** nTRST I/O pin: Set Output. -\param bit JTAG TRST Test Reset pin status: - - 0: issue a JTAG TRST Test Reset. - - 1: release JTAG TRST Test Reset. -*/ -__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { - ; -} - -// nRESET Pin I/O------------------------------------------ - -/** nRESET I/O pin: Get Input. -\return Current status of the nRESET DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { - return (0U); -} - -/** nRESET I/O pin: Set Output. -\param bit target device hardware reset pin status: - - 0: issue a device hardware reset. - - 1: release device hardware reset. -*/ -__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { - ; -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs -\ingroup DAP_ConfigIO_gr -@{ - -CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. - -It is recommended to provide the following LEDs for status indication: - - Connect LED: is active when the DAP hardware is connected to a debugger. - - Running LED: is active when the debugger has put the target device into running state. -*/ - -/** Debug Unit: Set status of Connected LED. -\param bit status of the Connect LED. - - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. - - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. -*/ -__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {} - -/** Debug Unit: Set status Target Running LED. -\param bit status of the Target Running LED. - - 1: Target Running LED ON: program execution in target started. - - 0: Target Running LED OFF: program execution in target stopped. -*/ -__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp -\ingroup DAP_ConfigIO_gr -@{ -Access function for Test Domain Timer. - -The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By -default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. - -*/ - -/** Get timestamp of Test Domain Timer. -\return Current timestamp value. -*/ -__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { - return (DWT->CYCCNT); -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization -\ingroup DAP_ConfigIO_gr -@{ - -CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. -*/ - -/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). -This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the -Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: - - I/O clock system enabled. - - all I/O pins: input buffer enabled, output pins are set to HighZ mode. - - for nTRST, nRESET a weak pull-up (if available) is enabled. - - LED output pins are enabled and LEDs are turned off. -*/ -__STATIC_INLINE void DAP_SETUP (void) { - ; -} - -/** Reset Target Device with custom specific I/O pin or command sequence. -This function allows the optional implementation of a device specific reset sequence. -It is called when the command \ref DAP_ResetTarget and is for example required -when a device needs a time-critical unlock sequence that enables the debug port. -\return 0 = no device specific reset sequence is implemented.\n - 1 = a device specific reset sequence is implemented. -*/ -__STATIC_INLINE uint8_t RESET_TARGET (void) { - return (0U); // change to '1' when a device reset sequence is implemented -} - -///@} - - -#endif /* __DAP_CONFIG_H__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvguix b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvguix deleted file mode 100644 index a104736..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvguix +++ /dev/null @@ -1,1878 +0,0 @@ - - - - -6.1 - -
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### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - LPC-Link2 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 8 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - - - - - - - - - - - BIN\UL2CM3.DLL - - - - 0 - UL2CM3 - -UV0018BME -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC180000000 -TT180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC10000 -FN1 -FF0LPC18xx43xx_S25FL032 -FS014000000 -FL0400000 - - - - - C:\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\RTX5.scvd - ARM.CMSIS.5.7.0 - 1 - - - C:\ARM\PACK\Keil\MDK-Middleware\7.13.0\USB\USB.scvd - Keil.MDK-Middleware.7.13.0 - 1 - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 0 - 0 - 1 - 10000000 - - - - - - LPC-Link2 on-board - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 0 - - 8 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - - - - - - - - - - - BIN\UL2CM3.DLL - - - - 0 - UL2CM3 - -UV0001BDE -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FN1 -FCFE0 -FD10000000 -FF0LPC18xx43xx_512_BA -FL080000 -FS01A000000 -FP0($$Device:LPC4322$Flash\LPC18xx43xx_512_BA.FLM) - - - - - C:\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\RTX5.scvd - ARM.CMSIS.5.7.0 - 1 - - - C:\ARM\PACK\Keil\MDK-Middleware\7.13.0\USB\USB.scvd - Keil.MDK-Middleware.7.13.0 - 1 - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 0 - 0 - 1 - 10000000 - - - - - - Source - 1 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - .\main.c - main.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - .\target.c - target.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - .\ser_num.c - ser_num.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - .\USBD_User_CustomClass_0.c - USBD_User_CustomClass_0.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - .\USBD_User_CDC_ACM_UART_0.c - USBD_User_CDC_ACM_UART_0.c - 0 - 0 - - - - - Documentation - 1 - 0 - 0 - 0 - - 2 - 6 - 5 - 0 - 0 - 0 - .\README.md - README.md - 0 - 0 - - - - - CMSIS DAP - 1 - 0 - 0 - 0 - - 3 - 7 - 5 - 0 - 0 - 0 - .\DAP_config.h - DAP_config.h - 0 - 0 - - - 3 - 8 - 1 - 0 - 0 - 0 - ..\..\Source\DAP.c - DAP.c - 0 - 0 - - - 3 - 9 - 1 - 0 - 0 - 0 - ..\..\Source\JTAG_DP.c - JTAG_DP.c - 0 - 0 - - - 3 - 10 - 1 - 0 - 0 - 0 - ..\..\Source\SW_DP.c - SW_DP.c - 0 - 0 - - - 3 - 11 - 1 - 0 - 0 - 0 - ..\..\Source\SWO.c - SWO.c - 0 - 0 - - - 3 - 12 - 1 - 0 - 0 - 0 - ..\..\Source\UART.c - UART.c - 0 - 0 - - - - - ::CMSIS - 1 - 0 - 0 - 1 - - - - ::CMSIS Driver - 1 - 0 - 0 - 1 - - - - ::Device - 1 - 0 - 0 - 1 - - - - ::USB - 1 - 0 - 0 - 1 - - - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvprojx b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvprojx deleted file mode 100644 index 24f10bc..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvprojx +++ /dev/null @@ -1,1208 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - LPC-Link2 - 0x4 - ARM-ADS - 6160000::V6.16::ARMCLANG - 1 - - - LPC4370:Cortex-M4 - NXP - Keil.LPC4300_DFP.2.9.0 - http://www.keil.com/pack/ - IRAM(0x10000000,0x20000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000) - 0 - $$Device:LPC4370$Device\Include\LPC43xx.h - - - - - - - - - - $$Device:LPC4370$SVD\LPC43xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - CMSIS_DAP - 1 - 0 - 1 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf.exe --bin -o "$L@L.bin" "#L" - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 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0 - $$Device:LPC4322$Device\Include\LPC43xx.h - - - - - - - - - - $$Device:LPC4322$SVD\LPC43xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - CMSIS_DAP - 1 - 0 - 1 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - $K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000) - fromelf.exe --bin -o "$L@L.bin" "#L" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - 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- - DAP.c - 1 - ..\..\Source\DAP.c - - - JTAG_DP.c - 1 - ..\..\Source\JTAG_DP.c - - - SW_DP.c - 1 - ..\..\Source\SW_DP.c - - - SWO.c - 1 - ..\..\Source\SWO.c - - - UART.c - 1 - ..\..\Source\UART.c - - - - - ::CMSIS - - - ::CMSIS Driver - - - ::Device - - - ::USB - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - USE_SPIFI=1 - - - NO_CRP - - - - - NO_CRP - - - - - - - - RTE\CMSIS\RTX_Config.c - - - - - - - - - RTE\CMSIS\RTX_Config.h - - - - - - - - - RTE\Device\LPC4322_Cortex-M4\RTE_Device.h - - - - - - - - RTE\Device\LPC4322_Cortex-M4\startup_LPC43xx.s - - - - - - - - RTE\Device\LPC4322_Cortex-M4\system_LPC43xx.c - - - - - - - - RTE\Device\LPC4370_Cortex-M4\RTE_Device.h - - - - - - - - RTE\Device\LPC4370_Cortex-M4\startup_LPC43xx.s - - - - - - - - RTE\Device\LPC4370_Cortex-M4\system_LPC43xx.c - - - - - - - - RTE\USB\USBD_Config_0.c - - - - - - - - - RTE\USB\USBD_Config_CDC_0.h - - - - - - - - - RTE\USB\USBD_Config_CustomClass_0.h - - - - - - - - - - - - - - CMSIS_DAP - 1 - - - - - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DAP_config.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DAP_config.h deleted file mode 100644 index 3e7a397..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DAP_config.h +++ /dev/null @@ -1,709 +0,0 @@ -/* - * Copyright (c) 2013-2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 16. June 2021 - * $Revision: V2.1.0 - * - * Project: CMSIS-DAP Examples LPC-Link2 - * Title: DAP_config.h CMSIS-DAP Configuration File for LPC-Link2 - * - *---------------------------------------------------------------------------*/ - -#ifndef __DAP_CONFIG_H__ -#define __DAP_CONFIG_H__ - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information -\ingroup DAP_ConfigIO_gr -@{ -Provides definitions about the hardware and configuration of the Debug Unit. - -This information includes: - - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. - - Debug Unit Identification strings (Vendor, Product, Serial Number). - - Debug Unit communication packet size. - - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - - Optional information about a connected Target Device (for Evaluation Boards). -*/ - -#ifdef _RTE_ -#include "RTE_Components.h" -#include CMSIS_device_header -#else -#include "device.h" // Debug Unit Cortex-M Processor Header File -#endif - -#ifdef LPC_LINK2_ONBOARD -#include -#include "ser_num.h" -#endif - -/// Processor Clock of the Cortex-M MCU used in the Debug Unit. -/// This value is used to calculate the SWD/JTAG clock speed. -#define CPU_CLOCK 180000000U ///< Specifies the CPU Clock in Hz. - -/// Number of processor cycles for I/O Port write operations. -/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O -/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses -/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// required. -#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. - -/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. - -/// Indicate that JTAG communication mode is available at the Debug Port. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. - -/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. -/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. -#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. - -/// Default communication mode on the Debug Access Port. -/// Used for the command \ref DAP_Connect when Port Default mode is selected. -#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. - -/// Default communication speed on the Debug Access Port for SWD and JTAG mode. -/// Used to initialize the default SWD/JTAG clock frequency. -/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. -#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. - -/// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimize the communication performance with the -/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, -/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. -#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes. - -/// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimize the communication performance with the -/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the -/// setting can be reduced (valid range is 1 .. 255). -#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered. - -/// Indicate that UART Serial Wire Output (SWO) trace is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available. - -/// USART Driver instance number for the UART SWO. -#define SWO_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). - -/// Maximum SWO UART Baudrate. -#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. - -/// Indicate that Manchester Serial Wire Output (SWO) trace is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. - -/// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n). - -/// SWO Streaming Trace. -#define SWO_STREAM 1 ///< SWO Streaming Trace: 1 = available, 0 = not available. - -/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. -#define TIMESTAMP_CLOCK 180000000U ///< Timestamp clock in Hz (0 = timestamps not supported). - -/// Indicate that UART Communication Port is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available. - -/// USART Driver instance number for the UART Communication Port. -#define DAP_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). - -/// UART Receive Buffer Size. -#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). - -/// UART Transmit Buffer Size. -#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). - -/// Indicate that UART Communication via USB COM Port is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. - -/// Debug Unit is connected to fixed Target Device. -/// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings -/// are stored and may be used by the debugger or IDE to configure device parameters. -#ifdef LPC_LINK2_ONBOARD -#define TARGET_FIXED 1 ///< Target: 1 = known, 0 = unknown; -#else -#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; -#endif - -#define TARGET_DEVICE_VENDOR "NXP" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device -#define TARGET_BOARD_VENDOR "NXP" ///< String indicating the Board Vendor -#define TARGET_BOARD_NAME "NXP board" ///< String indicating the Board Name - -#if TARGET_FIXED != 0 -extern const char TargetDeviceVendor []; -extern const char TargetDeviceName []; -extern const char TargetBoardVendor []; -extern const char TargetBoardName []; -#endif - -/** Get Vendor Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { - (void)str; - return (0U); -} - -/** Get Product Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { - (void)str; - return (0U); -} - -/** Get Serial Number string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { -#ifdef LPC_LINK2_ONBOARD - uint8_t len = 0U; - char *ser_num; - - ser_num = GetSerialNum(); - if (ser_num != NULL) { - strcpy(str, ser_num); - len = (uint8_t)(strlen(ser_num) + 1U); - } - - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Device Vendor string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceVendor); - len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Device Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceName); - len = (uint8_t)(strlen(TargetDeviceName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Board Vendor string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardVendor); - len = (uint8_t)(strlen(TargetBoardVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Board Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardName); - len = (uint8_t)(strlen(TargetBoardName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Product Firmware Version string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { - (void)str; - return (0U); -} - -///@} - - -// LPC43xx peripheral register bit masks (used by macros) -#define CCU_CLK_CFG_RUN (1U << 0) -#define CCU_CLK_CFG_AUTO (1U << 1) -#define CCU_CLK_STAT_RUN (1U << 0) -#define SCU_SFS_EPD (1U << 3) -#define SCU_SFS_EPUN (1U << 4) -#define SCU_SFS_EHS (1U << 5) -#define SCU_SFS_EZI (1U << 6) -#define SCU_SFS_ZIF (1U << 7) - - -// Debug Port I/O Pins - -// SWCLK/TCK Pin P1_17: GPIO0[12] -#define PIN_SWCLK_TCK_PORT 0 -#define PIN_SWCLK_TCK_BIT 12 - -// SWDIO/TMS Pin P1_6: GPIO1[9] -#define PIN_SWDIO_TMS_PORT 1 -#define PIN_SWDIO_TMS_BIT 9 - -// SWDIO Output Enable Pin P1_5: GPIO1[8] -#define PIN_SWDIO_OE_PORT 1 -#define PIN_SWDIO_OE_BIT 8 - -// TDI Pin P1_18: GPIO0[13] -#define PIN_TDI_PORT 0 -#define PIN_TDI_BIT 13 - -// TDO Pin P1_14: GPIO1[7] -#define PIN_TDO_PORT 1 -#define PIN_TDO_BIT 7 - -// nTRST Pin Not available -#define PIN_nTRST_PORT -#define PIN_nTRST_BIT - -// nRESET Pin P2_5: GPIO5[5] -#define PIN_nRESET_PORT 5 -#define PIN_nRESET_BIT 5 - -// nRESET Output Enable Pin P2_6: GPIO5[6] -#define PIN_nRESET_OE_PORT 5 -#define PIN_nRESET_OE_BIT 6 - - -// Debug Unit LEDs - -// Connected LED P1_1: GPIO0[8] -#define LED_CONNECTED_PORT 0 -#define LED_CONNECTED_BIT 8 - -// Target Running LED Not available - - -//************************************************************************************************** -/** -\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access -\ingroup DAP_ConfigIO_gr -@{ - -Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode -and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug -interface of a device. The following I/O Pins are provided: - -JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode ----------------------------- | -------------------- | --------------------------------------------- -TCK: Test Clock | SWCLK: Clock | Output Push/Pull -TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) -TDI: Test Data Input | | Output Push/Pull -TDO: Test Data Output | | Input -nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor -nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor - - -DAP Hardware I/O Pin Access Functions -------------------------------------- -The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to -these I/O Pins. - -For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. -This functions are provided to achieve faster I/O that is possible with some advanced GPIO -peripherals that can independently write/read a single I/O pin without affecting any other pins -of the same I/O port. The following SWDIO I/O Pin functions are provided: - - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. - - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. - - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. - - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. -*/ - - -// Configure DAP I/O pins ------------------------------ - -// LPC-Link2 HW uses buffers for debug port pins. Therefore it is not -// possible to disable outputs SWCLK/TCK, TDI and they are left active. -// Only SWDIO/TMS output can be disabled but it is also left active. -// nRESET is configured for open drain mode. - -/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. -Configures the DAP Hardware I/O pins for JTAG mode: - - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. - - TDO to input mode. -*/ -__STATIC_INLINE void PORT_JTAG_SETUP (void) { - LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U; - LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT); -} - -/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. -Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - - SWCLK, SWDIO, nRESET to output mode and set to default high level. - - TDI, nTRST to HighZ mode (pins are unused in SWD mode). -*/ -__STATIC_INLINE void PORT_SWD_SETUP (void) { - LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U; - LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT); -} - -/** Disable JTAG/SWD I/O Pins. -Disables the DAP Hardware I/O pins which configures: - - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. -*/ -__STATIC_INLINE void PORT_OFF (void) { - LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT); - LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT); - LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT); - LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT); - LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT); - LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT); -} - - -// SWCLK/TCK I/O pin ------------------------------------- - -/** SWCLK/TCK I/O pin: Get Input. -\return Current status of the SWCLK/TCK DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { - return ((LPC_GPIO_PORT->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1U); -} - -/** SWCLK/TCK I/O pin: Set Output to High. -Set the SWCLK/TCK DAP hardware I/O pin to high level. -*/ -__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { - LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT; -} - -/** SWCLK/TCK I/O pin: Set Output to Low. -Set the SWCLK/TCK DAP hardware I/O pin to low level. -*/ -__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { - LPC_GPIO_PORT->CLR[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT; -} - - -// SWDIO/TMS Pin I/O -------------------------------------- - -/** SWDIO/TMS I/O pin: Get Input. -\return Current status of the SWDIO/TMS DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { - return ((LPC_GPIO_PORT->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1U); -} - -/** SWDIO/TMS I/O pin: Set Output to High. -Set the SWDIO/TMS DAP hardware I/O pin to high level. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { - LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT; -} - -/** SWDIO/TMS I/O pin: Set Output to Low. -Set the SWDIO/TMS DAP hardware I/O pin to low level. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { - LPC_GPIO_PORT->CLR[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT; -} - -/** SWDIO I/O pin: Get Input (used in SWD mode only). -\return Current status of the SWDIO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { - return (LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT); -} - -/** SWDIO I/O pin: Set Output (used in SWD mode only). -\param bit Output value for the SWDIO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { - LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] = bit << PIN_SWDIO_TMS_BIT; -} - -/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). -Configure the SWDIO DAP hardware I/O pin to output mode. This function is -called prior \ref PIN_SWDIO_OUT function calls. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { - LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT; -} - -/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). -Configure the SWDIO DAP hardware I/O pin to input mode. This function is -called prior \ref PIN_SWDIO_IN function calls. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { - LPC_GPIO_PORT->CLR[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT; -} - - -// TDI Pin I/O --------------------------------------------- - -/** TDI I/O pin: Get Input. -\return Current status of the TDI DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { - return ((LPC_GPIO_PORT->PIN [PIN_TDI_PORT] >> PIN_TDI_BIT) & 1U); -} - -/** TDI I/O pin: Set Output. -\param bit Output value for the TDI DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { - LPC_GPIO_PORT->MPIN[PIN_TDI_PORT] = bit << PIN_TDI_BIT; -} - - -// TDO Pin I/O --------------------------------------------- - -/** TDO I/O pin: Get Input. -\return Current status of the TDO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { - return ((LPC_GPIO_PORT->PIN[PIN_TDO_PORT] >> PIN_TDO_BIT) & 1U); -} - - -// nTRST Pin I/O ------------------------------------------- - -/** nTRST I/O pin: Get Input. -\return Current status of the nTRST DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { - return (0U); // Not available -} - -/** nTRST I/O pin: Set Output. -\param bit JTAG TRST Test Reset pin status: - - 0: issue a JTAG TRST Test Reset. - - 1: release JTAG TRST Test Reset. -*/ -__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { - (void) bit; - // Not available -} - -// nRESET Pin I/O------------------------------------------ - -/** nRESET I/O pin: Get Input. -\return Current status of the nRESET DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { - return ((LPC_GPIO_PORT->PIN[PIN_nRESET_PORT] >> PIN_nRESET_BIT) & 1U); -} - -/** nRESET I/O pin: Set Output. -\param bit target device hardware reset pin status: - - 0: issue a device hardware reset. - - 1: release device hardware reset. -*/ -__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { - if (bit) { - LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT); - LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT); - } else { - LPC_GPIO_PORT->SET[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT); - LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] |= (1U << PIN_nRESET_BIT); - } -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs -\ingroup DAP_ConfigIO_gr -@{ - -CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. - -It is recommended to provide the following LEDs for status indication: - - Connect LED: is active when the DAP hardware is connected to a debugger. - - Running LED: is active when the debugger has put the target device into running state. -*/ - -/** Debug Unit: Set status of Connected LED. -\param bit status of the Connect LED. - - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. - - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. -*/ -__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { - LPC_GPIO_PORT->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = (uint8_t)bit; -} - -/** Debug Unit: Set status Target Running LED. -\param bit status of the Target Running LED. - - 1: Target Running LED ON: program execution in target started. - - 0: Target Running LED OFF: program execution in target stopped. -*/ -__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) { - (void) bit; - // Not available -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp -\ingroup DAP_ConfigIO_gr -@{ -Access function for Test Domain Timer. - -The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By -default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. - -*/ - -/** Get timestamp of Test Domain Timer. -\return Current timestamp value. -*/ -__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { - return (DWT->CYCCNT); -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization -\ingroup DAP_ConfigIO_gr -@{ - -CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. -*/ - -/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). -This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the -Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: - - I/O clock system enabled. - - all I/O pins: input buffer enabled, output pins are set to HighZ mode. - - for nTRST, nRESET a weak pull-up (if available) is enabled. - - LED output pins are enabled and LEDs are turned off. -*/ -__STATIC_INLINE void DAP_SETUP (void) { - - /* Enable clock and init GPIO outputs */ - LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; - while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN)); - - /* Configure I/O pins: function number, input buffer enabled, */ - /* no pull-up/down except nRESET (pull-up) */ - LPC_SCU->SFSP1_17 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWCLK/TCK: GPIO0[12] */ - LPC_SCU->SFSP1_6 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO/TMS: GPIO1[9] */ - LPC_SCU->SFSP1_5 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO_OE: GPIO1[8] */ - LPC_SCU->SFSP1_18 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDI: GPIO0[13] */ - LPC_SCU->SFSP1_14 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDO: GPIO1[7] */ - LPC_SCU->SFSP2_5 = 4U | SCU_SFS_EZI; /* nRESET: GPIO5[5] */ - LPC_SCU->SFSP2_6 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* nRESET_OE: GPIO5[6] */ - LPC_SCU->SFSP1_1 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* LED: GPIO0[8] */ -#ifdef TARGET_POWER_EN - LPC_SCU->SFSP3_1 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* Target Power enable P3_1 GPIO5[8] */ -#endif - - /* Configure: SWCLK/TCK, SWDIO/TMS, SWDIO_OE, TDI as outputs (high level) */ - /* TDO as input */ - /* nRESET as input with output latch set to low level */ - /* nRESET_OE as output (low level) */ - LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT); - LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT); - LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT); - LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT); - LPC_GPIO_PORT->CLR[PIN_nRESET_PORT] = (1U << PIN_nRESET_BIT); - LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT); - LPC_GPIO_PORT->DIR[PIN_SWCLK_TCK_PORT] |= (1U << PIN_SWCLK_TCK_BIT); - LPC_GPIO_PORT->DIR[PIN_SWDIO_TMS_PORT] |= (1U << PIN_SWDIO_TMS_BIT); - LPC_GPIO_PORT->DIR[PIN_SWDIO_OE_PORT] |= (1U << PIN_SWDIO_OE_BIT); - LPC_GPIO_PORT->DIR[PIN_TDI_PORT] |= (1U << PIN_TDI_BIT); - LPC_GPIO_PORT->DIR[PIN_TDO_PORT] &= ~(1U << PIN_TDO_BIT); - LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT); - LPC_GPIO_PORT->DIR[PIN_nRESET_OE_PORT] |= (1U << PIN_nRESET_OE_BIT); - -#ifdef TARGET_POWER_EN - /* Target Power enable as output (turned on) */ - LPC_GPIO_PORT->SET[5] = (1U << 8); - LPC_GPIO_PORT->DIR[5] |= (1U << 8); -#endif - - /* Configure: LED as output (turned off) */ - LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1U << LED_CONNECTED_BIT); - LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1U << LED_CONNECTED_BIT); - - /* Configure Peripheral Interrupt Priorities */ - NVIC_SetPriority(USB0_IRQn, 1U); -} - -/** Reset Target Device with custom specific I/O pin or command sequence. -This function allows the optional implementation of a device specific reset sequence. -It is called when the command \ref DAP_ResetTarget and is for example required -when a device needs a time-critical unlock sequence that enables the debug port. -\return 0 = no device specific reset sequence is implemented.\n - 1 = a device specific reset sequence is implemented. -*/ -__STATIC_INLINE uint8_t RESET_TARGET (void) { - return (0U); // change to '1' when a device reset sequence is implemented -} - -///@} - - -#endif /* __DAP_CONFIG_H__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf deleted file mode 100644 index fb89136..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf +++ /dev/null @@ -1,43 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// Debug Setup - -// Release M0 On Connect -// <0=> No -// <1=> Yes -// Debugger releases the M0 Application processor from reset when connecting to it. -ReleaseM0OnConnect = 1; - -// Release M0 Sub-System On Connect -// <0=> No -// <1=> Yes -// Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only). -ReleaseM0SubOnConnect = 1; - -// Vector Reset -// <0=> Processor Only -// <1=> Processor and Peripherals -// Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset -VecResetWithPeriph = 1; - -// - -// TPIU Pin Routing (TRACECLK fixed on PF_4) -// Configure the TPIU pin routing as used on your target platform. -// TRACEDATA0 -// <0=> Pin PF_5 -// <1=> Pin P7_4 -// TRACEDATA1 -// <0=> Pin PF_6 -// <1=> Pin P7_5 -// TRACEDATA2 -// <0=> Pin PF_7 -// <1=> Pin P7_6 -// TRACEDATA3 -// <0=> Pin PF_8 -// <1=> Pin P7_7 -RoutingTPIU = 0x00000000; - -// - -// <<< end of configuration section >>> diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_on-board_LPC4322_Cortex-M4.dbgconf b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_on-board_LPC4322_Cortex-M4.dbgconf deleted file mode 100644 index fb89136..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_on-board_LPC4322_Cortex-M4.dbgconf +++ /dev/null @@ -1,43 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// Debug Setup - -// Release M0 On Connect -// <0=> No -// <1=> Yes -// Debugger releases the M0 Application processor from reset when connecting to it. -ReleaseM0OnConnect = 1; - -// Release M0 Sub-System On Connect -// <0=> No -// <1=> Yes -// Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only). -ReleaseM0SubOnConnect = 1; - -// Vector Reset -// <0=> Processor Only -// <1=> Processor and Peripherals -// Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset -VecResetWithPeriph = 1; - -// - -// TPIU Pin Routing (TRACECLK fixed on PF_4) -// Configure the TPIU pin routing as used on your target platform. -// TRACEDATA0 -// <0=> Pin PF_5 -// <1=> Pin P7_4 -// TRACEDATA1 -// <0=> Pin PF_6 -// <1=> Pin P7_5 -// TRACEDATA2 -// <0=> Pin PF_7 -// <1=> Pin P7_6 -// TRACEDATA3 -// <0=> Pin PF_8 -// <1=> Pin P7_7 -RoutingTPIU = 0x00000000; - -// - -// <<< end of configuration section >>> diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/Objects/CMSIS_DAP.hex b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/Objects/CMSIS_DAP.hex deleted file mode 100644 index 5b640f4..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/Objects/CMSIS_DAP.hex +++ /dev/null @@ -1,4356 +0,0 @@ -:020000041400E6 -:10000000A0A10010659300146D9300146F93001469 -:100010007193001473930014759300145A5A5A5A2A -:100020000000000000000000000000002DA60014E9 -:100030007993001400000000C5A60014D5A6001492 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-:100F100000000000000000000000000000000000D1 -:100F200000000000000000000000000000000000C1 -:100F300000000000000000000000000000000000B1 -:100F400000000000000000000000000000000000A1 -:100F50000000000000000000000000000000000091 -:100F60000000000000000000000000000000000081 -:100F70000000000000000000000000000000000071 -:100F80000000000000000000000000000000000061 -:100F90000000000000000000000000000000000051 -:100FA0000000000000000000000000000000000041 -:100FB0000000000000000000000000000000000031 -:100FC0000000000000000000000000000000000021 -:100FD0000000000000000000000000000000000011 -:100FE0000000000000000000000000000000000001 -:100FF00000000000000000000000000000000000F1 -:0400000514000115CD -:00000001FF diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/README.md b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/README.md deleted file mode 100644 index 2029c8a..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/README.md +++ /dev/null @@ -1,8 +0,0 @@ -CMSIS-DAP v2 firmware for NXP LPC-Link2 debug probe. - -CMSIS-DAP v2 uses USB bulk endpoints for the communication with the host PC and is therefore faster. -Optionally, support for streaming SWO trace is provided via an additional USB endpoint. - -Following targets are available: - - LPC-Link2: stand-alone debug probe - - LPC-Link2 on-board: on-board debug probe (LPC55S69-EVK, MIMXRT1064-EVK, ...) diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.c deleted file mode 100644 index 22151e9..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.1.0 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration - * - * ----------------------------------------------------------------------------- - */ - -#include "cmsis_compiler.h" -#include "rtx_os.h" - -// OS Idle Thread -__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { - (void)argument; - - for (;;) {} -} - -// OS Error Callback function -__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { - (void)object_id; - - switch (code) { - case osRtxErrorStackUnderflow: - // Stack overflow detected for thread (thread_id=object_id) - break; - case osRtxErrorISRQueueOverflow: - // ISR Queue overflow detected when inserting object (object_id) - break; - case osRtxErrorTimerQueueOverflow: - // User Timer Callback Queue overflow detected for timer (timer_id=object_id) - break; - case osRtxErrorClibSpace: - // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM - break; - case osRtxErrorClibMutex: - // Standard C/C++ library mutex initialization failed - break; - default: - break; - } - for (;;) {} -//return 0U; -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.h deleted file mode 100644 index fb6a8c1..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.h +++ /dev/null @@ -1,580 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.5.1 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration definitions - * - * ----------------------------------------------------------------------------- - */ - -#ifndef RTX_CONFIG_H_ -#define RTX_CONFIG_H_ - -#ifdef _RTE_ -#include "RTE_Components.h" -#ifdef RTE_RTX_CONFIG_H -#include RTE_RTX_CONFIG_H -#endif -#endif - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Configuration -// ======================= - -// Global Dynamic Memory size [bytes] <0-1073741824:8> -// Defines the combined global dynamic memory size. -// Default: 32768 -#ifndef OS_DYNAMIC_MEM_SIZE -#define OS_DYNAMIC_MEM_SIZE 4096 -#endif - -// Kernel Tick Frequency [Hz] <1-1000000> -// Defines base time unit for delays and timeouts. -// Default: 1000 (1ms tick) -#ifndef OS_TICK_FREQ -#define OS_TICK_FREQ 1000 -#endif - -// Round-Robin Thread switching -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN_ENABLE -#define OS_ROBIN_ENABLE 1 -#endif - -// Round-Robin Timeout <1-1000> -// Defines how many ticks a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBIN_TIMEOUT -#define OS_ROBIN_TIMEOUT 5 -#endif - -// - -// ISR FIFO Queue -// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries -// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries -// RTOS Functions called from ISR store requests to this buffer. -// Default: 16 entries -#ifndef OS_ISR_FIFO_QUEUE -#define OS_ISR_FIFO_QUEUE 32 -#endif - -// Object Memory usage counters -// Enables object memory usage counters (requires RTX source variant). -#ifndef OS_OBJ_MEM_USAGE -#define OS_OBJ_MEM_USAGE 0 -#endif - -// - -// Thread Configuration -// ======================= - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_THREAD_OBJ_MEM -#define OS_THREAD_OBJ_MEM 0 -#endif - -// Number of user Threads <1-1000> -// Defines maximum number of user threads that can be active at the same time. -// Applies to user threads with system provided memory for control blocks. -#ifndef OS_THREAD_NUM -#define OS_THREAD_NUM 1 -#endif - -// Number of user Threads with default Stack size <0-1000> -// Defines maximum number of user threads with default stack size. -// Applies to user threads with zero stack size specified. -#ifndef OS_THREAD_DEF_STACK_NUM -#define OS_THREAD_DEF_STACK_NUM 0 -#endif - -// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> -// Defines the combined stack size for user threads with user-provided stack size. -// Applies to user threads with user-provided stack size and system provided memory for stack. -// Default: 0 -#ifndef OS_THREAD_USER_STACK_SIZE -#define OS_THREAD_USER_STACK_SIZE 0 -#endif - -// - -// Default Thread Stack size [bytes] <96-1073741824:8> -// Defines stack size for threads with zero stack size specified. -// Default: 3072 -#ifndef OS_STACK_SIZE -#define OS_STACK_SIZE 1024 -#endif - -// Idle Thread Stack size [bytes] <72-1073741824:8> -// Defines stack size for Idle thread. -// Default: 512 -#ifndef OS_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE 512 -#endif - -// Idle Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_IDLE_THREAD_TZ_MOD_ID -#define OS_IDLE_THREAD_TZ_MOD_ID 0 -#endif - -// Stack overrun checking -// Enables stack overrun check at thread switch. -// Enabling this option increases slightly the execution time of a thread switch. -#ifndef OS_STACK_CHECK -#define OS_STACK_CHECK 1 -#endif - -// Stack usage watermark -// Initializes thread stack with watermark pattern for analyzing stack usage. -// Enabling this option increases significantly the execution time of thread creation. -#ifndef OS_STACK_WATERMARK -#define OS_STACK_WATERMARK 0 -#endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_PRIVILEGE_MODE -#define OS_PRIVILEGE_MODE 1 -#endif - -// - -// Timer Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_TIMER_OBJ_MEM -#define OS_TIMER_OBJ_MEM 0 -#endif - -// Number of Timer objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_TIMER_NUM -#define OS_TIMER_NUM 1 -#endif - -// - -// Timer Thread Priority -// <8=> Low -// <16=> Below Normal <24=> Normal <32=> Above Normal -// <40=> High -// <48=> Realtime -// Defines priority for timer thread -// Default: High -#ifndef OS_TIMER_THREAD_PRIO -#define OS_TIMER_THREAD_PRIO 40 -#endif - -// Timer Thread Stack size [bytes] <0-1073741824:8> -// Defines stack size for Timer thread. -// May be set to 0 when timers are not used. -// Default: 512 -#ifndef OS_TIMER_THREAD_STACK_SIZE -#define OS_TIMER_THREAD_STACK_SIZE 512 -#endif - -// Timer Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_TIMER_THREAD_TZ_MOD_ID -#define OS_TIMER_THREAD_TZ_MOD_ID 0 -#endif - -// Timer Callback Queue entries <0-256> -// Number of concurrent active timer callback functions. -// May be set to 0 when timers are not used. -// Default: 4 -#ifndef OS_TIMER_CB_QUEUE -#define OS_TIMER_CB_QUEUE 4 -#endif - -// - -// Event Flags Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_EVFLAGS_OBJ_MEM -#define OS_EVFLAGS_OBJ_MEM 0 -#endif - -// Number of Event Flags objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_EVFLAGS_NUM -#define OS_EVFLAGS_NUM 1 -#endif - -// - -// - -// Mutex Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MUTEX_OBJ_MEM -#define OS_MUTEX_OBJ_MEM 0 -#endif - -// Number of Mutex objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MUTEX_NUM -#define OS_MUTEX_NUM 1 -#endif - -// - -// - -// Semaphore Configuration -// ========================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_SEMAPHORE_OBJ_MEM -#define OS_SEMAPHORE_OBJ_MEM 0 -#endif - -// Number of Semaphore objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_SEMAPHORE_NUM -#define OS_SEMAPHORE_NUM 1 -#endif - -// - -// - -// Memory Pool Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MEMPOOL_OBJ_MEM -#define OS_MEMPOOL_OBJ_MEM 0 -#endif - -// Number of Memory Pool objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MEMPOOL_NUM -#define OS_MEMPOOL_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MEMPOOL_DATA_SIZE -#define OS_MEMPOOL_DATA_SIZE 0 -#endif - -// - -// - -// Message Queue Configuration -// ============================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MSGQUEUE_OBJ_MEM -#define OS_MSGQUEUE_OBJ_MEM 0 -#endif - -// Number of Message Queue objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MSGQUEUE_NUM -#define OS_MSGQUEUE_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MSGQUEUE_DATA_SIZE -#define OS_MSGQUEUE_DATA_SIZE 0 -#endif - -// - -// - -// Event Recorder Configuration -// =============================== - -// Global Initialization -// Initialize Event Recorder during 'osKernelInitialize'. -#ifndef OS_EVR_INIT -#define OS_EVR_INIT 0 -#endif - -// Start recording -// Start event recording after initialization. -#ifndef OS_EVR_START -#define OS_EVR_START 1 -#endif - -// Global Event Filter Setup -// Initial recording level applied to all components. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_LEVEL -#define OS_EVR_LEVEL 0x00U -#endif - -// RTOS Event Filter Setup -// Recording levels for RTX components. -// Only applicable if events for the respective component are generated. - -// Memory Management -// Recording level for Memory Management events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMORY_LEVEL -#define OS_EVR_MEMORY_LEVEL 0x01U -#endif - -// Kernel -// Recording level for Kernel events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_KERNEL_LEVEL -#define OS_EVR_KERNEL_LEVEL 0x01U -#endif - -// Thread -// Recording level for Thread events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THREAD_LEVEL -#define OS_EVR_THREAD_LEVEL 0x05U -#endif - -// Generic Wait -// Recording level for Generic Wait events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_WAIT_LEVEL -#define OS_EVR_WAIT_LEVEL 0x01U -#endif - -// Thread Flags -// Recording level for Thread Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THFLAGS_LEVEL -#define OS_EVR_THFLAGS_LEVEL 0x01U -#endif - -// Event Flags -// Recording level for Event Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_EVFLAGS_LEVEL -#define OS_EVR_EVFLAGS_LEVEL 0x01U -#endif - -// Timer -// Recording level for Timer events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_TIMER_LEVEL -#define OS_EVR_TIMER_LEVEL 0x01U -#endif - -// Mutex -// Recording level for Mutex events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MUTEX_LEVEL -#define OS_EVR_MUTEX_LEVEL 0x01U -#endif - -// Semaphore -// Recording level for Semaphore events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_SEMAPHORE_LEVEL -#define OS_EVR_SEMAPHORE_LEVEL 0x01U -#endif - -// Memory Pool -// Recording level for Memory Pool events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMPOOL_LEVEL -#define OS_EVR_MEMPOOL_LEVEL 0x01U -#endif - -// Message Queue -// Recording level for Message Queue events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MSGQUEUE_LEVEL -#define OS_EVR_MSGQUEUE_LEVEL 0x01U -#endif - -// - -// - -// RTOS Event Generation -// Enables event generation for RTX components (requires RTX source variant). - -// Memory Management -// Enables Memory Management event generation. -#ifndef OS_EVR_MEMORY -#define OS_EVR_MEMORY 1 -#endif - -// Kernel -// Enables Kernel event generation. -#ifndef OS_EVR_KERNEL -#define OS_EVR_KERNEL 1 -#endif - -// Thread -// Enables Thread event generation. -#ifndef OS_EVR_THREAD -#define OS_EVR_THREAD 1 -#endif - -// Generic Wait -// Enables Generic Wait event generation. -#ifndef OS_EVR_WAIT -#define OS_EVR_WAIT 1 -#endif - -// Thread Flags -// Enables Thread Flags event generation. -#ifndef OS_EVR_THFLAGS -#define OS_EVR_THFLAGS 1 -#endif - -// Event Flags -// Enables Event Flags event generation. -#ifndef OS_EVR_EVFLAGS -#define OS_EVR_EVFLAGS 1 -#endif - -// Timer -// Enables Timer event generation. -#ifndef OS_EVR_TIMER -#define OS_EVR_TIMER 1 -#endif - -// Mutex -// Enables Mutex event generation. -#ifndef OS_EVR_MUTEX -#define OS_EVR_MUTEX 1 -#endif - -// Semaphore -// Enables Semaphore event generation. -#ifndef OS_EVR_SEMAPHORE -#define OS_EVR_SEMAPHORE 1 -#endif - -// Memory Pool -// Enables Memory Pool event generation. -#ifndef OS_EVR_MEMPOOL -#define OS_EVR_MEMPOOL 1 -#endif - -// Message Queue -// Enables Message Queue event generation. -#ifndef OS_EVR_MSGQUEUE -#define OS_EVR_MSGQUEUE 1 -#endif - -// - -// - -// Number of Threads which use standard C/C++ library libspace -// (when thread specific memory allocation is not used). -#if (OS_THREAD_OBJ_MEM == 0) -#ifndef OS_THREAD_LIBSPACE_NUM -#define OS_THREAD_LIBSPACE_NUM 4 -#endif -#else -#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM -#endif - -//------------- <<< end of configuration section >>> --------------------------- - -#endif // RTX_CONFIG_H_ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/RTE_Device.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/RTE_Device.h deleted file mode 100644 index 146a2d4..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/RTE_Device.h +++ /dev/null @@ -1,2483 +0,0 @@ -/* -------------------------------------------------------------------------- - * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All - * rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 25. April 2016 - * $Revision: V2.2.1 - * - * Project: RTE Device Configuration for NXP LPC43xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -// USB0 Controller [Driver_USBD0 and Driver_USBH0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host -#define RTE_USB_USB0 1 - -// Pin Configuration -// USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3 -// VBUS drive signal (towards external charge pump or power management unit). -#define RTE_USB0_PPWR_ID 0 -#if (RTE_USB0_PPWR_ID == 0) - #define RTE_USB0_PPWR_PIN_EN 0 -#elif (RTE_USB0_PPWR_ID == 1) - #define RTE_USB0_PPWR_PORT 1 - #define RTE_USB0_PPWR_BIT 7 - #define RTE_USB0_PPWR_FUNC 4 -#elif (RTE_USB0_PPWR_ID == 2) - #define RTE_USB0_PPWR_PORT 2 - #define RTE_USB0_PPWR_BIT 0 - #define RTE_USB0_PPWR_FUNC 3 -#elif (RTE_USB0_PPWR_ID == 3) - #define RTE_USB0_PPWR_PORT 2 - #define RTE_USB0_PPWR_BIT 3 - #define RTE_USB0_PPWR_FUNC 7 -#elif (RTE_USB0_PPWR_ID == 4) - #define RTE_USB0_PPWR_PORT 6 - #define RTE_USB0_PPWR_BIT 3 - #define RTE_USB0_PPWR_FUNC 1 -#else - #error "Invalid RTE_USB0_PPWR Pin Configuration!" -#endif -#ifndef RTE_USB0_PPWR_PIN_EN - #define RTE_USB0_PPWR_PIN_EN 1 -#endif -// USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0 -// Port power fault signal indicating overcurrent condition. -// This signal monitors over-current on the USB bus -// (external circuitry required to detect over-current condition). -#define RTE_USB0_PWR_FAULT_ID 0 -#if (RTE_USB0_PWR_FAULT_ID == 0) - #define RTE_USB0_PWR_FAULT_PIN_EN 0 -#elif (RTE_USB0_PWR_FAULT_ID == 1) - #define RTE_USB0_PWR_FAULT_PORT 1 - #define RTE_USB0_PWR_FAULT_BIT 5 - #define RTE_USB0_PWR_FAULT_FUNC 4 -#elif (RTE_USB0_PWR_FAULT_ID == 2) - #define RTE_USB0_PWR_FAULT_PORT 2 - #define RTE_USB0_PWR_FAULT_BIT 1 - #define RTE_USB0_PWR_FAULT_FUNC 3 -#elif (RTE_USB0_PWR_FAULT_ID == 3) - #define RTE_USB0_PWR_FAULT_PORT 2 - #define RTE_USB0_PWR_FAULT_BIT 4 - #define RTE_USB0_PWR_FAULT_FUNC 7 -#elif (RTE_USB0_PWR_FAULT_ID == 4) - #define RTE_USB0_PWR_FAULT_PORT 6 - #define RTE_USB0_PWR_FAULT_BIT 6 - #define RTE_USB0_PWR_FAULT_FUNC 3 -#elif (RTE_USB0_PWR_FAULT_ID == 5) - #define RTE_USB0_PWR_FAULT_PORT 8 - #define RTE_USB0_PWR_FAULT_BIT 0 - #define RTE_USB0_PWR_FAULT_FUNC 1 -#else - #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!" -#endif -#ifndef RTE_USB0_PWR_FAULT_PIN_EN - #define RTE_USB0_PWR_FAULT_PIN_EN 1 -#endif -// USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2 -// USB0 port indicator LED control output 0 -#define RTE_USB0_IND0_ID 0 -#if (RTE_USB0_IND0_ID == 0) - #define RTE_USB0_IND0_PIN_EN 0 -#elif (RTE_USB0_IND0_ID == 1) - #define RTE_USB0_IND0_PORT 1 - #define RTE_USB0_IND0_BIT 4 - #define RTE_USB0_IND0_FUNC 4 -#elif (RTE_USB0_IND0_ID == 2) - #define RTE_USB0_IND0_PORT 2 - #define RTE_USB0_IND0_BIT 5 - #define RTE_USB0_IND0_FUNC 7 -#elif (RTE_USB0_IND0_ID == 3) - #define RTE_USB0_IND0_PORT 2 - #define RTE_USB0_IND0_BIT 6 - #define RTE_USB0_IND0_FUNC 3 -#elif (RTE_USB0_IND0_ID == 4) - #define RTE_USB0_IND0_PORT 6 - #define RTE_USB0_IND0_BIT 8 - #define RTE_USB0_IND0_FUNC 3 -#elif (RTE_USB0_IND0_ID == 5) - #define RTE_USB0_IND0_PORT 8 - #define RTE_USB0_IND0_BIT 2 - #define RTE_USB0_IND0_FUNC 1 -#else - #error "Invalid RTE_USB0_IND0 Pin Configuration!" -#endif -#ifndef RTE_USB0_IND0_PIN_EN - #define RTE_USB0_IND0_PIN_EN 1 -#endif -// USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1 -// USB0 port indicator LED control output 1 -#define RTE_USB0_IND1_ID 0 -#if (RTE_USB0_IND1_ID == 0) - #define RTE_USB0_IND1_PIN_EN 0 -#elif (RTE_USB0_IND1_ID == 1) - #define RTE_USB0_IND1_PORT 1 - #define RTE_USB0_IND1_BIT 3 - #define RTE_USB0_IND1_FUNC 4 -#elif (RTE_USB0_IND1_ID == 2) - #define RTE_USB0_IND1_PORT 2 - #define RTE_USB0_IND1_BIT 2 - #define RTE_USB0_IND1_FUNC 3 -#elif (RTE_USB0_IND1_ID == 3) - #define RTE_USB0_IND1_PORT 6 - #define RTE_USB0_IND1_BIT 7 - #define RTE_USB0_IND1_FUNC 3 -#elif (RTE_USB0_IND1_ID == 4) - #define RTE_USB0_IND1_PORT 8 - #define RTE_USB0_IND1_BIT 1 - #define RTE_USB0_IND1_FUNC 1 -#else - #error "Invalid RTE_USB0_IND1 Pin Configuration!" -#endif -#ifndef RTE_USB0_IND1_PIN_EN - #define RTE_USB0_IND1_PIN_EN 1 -#endif -// Pin Configuration - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -// High-speed -// Enable high-speed functionality -#define RTE_USB_USB0_HS_EN 1 -// Device [Driver_USBD0] -// USB0 Controller [Driver_USBD0 and Driver_USBH0] - -// USB1 Controller [Driver_USBD1 and Driver_USBH1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_USB1 0 - -// Pin Configuration -// USB1_PPWR (Host) <0=>Not used <1=>P9_5 -// VBUS drive signal (towards external charge pump or power management unit). -#define RTE_USB1_PPWR_ID 1 -#if (RTE_USB1_PPWR_ID == 0) - #define RTE_USB1_PPWR_PIN_EN 0 -#elif (RTE_USB1_PPWR_ID == 1) - #define RTE_USB1_PPWR_PORT 9 - #define RTE_USB1_PPWR_BIT 5 - #define RTE_USB1_PPWR_FUNC 2 -#else - #error "Invalid RTE_USB1_PPWR Pin Configuration!" -#endif -#ifndef RTE_USB1_PPWR_PIN_EN - #define RTE_USB1_PPWR_PIN_EN 1 -#endif -// USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6 -// Port power fault signal indicating overcurrent condition. -// This signal monitors over-current on the USB bus -// (external circuitry required to detect over-current condition). -#define RTE_USB1_PWR_FAULT_ID 1 -#if (RTE_USB1_PWR_FAULT_ID == 0) - #define RTE_USB1_PWR_FAULT_PIN_EN 0 -#elif (RTE_USB1_PWR_FAULT_ID == 1) - #define RTE_USB1_PWR_FAULT_PORT 9 - #define RTE_USB1_PWR_FAULT_BIT 6 - #define RTE_USB1_PWR_FAULT_FUNC 2 -#else - #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!" -#endif -#ifndef RTE_USB1_PWR_FAULT_PIN_EN - #define RTE_USB1_PWR_FAULT_PIN_EN 1 -#endif -// USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4 -// USB1 port indicator LED control output 0 -#define RTE_USB1_IND0_ID 1 -#if (RTE_USB1_IND0_ID == 0) - #define RTE_USB1_IND0_PIN_EN 0 -#elif (RTE_USB1_IND0_ID == 1) - #define RTE_USB1_IND0_PORT 3 - #define RTE_USB1_IND0_BIT 2 - #define RTE_USB1_IND0_FUNC 3 -#elif (RTE_USB1_IND0_ID == 2) - #define RTE_USB1_IND0_PORT 9 - #define RTE_USB1_IND0_BIT 4 - #define RTE_USB1_IND0_FUNC 2 -#else - #error "Invalid RTE_USB1_IND0 Pin Configuration!" -#endif -#ifndef RTE_USB1_IND0_PIN_EN - #define RTE_USB1_IND0_PIN_EN 1 -#endif -// USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3 -// USB1 port indicator LED control output 1 -#define RTE_USB1_IND1_ID 1 -#if (RTE_USB1_IND1_ID == 0) - #define RTE_USB1_IND1_PIN_EN 0 -#elif (RTE_USB1_IND1_ID == 1) - #define RTE_USB1_IND1_PORT 3 - #define RTE_USB1_IND1_BIT 1 - #define RTE_USB1_IND1_FUNC 3 -#elif (RTE_USB1_IND1_ID == 2) - #define RTE_USB1_IND1_PORT 9 - #define RTE_USB1_IND1_BIT 3 - #define RTE_USB1_IND1_FUNC 2 -#else - #error "Invalid RTE_USB1_IND1 Pin Configuration!" -#endif -#ifndef RTE_USB1_IND1_PIN_EN - #define RTE_USB1_IND1_PIN_EN 1 -#endif - -// On-chip full-speed PHY -#define RTE_USB_USB1_FS_PHY_EN 1 - -// USB1_VBUS (Device) <0=>Not used <1=>P2_5 -// Monitors the presence of USB1 bus power. -#define RTE_USB1_VBUS_ID 1 -#if (RTE_USB1_VBUS_ID == 0) - #define RTE_USB1_VBUS_PIN_EN 0 -#elif (RTE_USB1_VBUS_ID == 1) - #define RTE_USB1_VBUS_PORT 2 - #define RTE_USB1_VBUS_BIT 5 - #define RTE_USB1_VBUS_FUNC 2 -#else - #error "Invalid RTE_USB1_VBUS Pin Configuration!" -#endif -#ifndef RTE_USB1_VBUS_PIN_EN - #define RTE_USB1_VBUS_PIN_EN 1 -#endif -// On-chip full-speed PHY - -// External high-speed ULPI PHY (UTMI+ Low Pin Interface) -#define RTE_USB_USB1_HS_PHY_EN 0 - -// USB1_ULPI_CLK <0=>P8_8 <1=>PC_0 -// USB1 ULPI link CLK signal. -// 60 MHz clock generated by the PHY. -#define RTE_USB1_ULPI_CLK_ID 0 -#if (RTE_USB1_ULPI_CLK_ID == 0) - #define RTE_USB1_ULPI_CLK_PORT 8 - #define RTE_USB1_ULPI_CLK_BIT 8 - #define RTE_USB1_ULPI_CLK_FUNC 1 -#elif (RTE_USB1_ULPI_CLK_ID == 1) - #define RTE_USB1_ULPI_CLK_PORT 0xC - #define RTE_USB1_ULPI_CLK_BIT 0 - #define RTE_USB1_ULPI_CLK_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!" -#endif -// USB1_ULPI_DIR <0=>PB_1 <1=>PC_11 -// USB1 ULPI link DIR signal. -// Controls the ULPI data line direction. -#define RTE_USB1_ULPI_DIR_ID 0 -#if (RTE_USB1_ULPI_DIR_ID == 0) - #define RTE_USB1_ULPI_DIR_PORT 0xB - #define RTE_USB1_ULPI_DIR_BIT 1 - #define RTE_USB1_ULPI_DIR_FUNC 1 -#elif (RTE_USB1_ULPI_DIR_ID == 1) - #define RTE_USB1_ULPI_DIR_PORT 0xC - #define RTE_USB1_ULPI_DIR_BIT 11 - #define RTE_USB1_ULPI_DIR_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!" -#endif -// USB1_ULPI_STP <0=>P8_7 <1=>PC_10 -// USB1 ULPI link STP signal. -// Asserted to end or interrupt transfers to the PHY. -#define RTE_USB1_ULPI_STP_ID 0 -#if (RTE_USB1_ULPI_STP_ID == 0) - #define RTE_USB1_ULPI_STP_PORT 8 - #define RTE_USB1_ULPI_STP_BIT 7 - #define RTE_USB1_ULPI_STP_FUNC 1 -#elif (RTE_USB1_ULPI_STP_ID == 1) - #define RTE_USB1_ULPI_STP_PORT 0xC - #define RTE_USB1_ULPI_STP_BIT 10 - #define RTE_USB1_ULPI_STP_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!" -#endif -// USB1_ULPI_NXT <0=>P8_6 <1=>PC_9 -// USB1 ULPI link NXT signal. -// Data flow control signal from the PHY. -#define RTE_USB1_ULPI_NXT_ID 0 -#if (RTE_USB1_ULPI_NXT_ID == 0) - #define RTE_USB1_ULPI_NXT_PORT 8 - #define RTE_USB1_ULPI_NXT_BIT 6 - #define RTE_USB1_ULPI_NXT_FUNC 1 -#elif (RTE_USB1_ULPI_NXT_ID == 1) - #define RTE_USB1_ULPI_NXT_PORT 0xC - #define RTE_USB1_ULPI_NXT_BIT 9 - #define RTE_USB1_ULPI_NXT_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!" -#endif -// USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11 -// USB1 ULPI link bidirectional data line 0. -#define RTE_USB1_ULPI_D0_ID 0 -#if (RTE_USB1_ULPI_D0_ID == 0) - #define RTE_USB1_ULPI_D0_PORT 8 - #define RTE_USB1_ULPI_D0_BIT 5 - #define RTE_USB1_ULPI_D0_FUNC 1 -#elif (RTE_USB1_ULPI_D0_ID == 1) - #define RTE_USB1_ULPI_D0_PORT 0xC - #define RTE_USB1_ULPI_D0_BIT 8 - #define RTE_USB1_ULPI_D0_FUNC 1 -#elif (RTE_USB1_ULPI_D0_ID == 2) - #define RTE_USB1_ULPI_D0_PORT 0xD - #define RTE_USB1_ULPI_D0_BIT 11 - #define RTE_USB1_ULPI_D0_FUNC 5 -#else - #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!" -#endif -// USB1_ULPI_D1 <0=>P8_4 <1=>PC_7 -// USB1 ULPI link bidirectional data line 1. -#define RTE_USB1_ULPI_D1_ID 0 -#if (RTE_USB1_ULPI_D1_ID == 0) - #define RTE_USB1_ULPI_D1_PORT 8 - #define RTE_USB1_ULPI_D1_BIT 4 - #define RTE_USB1_ULPI_D1_FUNC 1 -#elif (RTE_USB1_ULPI_D1_ID == 1) - #define RTE_USB1_ULPI_D1_PORT 0xC - #define RTE_USB1_ULPI_D1_BIT 7 - #define RTE_USB1_ULPI_D1_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!" -#endif -// USB1_ULPI_D2 <0=>P8_3 <1=>PC_6 -// USB1 ULPI link bidirectional data line 2. -#define RTE_USB1_ULPI_D2_ID 0 -#if (RTE_USB1_ULPI_D2_ID == 0) - #define RTE_USB1_ULPI_D2_PORT 8 - #define RTE_USB1_ULPI_D2_BIT 3 - #define RTE_USB1_ULPI_D2_FUNC 1 -#elif (RTE_USB1_ULPI_D2_ID == 1) - #define RTE_USB1_ULPI_D2_PORT 0xC - #define RTE_USB1_ULPI_D2_BIT 6 - #define RTE_USB1_ULPI_D2_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!" -#endif -// USB1_ULPI_D3 <0=>PB_6 <1=>PC_5 -// USB1 ULPI link bidirectional data line 3. -#define RTE_USB1_ULPI_D3_ID 0 -#if (RTE_USB1_ULPI_D3_ID == 0) - #define RTE_USB1_ULPI_D3_PORT 0xB - #define RTE_USB1_ULPI_D3_BIT 6 - #define RTE_USB1_ULPI_D3_FUNC 1 -#elif (RTE_USB1_ULPI_D3_ID == 1) - #define RTE_USB1_ULPI_D3_PORT 0xC - #define RTE_USB1_ULPI_D3_BIT 5 - #define RTE_USB1_ULPI_D3_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!" -#endif -// USB1_ULPI_D4 <0=>PB_5 <1=>PC_4 -// USB1 ULPI link bidirectional data line 4. -#define RTE_USB1_ULPI_D4_ID 0 -#if (RTE_USB1_ULPI_D4_ID == 0) - #define RTE_USB1_ULPI_D4_PORT 0xB - #define RTE_USB1_ULPI_D4_BIT 5 - #define RTE_USB1_ULPI_D4_FUNC 1 -#elif (RTE_USB1_ULPI_D4_ID == 1) - #define RTE_USB1_ULPI_D4_PORT 0xC - #define RTE_USB1_ULPI_D4_BIT 4 - #define RTE_USB1_ULPI_D4_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!" -#endif -// USB1_ULPI_D5 <0=>PB_4 <1=>PC_3 -// USB1 ULPI link bidirectional data line 5. -#define RTE_USB1_ULPI_D5_ID 0 -#if (RTE_USB1_ULPI_D5_ID == 0) - #define RTE_USB1_ULPI_D5_PORT 0xB - #define RTE_USB1_ULPI_D5_BIT 4 - #define RTE_USB1_ULPI_D5_FUNC 1 -#elif (RTE_USB1_ULPI_D5_ID == 1) - #define RTE_USB1_ULPI_D5_PORT 0xC - #define RTE_USB1_ULPI_D5_BIT 3 - #define RTE_USB1_ULPI_D5_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!" -#endif -// USB1_ULPI_D6 <0=>PB_3 <1=>PC_2 -// USB1 ULPI link bidirectional data line 6. -#define RTE_USB1_ULPI_D6_ID 0 -#if (RTE_USB1_ULPI_D6_ID == 0) - #define RTE_USB1_ULPI_D6_PORT 0xB - #define RTE_USB1_ULPI_D6_BIT 3 - #define RTE_USB1_ULPI_D6_FUNC 1 -#elif (RTE_USB1_ULPI_D6_ID == 1) - #define RTE_USB1_ULPI_D6_PORT 0xC - #define RTE_USB1_ULPI_D6_BIT 2 - #define RTE_USB1_ULPI_D6_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!" -#endif -// USB1_ULPI_D7 <0=>PB_2 <1=>PC_1 -// USB1 ULPI link bidirectional data line 7. -#define RTE_USB1_ULPI_D7_ID 0 -#if (RTE_USB1_ULPI_D7_ID == 0) - #define RTE_USB1_ULPI_D7_PORT 0xB - #define RTE_USB1_ULPI_D7_BIT 2 - #define RTE_USB1_ULPI_D7_FUNC 1 -#elif (RTE_USB1_ULPI_D7_ID == 1) - #define RTE_USB1_ULPI_D7_PORT 0xC - #define RTE_USB1_ULPI_D7_BIT 1 - #define RTE_USB1_ULPI_D7_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!" -#endif -// External high-speed ULPI PHY (UTMI+ Low Pin Interface) -// Pin Configuration -// USB1 Controller [Driver_USBD1 and Driver_USBH1] - -// ENET (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ENET 0 - -// MII (Media Independent Interface) -#define RTE_ENET_MII 0 - -// ENET_TXD0 Pin <0=>P1_18 -#define RTE_ENET_MII_TXD0_PORT_ID 0 -#if (RTE_ENET_MII_TXD0_PORT_ID == 0) - #define RTE_ENET_MII_TXD0_PORT 1 - #define RTE_ENET_MII_TXD0_PIN 18 - #define RTE_ENET_MII_TXD0_FUNC 3 -#else - #error "Invalid ENET_TXD0 Pin Configuration!" -#endif -// ENET_TXD1 Pin <0=>P1_20 -#define RTE_ENET_MII_TXD1_PORT_ID 0 -#if (RTE_ENET_MII_TXD1_PORT_ID == 0) - #define RTE_ENET_MII_TXD1_PORT 1 - #define RTE_ENET_MII_TXD1_PIN 20 - #define RTE_ENET_MII_TXD1_FUNC 3 -#else - #error "Invalid ENET_TXD1 Pin Configuration!" -#endif -// ENET_TXD2 Pin <0=>P9_4 <1=>PC_2 -#define RTE_ENET_MII_TXD2_PORT_ID 0 -#if (RTE_ENET_MII_TXD2_PORT_ID == 0) - #define RTE_ENET_MII_TXD2_PORT 9 - #define RTE_ENET_MII_TXD2_PIN 4 - #define RTE_ENET_MII_TXD2_FUNC 5 -#elif (RTE_ENET_MII_TXD2_PORT_ID == 1) - #define RTE_ENET_MII_TXD2_PORT 0xC - #define RTE_ENET_MII_TXD2_PIN 2 - #define RTE_ENET_MII_TXD2_FUNC 3 -#else - #error "Invalid ENET_TXD2 Pin Configuration!" -#endif -// ENET_TXD3 Pin <0=>P9_5 <1=>PC_3 -#define RTE_ENET_MII_TXD3_PORT_ID 0 -#if (RTE_ENET_MII_TXD3_PORT_ID == 0) - #define RTE_ENET_MII_TXD3_PORT 9 - #define RTE_ENET_MII_TXD3_PIN 5 - #define RTE_ENET_MII_TXD3_FUNC 5 -#elif (RTE_ENET_MII_TXD3_PORT_ID == 1) - #define RTE_ENET_MII_TXD3_PORT 0xC - #define RTE_ENET_MII_TXD3_PIN 3 - #define RTE_ENET_MII_TXD3_FUNC 3 -#else - #error "Invalid ENET_TXD3 Pin Configuration!" -#endif -// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 -#define RTE_ENET_MII_TX_EN_PORT_ID 0 -#if (RTE_ENET_MII_TX_EN_PORT_ID == 0) - #define RTE_ENET_MII_TX_EN_PORT 0 - #define RTE_ENET_MII_TX_EN_PIN 1 - #define RTE_ENET_MII_TX_EN_FUNC 6 -#elif (RTE_ENET_MII_TX_EN_PORT_ID == 1) - #define RTE_ENET_MII_TX_EN_PORT 0xC - #define RTE_ENET_MII_TX_EN_PIN 4 - #define RTE_ENET_MII_TX_EN_FUNC 3 -#else - #error "Invalid ENET_TX_EN Pin Configuration!" -#endif -// ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0 -#define RTE_ENET_MII_TX_CLK_PORT_ID 0 -#if (RTE_ENET_MII_TX_CLK_PORT_ID == 0) - #define RTE_ENET_MII_TX_CLK_PORT 1 - #define RTE_ENET_MII_TX_CLK_PIN 19 - #define RTE_ENET_MII_TX_CLK_FUNC 0 -#elif (RTE_ENET_MII_TX_CLK_PORT_ID == 1) - #define RTE_ENET_MII_TX_CLK_PORT 0x10 - #define RTE_ENET_MII_TX_CLK_PIN 0 - #define RTE_ENET_MII_TX_CLK_FUNC 7 -#else - #error "Invalid ENET_TX_CLK Pin Configuration!" -#endif -// ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14 -// Optional signal, rarely used -#define RTE_ENET_MII_TX_ER_PORT_ID 0 -#if (RTE_ENET_MII_TX_ER_PORT_ID == 0) - #define RTE_ENET_MII_TX_ER_PIN_EN 0 -#elif (RTE_ENET_MII_TX_ER_PORT_ID == 1) - #define RTE_ENET_MII_TX_ER_PORT 0xC - #define RTE_ENET_MII_TX_ER_PIN 5 - #define RTE_ENET_MII_TX_ER_FUNC 3 -#elif (RTE_ENET_MII_TX_ER_PORT_ID == 2) - #define RTE_ENET_MII_TX_ER_PORT 0xC - #define RTE_ENET_MII_TX_ER_PIN 14 - #define RTE_ENET_MII_TX_ER_FUNC 6 -#else - #error "Invalid ENET_TX_ER Pin Configuration!" -#endif -#ifndef RTE_ENET_MII_TX_ER_PIN_EN - #define RTE_ENET_MII_TX_ER_PIN_EN 1 -#endif -// ENET_RXD0 Pin <0=>P1_15 -#define RTE_ENET_MII_RXD0_PORT_ID 0 -#if (RTE_ENET_MII_RXD0_PORT_ID == 0) - #define RTE_ENET_MII_RXD0_PORT 1 - #define RTE_ENET_MII_RXD0_PIN 15 - #define RTE_ENET_MII_RXD0_FUNC 3 -#else - #error "Invalid ENET_RXD0 Pin Configuration!" -#endif -// ENET_RXD1 Pin <0=>P0_0 -#define RTE_ENET_MII_RXD1_PORT_ID 0 -#if (RTE_ENET_MII_RXD1_PORT_ID == 0) - #define RTE_ENET_MII_RXD1_PORT 0 - #define RTE_ENET_MII_RXD1_PIN 0 - #define RTE_ENET_MII_RXD1_FUNC 2 -#else - #error "Invalid ENET_RXD1 Pin Configuration!" -#endif -// ENET_RXD2 Pin <0=>P9_3 <1=>PC_6 -#define RTE_ENET_MII_RXD2_PORT_ID 0 -#if (RTE_ENET_MII_RXD2_PORT_ID == 0) - #define RTE_ENET_MII_RXD2_PORT 9 - #define RTE_ENET_MII_RXD2_PIN 3 - #define RTE_ENET_MII_RXD2_FUNC 5 -#elif (RTE_ENET_MII_RXD2_PORT_ID == 1) - #define RTE_ENET_MII_RXD2_PORT 0xC - #define RTE_ENET_MII_RXD2_PIN 6 - #define RTE_ENET_MII_RXD2_FUNC 3 -#else - #error "Invalid ENET_RXD2 Pin Configuration!" -#endif -// ENET_RXD3 Pin <0=>P9_2 <1=>PC_7 -#define RTE_ENET_MII_RXD3_PORT_ID 0 -#if (RTE_ENET_MII_RXD3_PORT_ID == 0) - #define RTE_ENET_MII_RXD3_PORT 9 - #define RTE_ENET_MII_RXD3_PIN 2 - #define RTE_ENET_MII_RXD3_FUNC 5 -#elif (RTE_ENET_MII_RXD3_PORT_ID == 1) - #define RTE_ENET_MII_RXD3_PORT 0xC - #define RTE_ENET_MII_RXD3_PIN 7 - #define RTE_ENET_MII_RXD3_FUNC 3 -#else - #error "Invalid ENET_RXD3 Pin Configuration!" -#endif -// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 -#define RTE_ENET_MII_RX_DV_PORT_ID 0 -#if (RTE_ENET_MII_RX_DV_PORT_ID == 0) - #define RTE_ENET_MII_RX_DV_PORT 1 - #define RTE_ENET_MII_RX_DV_PIN 16 - #define RTE_ENET_MII_RX_DV_FUNC 7 -#elif (RTE_ENET_MII_RX_DV_PORT_ID == 1) - #define RTE_ENET_MII_RX_DV_PORT 0xC - #define RTE_ENET_MII_RX_DV_PIN 8 - #define RTE_ENET_MII_RX_DV_FUNC 3 -#else - #error "Invalid ENET_RX_DV Pin Configuration!" -#endif -// ENET_RX_CLK Pin <0=>PC_0 -#define RTE_ENET_MII_RX_CLK_PORT_ID 0 -#if (RTE_ENET_MII_RX_CLK_PORT_ID == 0) - #define RTE_ENET_MII_RX_CLK_PORT 0xC - #define RTE_ENET_MII_RX_CLK_PIN 0 - #define RTE_ENET_MII_RX_CLK_FUNC 3 -#else - #error "Invalid ENET_RX_CLK Pin Configuration!" -#endif -// ENET_RX_ER Pin <0=>P9_1 <1=>PC_9 -#define RTE_ENET_MII_RX_ER_PORT_ID 0 -#if (RTE_ENET_MII_RX_ER_PORT_ID == 0) - #define RTE_ENET_MII_RX_ER_PORT 9 - #define RTE_ENET_MII_RX_ER_PIN 1 - #define RTE_ENET_MII_RX_ER_FUNC 5 -#elif (RTE_ENET_MII_RX_ER_PORT_ID == 1) - #define RTE_ENET_MII_RX_ER_PORT 0xC - #define RTE_ENET_MII_RX_ER_PIN 9 - #define RTE_ENET_MII_RX_ER_FUNC 3 -#else - #error "Invalid ENET_RX_ER Pin Configuration!" -#endif -// ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6 -#define RTE_ENET_MII_COL_PORT_ID 0 -#if (RTE_ENET_MII_COL_PORT_ID == 0) - #define RTE_ENET_MII_COL_PORT 0 - #define RTE_ENET_MII_COL_PIN 1 - #define RTE_ENET_MII_COL_FUNC 2 -#elif (RTE_ENET_MII_COL_PORT_ID == 1) - #define RTE_ENET_MII_COL_PORT 4 - #define RTE_ENET_MII_COL_PIN 1 - #define RTE_ENET_MII_COL_FUNC 7 -#elif (RTE_ENET_MII_COL_PORT_ID == 2) - #define RTE_ENET_MII_COL_PORT 9 - #define RTE_ENET_MII_COL_PIN 6 - #define RTE_ENET_MII_COL_FUNC 5 -#else - #error "Invalid ENET_COL Pin Configuration!" -#endif -// ENET_CRS Pin <0=>P1_16 <1=>P9_0 -#define RTE_ENET_MII_CRS_PORT_ID 0 -#if (RTE_ENET_MII_CRS_PORT_ID == 0) - #define RTE_ENET_MII_CRS_PORT 1 - #define RTE_ENET_MII_CRS_PIN 16 - #define RTE_ENET_MII_CRS_FUNC 3 -#elif (RTE_ENET_MII_CRS_PORT_ID == 1) - #define RTE_ENET_MII_CRS_PORT 9 - #define RTE_ENET_MII_CRS_PIN 0 - #define RTE_ENET_MII_CRS_FUNC 5 -#else - #error "Invalid ENET_CRS Pin Configuration!" -#endif -// MII (Media Independent Interface) - -// RMII (Reduced Media Independent Interface) -#define RTE_ENET_RMII 0 - -// ENET_TXD0 Pin <0=>P1_18 -#define RTE_ENET_RMII_TXD0_PORT_ID 0 -#if (RTE_ENET_RMII_TXD0_PORT_ID == 0) - #define RTE_ENET_RMII_TXD0_PORT 1 - #define RTE_ENET_RMII_TXD0_PIN 18 - #define RTE_ENET_RMII_TXD0_FUNC 3 -#else - #error "Invalid ENET_TXD0 Pin Configuration!" -#endif -// ENET_TXD1 Pin <0=>P1_20 -#define RTE_ENET_RMII_TXD1_PORT_ID 0 -#if (RTE_ENET_RMII_TXD1_PORT_ID == 0) - #define RTE_ENET_RMII_TXD1_PORT 1 - #define RTE_ENET_RMII_TXD1_PIN 20 - #define RTE_ENET_RMII_TXD1_FUNC 3 -#else - #error "Invalid ENET_TXD1 Pin Configuration!" -#endif -// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 -#define RTE_ENET_RMII_TX_EN_PORT_ID 0 -#if (RTE_ENET_RMII_TX_EN_PORT_ID == 0) - #define RTE_ENET_RMII_TX_EN_PORT 0 - #define RTE_ENET_RMII_TX_EN_PIN 1 - #define RTE_ENET_RMII_TX_EN_FUNC 6 -#elif (RTE_ENET_RMII_TX_EN_PORT_ID == 1) - #define RTE_ENET_RMII_TX_EN_PORT 0xC - #define RTE_ENET_RMII_TX_EN_PIN 4 - #define RTE_ENET_RMII_TX_EN_FUNC 3 -#else - #error "Invalid ENET_TX_EN Pin Configuration!" -#endif -// ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0 -#define RTE_ENET_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0) - #define RTE_ENET_RMII_REF_CLK_PORT 1 - #define RTE_ENET_RMII_REF_CLK_PIN 19 - #define RTE_ENET_RMII_REF_CLK_FUNC 0 -#elif (RTE_ENET_RMII_REF_CLK_PORT_ID == 1) - #define RTE_ENET_RMII_REF_CLK_PORT 0x10 - #define RTE_ENET_RMII_REF_CLK_PIN 0 - #define RTE_ENET_RMII_REF_CLK_FUNC 7 -#else - #error "Invalid ENET_REF_CLK Pin Configuration!" -#endif -// ENET_RXD0 Pin <0=>P1_15 -#define RTE_ENET_RMII_RXD0_PORT_ID 0 -#if (RTE_ENET_RMII_RXD0_PORT_ID == 0) - #define RTE_ENET_RMII_RXD0_PORT 1 - #define RTE_ENET_RMII_RXD0_PIN 15 - #define RTE_ENET_RMII_RXD0_FUNC 3 -#else - #error "Invalid ENET_RXD0 Pin Configuration!" -#endif -// ENET_RXD1 Pin <0=>P0_0 -#define RTE_ENET_RMII_RXD1_PORT_ID 0 -#if (RTE_ENET_RMII_RXD1_PORT_ID == 0) - #define RTE_ENET_RMII_RXD1_PORT 0 - #define RTE_ENET_RMII_RXD1_PIN 0 - #define RTE_ENET_RMII_RXD1_FUNC 2 -#else - #error "Invalid ENET_RXD1 Pin Configuration!" -#endif -// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 -#define RTE_ENET_RMII_RX_DV_PORT_ID 0 -#if (RTE_ENET_RMII_RX_DV_PORT_ID == 0) - #define RTE_ENET_RMII_RX_DV_PORT 1 - #define RTE_ENET_RMII_RX_DV_PIN 16 - #define RTE_ENET_RMII_RX_DV_FUNC 7 -#elif (RTE_ENET_RMII_RX_DV_PORT_ID == 1) - #define RTE_ENET_RMII_RX_DV_PORT 0xC - #define RTE_ENET_RMII_RX_DV_PIN 8 - #define RTE_ENET_RMII_RX_DV_FUNC 3 -#else - #error "Invalid ENET_RX_DV Pin Configuration!" -#endif -// RMII (Reduced Media Independent Interface) - -// MIIM (Management Data Interface) -// ENET_MDIO Pin <0=>P1_17 -#define RTE_ENET_MDI_MDIO_PORT_ID 0 -#if (RTE_ENET_MDI_MDIO_PORT_ID == 0) - #define RTE_ENET_MDI_MDIO_PORT 1 - #define RTE_ENET_MDI_MDIO_PIN 17 - #define RTE_ENET_MDI_MDIO_FUNC 3 -#else - #error "Invalid ENET_MDIO Pin Configuration!" -#endif -// ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1 -#define RTE_ENET_MDI_MDC_PORT_ID 2 -#if (RTE_ENET_MDI_MDC_PORT_ID == 0) - #define RTE_ENET_MDI_MDC_PORT 2 - #define RTE_ENET_MDI_MDC_PIN 0 - #define RTE_ENET_MDI_MDC_FUNC 7 -#elif (RTE_ENET_MDI_MDC_PORT_ID == 1) - #define RTE_ENET_MDI_MDC_PORT 7 - #define RTE_ENET_MDI_MDC_PIN 7 - #define RTE_ENET_MDI_MDC_FUNC 6 -#elif (RTE_ENET_MDI_MDC_PORT_ID == 2) - #define RTE_ENET_MDI_MDC_PORT 0xC - #define RTE_ENET_MDI_MDC_PIN 1 - #define RTE_ENET_MDI_MDC_FUNC 3 -#else - #error "Invalid ENET_MDC Pin Configuration!" -#endif -// MIIM (Management Data Interface) -// ENET (Ethernet Interface) [Driver_ETH_MAC0] - -// SD/MMC Interface [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDMMC 0 - -// SD/MMC Peripheral Bus -// SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2 -#define RTE_SD_CLK_PORT_ID 0 -#if (RTE_SD_CLK_PORT_ID == 0) - #define RTE_SD_CLK_PORT 0xC - #define RTE_SD_CLK_PIN 0 - #define RTE_SD_CLK_FUNC 7 -#elif (RTE_SD_CLK_PORT_ID == 1) - #define RTE_SD_CLK_PORT 0x10 - #define RTE_SD_CLK_PIN 0 - #define RTE_SD_CLK_FUNC 4 -#elif (RTE_SD_CLK_PORT_ID == 2) - #define RTE_SD_CLK_PORT 0x10 - #define RTE_SD_CLK_PIN 2 - #define RTE_SD_CLK_FUNC 4 -#else - #error "Invalid SD_CLK Pin Configuration!" -#endif -// SD_CMD Pin <0=>P1_6 <1=>PC_10 -#define RTE_SD_CMD_PORT_ID 0 -#if (RTE_SD_CMD_PORT_ID == 0) - #define RTE_SD_CMD_PORT 1 - #define RTE_SD_CMD_PIN 6 - #define RTE_SD_CMD_FUNC 7 -#elif (RTE_SD_CMD_PORT_ID == 1) - #define RTE_SD_CMD_PORT 0xC - #define RTE_SD_CMD_PIN 10 - #define RTE_SD_CMD_FUNC 7 -#else - #error "Invalid SD_CMD Pin Configuration!" -#endif -// SD_DAT0 Pin <0=>P1_9 <1=>PC_4 -#define RTE_SD_DAT0_PORT_ID 0 -#if (RTE_SD_DAT0_PORT_ID == 0) - #define RTE_SD_DAT0_PORT 1 - #define RTE_SD_DAT0_PIN 9 - #define RTE_SD_DAT0_FUNC 7 -#elif (RTE_SD_DAT0_PORT_ID == 1) - #define RTE_SD_DAT0_PORT 0xC - #define RTE_SD_DAT0_PIN 4 - #define RTE_SD_DAT0_FUNC 7 -#else - #error "Invalid SD_DAT0 Pin Configuration!" -#endif -// SD_DAT[1 .. 3] -#define RTE_SDMMC_BUS_WIDTH_4 0 -// SD_DAT1 Pin <0=>P1_10 <1=>PC_5 -#define RTE_SD_DAT1_PORT_ID 0 -#if (RTE_SD_DAT1_PORT_ID == 0) - #define RTE_SD_DAT1_PORT 1 - #define RTE_SD_DAT1_PIN 10 - #define RTE_SD_DAT1_FUNC 7 -#elif (RTE_SD_DAT1_PORT_ID == 1) - #define RTE_SD_DAT1_PORT 0xC - #define RTE_SD_DAT1_PIN 5 - #define RTE_SD_DAT1_FUNC 7 -#else - #error "Invalid SD_DAT1 Pin Configuration!" -#endif -// SD_DAT2 Pin <0=>P1_11 <1=>PC_6 -#define RTE_SD_DAT2_PORT_ID 0 -#if (RTE_SD_DAT2_PORT_ID == 0) - #define RTE_SD_DAT2_PORT 1 - #define RTE_SD_DAT2_PIN 11 - #define RTE_SD_DAT2_FUNC 7 -#elif (RTE_SD_DAT2_PORT_ID == 1) - #define RTE_SD_DAT2_PORT 0xC - #define RTE_SD_DAT2_PIN 6 - #define RTE_SD_DAT2_FUNC 7 -#else - #error "Invalid SD_DAT2 Pin Configuration!" -#endif -// SD_DAT3 Pin <0=>P1_12 <1=>PC_7 -#define RTE_SD_DAT3_PORT_ID 0 -#if (RTE_SD_DAT3_PORT_ID == 0) - #define RTE_SD_DAT3_PORT 1 - #define RTE_SD_DAT3_PIN 12 - #define RTE_SD_DAT3_FUNC 7 -#elif (RTE_SD_DAT3_PORT_ID == 1) - #define RTE_SD_DAT3_PORT 0xC - #define RTE_SD_DAT3_PIN 7 - #define RTE_SD_DAT3_FUNC 7 -#else - #error "Invalid SD_DAT3 Pin Configuration!" -#endif -// SD_DAT[1 .. 3] -// SD_DAT[4 .. 7] -#define RTE_SDMMC_BUS_WIDTH_8 0 -// SD_DAT4 Pin <0=>PC_11 -#define RTE_SD_DAT4_PORT_ID 0 -#if (RTE_SD_DAT4_PORT_ID == 0) - #define RTE_SD_DAT4_PORT 0xC - #define RTE_SD_DAT4_PIN 11 - #define RTE_SD_DAT4_FUNC 7 -#else - #error "Invalid SD_DAT4 Pin Configuration!" -#endif -// SD_DAT5 Pin <0=>PC_12 -#define RTE_SD_DAT5_PORT_ID 0 -#if (RTE_SD_DAT5_PORT_ID == 0) - #define RTE_SD_DAT5_PORT 0xC - #define RTE_SD_DAT5_PIN 12 - #define RTE_SD_DAT5_FUNC 7 -#else - #error "Invalid SD_DAT5 Pin Configuration!" -#endif -// SD_DAT6 Pin <0=>PC_13 -#define RTE_SD_DAT6_PORT_ID 0 -#if (RTE_SD_DAT6_PORT_ID == 0) - #define RTE_SD_DAT6_PORT 0xC - #define RTE_SD_DAT6_PIN 13 - #define RTE_SD_DAT6_FUNC 7 -#else - #error "Invalid SD_DAT6 Pin Configuration!" -#endif -// SD_DAT7 Pin <0=>PC_14 -#define RTE_SD_DAT7_PORT_ID 0 -#if (RTE_SD_DAT7_PORT_ID == 0) - #define RTE_SD_DAT7_PORT 0xC - #define RTE_SD_DAT7_PIN 14 - #define RTE_SD_DAT7_FUNC 7 -#else - #error "Invalid SD_DAT7 Pin Configuration!" -#endif -// SD_DAT[4 .. 7] -// SD/MMC Peripheral Bus - -// SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8 -// Configure Pin if exists -#define RTE_SD_CD_PORT_ID 0 -#if (RTE_SD_CD_PORT_ID == 0) - #define RTE_SD_CD_PIN_EN 0 -#elif (RTE_SD_CD_PORT_ID == 1) - #define RTE_SD_CD_PORT 1 - #define RTE_SD_CD_PIN 13 - #define RTE_SD_CD_FUNC 7 -#elif (RTE_SD_CD_PORT_ID == 2) - #define RTE_SD_CD_PORT 0xC - #define RTE_SD_CD_PIN 8 - #define RTE_SD_CD_FUNC 7 -#else - #error "Invalid SD_CD Pin Configuration!" -#endif -#ifndef RTE_SD_CD_PIN_EN - #define RTE_SD_CD_PIN_EN 1 -#endif -// SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10 -// Configure Pin if exists -#define RTE_SD_WP_PORT_ID 0 -#if (RTE_SD_WP_PORT_ID == 0) - #define RTE_SD_WP_PIN_EN 0 -#elif (RTE_SD_WP_PORT_ID == 1) - #define RTE_SD_WP_PORT 0xD - #define RTE_SD_WP_PIN 15 - #define RTE_SD_WP_FUNC 5 -#elif (RTE_SD_WP_PORT_ID == 2) - #define RTE_SD_WP_PORT 0xF - #define RTE_SD_WP_PIN 10 - #define RTE_SD_WP_FUNC 6 -#else - #error "Invalid SD_WP Pin Configuration!" -#endif -#ifndef RTE_SD_WP_PIN_EN - #define RTE_SD_WP_PIN_EN 1 -#endif -// SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1 -// Configure Pin if exists -#define RTE_SD_POW_PORT_ID 0 -#if (RTE_SD_POW_PORT_ID == 0) - #define RTE_SD_POW_PIN_EN 0 -#elif (RTE_SD_POW_PORT_ID == 1) - #define RTE_SD_POW_PORT 1 - #define RTE_SD_POW_PIN 5 - #define RTE_SD_POW_FUNC 7 -#elif (RTE_SD_POW_PORT_ID == 2) - #define RTE_SD_POW_PORT 0xC - #define RTE_SD_POW_PIN 9 - #define RTE_SD_POW_FUNC 7 -#elif (RTE_SD_POW_PORT_ID == 3) - #define RTE_SD_POW_PORT 0xD - #define RTE_SD_POW_PIN 1 - #define RTE_SD_POW_FUNC 5 -#else - #error "Invalid SD_POW Pin Configuration!" -#endif -#ifndef RTE_SD_POW_PIN_EN - #define RTE_SD_POW_PIN_EN 1 -#endif -// SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2 -// Configure Pin if exists -#define RTE_SD_RST_PORT_ID 0 -#if (RTE_SD_RST_PORT_ID == 0) - #define RTE_SD_RST_PIN_EN 0 -#elif (RTE_SD_RST_PORT_ID == 1) - #define RTE_SD_RST_PORT 1 - #define RTE_SD_RST_PIN 3 - #define RTE_SD_RST_FUNC 7 -#elif (RTE_SD_RST_PORT_ID == 2) - #define RTE_SD_RST_PORT 0xC - #define RTE_SD_RST_PIN 2 - #define RTE_SD_RST_FUNC 7 -#else - #error "Invalid SD_RST Pin Configuration!" -#endif -#ifndef RTE_SD_RST_PIN_EN - #define RTE_SD_RST_PIN_EN 1 -#endif -// SD/MMC Interface [Driver_MCI0] - -// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] -// Configuration settings for Driver_I2C0 in component ::Drivers:I2C -// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] -#define RTE_I2C0 0 - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>P2_4 <1=>PE_15 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) - #define RTE_I2C1_SCL_PORT 2 - #define RTE_I2C1_SCL_PIN 4 - #define RTE_I2C1_SCL_FUNC 1 -#elif (RTE_I2C1_SCL_PORT_ID == 1) - #define RTE_I2C1_SCL_PORT 0xE - #define RTE_I2C1_SCL_PIN 15 - #define RTE_I2C1_SCL_FUNC 2 -#else - #error "Invalid I2C1_SCL Pin Configuration!" -#endif -// I2C1_SDA Pin <0=>P2_3 <1=>PE_13 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) - #define RTE_I2C1_SDA_PORT 2 - #define RTE_I2C1_SDA_PIN 3 - #define RTE_I2C1_SDA_FUNC 1 -#elif (RTE_I2C1_SDA_PORT_ID == 1) - #define RTE_I2C1_SDA_PORT 0xE - #define RTE_I2C1_SDA_PIN 13 - #define RTE_I2C1_SDA_FUNC 2 -#else - #error "Invalid I2C1_SDA Pin Configuration!" -#endif -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -#define RTE_USART0 1 - -// Pin Configuration -// TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10 -// USART0 Serial Output pin -#define RTE_USART0_TX_ID 1 -#if (RTE_USART0_TX_ID == 0) - #define RTE_USART0_TX_PIN_EN 0 -#elif (RTE_USART0_TX_ID == 1) - #define RTE_USART0_TX_PORT 2 - #define RTE_USART0_TX_BIT 0 - #define RTE_USART0_TX_FUNC 1 -#elif (RTE_USART0_TX_ID == 2) - #define RTE_USART0_TX_PORT 6 - #define RTE_USART0_TX_BIT 4 - #define RTE_USART0_TX_FUNC 2 -#elif (RTE_USART0_TX_ID == 3) - #define RTE_USART0_TX_PORT 9 - #define RTE_USART0_TX_BIT 5 - #define RTE_USART0_TX_FUNC 7 -#elif (RTE_USART0_TX_ID == 4) - #define RTE_USART0_TX_PORT 0xF - #define RTE_USART0_TX_BIT 10 - #define RTE_USART0_TX_FUNC 1 -#else - #error "Invalid USART0_TX Pin Configuration!" -#endif -#ifndef RTE_USART0_TX_PIN_EN - #define RTE_USART0_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11 -// USART0 Serial Input pin -#define RTE_USART0_RX_ID 1 -#if (RTE_USART0_RX_ID == 0) - #define RTE_USART0_RX_PIN_EN 0 -#elif (RTE_USART0_RX_ID == 1) - #define RTE_USART0_RX_PORT 2 - #define RTE_USART0_RX_BIT 1 - #define RTE_USART0_RX_FUNC 1 -#elif (RTE_USART0_RX_ID == 2) - #define RTE_USART0_RX_PORT 6 - #define RTE_USART0_RX_BIT 5 - #define RTE_USART0_RX_FUNC 2 -#elif (RTE_USART0_RX_ID == 3) - #define RTE_USART0_RX_PORT 9 - #define RTE_USART0_RX_BIT 6 - #define RTE_USART0_RX_FUNC 7 -#elif (RTE_USART0_RX_ID == 4) - #define RTE_USART0_RX_PORT 0xF - #define RTE_USART0_RX_BIT 11 - #define RTE_USART0_RX_FUNC 1 -#else - #error "Invalid USART0_RX Pin Configuration!" -#endif -#ifndef RTE_USART0_RX_PIN_EN - #define RTE_USART0_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8 -// USART0 Serial Clock input/output synchronous mode -#define RTE_USART0_UCLK_ID 0 -#if (RTE_USART0_UCLK_ID == 0) - #define RTE_USART0_UCLK_PIN_EN 0 -#elif (RTE_USART0_UCLK_ID == 1) - #define RTE_USART0_UCLK_PORT 2 - #define RTE_USART0_UCLK_BIT 2 - #define RTE_USART0_UCLK_FUNC 1 -#elif (RTE_USART0_UCLK_ID == 2) - #define RTE_USART0_UCLK_PORT 6 - #define RTE_USART0_UCLK_BIT 1 - #define RTE_USART0_UCLK_FUNC 2 -#elif (RTE_USART0_UCLK_ID == 3) - #define RTE_USART0_UCLK_PORT 0xF - #define RTE_USART0_UCLK_BIT 8 - #define RTE_USART0_UCLK_FUNC 1 -#else - #error "Invalid USART0_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART0_UCLK_PIN_EN - #define RTE_USART0_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>1 (DMAMUXPER1) <1=>11 (DMAMUXPER11) -// -#define RTE_USART0_DMA_TX_EN 0 -#define RTE_USART0_DMA_TX_CH 0 -#define RTE_USART0_DMA_TX_PERI_ID 0 -#if (RTE_USART0_DMA_TX_PERI_ID == 0) - #define RTE_USART0_DMA_TX_PERI 1 - #define RTE_USART0_DMA_TX_PERI_SEL 1 -#elif (RTE_USART0_DMA_TX_PERI_ID == 1) - #define RTE_USART0_DMA_TX_PERI 11 - #define RTE_USART0_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>2 (DMAMUXPER2) <1=>12 (DMAMUXPER12) -// -#define RTE_USART0_DMA_RX_EN 0 -#define RTE_USART0_DMA_RX_CH 1 -#define RTE_USART0_DMA_RX_PERI_ID 0 -#if (RTE_USART0_DMA_RX_PERI_ID == 0) - #define RTE_USART0_DMA_RX_PERI 2 - #define RTE_USART0_DMA_RX_PERI_SEL 1 -#elif (RTE_USART0_DMA_RX_PERI_ID == 1) - #define RTE_USART0_DMA_RX_PERI 12 - #define RTE_USART0_DMA_RX_PERI_SEL 2 -#endif -// DMA -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] - -// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] -#define RTE_UART1 1 - -// Pin Configuration -// TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11 -// UART0 Serial Output pin -#define RTE_UART1_TX_ID 0 -#if (RTE_UART1_TX_ID == 0) - #define RTE_UART1_TX_PIN_EN 0 -#elif (RTE_UART1_TX_ID == 1) - #define RTE_UART1_TX_PORT 1 - #define RTE_UART1_TX_BIT 13 - #define RTE_UART1_TX_FUNC 1 -#elif (RTE_UART1_TX_ID == 2) - #define RTE_UART1_TX_PORT 3 - #define RTE_UART1_TX_BIT 4 - #define RTE_UART1_TX_FUNC 4 -#elif (RTE_UART1_TX_ID == 3) - #define RTE_UART1_TX_PORT 5 - #define RTE_UART1_TX_BIT 6 - #define RTE_UART1_TX_FUNC 4 -#elif (RTE_UART1_TX_ID == 4) - #define RTE_UART1_TX_PORT 0xC - #define RTE_UART1_TX_BIT 13 - #define RTE_UART1_TX_FUNC 2 -#elif (RTE_UART1_TX_ID == 5) - #define RTE_UART1_TX_PORT 0xE - #define RTE_UART1_TX_BIT 11 - #define RTE_UART1_TX_FUNC 2 -#else - #error "Invalid UART1_TX Pin Configuration!" -#endif -#ifndef RTE_UART1_TX_PIN_EN - #define RTE_UART1_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12 -// UART1 Serial Input pin -#define RTE_UART1_RX_ID 1 -#if (RTE_UART1_RX_ID == 0) - #define RTE_UART1_RX_PIN_EN 0 -#elif (RTE_UART1_RX_ID == 1) - #define RTE_UART1_RX_PORT 1 - #define RTE_UART1_RX_BIT 14 - #define RTE_UART1_RX_FUNC 1 -#elif (RTE_UART1_RX_ID == 2) - #define RTE_UART1_RX_PORT 3 - #define RTE_UART1_RX_BIT 5 - #define RTE_UART1_RX_FUNC 4 -#elif (RTE_UART1_RX_ID == 3) - #define RTE_UART1_RX_PORT 5 - #define RTE_UART1_RX_BIT 7 - #define RTE_UART1_RX_FUNC 4 -#elif (RTE_UART1_RX_ID == 4) - #define RTE_UART1_RX_PORT 0xC - #define RTE_UART1_RX_BIT 14 - #define RTE_UART1_RX_FUNC 2 -#elif (RTE_UART1_RX_ID == 5) - #define RTE_UART1_RX_PORT 0xE - #define RTE_UART1_RX_BIT 12 - #define RTE_UART1_RX_FUNC 2 -#else - #error "Invalid UART1_RX Pin Configuration!" -#endif -#ifndef RTE_UART1_RX_PIN_EN - #define RTE_UART1_RX_PIN_EN 1 -#endif - -// Modem Lines -// CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7 -#define RTE_UART1_CTS_ID 0 -#if (RTE_UART1_CTS_ID == 0) - #define RTE_UART1_CTS_PIN_EN 0 -#elif (RTE_UART1_CTS_ID == 1) - #define RTE_UART1_CTS_PORT 1 - #define RTE_UART1_CTS_BIT 11 - #define RTE_UART1_CTS_FUNC 1 -#elif (RTE_UART1_CTS_ID == 2) - #define RTE_UART1_CTS_PORT 5 - #define RTE_UART1_CTS_BIT 4 - #define RTE_UART1_CTS_FUNC 4 -#elif (RTE_UART1_CTS_ID == 3) - #define RTE_UART1_CTS_PORT 0xC - #define RTE_UART1_CTS_BIT 2 - #define RTE_UART1_CTS_FUNC 2 -#elif (RTE_UART1_CTS_ID == 4) - #define RTE_UART1_CTS_PORT 0xE - #define RTE_UART1_CTS_BIT 7 - #define RTE_UART1_CTS_FUNC 2 -#else - #error "Invalid UART1_CTS Pin Configuration!" -#endif -#ifndef RTE_UART1_CTS_PIN_EN - #define RTE_UART1_CTS_PIN_EN 1 -#endif -// RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5 -#define RTE_UART1_RTS_ID 0 -#if (RTE_UART1_RTS_ID == 0) - #define RTE_UART1_RTS_PIN_EN 0 -#elif (RTE_UART1_RTS_ID == 1) - #define RTE_UART1_RTS_PORT 1 - #define RTE_UART1_RTS_BIT 9 - #define RTE_UART1_RTS_FUNC 1 -#elif (RTE_UART1_RTS_ID == 2) - #define RTE_UART1_RTS_PORT 5 - #define RTE_UART1_RTS_BIT 2 - #define RTE_UART1_RTS_FUNC 4 -#elif (RTE_UART1_RTS_ID == 3) - #define RTE_UART1_RTS_PORT 0xC - #define RTE_UART1_RTS_BIT 3 - #define RTE_UART1_RTS_FUNC 2 -#elif (RTE_UART1_RTS_ID == 4) - #define RTE_UART1_RTS_PORT 0xE - #define RTE_UART1_RTS_BIT 5 - #define RTE_UART1_RTS_FUNC 2 -#else - #error "Invalid UART1_RTS Pin Configuration!" -#endif -#ifndef RTE_UART1_RTS_PIN_EN - #define RTE_UART1_RTS_PIN_EN 1 -#endif -// DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9 -#define RTE_UART1_DCD_ID 0 -#if (RTE_UART1_DCD_ID == 0) - #define RTE_UART1_DCD_PIN_EN 0 -#elif (RTE_UART1_DCD_ID == 1) - #define RTE_UART1_DCD_PORT 1 - #define RTE_UART1_DCD_BIT 12 - #define RTE_UART1_DCD_FUNC 1 -#elif (RTE_UART1_DCD_ID == 2) - #define RTE_UART1_DCD_PORT 5 - #define RTE_UART1_DCD_BIT 5 - #define RTE_UART1_DCD_FUNC 4 -#elif (RTE_UART1_DCD_ID == 3) - #define RTE_UART1_DCD_PORT 0xC - #define RTE_UART1_DCD_BIT 11 - #define RTE_UART1_DCD_FUNC 2 -#elif (RTE_UART1_DCD_ID == 4) - #define RTE_UART1_DCD_PORT 0xE - #define RTE_UART1_DCD_BIT 9 - #define RTE_UART1_DCD_FUNC 2 -#else - #error "Invalid UART1_DCD Pin Configuration!" -#endif -#ifndef RTE_UART1_DCD_PIN_EN - #define RTE_UART1_DCD_PIN_EN 1 -#endif -// DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8 -#define RTE_UART1_DSR_ID 0 -#if (RTE_UART1_DSR_ID == 0) - #define RTE_UART1_DSR_PIN_EN 0 -#elif (RTE_UART1_DSR_ID == 1) - #define RTE_UART1_DSR_PORT 1 - #define RTE_UART1_DSR_BIT 7 - #define RTE_UART1_DSR_FUNC 1 -#elif (RTE_UART1_DSR_ID == 2) - #define RTE_UART1_DSR_PORT 5 - #define RTE_UART1_DSR_BIT 0 - #define RTE_UART1_DSR_FUNC 4 -#elif (RTE_UART1_DSR_ID == 3) - #define RTE_UART1_DSR_PORT 0xC - #define RTE_UART1_DSR_BIT 10 - #define RTE_UART1_DSR_FUNC 2 -#elif (RTE_UART1_DSR_ID == 4) - #define RTE_UART1_DSR_PORT 0xE - #define RTE_UART1_DSR_BIT 8 - #define RTE_UART1_DSR_FUNC 2 -#else - #error "Invalid UART1_DSR Pin Configuration!" -#endif -#ifndef RTE_UART1_DSR_PIN_EN - #define RTE_UART1_DSR_PIN_EN 1 -#endif -// DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10 -#define RTE_UART1_DTR_ID 0 -#if (RTE_UART1_DTR_ID == 0) - #define RTE_UART1_DTR_PIN_EN 0 -#elif (RTE_UART1_DTR_ID == 1) - #define RTE_UART1_DTR_PORT 1 - #define RTE_UART1_DTR_BIT 8 - #define RTE_UART1_DTR_FUNC 1 -#elif (RTE_UART1_DTR_ID == 2) - #define RTE_UART1_DTR_PORT 5 - #define RTE_UART1_DTR_BIT 1 - #define RTE_UART1_DTR_FUNC 4 -#elif (RTE_UART1_DTR_ID == 3) - #define RTE_UART1_DTR_PORT 0xC - #define RTE_UART1_DTR_BIT 12 - #define RTE_UART1_DTR_FUNC 2 -#elif (RTE_UART1_DTR_ID == 4) - #define RTE_UART1_DTR_PORT 0xE - #define RTE_UART1_DTR_BIT 10 - #define RTE_UART1_DTR_FUNC 2 -#else - #error "Invalid UART1_DTR Pin Configuration!" -#endif -#ifndef RTE_UART1_DTR_PIN_EN - #define RTE_UART1_DTR_PIN_EN 1 -#endif -// RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6 -#define RTE_UART1_RI_ID 0 -#if (RTE_UART1_RI_ID == 0) - #define RTE_UART1_RI_PIN_EN 0 -#elif (RTE_UART1_RI_ID == 1) - #define RTE_UART1_RI_PORT 1 - #define RTE_UART1_RI_BIT 10 - #define RTE_UART1_RI_FUNC 1 -#elif (RTE_UART1_RI_ID == 2) - #define RTE_UART1_RI_PORT 5 - #define RTE_UART1_RI_BIT 3 - #define RTE_UART1_RI_FUNC 4 -#elif (RTE_UART1_RI_ID == 3) - #define RTE_UART1_RI_PORT 0xC - #define RTE_UART1_RI_BIT 1 - #define RTE_UART1_RI_FUNC 2 -#elif (RTE_UART1_RI_ID == 4) - #define RTE_UART1_RI_PORT 0xE - #define RTE_UART1_RI_BIT 6 - #define RTE_UART1_RI_FUNC 2 -#else - #error "Invalid UART1_RI Pin Configuration!" -#endif -#ifndef RTE_UART1_RI_PIN_EN - #define RTE_UART1_RI_PIN_EN 1 -#endif -// Modem Lines -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) -// -#define RTE_UART1_DMA_TX_EN 0 -#define RTE_UART1_DMA_TX_CH 0 -#define RTE_UART1_DMA_TX_PERI_ID 0 -#if (RTE_UART1_DMA_TX_PERI_ID == 0) - #define RTE_UART1_DMA_TX_PERI 3 - #define RTE_UART1_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) -// -#define RTE_UART1_DMA_RX_EN 1 -#define RTE_UART1_DMA_RX_CH 1 -#define RTE_UART1_DMA_RX_PERI_ID 0 -#if (RTE_UART1_DMA_RX_PERI_ID == 0) - #define RTE_UART1_DMA_RX_PERI 4 - #define RTE_UART1_DMA_RX_PERI_SEL 1 -#endif -// DMA -// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -#define RTE_USART2 0 - -// Pin Configuration -// TX <0=>Not used <1=>P1_15 <2=>P2_10 <3=>P7_1 <4=>PA_1 -// USART2 Serial Output pin -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) - #define RTE_USART2_TX_PIN_EN 0 -#elif (RTE_USART2_TX_ID == 1) - #define RTE_USART2_TX_PORT 1 - #define RTE_USART2_TX_BIT 15 - #define RTE_USART2_TX_FUNC 1 -#elif (RTE_USART2_TX_ID == 2) - #define RTE_USART2_TX_PORT 2 - #define RTE_USART2_TX_BIT 10 - #define RTE_USART2_TX_FUNC 2 -#elif (RTE_USART2_TX_ID == 3) - #define RTE_USART2_TX_PORT 7 - #define RTE_USART2_TX_BIT 1 - #define RTE_USART2_TX_FUNC 6 -#elif (RTE_USART2_TX_ID == 4) - #define RTE_USART2_TX_PORT 0xA - #define RTE_USART2_TX_BIT 1 - #define RTE_USART2_TX_FUNC 3 -#else - #error "Invalid USART2_TX Pin Configuration!" -#endif -#ifndef RTE_USART2_TX_PIN_EN - #define RTE_USART2_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P1_16 <2=>P2_11 <3=>P7_2 <4=>PA_2 -// USART2 Serial Input pin -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) - #define RTE_USART2_RX_PIN_EN 0 -#elif (RTE_USART2_RX_ID == 1) - #define RTE_USART2_RX_PORT 1 - #define RTE_USART2_RX_BIT 16 - #define RTE_USART2_RX_FUNC 1 -#elif (RTE_USART2_RX_ID == 2) - #define RTE_USART2_RX_PORT 2 - #define RTE_USART2_RX_BIT 11 - #define RTE_USART2_RX_FUNC 2 -#elif (RTE_USART2_RX_ID == 3) - #define RTE_USART2_RX_PORT 7 - #define RTE_USART2_RX_BIT 2 - #define RTE_USART2_RX_FUNC 6 -#elif (RTE_USART2_RX_ID == 4) - #define RTE_USART2_RX_PORT 0xA - #define RTE_USART2_RX_BIT 2 - #define RTE_USART2_RX_FUNC 3 -#else - #error "Invalid USART2_RX Pin Configuration!" -#endif -#ifndef RTE_USART2_RX_PIN_EN - #define RTE_USART2_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12 -// USART2 Serial Clock input/output synchronous mode -#define RTE_USART2_UCLK_ID 0 -#if (RTE_USART2_UCLK_ID == 0) - #define RTE_USART2_UCLK_PIN_EN 0 -#elif (RTE_USART2_UCLK_ID == 1) - #define RTE_USART2_UCLK_PORT 1 - #define RTE_USART2_UCLK_BIT 17 - #define RTE_USART2_UCLK_FUNC 1 -#elif (RTE_USART2_UCLK_ID == 2) - #define RTE_USART2_UCLK_PORT 2 - #define RTE_USART2_UCLK_BIT 12 - #define RTE_USART2_UCLK_FUNC 7 -#else - #error "Invalid USART2_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART2_UCLK_PIN_EN - #define RTE_USART2_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>5 (DMAMUXPER5) -// -#define RTE_USART2_DMA_TX_EN 0 -#define RTE_USART2_DMA_TX_CH 0 -#define RTE_USART2_DMA_TX_PERI_ID 0 -#if (RTE_USART2_DMA_TX_PERI_ID == 0) - #define RTE_USART2_DMA_TX_PERI 5 - #define RTE_USART2_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>6 (DMAMUXPER6) -// -#define RTE_USART2_DMA_RX_EN 0 -#define RTE_USART2_DMA_RX_CH 1 -#define RTE_USART2_DMA_RX_PERI_ID 0 -#if (RTE_USART2_DMA_RX_PERI_ID == 0) - #define RTE_USART2_DMA_RX_PERI 6 - #define RTE_USART2_DMA_RX_PERI_SEL 1 -#endif -// DMA -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -#define RTE_USART3 0 - -// Pin Configuration -// TX <0=>Not used <1=>P2_3 <2=>P4_1 <3=>P9_3 <4=>PF_2 -// USART3 Serial Output pin -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) - #define RTE_USART3_TX_PIN_EN 0 -#elif (RTE_USART3_TX_ID == 1) - #define RTE_USART3_TX_PORT 2 - #define RTE_USART3_TX_BIT 3 - #define RTE_USART3_TX_FUNC 2 -#elif (RTE_USART3_TX_ID == 2) - #define RTE_USART3_TX_PORT 4 - #define RTE_USART3_TX_BIT 1 - #define RTE_USART3_TX_FUNC 6 -#elif (RTE_USART3_TX_ID == 3) - #define RTE_USART3_TX_PORT 9 - #define RTE_USART3_TX_BIT 3 - #define RTE_USART3_TX_FUNC 7 -#elif (RTE_USART3_TX_ID == 4) - #define RTE_USART3_TX_PORT 0xF - #define RTE_USART3_TX_BIT 2 - #define RTE_USART3_TX_FUNC 1 -#else - #error "Invalid USART3_TX Pin Configuration!" -#endif -#ifndef RTE_USART3_TX_PIN_EN - #define RTE_USART3_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P2_4 <2=>P4_2 <3=>P9_4 <4=>PF_3 -// USART3 Serial Input pin -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) - #define RTE_USART3_RX_PIN_EN 0 -#elif (RTE_USART3_RX_ID == 1) - #define RTE_USART3_RX_PORT 2 - #define RTE_USART3_RX_BIT 4 - #define RTE_USART3_RX_FUNC 2 -#elif (RTE_USART3_RX_ID == 2) - #define RTE_USART3_RX_PORT 4 - #define RTE_USART3_RX_BIT 2 - #define RTE_USART3_RX_FUNC 6 -#elif (RTE_USART3_RX_ID == 3) - #define RTE_USART3_RX_PORT 9 - #define RTE_USART3_RX_BIT 4 - #define RTE_USART3_RX_FUNC 7 -#elif (RTE_USART3_RX_ID == 4) - #define RTE_USART3_RX_PORT 0xF - #define RTE_USART3_RX_BIT 3 - #define RTE_USART3_RX_FUNC 1 -#else - #error "Invalid USART3_RX Pin Configuration!" -#endif -#ifndef RTE_USART3_RX_PIN_EN - #define RTE_USART3_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5 -// USART3 Serial Clock input/output synchronous mode -#define RTE_USART3_UCLK_ID 0 -#if (RTE_USART3_UCLK_ID == 0) - #define RTE_USART3_UCLK_PIN_EN 0 -#elif (RTE_USART3_UCLK_ID == 1) - #define RTE_USART3_UCLK_PORT 2 - #define RTE_USART3_UCLK_BIT 7 - #define RTE_USART3_UCLK_FUNC 2 -#elif (RTE_USART3_UCLK_ID == 2) - #define RTE_USART3_UCLK_PORT 4 - #define RTE_USART3_UCLK_BIT 0 - #define RTE_USART3_UCLK_FUNC 6 -#elif (RTE_USART3_UCLK_ID == 3) - #define RTE_USART3_UCLK_PORT 0xF - #define RTE_USART3_UCLK_BIT 5 - #define RTE_USART3_UCLK_FUNC 1 -#else - #error "Invalid USART3_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART3_UCLK_PIN_EN - #define RTE_USART3_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>7 (DMAMUXPER7) <1=>14 (DMAMUXPER14) -// -#define RTE_USART3_DMA_TX_EN 0 -#define RTE_USART3_DMA_TX_CH 0 -#define RTE_USART3_DMA_TX_PERI_ID 0 -#if (RTE_USART3_DMA_TX_PERI_ID == 0) - #define RTE_USART3_DMA_TX_PERI 7 - #define RTE_USART3_DMA_TX_PERI_SEL 1 -#elif (RTE_USART3_DMA_TX_PERI_ID == 1) - #define RTE_USART3_DMA_TX_PERI 14 - #define RTE_USART3_DMA_TX_PERI_SEL 3 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>8 (DMAMUXPER8) <1=>13 (DMAMUXPER13) -// -#define RTE_USART3_DMA_RX_EN 0 -#define RTE_USART3_DMA_RX_CH 1 -#define RTE_USART3_DMA_RX_PERI_ID 0 -#if (RTE_USART3_DMA_RX_PERI_ID == 0) - #define RTE_USART3_DMA_RX_PERI 8 - #define RTE_USART3_DMA_RX_PERI_SEL 1 -#elif (RTE_USART3_DMA_RX_PERI_ID == 1) - #define RTE_USART3_DMA_RX_PERI 13 - #define RTE_USART3_DMA_RX_PERI_SEL 3 -#endif -// DMA -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] - -// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] -// Configuration settings for Driver_SPI0 in component ::Drivers:SPI -#define RTE_SSP0 0 - -// Pin Configuration -// SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1 -// Slave Select for SSP0 -#define RTE_SSP0_SSEL_PIN_SEL 1 -#if (RTE_SSP0_SSEL_PIN_SEL == 0) -#define RTE_SSP0_SSEL_PIN_EN 0 -#elif (RTE_SSP0_SSEL_PIN_SEL == 1) - #define RTE_SSP0_SSEL_PORT 1 - #define RTE_SSP0_SSEL_BIT 0 - #define RTE_SSP0_SSEL_FUNC 5 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 0 - #define RTE_SSP0_SSEL_GPIO_BIT 4 -#elif (RTE_SSP0_SSEL_PIN_SEL == 2) - #define RTE_SSP0_SSEL_PORT 3 - #define RTE_SSP0_SSEL_BIT 6 - #define RTE_SSP0_SSEL_FUNC 2 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 0 - #define RTE_SSP0_SSEL_GPIO_BIT 6 -#elif (RTE_SSP0_SSEL_PIN_SEL == 3) - #define RTE_SSP0_SSEL_PORT 3 - #define RTE_SSP0_SSEL_BIT 8 - #define RTE_SSP0_SSEL_FUNC 5 - #define RTE_SSP0_SSEL_GPIO_FUNC 4 - #define RTE_SSP0_SSEL_GPIO_PORT 5 - #define RTE_SSP0_SSEL_GPIO_BIT 11 -#elif (RTE_SSP0_SSEL_PIN_SEL == 4) - #define RTE_SSP0_SSEL_PORT 9 - #define RTE_SSP0_SSEL_BIT 0 - #define RTE_SSP0_SSEL_FUNC 7 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 4 - #define RTE_SSP0_SSEL_GPIO_BIT 12 -#elif (RTE_SSP0_SSEL_PIN_SEL == 5) - #define RTE_SSP0_SSEL_PORT 0xF - #define RTE_SSP0_SSEL_BIT 1 - #define RTE_SSP0_SSEL_FUNC 2 - #define RTE_SSP0_SSEL_GPIO_FUNC 4 - #define RTE_SSP0_SSEL_GPIO_PORT 7 - #define RTE_SSP0_SSEL_GPIO_BIT 16 -#else - #error "Invalid SSP0 SSP0_SSEL Pin Configuration!" -#endif -#ifndef RTE_SSP0_SSEL_PIN_EN -#define RTE_SSP0_SSEL_PIN_EN 1 -#endif -// SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0 -// Serial clock for SSP0 -#define RTE_SSP0_SCK_PIN_SEL 0 -#if (RTE_SSP0_SCK_PIN_SEL == 0) - #define RTE_SSP0_SCK_PORT 3 - #define RTE_SSP0_SCK_BIT 0 - #define RTE_SSP0_SCK_FUNC 4 -#elif (RTE_SSP0_SCK_PIN_SEL == 1) - #define RTE_SSP0_SCK_PORT 3 - #define RTE_SSP0_SCK_BIT 3 - #define RTE_SSP0_SCK_FUNC 2 -#elif (RTE_SSP0_SCK_PIN_SEL == 2) - #define RTE_SSP0_SCK_PORT 0xF - #define RTE_SSP0_SCK_BIT 0 - #define RTE_SSP0_SCK_FUNC 0 -#else - #error "Invalid SSP0 SSP0_SCK Pin Configuration!" -#endif -// SSP0_MISO <0=>Not used <1=>P1_1 <2=>P3_6 <3=>P3_7 <4=>P9_1 <5=>PF_2 -// Master In Slave Out for SSP0 -#define RTE_SSP0_MISO_PIN_SEL 0 -#if (RTE_SSP0_MISO_PIN_SEL == 0) - #define RTE_SSP0_MISO_PIN_EN 0 -#elif (RTE_SSP0_MISO_PIN_SEL == 1) - #define RTE_SSP0_MISO_PORT 1 - #define RTE_SSP0_MISO_BIT 1 - #define RTE_SSP0_MISO_FUNC 5 -#elif (RTE_SSP0_MISO_PIN_SEL == 2) - #define RTE_SSP0_MISO_PORT 3 - #define RTE_SSP0_MISO_BIT 6 - #define RTE_SSP0_MISO_FUNC 5 -#elif (RTE_SSP0_MISO_PIN_SEL == 3) - #define RTE_SSP0_MISO_PORT 3 - #define RTE_SSP0_MISO_BIT 7 - #define RTE_SSP0_MISO_FUNC 2 -#elif (RTE_SSP0_MISO_PIN_SEL == 4) - #define RTE_SSP0_MISO_PORT 9 - #define RTE_SSP0_MISO_BIT 1 - #define RTE_SSP0_MISO_FUNC 7 -#elif (RTE_SSP0_MISO_PIN_SEL == 5) - #define RTE_SSP0_MISO_PORT 0xF - #define RTE_SSP0_MISO_BIT 2 - #define RTE_SSP0_MISO_FUNC 2 -#else - #error "Invalid SSP0 SSP0_MISO Pin Configuration!" -#endif -#ifndef RTE_SSP0_MISO_PIN_EN - #define RTE_SSP0_MISO_PIN_EN 1 -#endif -// SSP0_MOSI <0=>Not used <1=>P1_2 <2=>P3_7 <3=>P3_8 <4=>P9_2 <5=>PF_3 -// Master Out Slave In for SSP0 -#define RTE_SSP0_MOSI_PIN_SEL 0 -#if (RTE_SSP0_MOSI_PIN_SEL == 0) - #define RTE_SSP0_MOSI_PIN_EN 0 -#elif (RTE_SSP0_MOSI_PIN_SEL == 1) - #define RTE_SSP0_MOSI_PORT 1 - #define RTE_SSP0_MOSI_BIT 2 - #define RTE_SSP0_MOSI_FUNC 5 -#elif (RTE_SSP0_MOSI_PIN_SEL == 2) - #define RTE_SSP0_MOSI_PORT 3 - #define RTE_SSP0_MOSI_BIT 7 - #define RTE_SSP0_MOSI_FUNC 5 -#elif (RTE_SSP0_MOSI_PIN_SEL == 3) - #define RTE_SSP0_MOSI_PORT 3 - #define RTE_SSP0_MOSI_BIT 8 - #define RTE_SSP0_MOSI_FUNC 2 -#elif (RTE_SSP0_MOSI_PIN_SEL == 4) - #define RTE_SSP0_MOSI_PORT 9 - #define RTE_SSP0_MOSI_BIT 2 - #define RTE_SSP0_MOSI_FUNC 7 -#elif (RTE_SSP0_MOSI_PIN_SEL == 5) - #define RTE_SSP0_MOSI_PORT 0xF - #define RTE_SSP0_MOSI_BIT 3 - #define RTE_SSP0_MOSI_FUNC 2 -#else - #error "Invalid SSP0 SSP0_MOSI Pin Configuration!" -#endif -#ifndef RTE_SSP0_MOSI_PIN_EN - #define RTE_SSP0_MOSI_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>10 (DMAMUXPER10) -// -#define RTE_SSP0_DMA_TX_EN 0 -#define RTE_SSP0_DMA_TX_CH 0 -#define RTE_SSP0_DMA_TX_PERI_ID 0 -#if (RTE_SSP0_DMA_TX_PERI_ID == 0) - #define RTE_SSP0_DMA_TX_PERI 10 - #define RTE_SSP0_DMA_TX_PERI_SEL 0 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>9 (DMAMUXPER9) -// -#define RTE_SSP0_DMA_RX_EN 0 -#define RTE_SSP0_DMA_RX_CH 1 -#define RTE_SSP0_DMA_RX_PERI_ID 0 -#if (RTE_SSP0_DMA_RX_PERI_ID == 0) - #define RTE_SSP0_DMA_RX_PERI 9 - #define RTE_SSP0_DMA_RX_PERI_SEL 0 -#endif -// DMA -// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] - -// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SSP1 0 - -// Pin Configuration -// SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5 -// Slave Select for SSP1 -#define RTE_SSP1_SSEL_PIN_SEL 1 -#if (RTE_SSP1_SSEL_PIN_SEL == 0) - #define RTE_SSP1_SSEL_PIN_EN 0 -#elif (RTE_SSP1_SSEL_PIN_SEL == 1) - #define RTE_SSP1_SSEL_PORT 1 - #define RTE_SSP1_SSEL_BIT 5 - #define RTE_SSP1_SSEL_FUNC 5 - #define RTE_SSP1_SSEL_GPIO_FUNC 0 - #define RTE_SSP1_SSEL_GPIO_PORT 1 - #define RTE_SSP1_SSEL_GPIO_BIT 8 -#elif (RTE_SSP1_SSEL_PIN_SEL == 2) - #define RTE_SSP1_SSEL_PORT 1 - #define RTE_SSP1_SSEL_BIT 20 - #define RTE_SSP1_SSEL_FUNC 1 - #define RTE_SSP1_SSEL_GPIO_FUNC 0 - #define RTE_SSP1_SSEL_GPIO_PORT 0 - #define RTE_SSP1_SSEL_GPIO_BIT 15 -#elif (RTE_SSP1_SSEL_PIN_SEL == 3) - #define RTE_SSP1_SSEL_PORT 0xF - #define RTE_SSP1_SSEL_BIT 5 - #define RTE_SSP1_SSEL_FUNC 2 - #define RTE_SSP1_SSEL_GPIO_FUNC 4 - #define RTE_SSP1_SSEL_GPIO_PORT 7 - #define RTE_SSP1_SSEL_GPIO_BIT 19 -#else - #error "Invalid SSP1 SSP1_SSEL Pin Configuration!" -#endif -#ifndef RTE_SSP1_SSEL_PIN_EN -#define RTE_SSP1_SSEL_PIN_EN 1 -#endif -// SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0 -// Serial clock for SSP1 -#define RTE_SSP1_SCK_PIN_SEL 0 -#if (RTE_SSP1_SCK_PIN_SEL == 0) - #define RTE_SSP1_SCK_PORT 1 - #define RTE_SSP1_SCK_BIT 19 - #define RTE_SSP1_SCK_FUNC 1 -#elif (RTE_SSP1_SCK_PIN_SEL == 1) - #define RTE_SSP1_SCK_PORT 0xF - #define RTE_SSP1_SCK_BIT 4 - #define RTE_SSP1_SCK_FUNC 0 -#elif (RTE_SSP1_SCK_PIN_SEL == 2) - #define RTE_SSP1_SCK_PORT 0x10 - #define RTE_SSP1_SCK_BIT 0 - #define RTE_SSP1_SCK_FUNC 6 -#else - #error "Invalid SSP1 SSP1_SCK Pin Configuration!" -#endif -// SSP1_MISO <0=>Not used <1=>P0_0 <2=>P1_3 <3=>PF_6 -// Master In Slave Out for SSP1 -#define RTE_SSP1_MISO_PIN_SEL 0 -#if (RTE_SSP1_MISO_PIN_SEL == 0) - #define RTE_SSP1_MISO_PIN_EN 0 -#elif (RTE_SSP1_MISO_PIN_SEL == 1) - #define RTE_SSP1_MISO_PORT 0 - #define RTE_SSP1_MISO_BIT 0 - #define RTE_SSP1_MISO_FUNC 1 -#elif (RTE_SSP1_MISO_PIN_SEL == 2) - #define RTE_SSP1_MISO_PORT 1 - #define RTE_SSP1_MISO_BIT 3 - #define RTE_SSP1_MISO_FUNC 5 -#elif (RTE_SSP1_MISO_PIN_SEL == 3) - #define RTE_SSP1_MISO_PORT 0xF - #define RTE_SSP1_MISO_BIT 6 - #define RTE_SSP1_MISO_FUNC 2 -#else - #error "Invalid SSP1 SSP1_MISO Pin Configuration!" -#endif -#ifndef RTE_SSP1_MISO_PIN_EN - #define RTE_SSP1_MISO_PIN_EN 1 -#endif -// SSP1_MOSI <0=>Not used <1=>P0_1 <2=>P1_4 <3=>PF_7 -// Master Out Slave In for SSP1 -#define RTE_SSP1_MOSI_PIN_SEL 0 -#if (RTE_SSP1_MOSI_PIN_SEL == 0) - #define RTE_SSP1_MOSI_PIN_EN 0 -#elif (RTE_SSP1_MOSI_PIN_SEL == 1) - #define RTE_SSP1_MOSI_PORT 0 - #define RTE_SSP1_MOSI_BIT 1 - #define RTE_SSP1_MOSI_FUNC 1 -#elif (RTE_SSP1_MOSI_PIN_SEL == 2) - #define RTE_SSP1_MOSI_PORT 1 - #define RTE_SSP1_MOSI_BIT 4 - #define RTE_SSP1_MOSI_FUNC 5 -#elif (RTE_SSP1_MOSI_PIN_SEL == 3) - #define RTE_SSP1_MOSI_PORT 0xF - #define RTE_SSP1_MOSI_BIT 7 - #define RTE_SSP1_MOSI_FUNC 2 -#else - #error "Invalid SSP1 SSP1_MOSI Pin Configuration!" -#endif -#ifndef RTE_SSP1_MOSI_PIN_EN - #define RTE_SSP1_MOSI_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14) -// -#define RTE_SSP1_DMA_TX_EN 0 -#define RTE_SSP1_DMA_TX_CH 0 -#define RTE_SSP1_DMA_TX_PERI_ID 0 -#if (RTE_SSP1_DMA_TX_PERI_ID == 0) - #define RTE_SSP1_DMA_TX_PERI 3 - #define RTE_SSP1_DMA_TX_PERI_SEL 3 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 1) - #define RTE_SSP1_DMA_TX_PERI 5 - #define RTE_SSP1_DMA_TX_PERI_SEL 2 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 2) - #define RTE_SSP1_DMA_TX_PERI 12 - #define RTE_SSP1_DMA_TX_PERI_SEL 0 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 3) - #define RTE_SSP1_DMA_TX_PERI 14 - #define RTE_SSP1_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13) -// -#define RTE_SSP1_DMA_RX_EN 0 -#define RTE_SSP1_DMA_RX_CH 1 -#define RTE_SSP1_DMA_RX_PERI_ID 0 -#if (RTE_SSP1_DMA_RX_PERI_ID == 0) - #define RTE_SSP1_DMA_RX_PERI 4 - #define RTE_SSP1_DMA_RX_PERI_SEL 3 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 1) - #define RTE_SSP1_DMA_RX_PERI 6 - #define RTE_SSP1_DMA_RX_PERI_SEL 2 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 2) - #define RTE_SSP1_DMA_RX_PERI 11 - #define RTE_SSP1_DMA_RX_PERI_SEL 0 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 3) - #define RTE_SSP1_DMA_RX_PERI 13 - #define RTE_SSP1_DMA_RX_PERI_SEL 2 -#endif -// DMA -// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] - -// SPI (Serial Peripheral Interface) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI 0 - -// Pin Configuration -// SPI_SSEL <0=>Not used <1=>P3_8 -// Slave Select for SPI -#define RTE_SPI_SSEL_PIN_SEL 0 -#if (RTE_SPI_SSEL_PIN_SEL == 0) -#define RTE_SPI_SSEL_PIN_EN 0 -#elif (RTE_SPI_SSEL_PIN_SEL == 1) - #define RTE_SPI_SSEL_PORT 3 - #define RTE_SPI_SSEL_BIT 8 - #define RTE_SPI_SSEL_FUNC 1 - #define RTE_SPI_SSEL_GPIO_FUNC 4 - #define RTE_SPI_SSEL_GPIO_PORT 5 - #define RTE_SPI_SSEL_GPIO_BIT 11 -#else - #error "Invalid SPI SPI_SSEL Pin Configuration!" -#endif -#ifndef RTE_SPI_SSEL_PIN_EN -#define RTE_SPI_SSEL_PIN_EN 1 -#endif -// SPI_SCK <0=>P3_3 -// Serial clock for SPI -#define RTE_SPI_SCK_PIN_SEL 0 -#if (RTE_SPI_SCK_PIN_SEL == 0) - #define RTE_SPI_SCK_PORT 3 - #define RTE_SPI_SCK_BIT 3 - #define RTE_SPI_SCK_FUNC 1 -#else - #error "Invalid SPI SPI_SCK Pin Configuration!" -#endif -// SPI_MISO <0=>Not used <1=>P3_6 -// Master In Slave Out for SPI -#define RTE_SPI_MISO_PIN_SEL 0 -#if (RTE_SPI_MISO_PIN_SEL == 0) - #define RTE_SPI_MISO_PIN_EN 0 -#elif (RTE_SPI_MISO_PIN_SEL == 1) - #define RTE_SPI_MISO_PORT 3 - #define RTE_SPI_MISO_BIT 6 - #define RTE_SPI_MISO_FUNC 1 -#else - #error "Invalid SPI SPI_MISO Pin Configuration!" -#endif -#ifndef RTE_SPI_MISO_PIN_EN - #define RTE_SPI_MISO_PIN_EN 1 -#endif -// SPI_MOSI <0=>Not used <1=>P3_7 -// Master Out Slave In for SPI -#define RTE_SPI_MOSI_PIN_SEL 0 -#if (RTE_SPI_MOSI_PIN_SEL == 0) - #define RTE_SPI_MOSI_PIN_EN 0 -#elif (RTE_SPI_MOSI_PIN_SEL == 1) - #define RTE_SPI_MOSI_PORT 3 - #define RTE_SPI_MOSI_BIT 7 - #define RTE_SPI_MOSI_FUNC 1 -#else - #error "Invalid SPI SPI_MOSI Pin Configuration!" -#endif -#ifndef RTE_SPI_MOSI_PIN_EN - #define RTE_SPI_MOSI_PIN_EN 1 -#endif -// Pin Configuration -// SPI (Serial Peripheral Interface) [Driver_SPI2] - -// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] -// Configuration settings for Driver_SAI0 in component ::Drivers:SAI -#define RTE_I2S0 0 - -// Pin Configuration -// I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4 -// Receive clock for I2S0 -#define RTE_I2S0_RX_SCK_PIN_SEL 2 -#if (RTE_I2S0_RX_SCK_PIN_SEL == 0) -#define RTE_I2S0_RX_SCK_PIN_EN 0 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 1) - #define RTE_I2S0_RX_SCK_PORT 3 - #define RTE_I2S0_RX_SCK_BIT 0 - #define RTE_I2S0_RX_SCK_FUNC 0 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 2) - #define RTE_I2S0_RX_SCK_PORT 6 - #define RTE_I2S0_RX_SCK_BIT 0 - #define RTE_I2S0_RX_SCK_FUNC 4 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 3) - #define RTE_I2S0_RX_SCK_PORT 0xF - #define RTE_I2S0_RX_SCK_BIT 4 - #define RTE_I2S0_RX_SCK_FUNC 7 -#else - #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_SCK_PIN_EN -#define RTE_I2S0_RX_SCK_PIN_EN 1 -#endif -// I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1 -// Receive word select for I2S0 -#define RTE_I2S0_RX_WS_PIN_SEL 2 -#if (RTE_I2S0_RX_WS_PIN_SEL == 0) -#define RTE_I2S0_RX_WS_PIN_EN 0 -#elif (RTE_I2S0_RX_WS_PIN_SEL == 1) - #define RTE_I2S0_RX_WS_PORT 3 - #define RTE_I2S0_RX_WS_BIT 1 - #define RTE_I2S0_RX_WS_FUNC 1 -#elif (RTE_I2S0_RX_WS_PIN_SEL == 2) - #define RTE_I2S0_RX_WS_PORT 6 - #define RTE_I2S0_RX_WS_BIT 1 - #define RTE_I2S0_RX_WS_FUNC 3 -#else - #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_WS_PIN_EN -#define RTE_I2S0_RX_WS_PIN_EN 1 -#endif -// I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2 -// Receive master clock for I2S0 -#define RTE_I2S0_RX_SDA_PIN_SEL 2 -#if (RTE_I2S0_RX_SDA_PIN_SEL == 0) -#define RTE_I2S0_RX_SDA_PIN_EN 0 -#elif (RTE_I2S0_RX_SDA_PIN_SEL == 1) - #define RTE_I2S0_RX_SDA_PORT 3 - #define RTE_I2S0_RX_SDA_BIT 2 - #define RTE_I2S0_RX_SDA_FUNC 1 -#elif (RTE_I2S0_RX_SDA_PIN_SEL == 2) - #define RTE_I2S0_RX_SDA_PORT 6 - #define RTE_I2S0_RX_SDA_BIT 2 - #define RTE_I2S0_RX_SDA_FUNC 3 -#else - #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_SDA_PIN_EN -#define RTE_I2S0_RX_SDA_PIN_EN 1 -#endif -// I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0 -// Receive master clock for I2S0 -#define RTE_I2S0_RX_MCLK_PIN_SEL 0 -#if (RTE_I2S0_RX_MCLK_PIN_SEL == 0) -#define RTE_I2S0_RX_MCLK_PIN_EN 0 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1) - #define RTE_I2S0_RX_MCLK_PORT 1 - #define RTE_I2S0_RX_MCLK_BIT 19 - #define RTE_I2S0_RX_MCLK_FUNC 6 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 2) - #define RTE_I2S0_RX_MCLK_PORT 3 - #define RTE_I2S0_RX_MCLK_BIT 0 - #define RTE_I2S0_RX_MCLK_FUNC 1 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 3) - #define RTE_I2S0_RX_MCLK_PORT 6 - #define RTE_I2S0_RX_MCLK_BIT 0 - #define RTE_I2S0_RX_MCLK_FUNC 1 -#else - #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_MCLK_PIN_EN -#define RTE_I2S0_RX_MCLK_PIN_EN 1 -#endif -// I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7 -// Transmit clock for I2S0 -#define RTE_I2S0_TX_SCK_PIN_SEL 1 -#if (RTE_I2S0_TX_SCK_PIN_SEL == 0) -#define RTE_I2S0_TX_SCK_PIN_EN 0 -#elif (RTE_I2S0_TX_SCK_PIN_SEL == 1) - #define RTE_I2S0_TX_SCK_PORT 3 - #define RTE_I2S0_TX_SCK_BIT 0 - #define RTE_I2S0_TX_SCK_FUNC 2 -#elif (RTE_I2S0_TX_SCK_PIN_SEL == 2) - #define RTE_I2S0_TX_SCK_PORT 4 - #define RTE_I2S0_TX_SCK_BIT 7 - #define RTE_I2S0_TX_SCK_FUNC 7 -#else - #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_SCK_PIN_EN -#define RTE_I2S0_TX_SCK_PIN_EN 1 -#endif -// I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13 -// Transmit word select for I2S0 -#define RTE_I2S0_TX_WS_PIN_SEL 4 -#if (RTE_I2S0_TX_WS_PIN_SEL == 0) -#define RTE_I2S0_TX_WS_PIN_EN 0 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 1) - #define RTE_I2S0_TX_WS_PORT 0 - #define RTE_I2S0_TX_WS_BIT 0 - #define RTE_I2S0_TX_WS_FUNC 6 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 2) - #define RTE_I2S0_TX_WS_PORT 3 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 0 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 3) - #define RTE_I2S0_TX_WS_PORT 3 - #define RTE_I2S0_TX_WS_BIT 4 - #define RTE_I2S0_TX_WS_FUNC 5 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 4) - #define RTE_I2S0_TX_WS_PORT 7 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 2 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 5) - #define RTE_I2S0_TX_WS_PORT 9 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 4 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 6) - #define RTE_I2S0_TX_WS_PORT 0xC - #define RTE_I2S0_TX_WS_BIT 13 - #define RTE_I2S0_TX_WS_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_WS_PIN_EN -#define RTE_I2S0_TX_WS_PIN_EN 1 -#endif -// I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2 <5=>PC_12 -// Transmit data for I2S0 -#define RTE_I2S0_TX_SDA_PIN_SEL 3 -#if (RTE_I2S0_TX_SDA_PIN_SEL == 0) -#define RTE_I2S0_TX_SDA_PIN_EN 0 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 1) - #define RTE_I2S0_TX_SDA_PORT 3 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 0 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 2) - #define RTE_I2S0_TX_SDA_PORT 3 - #define RTE_I2S0_TX_SDA_BIT 5 - #define RTE_I2S0_TX_SDA_FUNC 5 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 3) - #define RTE_I2S0_TX_SDA_PORT 7 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 2 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 4) - #define RTE_I2S0_TX_SDA_PORT 9 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 4 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 5) - #define RTE_I2S0_TX_SDA_PORT 0xC - #define RTE_I2S0_TX_SDA_BIT 12 - #define RTE_I2S0_TX_SDA_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_SDA_PIN_EN -#define RTE_I2S0_TX_SDA_PIN_EN 1 -#endif -// I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2 -// Transmit master clock for I2S0 -#define RTE_I2S0_TX_MCLK_PIN_SEL 2 -#if (RTE_I2S0_TX_MCLK_PIN_SEL == 0) -#define RTE_I2S0_TX_MCLK_PIN_EN 0 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1) - #define RTE_I2S0_TX_MCLK_PORT 3 - #define RTE_I2S0_TX_MCLK_BIT 0 - #define RTE_I2S0_TX_MCLK_FUNC 3 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 2) - #define RTE_I2S0_TX_MCLK_PORT 3 - #define RTE_I2S0_TX_MCLK_BIT 3 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 3) - #define RTE_I2S0_TX_MCLK_PORT 0xf - #define RTE_I2S0_TX_MCLK_BIT 4 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 4) - #define RTE_I2S0_TX_MCLK_PORT 0x10 - #define RTE_I2S0_TX_MCLK_BIT 2 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_MCLK_PIN_EN -#define RTE_I2S0_TX_MCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>9 (DMAMUXPER9) -// -#define RTE_I2S0_DMA_TX_EN 0 -#define RTE_I2S0_DMA_TX_CH 0 -#define RTE_I2S0_DMA_TX_PERI_ID 0 -#if (RTE_I2S0_DMA_TX_PERI_ID == 0) - #define RTE_I2S0_DMA_TX_PERI 9 - #define RTE_I2S0_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>10 (DMAMUXPER10) -// -#define RTE_I2S0_DMA_RX_EN 0 -#define RTE_I2S0_DMA_RX_CH 1 -#define RTE_I2S0_DMA_RX_PERI_ID 0 -#if (RTE_I2S0_DMA_RX_PERI_ID == 0) - #define RTE_I2S0_DMA_RX_PERI 10 - #define RTE_I2S0_DMA_RX_PERI_SEL 1 -#endif -// DMA -// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] - -// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] -// Configuration settings for Driver_I2S1 in component ::Drivers:SAI -#define RTE_I2S1 0 - -// Pin Configuration -// I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3 -// Receive clock for I2S1 -#define RTE_I2S1_RX_SCK_PIN_SEL 0 -#if (RTE_I2S1_RX_SCK_PIN_SEL == 0) -#define RTE_I2S1_RX_SCK_PIN_EN 0 -#elif (RTE_I2S1_RX_SCK_PIN_SEL == 1) - #define RTE_I2S1_RX_SCK_PORT 0x10 - #define RTE_I2S1_RX_SCK_BIT 2 - #define RTE_I2S1_RX_SCK_FUNC 7 -#elif (RTE_I2S1_RX_SCK_PIN_SEL == 2) - #define RTE_I2S1_RX_SCK_PORT 0x10 - #define RTE_I2S1_RX_SCK_BIT 3 - #define RTE_I2S1_RX_SCK_FUNC 7 -#else - #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_SCK_PIN_EN -#define RTE_I2S1_RX_SCK_PIN_EN 1 -#endif -// I2S1_RX_WS <0=>Not used <1=>P3_5 -// Receive word select for I2S1 -#define RTE_I2S1_RX_WS_PIN_SEL 0 -#if (RTE_I2S1_RX_WS_PIN_SEL == 0) -#define RTE_I2S1_RX_WS_PIN_EN 0 -#elif (RTE_I2S1_RX_WS_PIN_SEL == 1) - #define RTE_I2S1_RX_WS_PORT 3 - #define RTE_I2S1_RX_WS_BIT 5 - #define RTE_I2S1_RX_WS_FUNC 6 -#else - #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_WS_PIN_EN -#define RTE_I2S1_RX_WS_PIN_EN 1 -#endif -// I2S1_RX_SDA <0=>Not used <1=>P3_4 -// Receive master clock for I2S1 -#define RTE_I2S1_RX_SDA_PIN_SEL 0 -#if (RTE_I2S1_RX_SDA_PIN_SEL == 0) -#define RTE_I2S1_RX_SDA_PIN_EN 0 -#elif (RTE_I2S1_RX_SDA_PIN_SEL == 1) - #define RTE_I2S1_RX_SDA_PORT 3 - #define RTE_I2S1_RX_SDA_BIT 4 - #define RTE_I2S1_RX_SDA_FUNC 6 -#else - #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_SDA_PIN_EN -#define RTE_I2S1_RX_SDA_PIN_EN 1 -#endif -// I2S1_RX_MCLK <0=>Not used <1=>PA_0 -// Receive master clock for I2S1 -#define RTE_I2S1_RX_MCLK_PIN_SEL 0 -#if (RTE_I2S1_RX_MCLK_PIN_SEL == 0) -#define RTE_I2S1_RX_MCLK_PIN_EN 0 -#elif (RTE_I2S1_RX_MCLK_PIN_SEL == 1) - #define RTE_I2S1_RX_MCLK_PORT 0x0A - #define RTE_I2S1_RX_MCLK_BIT 0 - #define RTE_I2S1_RX_MCLK_FUNC 5 -#else - #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_MCLK_PIN_EN -#define RTE_I2S1_RX_MCLK_PIN_EN 1 -#endif -// I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7 -// Transmit clock for I2S1 -#define RTE_I2S1_TX_SCK_PIN_SEL 0 -#if (RTE_I2S1_TX_SCK_PIN_SEL == 0) -#define RTE_I2S1_TX_SCK_PIN_EN 0 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 1) - #define RTE_I2S1_TX_SCK_PORT 1 - #define RTE_I2S1_TX_SCK_BIT 19 - #define RTE_I2S1_TX_SCK_FUNC 7 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 2) - #define RTE_I2S1_TX_SCK_PORT 3 - #define RTE_I2S1_TX_SCK_BIT 3 - #define RTE_I2S1_TX_SCK_FUNC 7 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 3) - #define RTE_I2S1_TX_SCK_PORT 4 - #define RTE_I2S1_TX_SCK_BIT 7 - #define RTE_I2S1_TX_SCK_FUNC 6 -#else - #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_SCK_PIN_EN -#define RTE_I2S1_TX_SCK_PIN_EN 1 -#endif -// I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7 -// Transmit word select for I2S1 -#define RTE_I2S1_TX_WS_PIN_SEL 0 -#if (RTE_I2S1_TX_WS_PIN_SEL == 0) -#define RTE_I2S1_TX_WS_PIN_EN 0 -#elif (RTE_I2S1_TX_WS_PIN_SEL == 1) - #define RTE_I2S1_TX_WS_PORT 0 - #define RTE_I2S1_TX_WS_BIT 0 - #define RTE_I2S1_TX_WS_FUNC 7 -#elif (RTE_I2S1_TX_WS_PIN_SEL == 2) - #define RTE_I2S1_TX_WS_PORT 0x0F - #define RTE_I2S1_TX_WS_BIT 7 - #define RTE_I2S1_TX_WS_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_WS_PIN_EN -#define RTE_I2S1_TX_WS_PIN_EN 1 -#endif -// I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6 -// Transmit data for I2S -#define RTE_I2S1_TX_SDA_PIN_SEL 0 -#if (RTE_I2S1_TX_SDA_PIN_SEL == 0) -#define RTE_I2S1_TX_SDA_PIN_EN 0 -#elif (RTE_I2S1_TX_SDA_PIN_SEL == 1) - #define RTE_I2S1_TX_SDA_PORT 0 - #define RTE_I2S1_TX_SDA_BIT 1 - #define RTE_I2S1_TX_SDA_FUNC 7 -#elif (RTE_I2S1_TX_SDA_PIN_SEL == 2) - #define RTE_I2S1_TX_SDA_PORT 0x0F - #define RTE_I2S1_TX_SDA_BIT 6 - #define RTE_I2S1_TX_SDA_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_SDA_PIN_EN -#define RTE_I2S1_TX_SDA_PIN_EN 1 -#endif -// I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1 -// Transmit master clock for I2S1 -#define RTE_I2S1_TX_MCLK_PIN_SEL 0 -#if (RTE_I2S1_TX_MCLK_PIN_SEL == 0) -#define RTE_I2S1_TX_MCLK_PIN_EN 0 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 1) - #define RTE_I2S1_TX_MCLK_PORT 8 - #define RTE_I2S1_TX_MCLK_BIT 8 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 2) - #define RTE_I2S1_TX_MCLK_PORT 0x0F - #define RTE_I2S1_TX_MCLK_BIT 0 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 3) - #define RTE_I2S1_TX_MCLK_PORT 0x10 - #define RTE_I2S1_TX_MCLK_BIT 1 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_MCLK_PIN_EN -#define RTE_I2S1_TX_MCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) -// -#define RTE_I2S1_DMA_TX_EN 0 -#define RTE_I2S1_DMA_TX_CH 0 -#define RTE_I2S1_DMA_TX_PERI_ID 0 -#if (RTE_I2S1_DMA_TX_PERI_ID == 0) - #define RTE_I2S1_DMA_TX_PERI 3 - #define RTE_I2S1_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) -// -#define RTE_I2S1_DMA_RX_EN 0 -#define RTE_I2S1_DMA_RX_CH 1 -#define RTE_I2S1_DMA_RX_PERI_ID 0 -#if (RTE_I2S1_DMA_RX_PERI_ID == 0) - #define RTE_I2S1_DMA_RX_PERI 4 - #define RTE_I2S1_DMA_RX_PERI_SEL 2 -#endif -// DMA -// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] - -// CAN0 Controller [Driver_CAN0] -// Configuration settings for Driver_CAN0 in component ::Drivers:CAN -#define RTE_CAN_CAN0 0 - -// Pin Configuration -// CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2 -// CAN0 receiver input. -#define RTE_CAN0_RD_ID 0 -#if (RTE_CAN0_RD_ID == 0) - #define RTE_CAN0_RD_PIN_EN 0 -#elif (RTE_CAN0_RD_ID == 1) - #define RTE_CAN0_RD_PORT 3 - #define RTE_CAN0_RD_BIT 1 - #define RTE_CAN0_RD_FUNC 2 -#elif (RTE_CAN0_RD_ID == 2) - #define RTE_CAN0_RD_PORT 0xE - #define RTE_CAN0_RD_BIT 2 - #define RTE_CAN0_RD_FUNC 1 -#else - #error "Invalid RTE_CAN0_RD Pin Configuration!" -#endif -#ifndef RTE_CAN0_RD_PIN_EN - #define RTE_CAN0_RD_PIN_EN 1 -#endif -// CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3 -// CAN0 transmitter output. -#define RTE_CAN0_TD_ID 0 -#if (RTE_CAN0_TD_ID == 0) - #define RTE_CAN0_TD_PIN_EN 0 -#elif (RTE_CAN0_TD_ID == 1) - #define RTE_CAN0_TD_PORT 3 - #define RTE_CAN0_TD_BIT 2 - #define RTE_CAN0_TD_FUNC 2 -#elif (RTE_CAN0_TD_ID == 2) - #define RTE_CAN0_TD_PORT 0xE - #define RTE_CAN0_TD_BIT 3 - #define RTE_CAN0_TD_FUNC 1 -#else - #error "Invalid RTE_CAN0_TD Pin Configuration!" -#endif -#ifndef RTE_CAN0_TD_PIN_EN - #define RTE_CAN0_TD_PIN_EN 1 -#endif -// Pin Configuration -// CAN0 Controller [Driver_CAN0] - -// CAN1 Controller [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::Drivers:CAN -#define RTE_CAN_CAN1 0 - -// Pin Configuration -// CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1 -// CAN1 receiver input. -#define RTE_CAN1_RD_ID 0 -#if (RTE_CAN1_RD_ID == 0) - #define RTE_CAN1_RD_PIN_EN 0 -#elif (RTE_CAN1_RD_ID == 1) - #define RTE_CAN1_RD_PORT 1 - #define RTE_CAN1_RD_BIT 18 - #define RTE_CAN1_RD_FUNC 5 -#elif (RTE_CAN1_RD_ID == 2) - #define RTE_CAN1_RD_PORT 4 - #define RTE_CAN1_RD_BIT 9 - #define RTE_CAN1_RD_FUNC 6 -#elif (RTE_CAN1_RD_ID == 3) - #define RTE_CAN1_RD_PORT 0xE - #define RTE_CAN1_RD_BIT 1 - #define RTE_CAN1_RD_FUNC 5 -#else - #error "Invalid RTE_CAN1_RD Pin Configuration!" -#endif -#ifndef RTE_CAN1_RD_PIN_EN - #define RTE_CAN1_RD_PIN_EN 1 -#endif -// CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0 -// CAN1 transmitter output. -#define RTE_CAN1_TD_ID 0 -#if (RTE_CAN1_TD_ID == 0) - #define RTE_CAN1_TD_PIN_EN 0 -#elif (RTE_CAN1_TD_ID == 1) - #define RTE_CAN1_TD_PORT 1 - #define RTE_CAN1_TD_BIT 17 - #define RTE_CAN1_TD_FUNC 5 -#elif (RTE_CAN1_TD_ID == 2) - #define RTE_CAN1_TD_PORT 4 - #define RTE_CAN1_TD_BIT 8 - #define RTE_CAN1_TD_FUNC 6 -#elif (RTE_CAN1_TD_ID == 3) - #define RTE_CAN1_TD_PORT 0xE - #define RTE_CAN1_TD_BIT 0 - #define RTE_CAN1_TD_FUNC 5 -#else - #error "Invalid RTE_CAN1_TD Pin Configuration!" -#endif -#ifndef RTE_CAN1_TD_PIN_EN - #define RTE_CAN1_TD_PIN_EN 1 -#endif -// Pin Configuration -// CAN1 Controller [Driver_CAN1] - - -#endif /* __RTE_DEVICE_H */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/startup_LPC43xx.s b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/startup_LPC43xx.s deleted file mode 100644 index 19eac6d..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/startup_LPC43xx.s +++ /dev/null @@ -1,333 +0,0 @@ -;/**************************************************************************//** -; * @file LPC43xx.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * NXP LPC43xxDevice Series -; * @version V1.00 -; * @date 03. September 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; * <<< Use Configuration Wizard in Context Menu >>> -; ******************************************************************************/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -Sign_Value EQU 0x5A5A5A5A - -__Vectors DCD __initial_sp ; 0 Top of Stack - DCD Reset_Handler ; 1 Reset Handler - DCD NMI_Handler ; 2 NMI Handler - DCD HardFault_Handler ; 3 Hard Fault Handler - DCD MemManage_Handler ; 4 MPU Fault Handler - DCD BusFault_Handler ; 5 Bus Fault Handler - DCD UsageFault_Handler ; 6 Usage Fault Handler - DCD Sign_Value ; 7 Reserved - DCD 0 ; 8 Reserved - DCD 0 ; 9 Reserved - DCD 0 ; 10 Reserved - DCD SVC_Handler ; 11 SVCall Handler - DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD 0 ; 13 Reserved - DCD PendSV_Handler ; 14 PendSV Handler - DCD SysTick_Handler ; 15 SysTick Handler - - ; External LPC43xx/M4 Interrupts - DCD DAC_IRQHandler ; 0 DAC interrupt - DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication - DCD DMA_IRQHandler ; 2 DMA interrupt - DCD 0 ; 3 Reserved - DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt - DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt - DCD SDIO_IRQHandler ; 6 SD/MMC interrupt - DCD LCD_IRQHandler ; 7 LCD interrupt - DCD USB0_IRQHandler ; 8 OTG interrupt - DCD USB1_IRQHandler ; 9 USB1 interrupt - DCD SCT_IRQHandler ; 10 SCT combined interrupt - DCD RITIMER_IRQHandler ; 11 RI Timer interrupt - DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt - DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt - DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt - DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt - DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt - DCD ADC0_IRQHandler ; 17 ADC0 interrupt - DCD I2C0_IRQHandler ; 18 I2C0 interrupt - DCD I2C1_IRQHandler ; 19 I2C1 interrupt - DCD SPI_IRQHandler ; 20 SPI interrupt - DCD ADC1_IRQHandler ; 21 ADC1 interrupt - DCD SSP0_IRQHandler ; 22 SSP0 interrupt - DCD SSP1_IRQHandler ; 23 SSP1 interrupt - DCD USART0_IRQHandler ; 24 USART0 interrupt - DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt - DCD USART2_IRQHandler ; 26 USART2 interrupt - DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt - DCD I2S0_IRQHandler ; 28 I2S0 interrupt - DCD I2S1_IRQHandler ; 29 I2S1 interrupt - DCD SPIFI_IRQHandler ; 30 SPISI interrupt - DCD SGPIO_IRQHandler ; 31 SGPIO interrupt - DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0 - DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1 - DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2 - DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3 - DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4 - DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5 - DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6 - DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7 - DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0 - DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1 - DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt - DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt - DCD 0 ; 44 Reserved - DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt - DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt - DCD RTC_IRQHandler ; 47 RTC interrupt - DCD 0 ; 48 Reserved - DCD WWDT_IRQHandler ; 49 WWDT interrupt - DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt - DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt - DCD QEI_IRQHandler ; 52 QEI interrupt - - -;CRP address at offset 0x2FC relative to the BOOT Bank address - IF :LNOT::DEF:NO_CRP - SPACE (0x2FC - (. - __Vectors)) -; EXPORT CRP_Key -CRP_Key DCD 0xFFFFFFFF -; 0xFFFFFFFF => CRP Disabled -; 0x12345678 => CRP Level 1 -; 0x87654321 => CRP Level 2 -; 0x43218765 => CRP Level 3 (ARE YOU SURE?) -; 0x4E697370 => NO ISP (ARE YOU SURE?) - ENDIF - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DAC_IRQHandler [WEAK] - EXPORT M0APP_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT FLASHEEPROM_IRQHandler [WEAK] - EXPORT ETHERNET_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USB1_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT RITIMER_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT I2S1_IRQHandler [WEAK] - EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SGPIO_IRQHandler [WEAK] - EXPORT PIN_INT0_IRQHandler [WEAK] - EXPORT PIN_INT1_IRQHandler [WEAK] - EXPORT PIN_INT2_IRQHandler [WEAK] - EXPORT PIN_INT3_IRQHandler [WEAK] - EXPORT PIN_INT4_IRQHandler [WEAK] - EXPORT PIN_INT5_IRQHandler [WEAK] - EXPORT PIN_INT6_IRQHandler [WEAK] - EXPORT PIN_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT EVENTROUTER_IRQHandler [WEAK] - EXPORT C_CAN1_IRQHandler [WEAK] - EXPORT ADCHS_IRQHandler [WEAK] - EXPORT ATIMER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT WWDT_IRQHandler [WEAK] - EXPORT M0SUB_IRQHandler [WEAK] - EXPORT C_CAN0_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - -DAC_IRQHandler -M0APP_IRQHandler -DMA_IRQHandler -FLASHEEPROM_IRQHandler -ETHERNET_IRQHandler -SDIO_IRQHandler -LCD_IRQHandler -USB0_IRQHandler -USB1_IRQHandler -SCT_IRQHandler -RITIMER_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -MCPWM_IRQHandler -ADC0_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI_IRQHandler -ADC1_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -USART0_IRQHandler -UART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -I2S0_IRQHandler -I2S1_IRQHandler -SPIFI_IRQHandler -SGPIO_IRQHandler -PIN_INT0_IRQHandler -PIN_INT1_IRQHandler -PIN_INT2_IRQHandler -PIN_INT3_IRQHandler -PIN_INT4_IRQHandler -PIN_INT5_IRQHandler -PIN_INT6_IRQHandler -PIN_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -EVENTROUTER_IRQHandler -C_CAN1_IRQHandler -ADCHS_IRQHandler -ATIMER_IRQHandler -RTC_IRQHandler -WWDT_IRQHandler -M0SUB_IRQHandler -C_CAN0_IRQHandler -QEI_IRQHandler - - B . - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/system_LPC43xx.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/system_LPC43xx.c deleted file mode 100644 index 5c46381..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/system_LPC43xx.c +++ /dev/null @@ -1,938 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013 - 2017 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 10. September 2018 - * $Revision: V1.0.3 - * - * Project: NXP LPC43xx System initialization - * -------------------------------------------------------------------------- */ - -#include "LPC43xx.h" - -/*---------------------------------------------------------------------------- - This file configures the clocks as follows: - ----------------------------------------------------------------------------- - Clock Unit | Output clock | Source clock | Note - ----------------------------------------------------------------------------- - PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz - ----------------------------------------------------------------------------- - PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz - ----------------------------------------------------------------------------- - CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK - ----------------------------------------------------------------------------- - IDIV A | 60 MHz | PLL1 | To the USB1 peripheral - ----------------------------------------------------------------------------- - IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz - ----------------------------------------------------------------------------- - IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz - ----------------------------------------------------------------------------- - IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz - ----------------------------------------------------------------------------- - IDIV E | 5.3 MHz | PLL1 | To the LCD controller - -----------------------------------------------------------------------------*/ - - -/*---------------------------------------------------------------------------- - Clock source selection definitions (do not change) - *----------------------------------------------------------------------------*/ -#define CLK_SRC_32KHZ 0x00 -#define CLK_SRC_IRC 0x01 -#define CLK_SRC_ENET_RX 0x02 -#define CLK_SRC_ENET_TX 0x03 -#define CLK_SRC_GP_CLKIN 0x04 -#define CLK_SRC_XTAL 0x06 -#define CLK_SRC_PLL0U 0x07 -#define CLK_SRC_PLL0A 0x08 -#define CLK_SRC_PLL1 0x09 -#define CLK_SRC_IDIVA 0x0C -#define CLK_SRC_IDIVB 0x0D -#define CLK_SRC_IDIVC 0x0E -#define CLK_SRC_IDIVD 0x0F -#define CLK_SRC_IDIVE 0x10 - - -/*---------------------------------------------------------------------------- - Define external input frequency values - *----------------------------------------------------------------------------*/ -#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */ -#define CLK_IRC 12000000UL /* Internal oscillator frequency */ -#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */ -#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */ -#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */ -#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */ - - -/*---------------------------------------------------------------------------- - Define clock sources - *----------------------------------------------------------------------------*/ -#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */ -#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */ -#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */ -#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */ -#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */ -#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */ -#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */ - - -/*---------------------------------------------------------------------------- - Configure integer divider values - *----------------------------------------------------------------------------*/ -#define IDIVA_IDIV 2 /* Divide input clock by 3 */ -#define IDIVB_IDIV 1 /* Divide input clock by 2 */ -#define IDIVC_IDIV 0 /* Divide input clock by 1 */ -#define IDIVD_IDIV 0 /* Divide input clock by 1 */ -#define IDIVE_IDIV 33 /* Divide input clock by 34 */ - - -/*---------------------------------------------------------------------------- - Define CPU clock input - *----------------------------------------------------------------------------*/ -#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */ - - -/*---------------------------------------------------------------------------- - Configure external memory controller options - *----------------------------------------------------------------------------*/ -#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */ -#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */ - - -/*---------------------------------------------------------------------------- - * Configure PLL1 - *---------------------------------------------------------------------------- - * Integer mode: - * - PLL1_DIRECT = 0 (Post divider enabled) - * - PLL1_FBSEL = 1 (Feedback divider runs from PLL output) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M - * FCCO = FCLKOUT * 2 * P - * - * Non-integer: - * - PLL1_DIRECT = 0 (Post divider enabled) - * - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M / (2 * P) - * FCCO = FCLKOUT * 2 * P - * - * Direct mode: - * - PLL1_DIRECT = 1 (Post divider disabled) - * - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M - * FCCO = FCLKOUT - * - *---------------------------------------------------------------------------- - * PLL1 requirements: - * | Frequency | Minimum | Maximum | Note | - * | FCLKIN | 1MHz | 25MHz | Clock source is external crystal | - * | FCLKIN | 1MHz | 50MHz | | - * | FCCO | 156MHz | 320MHz | | - * | FCLKOUT | 9.75MHz | 320MHz | | - *---------------------------------------------------------------------------- - * Configuration examples: - * | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS | - * | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 | - * | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 | - * | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 | - * | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 | - * | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 | - * | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 | - * | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 | - *---------------------------------------------------------------------------- - * Relations beetwen PLL dividers and definitions: - * N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL - *----------------------------------------------------------------------------*/ - -/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */ -#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */ -#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */ -#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */ - -#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ -#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */ -#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */ - /* 1: FCLKOUT is used as PLL feedback */ - -/*---------------------------------------------------------------------------- - * Configure Flash Accelerator - *---------------------------------------------------------------------------- - * Flash acces time: - * | CPU clock | FLASHTIM | - * | up to 21MHz | 0 | - * | up to 43MHz | 1 | - * | up to 64MHz | 2 | - * | up to 86MHz | 3 | - * | up to 107MHz | 4 | - * | up to 129MHz | 5 | - * | up to 150MHz | 6 | - * | up to 172MHz | 7 | - * | up to 193MHz | 8 | - * | up to 204MHz | 9 | - *----------------------------------------------------------------------------*/ -#define FLASHCFG_FLASHTIM 9 - - -/*---------------------------------------------------------------------------- - * Configure PLL0USB - *---------------------------------------------------------------------------- - * - * Normal operating mode without post-divider and without pre-divider - * - PLL0USB_DIRECTI = 1 - * - PLL0USB_DIRECTO = 1 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * 2 * M - * FCCO = FOUT - * - * Normal operating mode with post-divider and without pre-divider - * - PLL0USB_DIRECTI = 1 - * - PLL0USB_DIRECTO = 0 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * (M / P) - * FCCO = FOUT * 2 * P - * - * Normal operating mode without post-divider and with pre-divider - * - PLL0USB_DIRECTI = 0 - * - PLL0USB_DIRECTO = 1 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * 2 * M / N - * FCCO = FOUT - * - * Normal operating mode with post-divider and with pre-divider - * - PLL0USB_DIRECTI = 0 - * - PLL0USB_DIRECTO = 0 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * M / (P * N) - * FCCO = FOUT * 2 * P - *---------------------------------------------------------------------------- - * PLL0 requirements: - * | Frequency | Minimum | Maximum | Note | - * | FCLKIN | 14kHz | 25MHz | Clock source is external crystal | - * | FCLKIN | 14kHz | 150MHz | | - * | FCCO | 275MHz | 550MHz | | - * | FCLKOUT | 4.3MHz | 550MHz | | - *---------------------------------------------------------------------------- - * Configuration examples: - * | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS | - * | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 | - * | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 | - *----------------------------------------------------------------------------*/ - -/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */ -#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */ -#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */ -#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */ - -#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */ -#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */ -#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ - - -/*---------------------------------------------------------------------------- - End of configuration - *----------------------------------------------------------------------------*/ - -/* PLL0 Setting Check */ -#if (PLL0USB_BYPASS == 0) - #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL) - #define PLL0USB_CLKIN CLK_XTAL - #else - #define PLL0USB_CLKIN CLK_IRC - #endif - - #if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M) - #define PLL0USB_FCCO (PLL0USB_FOUT) - #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P) - #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) - #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N) - #define PLL0USB_FCCO (PLL0USB_FOUT) - #else /* Mode 1d */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N)) - #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) - #endif - - #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL) - #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)" - #endif - #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL) - #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)" - #endif -#endif - -/* PLL1 Setting Check */ -#if (PLL1_BYPASS == 0) - #if (PLL1_CLK_SEL == CLK_SRC_XTAL) - #define PLL1_CLKIN CLK_XTAL - #else - #define PLL1_CLKIN CLK_IRC - #endif - - #if (PLL1_DIRECT == 1) /* Direct Mode */ - #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #elif (PLL1_FBSEL == 1) /* Integer Mode */ - #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #else /* Noninteger Mode */ - #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL))) - #endif - #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL) - #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)" - #endif - #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL) - #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)" - #endif -#endif - - -/*---------------------------------------------------------------------------- - System Core Clock variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */ - - -/****************************************************************************** - * SetClock - ******************************************************************************/ -void SetClock (void) { - uint32_t x, i; - uint32_t selp, seli; - - - /* Set flash accelerator configuration for bank A and B to reset value */ - LPC_CREG->FLASHCFGA |= (0xF << 12); - LPC_CREG->FLASHCFGB |= (0xF << 12); - - /* Set flash wait states to maximum */ - LPC_EMC->STATICWAITRD0 = 0x1F; - - /* Switch BASE_M4_CLOCK to IRC */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (CLK_SRC_IRC << 24) ; /* Set clock source */ - - /* Configure input to crystal oscilator */ - LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */ - (0 << 1) | /* Operation with crystal connected */ - (0 << 2) ; /* Low-frequency mode */ - - /* Wait ~250us @ 12MHz */ - for (i = 1500; i; i--); - -#if (USE_SPIFI) -/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */ - LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ - (0 << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (CLK_SRC_IRC << 24) ; /* Clock source */ - - LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */ - (0 << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (CLK_SRC_IDIVA << 24) ; /* Clock source */ -#endif - -/*---------------------------------------------------------------------------- - PLL1 Setup - *----------------------------------------------------------------------------*/ - /* Power down PLL */ - LPC_CGU->PLL1_CTRL |= 1; - -#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1)) - /* To run at full speed, CPU must first run at an intermediate speed */ - LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ - (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ - (PLL1_FBSEL << 6) | /* PLL output used as feedback */ - (0 << 7) | /* Direct on/off */ - (PLL1_PSEL << 8) | /* PSEL */ - (0 << 11)| /* Autoblock Disabled */ - (PLL1_NSEL << 12)| /* NSEL */ - (PLL1_MSEL << 16)| /* MSEL */ - (PLL1_CLK_SEL << 24); /* Clock source */ - /* Wait for lock */ - while (!(LPC_CGU->PLL1_STAT & 1)); - - /* CPU base clock is in the mid frequency range before final clock set */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (0x09 << 24) ; /* Clock source: PLL1 */ - - /* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */ - for (i = 1050; i; i--); /* Wait minimum 2100 cycles */ -#endif - /* Configure PLL1 */ - LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ - (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ - (PLL1_FBSEL << 6) | /* PLL output used as feedback */ - (PLL1_DIRECT << 7) | /* Direct on/off */ - (PLL1_PSEL << 8) | /* PSEL */ - (1 << 11)| /* Autoblock En */ - (PLL1_NSEL << 12)| /* NSEL */ - (PLL1_MSEL << 16)| /* MSEL */ - (PLL1_CLK_SEL << 24); /* Clock source */ - - /* Wait for lock */ - while (!(LPC_CGU->PLL1_STAT & 1)); - - /* Set CPU base clock source */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (CPU_CLK_SEL << 24) ; /* Set clock source */ - - /* Set flash accelerator configuration for internal flash bank A and B */ - LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12); - LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12); - -/*---------------------------------------------------------------------------- - PLL0USB Setup - *----------------------------------------------------------------------------*/ - - /* Power down PLL0USB */ - LPC_CGU->PLL0USB_CTRL |= 1; - - /* M divider */ - x = 0x00004000; - switch (PLL0USB_M) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00018003; - break; - case 2: x = 0x00010003; - break; - default: - for (i = PLL0USB_M; i <= 0x8000; i++) { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - } - } - - if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1; - else selp = 31; - - if (PLL0USB_M > 16384) seli = 1; - else if (PLL0USB_M > 8192) seli = 2; - else if (PLL0USB_M > 2048) seli = 4; - else if (PLL0USB_M >= 501) seli = 8; - else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9)); - else seli = (PLL0USB_M & 0x3C) + 4; - LPC_CGU->PLL0USB_MDIV = (selp << 17) | - (seli << 22) | - (x << 0); - - /* N divider */ - x = 0x80; - switch (PLL0USB_N) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00000302; - break; - case 2: x = 0x00000202; - break; - default: - for (i = PLL0USB_N; i <= 0x0100; i++) { - x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - } - } - LPC_CGU->PLL0USB_NP_DIV = (x << 12); - - /* P divider */ - x = 0x10; - switch (PLL0USB_P) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00000062; - break; - case 2: x = 0x00000042; - break; - default: - for (i = PLL0USB_P; i <= 0x200; i++) { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F); - } - } - LPC_CGU->PLL0USB_NP_DIV |= x; - - LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */ - (1 << 11) | /* Autoblock En */ - (1 << 4 ) | /* PLL0USB clock en */ - (PLL0USB_DIRECTO << 3 ) | /* Direct output */ - (PLL0USB_DIRECTI << 2 ) | /* Direct input */ - (PLL0USB_BYPASS << 1 ) | /* PLL bypass */ - (0 << 0 ) ; /* PLL0USB Enabled */ - while (!(LPC_CGU->PLL0USB_STAT & 1)); - - -/*---------------------------------------------------------------------------- - Integer divider Setup - *----------------------------------------------------------------------------*/ - - /* Configure integer dividers */ - LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVA_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVA_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVB_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVB_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVC_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVC_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVD_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVD_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVE_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVE_CLK_SEL << 24) ; /* Clock source */ -} - - -/*---------------------------------------------------------------------------- - Approximate delay function (must be used after SystemCoreClockUpdate() call) - *----------------------------------------------------------------------------*/ -#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000) - -static void WaitUs (uint32_t us) { - uint32_t cyc = us * CPU_NANOSEC(1000)/4; - while(cyc--); -} - - -/*---------------------------------------------------------------------------- - External Memory Controller Definitions - *----------------------------------------------------------------------------*/ -#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */ -/* Write Mode register macro */ -#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x)))) - -/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */ -#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)) -#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000) - -#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */ -#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */ - -typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg); - -const uint16_t emcdivby2_opc[] = { - 0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */ - 0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */ - 0x6003, /* STR R3,[R0,#0] ; Store CREG6 */ - 0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */ - 0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */ - 0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */ - 0xD0FC, /* BEQ loop ; Jump if 0 */ - 0x4770, /* BX LR ; Exit */ - 0, -}; - -#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4) -#define emcdivby2_ram 0x10000000 - -/*---------------------------------------------------------------------------- - Initialize external memory controller - *----------------------------------------------------------------------------*/ - -void SystemInit_ExtMemCtl (void) { - uint32_t emcdivby2_buf[emcdivby2_szw]; - uint32_t div, n; - - /* Select and enable EMC branch clock */ - LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1; - while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1)); - - /* Set EMC clock output delay */ - if (SystemCoreClock < 80000000UL) { - LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */ - } - else { - LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */ - } - - /* Configure EMC port pins */ - LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */ - LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */ - LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */ - LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */ - LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */ - LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */ - LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */ - LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */ - LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */ - LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */ - LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */ - LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */ - LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */ - LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */ - LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */ - - LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */ - LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */ - LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */ - LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */ - LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */ - LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */ - LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */ - LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */ - LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */ - LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */ - LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */ - - LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */ - LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */ - LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */ - LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */ - LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */ - LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */ - LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */ - LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */ - - LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */ - LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */ - LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */ - LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */ - LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */ - LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */ - LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */ - LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */ - LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */ - LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */ - LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */ - LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */ - - LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */ - - LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */ - LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */ - LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */ - LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */ - LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */ - LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */ - LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */ - LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */ - LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */ - LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */ - LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */ - LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */ - LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */ - LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */ - LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */ - LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */ - LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */ - - LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */ - LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */ - LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */ - LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */ - LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */ - LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */ - LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */ - LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */ - LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */ - LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */ - LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */ - LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */ - LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */ - LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */ - LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */ - LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */ - - LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */ - LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */ - - div = 0; - if (SystemCoreClock > 120000000UL) { - /* Use EMC clock divider and EMC clock output delay */ - div = 1; - /* Following code must be executed in RAM to ensure stable operation */ - /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */ - /* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */ - /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */ - - /* This code configures EMC clock divider and is executed in RAM */ - for (n = 0; n < emcdivby2_szw; n++) { - emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n); - *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n); - } - __ISB(); - ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1); - for (n = 0; n < emcdivby2_szw; n++) { - *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n]; - } - } - - /* Configure EMC clock-out pins */ - LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */ - LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */ - LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */ - LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */ - - /* Static memory configuration (chip select 0) */ -#if (USE_EXT_STAT_MEM_CS0) - LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */ - (2 << 0) | /* Memory width 32-bit */ - (1 << 3); /* Async page mode enable */ - - LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */ - - LPC_EMC->STATICWAITPAGE0 = 2; - - /* Set Static Memory Read Delay for 90ns External NOR Flash */ - LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div); - LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */ -#endif - - /* Dynamic memory configuration (chip select 0) */ -#if (USE_EXT_DYN_MEM_CS0) - - /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */ - LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */ - (0 << 12) | /* AM[12] = 0 */ - (2 << 9) | /* AM[11:9] = 2 */ - (2 << 7) ; /* AM[8:7] = 2 */ - - LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/ - LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */ - - LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div); - LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div); - LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div); - LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div); - LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div); - LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div); - LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div); - - WaitUs (100); - LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */ - WaitUs (1); - LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ - WaitUs (1); - LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1; - WaitUs (10); - LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1; - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */ - - /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */ - WR_MODE(((3 << 4) | 2) << 12); - - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */ - LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */ -#endif -} - - -/*---------------------------------------------------------------------------- - Measure frequency using frequency monitor - *----------------------------------------------------------------------------*/ -uint32_t MeasureFreq (uint32_t clk_sel) { - uint32_t fcnt, rcnt, fout; - - /* Set register values */ - LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */ - LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */ - LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */ - while (LPC_CGU->FREQ_MON & (1 << 23)) { - fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; - rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF; - if (fcnt == 0 && rcnt == 0) { - return (0); /* No input clock present */ - } - } - fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; - fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */ - - return (fout); -} - - -/*---------------------------------------------------------------------------- - Get PLL1 (divider and multiplier) parameters - *----------------------------------------------------------------------------*/ -static __inline uint32_t GetPLL1Param (void) { - uint32_t ctrl; - uint32_t p; - uint32_t div, mul; - - ctrl = LPC_CGU->PLL1_CTRL; - div = ((ctrl >> 12) & 0x03) + 1; - mul = ((ctrl >> 16) & 0xFF) + 1; - p = 1 << ((ctrl >> 8) & 0x03); - - if (ctrl & (1 << 1)) { - /* Bypass = 1, PLL1 input clock sent to post-dividers */ - if (ctrl & (1 << 7)) { - div *= (2*p); - } - } - else { - /* Direct and integer mode */ - if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) { - /* Non-integer mode */ - div *= (2*p); - } - } - return ((div << 8) | (mul)); -} - - -/*---------------------------------------------------------------------------- - Get input clock source for specified clock generation block - *----------------------------------------------------------------------------*/ -int32_t GetClkSel (uint32_t clk_src) { - uint32_t reg; - int32_t clk_sel = -1; - - switch (clk_src) { - case CLK_SRC_IRC: - case CLK_SRC_ENET_RX: - case CLK_SRC_ENET_TX: - case CLK_SRC_GP_CLKIN: - return (clk_src); - - case CLK_SRC_32KHZ: - return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ); - case CLK_SRC_XTAL: - return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL); - - case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break; - case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break; - case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break; - - case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break; - case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break; - case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break; - case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break; - case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break; - - default: - return (clk_sel); - } - if (!(reg & 1)) { - clk_sel = (reg >> 24) & 0x1F; - } - return (clk_sel); -} - - -/*---------------------------------------------------------------------------- - Get clock frequency for specified clock source - *----------------------------------------------------------------------------*/ -uint32_t GetClockFreq (uint32_t clk_src) { - uint32_t tmp; - uint32_t mul = 1; - uint32_t div = 1; - uint32_t main_freq = 0; - int32_t clk_sel = clk_src; - - do { - switch (clk_sel) { - case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break; - case CLK_SRC_IRC: main_freq = CLK_IRC; break; - case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break; - case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break; - case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break; - case CLK_SRC_XTAL: main_freq = CLK_XTAL; break; - - case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break; - case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break; - - case CLK_SRC_PLL0U: /* Not implemented */ break; - case CLK_SRC_PLL0A: /* Not implemented */ break; - - case CLK_SRC_PLL1: - tmp = GetPLL1Param (); - mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */ - div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */ - break; - - default: - return (0); /* Clock not running or not supported */ - } - if (main_freq == 0) { - clk_sel = GetClkSel (clk_sel); - } - } - while (main_freq == 0); - - return ((main_freq * mul) / div); -} - - -/*---------------------------------------------------------------------------- - System Core Clock update - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) { - /* Check BASE_M4_CLK connection */ - uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F; - - /* Update core clock frequency */ - SystemCoreClock = GetClockFreq (base_src); -} - - -extern uint32_t __Vectors; /* see startup_LPC43xx.s */ - -/*---------------------------------------------------------------------------- - Initialize the system - *----------------------------------------------------------------------------*/ -void SystemInit (void) { - - #if (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ - #endif - - /* Stop CM0 core */ - LPC_RGU->RESET_CTRL1 = (1 << 24); - - /* Disable SysTick timer */ - SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); - - /* Set vector table pointer */ - SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL; - - /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */ - SetClock(); - - /* Update SystemCoreClock variable */ - SystemCoreClockUpdate(); - - /* Configure External Memory Controller */ -//SystemInit_ExtMemCtl (); -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h deleted file mode 100644 index 146a2d4..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h +++ /dev/null @@ -1,2483 +0,0 @@ -/* -------------------------------------------------------------------------- - * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All - * rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 25. April 2016 - * $Revision: V2.2.1 - * - * Project: RTE Device Configuration for NXP LPC43xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -// USB0 Controller [Driver_USBD0 and Driver_USBH0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host -#define RTE_USB_USB0 1 - -// Pin Configuration -// USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3 -// VBUS drive signal (towards external charge pump or power management unit). -#define RTE_USB0_PPWR_ID 0 -#if (RTE_USB0_PPWR_ID == 0) - #define RTE_USB0_PPWR_PIN_EN 0 -#elif (RTE_USB0_PPWR_ID == 1) - #define RTE_USB0_PPWR_PORT 1 - #define RTE_USB0_PPWR_BIT 7 - #define RTE_USB0_PPWR_FUNC 4 -#elif (RTE_USB0_PPWR_ID == 2) - #define RTE_USB0_PPWR_PORT 2 - #define RTE_USB0_PPWR_BIT 0 - #define RTE_USB0_PPWR_FUNC 3 -#elif (RTE_USB0_PPWR_ID == 3) - #define RTE_USB0_PPWR_PORT 2 - #define RTE_USB0_PPWR_BIT 3 - #define RTE_USB0_PPWR_FUNC 7 -#elif (RTE_USB0_PPWR_ID == 4) - #define RTE_USB0_PPWR_PORT 6 - #define RTE_USB0_PPWR_BIT 3 - #define RTE_USB0_PPWR_FUNC 1 -#else - #error "Invalid RTE_USB0_PPWR Pin Configuration!" -#endif -#ifndef RTE_USB0_PPWR_PIN_EN - #define RTE_USB0_PPWR_PIN_EN 1 -#endif -// USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0 -// Port power fault signal indicating overcurrent condition. -// This signal monitors over-current on the USB bus -// (external circuitry required to detect over-current condition). -#define RTE_USB0_PWR_FAULT_ID 0 -#if (RTE_USB0_PWR_FAULT_ID == 0) - #define RTE_USB0_PWR_FAULT_PIN_EN 0 -#elif (RTE_USB0_PWR_FAULT_ID == 1) - #define RTE_USB0_PWR_FAULT_PORT 1 - #define RTE_USB0_PWR_FAULT_BIT 5 - #define RTE_USB0_PWR_FAULT_FUNC 4 -#elif (RTE_USB0_PWR_FAULT_ID == 2) - #define RTE_USB0_PWR_FAULT_PORT 2 - #define RTE_USB0_PWR_FAULT_BIT 1 - #define RTE_USB0_PWR_FAULT_FUNC 3 -#elif (RTE_USB0_PWR_FAULT_ID == 3) - #define RTE_USB0_PWR_FAULT_PORT 2 - #define RTE_USB0_PWR_FAULT_BIT 4 - #define RTE_USB0_PWR_FAULT_FUNC 7 -#elif (RTE_USB0_PWR_FAULT_ID == 4) - #define RTE_USB0_PWR_FAULT_PORT 6 - #define RTE_USB0_PWR_FAULT_BIT 6 - #define RTE_USB0_PWR_FAULT_FUNC 3 -#elif (RTE_USB0_PWR_FAULT_ID == 5) - #define RTE_USB0_PWR_FAULT_PORT 8 - #define RTE_USB0_PWR_FAULT_BIT 0 - #define RTE_USB0_PWR_FAULT_FUNC 1 -#else - #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!" -#endif -#ifndef RTE_USB0_PWR_FAULT_PIN_EN - #define RTE_USB0_PWR_FAULT_PIN_EN 1 -#endif -// USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2 -// USB0 port indicator LED control output 0 -#define RTE_USB0_IND0_ID 0 -#if (RTE_USB0_IND0_ID == 0) - #define RTE_USB0_IND0_PIN_EN 0 -#elif (RTE_USB0_IND0_ID == 1) - #define RTE_USB0_IND0_PORT 1 - #define RTE_USB0_IND0_BIT 4 - #define RTE_USB0_IND0_FUNC 4 -#elif (RTE_USB0_IND0_ID == 2) - #define RTE_USB0_IND0_PORT 2 - #define RTE_USB0_IND0_BIT 5 - #define RTE_USB0_IND0_FUNC 7 -#elif (RTE_USB0_IND0_ID == 3) - #define RTE_USB0_IND0_PORT 2 - #define RTE_USB0_IND0_BIT 6 - #define RTE_USB0_IND0_FUNC 3 -#elif (RTE_USB0_IND0_ID == 4) - #define RTE_USB0_IND0_PORT 6 - #define RTE_USB0_IND0_BIT 8 - #define RTE_USB0_IND0_FUNC 3 -#elif (RTE_USB0_IND0_ID == 5) - #define RTE_USB0_IND0_PORT 8 - #define RTE_USB0_IND0_BIT 2 - #define RTE_USB0_IND0_FUNC 1 -#else - #error "Invalid RTE_USB0_IND0 Pin Configuration!" -#endif -#ifndef RTE_USB0_IND0_PIN_EN - #define RTE_USB0_IND0_PIN_EN 1 -#endif -// USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1 -// USB0 port indicator LED control output 1 -#define RTE_USB0_IND1_ID 0 -#if (RTE_USB0_IND1_ID == 0) - #define RTE_USB0_IND1_PIN_EN 0 -#elif (RTE_USB0_IND1_ID == 1) - #define RTE_USB0_IND1_PORT 1 - #define RTE_USB0_IND1_BIT 3 - #define RTE_USB0_IND1_FUNC 4 -#elif (RTE_USB0_IND1_ID == 2) - #define RTE_USB0_IND1_PORT 2 - #define RTE_USB0_IND1_BIT 2 - #define RTE_USB0_IND1_FUNC 3 -#elif (RTE_USB0_IND1_ID == 3) - #define RTE_USB0_IND1_PORT 6 - #define RTE_USB0_IND1_BIT 7 - #define RTE_USB0_IND1_FUNC 3 -#elif (RTE_USB0_IND1_ID == 4) - #define RTE_USB0_IND1_PORT 8 - #define RTE_USB0_IND1_BIT 1 - #define RTE_USB0_IND1_FUNC 1 -#else - #error "Invalid RTE_USB0_IND1 Pin Configuration!" -#endif -#ifndef RTE_USB0_IND1_PIN_EN - #define RTE_USB0_IND1_PIN_EN 1 -#endif -// Pin Configuration - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -// High-speed -// Enable high-speed functionality -#define RTE_USB_USB0_HS_EN 1 -// Device [Driver_USBD0] -// USB0 Controller [Driver_USBD0 and Driver_USBH0] - -// USB1 Controller [Driver_USBD1 and Driver_USBH1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_USB1 0 - -// Pin Configuration -// USB1_PPWR (Host) <0=>Not used <1=>P9_5 -// VBUS drive signal (towards external charge pump or power management unit). -#define RTE_USB1_PPWR_ID 1 -#if (RTE_USB1_PPWR_ID == 0) - #define RTE_USB1_PPWR_PIN_EN 0 -#elif (RTE_USB1_PPWR_ID == 1) - #define RTE_USB1_PPWR_PORT 9 - #define RTE_USB1_PPWR_BIT 5 - #define RTE_USB1_PPWR_FUNC 2 -#else - #error "Invalid RTE_USB1_PPWR Pin Configuration!" -#endif -#ifndef RTE_USB1_PPWR_PIN_EN - #define RTE_USB1_PPWR_PIN_EN 1 -#endif -// USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6 -// Port power fault signal indicating overcurrent condition. -// This signal monitors over-current on the USB bus -// (external circuitry required to detect over-current condition). -#define RTE_USB1_PWR_FAULT_ID 1 -#if (RTE_USB1_PWR_FAULT_ID == 0) - #define RTE_USB1_PWR_FAULT_PIN_EN 0 -#elif (RTE_USB1_PWR_FAULT_ID == 1) - #define RTE_USB1_PWR_FAULT_PORT 9 - #define RTE_USB1_PWR_FAULT_BIT 6 - #define RTE_USB1_PWR_FAULT_FUNC 2 -#else - #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!" -#endif -#ifndef RTE_USB1_PWR_FAULT_PIN_EN - #define RTE_USB1_PWR_FAULT_PIN_EN 1 -#endif -// USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4 -// USB1 port indicator LED control output 0 -#define RTE_USB1_IND0_ID 1 -#if (RTE_USB1_IND0_ID == 0) - #define RTE_USB1_IND0_PIN_EN 0 -#elif (RTE_USB1_IND0_ID == 1) - #define RTE_USB1_IND0_PORT 3 - #define RTE_USB1_IND0_BIT 2 - #define RTE_USB1_IND0_FUNC 3 -#elif (RTE_USB1_IND0_ID == 2) - #define RTE_USB1_IND0_PORT 9 - #define RTE_USB1_IND0_BIT 4 - #define RTE_USB1_IND0_FUNC 2 -#else - #error "Invalid RTE_USB1_IND0 Pin Configuration!" -#endif -#ifndef RTE_USB1_IND0_PIN_EN - #define RTE_USB1_IND0_PIN_EN 1 -#endif -// USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3 -// USB1 port indicator LED control output 1 -#define RTE_USB1_IND1_ID 1 -#if (RTE_USB1_IND1_ID == 0) - #define RTE_USB1_IND1_PIN_EN 0 -#elif (RTE_USB1_IND1_ID == 1) - #define RTE_USB1_IND1_PORT 3 - #define RTE_USB1_IND1_BIT 1 - #define RTE_USB1_IND1_FUNC 3 -#elif (RTE_USB1_IND1_ID == 2) - #define RTE_USB1_IND1_PORT 9 - #define RTE_USB1_IND1_BIT 3 - #define RTE_USB1_IND1_FUNC 2 -#else - #error "Invalid RTE_USB1_IND1 Pin Configuration!" -#endif -#ifndef RTE_USB1_IND1_PIN_EN - #define RTE_USB1_IND1_PIN_EN 1 -#endif - -// On-chip full-speed PHY -#define RTE_USB_USB1_FS_PHY_EN 1 - -// USB1_VBUS (Device) <0=>Not used <1=>P2_5 -// Monitors the presence of USB1 bus power. -#define RTE_USB1_VBUS_ID 1 -#if (RTE_USB1_VBUS_ID == 0) - #define RTE_USB1_VBUS_PIN_EN 0 -#elif (RTE_USB1_VBUS_ID == 1) - #define RTE_USB1_VBUS_PORT 2 - #define RTE_USB1_VBUS_BIT 5 - #define RTE_USB1_VBUS_FUNC 2 -#else - #error "Invalid RTE_USB1_VBUS Pin Configuration!" -#endif -#ifndef RTE_USB1_VBUS_PIN_EN - #define RTE_USB1_VBUS_PIN_EN 1 -#endif -// On-chip full-speed PHY - -// External high-speed ULPI PHY (UTMI+ Low Pin Interface) -#define RTE_USB_USB1_HS_PHY_EN 0 - -// USB1_ULPI_CLK <0=>P8_8 <1=>PC_0 -// USB1 ULPI link CLK signal. -// 60 MHz clock generated by the PHY. -#define RTE_USB1_ULPI_CLK_ID 0 -#if (RTE_USB1_ULPI_CLK_ID == 0) - #define RTE_USB1_ULPI_CLK_PORT 8 - #define RTE_USB1_ULPI_CLK_BIT 8 - #define RTE_USB1_ULPI_CLK_FUNC 1 -#elif (RTE_USB1_ULPI_CLK_ID == 1) - #define RTE_USB1_ULPI_CLK_PORT 0xC - #define RTE_USB1_ULPI_CLK_BIT 0 - #define RTE_USB1_ULPI_CLK_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!" -#endif -// USB1_ULPI_DIR <0=>PB_1 <1=>PC_11 -// USB1 ULPI link DIR signal. -// Controls the ULPI data line direction. -#define RTE_USB1_ULPI_DIR_ID 0 -#if (RTE_USB1_ULPI_DIR_ID == 0) - #define RTE_USB1_ULPI_DIR_PORT 0xB - #define RTE_USB1_ULPI_DIR_BIT 1 - #define RTE_USB1_ULPI_DIR_FUNC 1 -#elif (RTE_USB1_ULPI_DIR_ID == 1) - #define RTE_USB1_ULPI_DIR_PORT 0xC - #define RTE_USB1_ULPI_DIR_BIT 11 - #define RTE_USB1_ULPI_DIR_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!" -#endif -// USB1_ULPI_STP <0=>P8_7 <1=>PC_10 -// USB1 ULPI link STP signal. -// Asserted to end or interrupt transfers to the PHY. -#define RTE_USB1_ULPI_STP_ID 0 -#if (RTE_USB1_ULPI_STP_ID == 0) - #define RTE_USB1_ULPI_STP_PORT 8 - #define RTE_USB1_ULPI_STP_BIT 7 - #define RTE_USB1_ULPI_STP_FUNC 1 -#elif (RTE_USB1_ULPI_STP_ID == 1) - #define RTE_USB1_ULPI_STP_PORT 0xC - #define RTE_USB1_ULPI_STP_BIT 10 - #define RTE_USB1_ULPI_STP_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!" -#endif -// USB1_ULPI_NXT <0=>P8_6 <1=>PC_9 -// USB1 ULPI link NXT signal. -// Data flow control signal from the PHY. -#define RTE_USB1_ULPI_NXT_ID 0 -#if (RTE_USB1_ULPI_NXT_ID == 0) - #define RTE_USB1_ULPI_NXT_PORT 8 - #define RTE_USB1_ULPI_NXT_BIT 6 - #define RTE_USB1_ULPI_NXT_FUNC 1 -#elif (RTE_USB1_ULPI_NXT_ID == 1) - #define RTE_USB1_ULPI_NXT_PORT 0xC - #define RTE_USB1_ULPI_NXT_BIT 9 - #define RTE_USB1_ULPI_NXT_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!" -#endif -// USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11 -// USB1 ULPI link bidirectional data line 0. -#define RTE_USB1_ULPI_D0_ID 0 -#if (RTE_USB1_ULPI_D0_ID == 0) - #define RTE_USB1_ULPI_D0_PORT 8 - #define RTE_USB1_ULPI_D0_BIT 5 - #define RTE_USB1_ULPI_D0_FUNC 1 -#elif (RTE_USB1_ULPI_D0_ID == 1) - #define RTE_USB1_ULPI_D0_PORT 0xC - #define RTE_USB1_ULPI_D0_BIT 8 - #define RTE_USB1_ULPI_D0_FUNC 1 -#elif (RTE_USB1_ULPI_D0_ID == 2) - #define RTE_USB1_ULPI_D0_PORT 0xD - #define RTE_USB1_ULPI_D0_BIT 11 - #define RTE_USB1_ULPI_D0_FUNC 5 -#else - #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!" -#endif -// USB1_ULPI_D1 <0=>P8_4 <1=>PC_7 -// USB1 ULPI link bidirectional data line 1. -#define RTE_USB1_ULPI_D1_ID 0 -#if (RTE_USB1_ULPI_D1_ID == 0) - #define RTE_USB1_ULPI_D1_PORT 8 - #define RTE_USB1_ULPI_D1_BIT 4 - #define RTE_USB1_ULPI_D1_FUNC 1 -#elif (RTE_USB1_ULPI_D1_ID == 1) - #define RTE_USB1_ULPI_D1_PORT 0xC - #define RTE_USB1_ULPI_D1_BIT 7 - #define RTE_USB1_ULPI_D1_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!" -#endif -// USB1_ULPI_D2 <0=>P8_3 <1=>PC_6 -// USB1 ULPI link bidirectional data line 2. -#define RTE_USB1_ULPI_D2_ID 0 -#if (RTE_USB1_ULPI_D2_ID == 0) - #define RTE_USB1_ULPI_D2_PORT 8 - #define RTE_USB1_ULPI_D2_BIT 3 - #define RTE_USB1_ULPI_D2_FUNC 1 -#elif (RTE_USB1_ULPI_D2_ID == 1) - #define RTE_USB1_ULPI_D2_PORT 0xC - #define RTE_USB1_ULPI_D2_BIT 6 - #define RTE_USB1_ULPI_D2_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!" -#endif -// USB1_ULPI_D3 <0=>PB_6 <1=>PC_5 -// USB1 ULPI link bidirectional data line 3. -#define RTE_USB1_ULPI_D3_ID 0 -#if (RTE_USB1_ULPI_D3_ID == 0) - #define RTE_USB1_ULPI_D3_PORT 0xB - #define RTE_USB1_ULPI_D3_BIT 6 - #define RTE_USB1_ULPI_D3_FUNC 1 -#elif (RTE_USB1_ULPI_D3_ID == 1) - #define RTE_USB1_ULPI_D3_PORT 0xC - #define RTE_USB1_ULPI_D3_BIT 5 - #define RTE_USB1_ULPI_D3_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!" -#endif -// USB1_ULPI_D4 <0=>PB_5 <1=>PC_4 -// USB1 ULPI link bidirectional data line 4. -#define RTE_USB1_ULPI_D4_ID 0 -#if (RTE_USB1_ULPI_D4_ID == 0) - #define RTE_USB1_ULPI_D4_PORT 0xB - #define RTE_USB1_ULPI_D4_BIT 5 - #define RTE_USB1_ULPI_D4_FUNC 1 -#elif (RTE_USB1_ULPI_D4_ID == 1) - #define RTE_USB1_ULPI_D4_PORT 0xC - #define RTE_USB1_ULPI_D4_BIT 4 - #define RTE_USB1_ULPI_D4_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!" -#endif -// USB1_ULPI_D5 <0=>PB_4 <1=>PC_3 -// USB1 ULPI link bidirectional data line 5. -#define RTE_USB1_ULPI_D5_ID 0 -#if (RTE_USB1_ULPI_D5_ID == 0) - #define RTE_USB1_ULPI_D5_PORT 0xB - #define RTE_USB1_ULPI_D5_BIT 4 - #define RTE_USB1_ULPI_D5_FUNC 1 -#elif (RTE_USB1_ULPI_D5_ID == 1) - #define RTE_USB1_ULPI_D5_PORT 0xC - #define RTE_USB1_ULPI_D5_BIT 3 - #define RTE_USB1_ULPI_D5_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!" -#endif -// USB1_ULPI_D6 <0=>PB_3 <1=>PC_2 -// USB1 ULPI link bidirectional data line 6. -#define RTE_USB1_ULPI_D6_ID 0 -#if (RTE_USB1_ULPI_D6_ID == 0) - #define RTE_USB1_ULPI_D6_PORT 0xB - #define RTE_USB1_ULPI_D6_BIT 3 - #define RTE_USB1_ULPI_D6_FUNC 1 -#elif (RTE_USB1_ULPI_D6_ID == 1) - #define RTE_USB1_ULPI_D6_PORT 0xC - #define RTE_USB1_ULPI_D6_BIT 2 - #define RTE_USB1_ULPI_D6_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!" -#endif -// USB1_ULPI_D7 <0=>PB_2 <1=>PC_1 -// USB1 ULPI link bidirectional data line 7. -#define RTE_USB1_ULPI_D7_ID 0 -#if (RTE_USB1_ULPI_D7_ID == 0) - #define RTE_USB1_ULPI_D7_PORT 0xB - #define RTE_USB1_ULPI_D7_BIT 2 - #define RTE_USB1_ULPI_D7_FUNC 1 -#elif (RTE_USB1_ULPI_D7_ID == 1) - #define RTE_USB1_ULPI_D7_PORT 0xC - #define RTE_USB1_ULPI_D7_BIT 1 - #define RTE_USB1_ULPI_D7_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!" -#endif -// External high-speed ULPI PHY (UTMI+ Low Pin Interface) -// Pin Configuration -// USB1 Controller [Driver_USBD1 and Driver_USBH1] - -// ENET (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ENET 0 - -// MII (Media Independent Interface) -#define RTE_ENET_MII 0 - -// ENET_TXD0 Pin <0=>P1_18 -#define RTE_ENET_MII_TXD0_PORT_ID 0 -#if (RTE_ENET_MII_TXD0_PORT_ID == 0) - #define RTE_ENET_MII_TXD0_PORT 1 - #define RTE_ENET_MII_TXD0_PIN 18 - #define RTE_ENET_MII_TXD0_FUNC 3 -#else - #error "Invalid ENET_TXD0 Pin Configuration!" -#endif -// ENET_TXD1 Pin <0=>P1_20 -#define RTE_ENET_MII_TXD1_PORT_ID 0 -#if (RTE_ENET_MII_TXD1_PORT_ID == 0) - #define RTE_ENET_MII_TXD1_PORT 1 - #define RTE_ENET_MII_TXD1_PIN 20 - #define RTE_ENET_MII_TXD1_FUNC 3 -#else - #error "Invalid ENET_TXD1 Pin Configuration!" -#endif -// ENET_TXD2 Pin <0=>P9_4 <1=>PC_2 -#define RTE_ENET_MII_TXD2_PORT_ID 0 -#if (RTE_ENET_MII_TXD2_PORT_ID == 0) - #define RTE_ENET_MII_TXD2_PORT 9 - #define RTE_ENET_MII_TXD2_PIN 4 - #define RTE_ENET_MII_TXD2_FUNC 5 -#elif (RTE_ENET_MII_TXD2_PORT_ID == 1) - #define RTE_ENET_MII_TXD2_PORT 0xC - #define RTE_ENET_MII_TXD2_PIN 2 - #define RTE_ENET_MII_TXD2_FUNC 3 -#else - #error "Invalid ENET_TXD2 Pin Configuration!" -#endif -// ENET_TXD3 Pin <0=>P9_5 <1=>PC_3 -#define RTE_ENET_MII_TXD3_PORT_ID 0 -#if (RTE_ENET_MII_TXD3_PORT_ID == 0) - #define RTE_ENET_MII_TXD3_PORT 9 - #define RTE_ENET_MII_TXD3_PIN 5 - #define RTE_ENET_MII_TXD3_FUNC 5 -#elif (RTE_ENET_MII_TXD3_PORT_ID == 1) - #define RTE_ENET_MII_TXD3_PORT 0xC - #define RTE_ENET_MII_TXD3_PIN 3 - #define RTE_ENET_MII_TXD3_FUNC 3 -#else - #error "Invalid ENET_TXD3 Pin Configuration!" -#endif -// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 -#define RTE_ENET_MII_TX_EN_PORT_ID 0 -#if (RTE_ENET_MII_TX_EN_PORT_ID == 0) - #define RTE_ENET_MII_TX_EN_PORT 0 - #define RTE_ENET_MII_TX_EN_PIN 1 - #define RTE_ENET_MII_TX_EN_FUNC 6 -#elif (RTE_ENET_MII_TX_EN_PORT_ID == 1) - #define RTE_ENET_MII_TX_EN_PORT 0xC - #define RTE_ENET_MII_TX_EN_PIN 4 - #define RTE_ENET_MII_TX_EN_FUNC 3 -#else - #error "Invalid ENET_TX_EN Pin Configuration!" -#endif -// ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0 -#define RTE_ENET_MII_TX_CLK_PORT_ID 0 -#if (RTE_ENET_MII_TX_CLK_PORT_ID == 0) - #define RTE_ENET_MII_TX_CLK_PORT 1 - #define RTE_ENET_MII_TX_CLK_PIN 19 - #define RTE_ENET_MII_TX_CLK_FUNC 0 -#elif (RTE_ENET_MII_TX_CLK_PORT_ID == 1) - #define RTE_ENET_MII_TX_CLK_PORT 0x10 - #define RTE_ENET_MII_TX_CLK_PIN 0 - #define RTE_ENET_MII_TX_CLK_FUNC 7 -#else - #error "Invalid ENET_TX_CLK Pin Configuration!" -#endif -// ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14 -// Optional signal, rarely used -#define RTE_ENET_MII_TX_ER_PORT_ID 0 -#if (RTE_ENET_MII_TX_ER_PORT_ID == 0) - #define RTE_ENET_MII_TX_ER_PIN_EN 0 -#elif (RTE_ENET_MII_TX_ER_PORT_ID == 1) - #define RTE_ENET_MII_TX_ER_PORT 0xC - #define RTE_ENET_MII_TX_ER_PIN 5 - #define RTE_ENET_MII_TX_ER_FUNC 3 -#elif (RTE_ENET_MII_TX_ER_PORT_ID == 2) - #define RTE_ENET_MII_TX_ER_PORT 0xC - #define RTE_ENET_MII_TX_ER_PIN 14 - #define RTE_ENET_MII_TX_ER_FUNC 6 -#else - #error "Invalid ENET_TX_ER Pin Configuration!" -#endif -#ifndef RTE_ENET_MII_TX_ER_PIN_EN - #define RTE_ENET_MII_TX_ER_PIN_EN 1 -#endif -// ENET_RXD0 Pin <0=>P1_15 -#define RTE_ENET_MII_RXD0_PORT_ID 0 -#if (RTE_ENET_MII_RXD0_PORT_ID == 0) - #define RTE_ENET_MII_RXD0_PORT 1 - #define RTE_ENET_MII_RXD0_PIN 15 - #define RTE_ENET_MII_RXD0_FUNC 3 -#else - #error "Invalid ENET_RXD0 Pin Configuration!" -#endif -// ENET_RXD1 Pin <0=>P0_0 -#define RTE_ENET_MII_RXD1_PORT_ID 0 -#if (RTE_ENET_MII_RXD1_PORT_ID == 0) - #define RTE_ENET_MII_RXD1_PORT 0 - #define RTE_ENET_MII_RXD1_PIN 0 - #define RTE_ENET_MII_RXD1_FUNC 2 -#else - #error "Invalid ENET_RXD1 Pin Configuration!" -#endif -// ENET_RXD2 Pin <0=>P9_3 <1=>PC_6 -#define RTE_ENET_MII_RXD2_PORT_ID 0 -#if (RTE_ENET_MII_RXD2_PORT_ID == 0) - #define RTE_ENET_MII_RXD2_PORT 9 - #define RTE_ENET_MII_RXD2_PIN 3 - #define RTE_ENET_MII_RXD2_FUNC 5 -#elif (RTE_ENET_MII_RXD2_PORT_ID == 1) - #define RTE_ENET_MII_RXD2_PORT 0xC - #define RTE_ENET_MII_RXD2_PIN 6 - #define RTE_ENET_MII_RXD2_FUNC 3 -#else - #error "Invalid ENET_RXD2 Pin Configuration!" -#endif -// ENET_RXD3 Pin <0=>P9_2 <1=>PC_7 -#define RTE_ENET_MII_RXD3_PORT_ID 0 -#if (RTE_ENET_MII_RXD3_PORT_ID == 0) - #define RTE_ENET_MII_RXD3_PORT 9 - #define RTE_ENET_MII_RXD3_PIN 2 - #define RTE_ENET_MII_RXD3_FUNC 5 -#elif (RTE_ENET_MII_RXD3_PORT_ID == 1) - #define RTE_ENET_MII_RXD3_PORT 0xC - #define RTE_ENET_MII_RXD3_PIN 7 - #define RTE_ENET_MII_RXD3_FUNC 3 -#else - #error "Invalid ENET_RXD3 Pin Configuration!" -#endif -// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 -#define RTE_ENET_MII_RX_DV_PORT_ID 0 -#if (RTE_ENET_MII_RX_DV_PORT_ID == 0) - #define RTE_ENET_MII_RX_DV_PORT 1 - #define RTE_ENET_MII_RX_DV_PIN 16 - #define RTE_ENET_MII_RX_DV_FUNC 7 -#elif (RTE_ENET_MII_RX_DV_PORT_ID == 1) - #define RTE_ENET_MII_RX_DV_PORT 0xC - #define RTE_ENET_MII_RX_DV_PIN 8 - #define RTE_ENET_MII_RX_DV_FUNC 3 -#else - #error "Invalid ENET_RX_DV Pin Configuration!" -#endif -// ENET_RX_CLK Pin <0=>PC_0 -#define RTE_ENET_MII_RX_CLK_PORT_ID 0 -#if (RTE_ENET_MII_RX_CLK_PORT_ID == 0) - #define RTE_ENET_MII_RX_CLK_PORT 0xC - #define RTE_ENET_MII_RX_CLK_PIN 0 - #define RTE_ENET_MII_RX_CLK_FUNC 3 -#else - #error "Invalid ENET_RX_CLK Pin Configuration!" -#endif -// ENET_RX_ER Pin <0=>P9_1 <1=>PC_9 -#define RTE_ENET_MII_RX_ER_PORT_ID 0 -#if (RTE_ENET_MII_RX_ER_PORT_ID == 0) - #define RTE_ENET_MII_RX_ER_PORT 9 - #define RTE_ENET_MII_RX_ER_PIN 1 - #define RTE_ENET_MII_RX_ER_FUNC 5 -#elif (RTE_ENET_MII_RX_ER_PORT_ID == 1) - #define RTE_ENET_MII_RX_ER_PORT 0xC - #define RTE_ENET_MII_RX_ER_PIN 9 - #define RTE_ENET_MII_RX_ER_FUNC 3 -#else - #error "Invalid ENET_RX_ER Pin Configuration!" -#endif -// ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6 -#define RTE_ENET_MII_COL_PORT_ID 0 -#if (RTE_ENET_MII_COL_PORT_ID == 0) - #define RTE_ENET_MII_COL_PORT 0 - #define RTE_ENET_MII_COL_PIN 1 - #define RTE_ENET_MII_COL_FUNC 2 -#elif (RTE_ENET_MII_COL_PORT_ID == 1) - #define RTE_ENET_MII_COL_PORT 4 - #define RTE_ENET_MII_COL_PIN 1 - #define RTE_ENET_MII_COL_FUNC 7 -#elif (RTE_ENET_MII_COL_PORT_ID == 2) - #define RTE_ENET_MII_COL_PORT 9 - #define RTE_ENET_MII_COL_PIN 6 - #define RTE_ENET_MII_COL_FUNC 5 -#else - #error "Invalid ENET_COL Pin Configuration!" -#endif -// ENET_CRS Pin <0=>P1_16 <1=>P9_0 -#define RTE_ENET_MII_CRS_PORT_ID 0 -#if (RTE_ENET_MII_CRS_PORT_ID == 0) - #define RTE_ENET_MII_CRS_PORT 1 - #define RTE_ENET_MII_CRS_PIN 16 - #define RTE_ENET_MII_CRS_FUNC 3 -#elif (RTE_ENET_MII_CRS_PORT_ID == 1) - #define RTE_ENET_MII_CRS_PORT 9 - #define RTE_ENET_MII_CRS_PIN 0 - #define RTE_ENET_MII_CRS_FUNC 5 -#else - #error "Invalid ENET_CRS Pin Configuration!" -#endif -// MII (Media Independent Interface) - -// RMII (Reduced Media Independent Interface) -#define RTE_ENET_RMII 0 - -// ENET_TXD0 Pin <0=>P1_18 -#define RTE_ENET_RMII_TXD0_PORT_ID 0 -#if (RTE_ENET_RMII_TXD0_PORT_ID == 0) - #define RTE_ENET_RMII_TXD0_PORT 1 - #define RTE_ENET_RMII_TXD0_PIN 18 - #define RTE_ENET_RMII_TXD0_FUNC 3 -#else - #error "Invalid ENET_TXD0 Pin Configuration!" -#endif -// ENET_TXD1 Pin <0=>P1_20 -#define RTE_ENET_RMII_TXD1_PORT_ID 0 -#if (RTE_ENET_RMII_TXD1_PORT_ID == 0) - #define RTE_ENET_RMII_TXD1_PORT 1 - #define RTE_ENET_RMII_TXD1_PIN 20 - #define RTE_ENET_RMII_TXD1_FUNC 3 -#else - #error "Invalid ENET_TXD1 Pin Configuration!" -#endif -// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 -#define RTE_ENET_RMII_TX_EN_PORT_ID 0 -#if (RTE_ENET_RMII_TX_EN_PORT_ID == 0) - #define RTE_ENET_RMII_TX_EN_PORT 0 - #define RTE_ENET_RMII_TX_EN_PIN 1 - #define RTE_ENET_RMII_TX_EN_FUNC 6 -#elif (RTE_ENET_RMII_TX_EN_PORT_ID == 1) - #define RTE_ENET_RMII_TX_EN_PORT 0xC - #define RTE_ENET_RMII_TX_EN_PIN 4 - #define RTE_ENET_RMII_TX_EN_FUNC 3 -#else - #error "Invalid ENET_TX_EN Pin Configuration!" -#endif -// ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0 -#define RTE_ENET_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0) - #define RTE_ENET_RMII_REF_CLK_PORT 1 - #define RTE_ENET_RMII_REF_CLK_PIN 19 - #define RTE_ENET_RMII_REF_CLK_FUNC 0 -#elif (RTE_ENET_RMII_REF_CLK_PORT_ID == 1) - #define RTE_ENET_RMII_REF_CLK_PORT 0x10 - #define RTE_ENET_RMII_REF_CLK_PIN 0 - #define RTE_ENET_RMII_REF_CLK_FUNC 7 -#else - #error "Invalid ENET_REF_CLK Pin Configuration!" -#endif -// ENET_RXD0 Pin <0=>P1_15 -#define RTE_ENET_RMII_RXD0_PORT_ID 0 -#if (RTE_ENET_RMII_RXD0_PORT_ID == 0) - #define RTE_ENET_RMII_RXD0_PORT 1 - #define RTE_ENET_RMII_RXD0_PIN 15 - #define RTE_ENET_RMII_RXD0_FUNC 3 -#else - #error "Invalid ENET_RXD0 Pin Configuration!" -#endif -// ENET_RXD1 Pin <0=>P0_0 -#define RTE_ENET_RMII_RXD1_PORT_ID 0 -#if (RTE_ENET_RMII_RXD1_PORT_ID == 0) - #define RTE_ENET_RMII_RXD1_PORT 0 - #define RTE_ENET_RMII_RXD1_PIN 0 - #define RTE_ENET_RMII_RXD1_FUNC 2 -#else - #error "Invalid ENET_RXD1 Pin Configuration!" -#endif -// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 -#define RTE_ENET_RMII_RX_DV_PORT_ID 0 -#if (RTE_ENET_RMII_RX_DV_PORT_ID == 0) - #define RTE_ENET_RMII_RX_DV_PORT 1 - #define RTE_ENET_RMII_RX_DV_PIN 16 - #define RTE_ENET_RMII_RX_DV_FUNC 7 -#elif (RTE_ENET_RMII_RX_DV_PORT_ID == 1) - #define RTE_ENET_RMII_RX_DV_PORT 0xC - #define RTE_ENET_RMII_RX_DV_PIN 8 - #define RTE_ENET_RMII_RX_DV_FUNC 3 -#else - #error "Invalid ENET_RX_DV Pin Configuration!" -#endif -// RMII (Reduced Media Independent Interface) - -// MIIM (Management Data Interface) -// ENET_MDIO Pin <0=>P1_17 -#define RTE_ENET_MDI_MDIO_PORT_ID 0 -#if (RTE_ENET_MDI_MDIO_PORT_ID == 0) - #define RTE_ENET_MDI_MDIO_PORT 1 - #define RTE_ENET_MDI_MDIO_PIN 17 - #define RTE_ENET_MDI_MDIO_FUNC 3 -#else - #error "Invalid ENET_MDIO Pin Configuration!" -#endif -// ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1 -#define RTE_ENET_MDI_MDC_PORT_ID 2 -#if (RTE_ENET_MDI_MDC_PORT_ID == 0) - #define RTE_ENET_MDI_MDC_PORT 2 - #define RTE_ENET_MDI_MDC_PIN 0 - #define RTE_ENET_MDI_MDC_FUNC 7 -#elif (RTE_ENET_MDI_MDC_PORT_ID == 1) - #define RTE_ENET_MDI_MDC_PORT 7 - #define RTE_ENET_MDI_MDC_PIN 7 - #define RTE_ENET_MDI_MDC_FUNC 6 -#elif (RTE_ENET_MDI_MDC_PORT_ID == 2) - #define RTE_ENET_MDI_MDC_PORT 0xC - #define RTE_ENET_MDI_MDC_PIN 1 - #define RTE_ENET_MDI_MDC_FUNC 3 -#else - #error "Invalid ENET_MDC Pin Configuration!" -#endif -// MIIM (Management Data Interface) -// ENET (Ethernet Interface) [Driver_ETH_MAC0] - -// SD/MMC Interface [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDMMC 0 - -// SD/MMC Peripheral Bus -// SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2 -#define RTE_SD_CLK_PORT_ID 0 -#if (RTE_SD_CLK_PORT_ID == 0) - #define RTE_SD_CLK_PORT 0xC - #define RTE_SD_CLK_PIN 0 - #define RTE_SD_CLK_FUNC 7 -#elif (RTE_SD_CLK_PORT_ID == 1) - #define RTE_SD_CLK_PORT 0x10 - #define RTE_SD_CLK_PIN 0 - #define RTE_SD_CLK_FUNC 4 -#elif (RTE_SD_CLK_PORT_ID == 2) - #define RTE_SD_CLK_PORT 0x10 - #define RTE_SD_CLK_PIN 2 - #define RTE_SD_CLK_FUNC 4 -#else - #error "Invalid SD_CLK Pin Configuration!" -#endif -// SD_CMD Pin <0=>P1_6 <1=>PC_10 -#define RTE_SD_CMD_PORT_ID 0 -#if (RTE_SD_CMD_PORT_ID == 0) - #define RTE_SD_CMD_PORT 1 - #define RTE_SD_CMD_PIN 6 - #define RTE_SD_CMD_FUNC 7 -#elif (RTE_SD_CMD_PORT_ID == 1) - #define RTE_SD_CMD_PORT 0xC - #define RTE_SD_CMD_PIN 10 - #define RTE_SD_CMD_FUNC 7 -#else - #error "Invalid SD_CMD Pin Configuration!" -#endif -// SD_DAT0 Pin <0=>P1_9 <1=>PC_4 -#define RTE_SD_DAT0_PORT_ID 0 -#if (RTE_SD_DAT0_PORT_ID == 0) - #define RTE_SD_DAT0_PORT 1 - #define RTE_SD_DAT0_PIN 9 - #define RTE_SD_DAT0_FUNC 7 -#elif (RTE_SD_DAT0_PORT_ID == 1) - #define RTE_SD_DAT0_PORT 0xC - #define RTE_SD_DAT0_PIN 4 - #define RTE_SD_DAT0_FUNC 7 -#else - #error "Invalid SD_DAT0 Pin Configuration!" -#endif -// SD_DAT[1 .. 3] -#define RTE_SDMMC_BUS_WIDTH_4 0 -// SD_DAT1 Pin <0=>P1_10 <1=>PC_5 -#define RTE_SD_DAT1_PORT_ID 0 -#if (RTE_SD_DAT1_PORT_ID == 0) - #define RTE_SD_DAT1_PORT 1 - #define RTE_SD_DAT1_PIN 10 - #define RTE_SD_DAT1_FUNC 7 -#elif (RTE_SD_DAT1_PORT_ID == 1) - #define RTE_SD_DAT1_PORT 0xC - #define RTE_SD_DAT1_PIN 5 - #define RTE_SD_DAT1_FUNC 7 -#else - #error "Invalid SD_DAT1 Pin Configuration!" -#endif -// SD_DAT2 Pin <0=>P1_11 <1=>PC_6 -#define RTE_SD_DAT2_PORT_ID 0 -#if (RTE_SD_DAT2_PORT_ID == 0) - #define RTE_SD_DAT2_PORT 1 - #define RTE_SD_DAT2_PIN 11 - #define RTE_SD_DAT2_FUNC 7 -#elif (RTE_SD_DAT2_PORT_ID == 1) - #define RTE_SD_DAT2_PORT 0xC - #define RTE_SD_DAT2_PIN 6 - #define RTE_SD_DAT2_FUNC 7 -#else - #error "Invalid SD_DAT2 Pin Configuration!" -#endif -// SD_DAT3 Pin <0=>P1_12 <1=>PC_7 -#define RTE_SD_DAT3_PORT_ID 0 -#if (RTE_SD_DAT3_PORT_ID == 0) - #define RTE_SD_DAT3_PORT 1 - #define RTE_SD_DAT3_PIN 12 - #define RTE_SD_DAT3_FUNC 7 -#elif (RTE_SD_DAT3_PORT_ID == 1) - #define RTE_SD_DAT3_PORT 0xC - #define RTE_SD_DAT3_PIN 7 - #define RTE_SD_DAT3_FUNC 7 -#else - #error "Invalid SD_DAT3 Pin Configuration!" -#endif -// SD_DAT[1 .. 3] -// SD_DAT[4 .. 7] -#define RTE_SDMMC_BUS_WIDTH_8 0 -// SD_DAT4 Pin <0=>PC_11 -#define RTE_SD_DAT4_PORT_ID 0 -#if (RTE_SD_DAT4_PORT_ID == 0) - #define RTE_SD_DAT4_PORT 0xC - #define RTE_SD_DAT4_PIN 11 - #define RTE_SD_DAT4_FUNC 7 -#else - #error "Invalid SD_DAT4 Pin Configuration!" -#endif -// SD_DAT5 Pin <0=>PC_12 -#define RTE_SD_DAT5_PORT_ID 0 -#if (RTE_SD_DAT5_PORT_ID == 0) - #define RTE_SD_DAT5_PORT 0xC - #define RTE_SD_DAT5_PIN 12 - #define RTE_SD_DAT5_FUNC 7 -#else - #error "Invalid SD_DAT5 Pin Configuration!" -#endif -// SD_DAT6 Pin <0=>PC_13 -#define RTE_SD_DAT6_PORT_ID 0 -#if (RTE_SD_DAT6_PORT_ID == 0) - #define RTE_SD_DAT6_PORT 0xC - #define RTE_SD_DAT6_PIN 13 - #define RTE_SD_DAT6_FUNC 7 -#else - #error "Invalid SD_DAT6 Pin Configuration!" -#endif -// SD_DAT7 Pin <0=>PC_14 -#define RTE_SD_DAT7_PORT_ID 0 -#if (RTE_SD_DAT7_PORT_ID == 0) - #define RTE_SD_DAT7_PORT 0xC - #define RTE_SD_DAT7_PIN 14 - #define RTE_SD_DAT7_FUNC 7 -#else - #error "Invalid SD_DAT7 Pin Configuration!" -#endif -// SD_DAT[4 .. 7] -// SD/MMC Peripheral Bus - -// SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8 -// Configure Pin if exists -#define RTE_SD_CD_PORT_ID 0 -#if (RTE_SD_CD_PORT_ID == 0) - #define RTE_SD_CD_PIN_EN 0 -#elif (RTE_SD_CD_PORT_ID == 1) - #define RTE_SD_CD_PORT 1 - #define RTE_SD_CD_PIN 13 - #define RTE_SD_CD_FUNC 7 -#elif (RTE_SD_CD_PORT_ID == 2) - #define RTE_SD_CD_PORT 0xC - #define RTE_SD_CD_PIN 8 - #define RTE_SD_CD_FUNC 7 -#else - #error "Invalid SD_CD Pin Configuration!" -#endif -#ifndef RTE_SD_CD_PIN_EN - #define RTE_SD_CD_PIN_EN 1 -#endif -// SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10 -// Configure Pin if exists -#define RTE_SD_WP_PORT_ID 0 -#if (RTE_SD_WP_PORT_ID == 0) - #define RTE_SD_WP_PIN_EN 0 -#elif (RTE_SD_WP_PORT_ID == 1) - #define RTE_SD_WP_PORT 0xD - #define RTE_SD_WP_PIN 15 - #define RTE_SD_WP_FUNC 5 -#elif (RTE_SD_WP_PORT_ID == 2) - #define RTE_SD_WP_PORT 0xF - #define RTE_SD_WP_PIN 10 - #define RTE_SD_WP_FUNC 6 -#else - #error "Invalid SD_WP Pin Configuration!" -#endif -#ifndef RTE_SD_WP_PIN_EN - #define RTE_SD_WP_PIN_EN 1 -#endif -// SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1 -// Configure Pin if exists -#define RTE_SD_POW_PORT_ID 0 -#if (RTE_SD_POW_PORT_ID == 0) - #define RTE_SD_POW_PIN_EN 0 -#elif (RTE_SD_POW_PORT_ID == 1) - #define RTE_SD_POW_PORT 1 - #define RTE_SD_POW_PIN 5 - #define RTE_SD_POW_FUNC 7 -#elif (RTE_SD_POW_PORT_ID == 2) - #define RTE_SD_POW_PORT 0xC - #define RTE_SD_POW_PIN 9 - #define RTE_SD_POW_FUNC 7 -#elif (RTE_SD_POW_PORT_ID == 3) - #define RTE_SD_POW_PORT 0xD - #define RTE_SD_POW_PIN 1 - #define RTE_SD_POW_FUNC 5 -#else - #error "Invalid SD_POW Pin Configuration!" -#endif -#ifndef RTE_SD_POW_PIN_EN - #define RTE_SD_POW_PIN_EN 1 -#endif -// SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2 -// Configure Pin if exists -#define RTE_SD_RST_PORT_ID 0 -#if (RTE_SD_RST_PORT_ID == 0) - #define RTE_SD_RST_PIN_EN 0 -#elif (RTE_SD_RST_PORT_ID == 1) - #define RTE_SD_RST_PORT 1 - #define RTE_SD_RST_PIN 3 - #define RTE_SD_RST_FUNC 7 -#elif (RTE_SD_RST_PORT_ID == 2) - #define RTE_SD_RST_PORT 0xC - #define RTE_SD_RST_PIN 2 - #define RTE_SD_RST_FUNC 7 -#else - #error "Invalid SD_RST Pin Configuration!" -#endif -#ifndef RTE_SD_RST_PIN_EN - #define RTE_SD_RST_PIN_EN 1 -#endif -// SD/MMC Interface [Driver_MCI0] - -// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] -// Configuration settings for Driver_I2C0 in component ::Drivers:I2C -// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] -#define RTE_I2C0 0 - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>P2_4 <1=>PE_15 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) - #define RTE_I2C1_SCL_PORT 2 - #define RTE_I2C1_SCL_PIN 4 - #define RTE_I2C1_SCL_FUNC 1 -#elif (RTE_I2C1_SCL_PORT_ID == 1) - #define RTE_I2C1_SCL_PORT 0xE - #define RTE_I2C1_SCL_PIN 15 - #define RTE_I2C1_SCL_FUNC 2 -#else - #error "Invalid I2C1_SCL Pin Configuration!" -#endif -// I2C1_SDA Pin <0=>P2_3 <1=>PE_13 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) - #define RTE_I2C1_SDA_PORT 2 - #define RTE_I2C1_SDA_PIN 3 - #define RTE_I2C1_SDA_FUNC 1 -#elif (RTE_I2C1_SDA_PORT_ID == 1) - #define RTE_I2C1_SDA_PORT 0xE - #define RTE_I2C1_SDA_PIN 13 - #define RTE_I2C1_SDA_FUNC 2 -#else - #error "Invalid I2C1_SDA Pin Configuration!" -#endif -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -#define RTE_USART0 1 - -// Pin Configuration -// TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10 -// USART0 Serial Output pin -#define RTE_USART0_TX_ID 1 -#if (RTE_USART0_TX_ID == 0) - #define RTE_USART0_TX_PIN_EN 0 -#elif (RTE_USART0_TX_ID == 1) - #define RTE_USART0_TX_PORT 2 - #define RTE_USART0_TX_BIT 0 - #define RTE_USART0_TX_FUNC 1 -#elif (RTE_USART0_TX_ID == 2) - #define RTE_USART0_TX_PORT 6 - #define RTE_USART0_TX_BIT 4 - #define RTE_USART0_TX_FUNC 2 -#elif (RTE_USART0_TX_ID == 3) - #define RTE_USART0_TX_PORT 9 - #define RTE_USART0_TX_BIT 5 - #define RTE_USART0_TX_FUNC 7 -#elif (RTE_USART0_TX_ID == 4) - #define RTE_USART0_TX_PORT 0xF - #define RTE_USART0_TX_BIT 10 - #define RTE_USART0_TX_FUNC 1 -#else - #error "Invalid USART0_TX Pin Configuration!" -#endif -#ifndef RTE_USART0_TX_PIN_EN - #define RTE_USART0_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11 -// USART0 Serial Input pin -#define RTE_USART0_RX_ID 1 -#if (RTE_USART0_RX_ID == 0) - #define RTE_USART0_RX_PIN_EN 0 -#elif (RTE_USART0_RX_ID == 1) - #define RTE_USART0_RX_PORT 2 - #define RTE_USART0_RX_BIT 1 - #define RTE_USART0_RX_FUNC 1 -#elif (RTE_USART0_RX_ID == 2) - #define RTE_USART0_RX_PORT 6 - #define RTE_USART0_RX_BIT 5 - #define RTE_USART0_RX_FUNC 2 -#elif (RTE_USART0_RX_ID == 3) - #define RTE_USART0_RX_PORT 9 - #define RTE_USART0_RX_BIT 6 - #define RTE_USART0_RX_FUNC 7 -#elif (RTE_USART0_RX_ID == 4) - #define RTE_USART0_RX_PORT 0xF - #define RTE_USART0_RX_BIT 11 - #define RTE_USART0_RX_FUNC 1 -#else - #error "Invalid USART0_RX Pin Configuration!" -#endif -#ifndef RTE_USART0_RX_PIN_EN - #define RTE_USART0_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8 -// USART0 Serial Clock input/output synchronous mode -#define RTE_USART0_UCLK_ID 0 -#if (RTE_USART0_UCLK_ID == 0) - #define RTE_USART0_UCLK_PIN_EN 0 -#elif (RTE_USART0_UCLK_ID == 1) - #define RTE_USART0_UCLK_PORT 2 - #define RTE_USART0_UCLK_BIT 2 - #define RTE_USART0_UCLK_FUNC 1 -#elif (RTE_USART0_UCLK_ID == 2) - #define RTE_USART0_UCLK_PORT 6 - #define RTE_USART0_UCLK_BIT 1 - #define RTE_USART0_UCLK_FUNC 2 -#elif (RTE_USART0_UCLK_ID == 3) - #define RTE_USART0_UCLK_PORT 0xF - #define RTE_USART0_UCLK_BIT 8 - #define RTE_USART0_UCLK_FUNC 1 -#else - #error "Invalid USART0_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART0_UCLK_PIN_EN - #define RTE_USART0_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>1 (DMAMUXPER1) <1=>11 (DMAMUXPER11) -// -#define RTE_USART0_DMA_TX_EN 0 -#define RTE_USART0_DMA_TX_CH 0 -#define RTE_USART0_DMA_TX_PERI_ID 0 -#if (RTE_USART0_DMA_TX_PERI_ID == 0) - #define RTE_USART0_DMA_TX_PERI 1 - #define RTE_USART0_DMA_TX_PERI_SEL 1 -#elif (RTE_USART0_DMA_TX_PERI_ID == 1) - #define RTE_USART0_DMA_TX_PERI 11 - #define RTE_USART0_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>2 (DMAMUXPER2) <1=>12 (DMAMUXPER12) -// -#define RTE_USART0_DMA_RX_EN 0 -#define RTE_USART0_DMA_RX_CH 1 -#define RTE_USART0_DMA_RX_PERI_ID 0 -#if (RTE_USART0_DMA_RX_PERI_ID == 0) - #define RTE_USART0_DMA_RX_PERI 2 - #define RTE_USART0_DMA_RX_PERI_SEL 1 -#elif (RTE_USART0_DMA_RX_PERI_ID == 1) - #define RTE_USART0_DMA_RX_PERI 12 - #define RTE_USART0_DMA_RX_PERI_SEL 2 -#endif -// DMA -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] - -// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] -#define RTE_UART1 1 - -// Pin Configuration -// TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11 -// UART0 Serial Output pin -#define RTE_UART1_TX_ID 0 -#if (RTE_UART1_TX_ID == 0) - #define RTE_UART1_TX_PIN_EN 0 -#elif (RTE_UART1_TX_ID == 1) - #define RTE_UART1_TX_PORT 1 - #define RTE_UART1_TX_BIT 13 - #define RTE_UART1_TX_FUNC 1 -#elif (RTE_UART1_TX_ID == 2) - #define RTE_UART1_TX_PORT 3 - #define RTE_UART1_TX_BIT 4 - #define RTE_UART1_TX_FUNC 4 -#elif (RTE_UART1_TX_ID == 3) - #define RTE_UART1_TX_PORT 5 - #define RTE_UART1_TX_BIT 6 - #define RTE_UART1_TX_FUNC 4 -#elif (RTE_UART1_TX_ID == 4) - #define RTE_UART1_TX_PORT 0xC - #define RTE_UART1_TX_BIT 13 - #define RTE_UART1_TX_FUNC 2 -#elif (RTE_UART1_TX_ID == 5) - #define RTE_UART1_TX_PORT 0xE - #define RTE_UART1_TX_BIT 11 - #define RTE_UART1_TX_FUNC 2 -#else - #error "Invalid UART1_TX Pin Configuration!" -#endif -#ifndef RTE_UART1_TX_PIN_EN - #define RTE_UART1_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12 -// UART1 Serial Input pin -#define RTE_UART1_RX_ID 1 -#if (RTE_UART1_RX_ID == 0) - #define RTE_UART1_RX_PIN_EN 0 -#elif (RTE_UART1_RX_ID == 1) - #define RTE_UART1_RX_PORT 1 - #define RTE_UART1_RX_BIT 14 - #define RTE_UART1_RX_FUNC 1 -#elif (RTE_UART1_RX_ID == 2) - #define RTE_UART1_RX_PORT 3 - #define RTE_UART1_RX_BIT 5 - #define RTE_UART1_RX_FUNC 4 -#elif (RTE_UART1_RX_ID == 3) - #define RTE_UART1_RX_PORT 5 - #define RTE_UART1_RX_BIT 7 - #define RTE_UART1_RX_FUNC 4 -#elif (RTE_UART1_RX_ID == 4) - #define RTE_UART1_RX_PORT 0xC - #define RTE_UART1_RX_BIT 14 - #define RTE_UART1_RX_FUNC 2 -#elif (RTE_UART1_RX_ID == 5) - #define RTE_UART1_RX_PORT 0xE - #define RTE_UART1_RX_BIT 12 - #define RTE_UART1_RX_FUNC 2 -#else - #error "Invalid UART1_RX Pin Configuration!" -#endif -#ifndef RTE_UART1_RX_PIN_EN - #define RTE_UART1_RX_PIN_EN 1 -#endif - -// Modem Lines -// CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7 -#define RTE_UART1_CTS_ID 0 -#if (RTE_UART1_CTS_ID == 0) - #define RTE_UART1_CTS_PIN_EN 0 -#elif (RTE_UART1_CTS_ID == 1) - #define RTE_UART1_CTS_PORT 1 - #define RTE_UART1_CTS_BIT 11 - #define RTE_UART1_CTS_FUNC 1 -#elif (RTE_UART1_CTS_ID == 2) - #define RTE_UART1_CTS_PORT 5 - #define RTE_UART1_CTS_BIT 4 - #define RTE_UART1_CTS_FUNC 4 -#elif (RTE_UART1_CTS_ID == 3) - #define RTE_UART1_CTS_PORT 0xC - #define RTE_UART1_CTS_BIT 2 - #define RTE_UART1_CTS_FUNC 2 -#elif (RTE_UART1_CTS_ID == 4) - #define RTE_UART1_CTS_PORT 0xE - #define RTE_UART1_CTS_BIT 7 - #define RTE_UART1_CTS_FUNC 2 -#else - #error "Invalid UART1_CTS Pin Configuration!" -#endif -#ifndef RTE_UART1_CTS_PIN_EN - #define RTE_UART1_CTS_PIN_EN 1 -#endif -// RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5 -#define RTE_UART1_RTS_ID 0 -#if (RTE_UART1_RTS_ID == 0) - #define RTE_UART1_RTS_PIN_EN 0 -#elif (RTE_UART1_RTS_ID == 1) - #define RTE_UART1_RTS_PORT 1 - #define RTE_UART1_RTS_BIT 9 - #define RTE_UART1_RTS_FUNC 1 -#elif (RTE_UART1_RTS_ID == 2) - #define RTE_UART1_RTS_PORT 5 - #define RTE_UART1_RTS_BIT 2 - #define RTE_UART1_RTS_FUNC 4 -#elif (RTE_UART1_RTS_ID == 3) - #define RTE_UART1_RTS_PORT 0xC - #define RTE_UART1_RTS_BIT 3 - #define RTE_UART1_RTS_FUNC 2 -#elif (RTE_UART1_RTS_ID == 4) - #define RTE_UART1_RTS_PORT 0xE - #define RTE_UART1_RTS_BIT 5 - #define RTE_UART1_RTS_FUNC 2 -#else - #error "Invalid UART1_RTS Pin Configuration!" -#endif -#ifndef RTE_UART1_RTS_PIN_EN - #define RTE_UART1_RTS_PIN_EN 1 -#endif -// DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9 -#define RTE_UART1_DCD_ID 0 -#if (RTE_UART1_DCD_ID == 0) - #define RTE_UART1_DCD_PIN_EN 0 -#elif (RTE_UART1_DCD_ID == 1) - #define RTE_UART1_DCD_PORT 1 - #define RTE_UART1_DCD_BIT 12 - #define RTE_UART1_DCD_FUNC 1 -#elif (RTE_UART1_DCD_ID == 2) - #define RTE_UART1_DCD_PORT 5 - #define RTE_UART1_DCD_BIT 5 - #define RTE_UART1_DCD_FUNC 4 -#elif (RTE_UART1_DCD_ID == 3) - #define RTE_UART1_DCD_PORT 0xC - #define RTE_UART1_DCD_BIT 11 - #define RTE_UART1_DCD_FUNC 2 -#elif (RTE_UART1_DCD_ID == 4) - #define RTE_UART1_DCD_PORT 0xE - #define RTE_UART1_DCD_BIT 9 - #define RTE_UART1_DCD_FUNC 2 -#else - #error "Invalid UART1_DCD Pin Configuration!" -#endif -#ifndef RTE_UART1_DCD_PIN_EN - #define RTE_UART1_DCD_PIN_EN 1 -#endif -// DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8 -#define RTE_UART1_DSR_ID 0 -#if (RTE_UART1_DSR_ID == 0) - #define RTE_UART1_DSR_PIN_EN 0 -#elif (RTE_UART1_DSR_ID == 1) - #define RTE_UART1_DSR_PORT 1 - #define RTE_UART1_DSR_BIT 7 - #define RTE_UART1_DSR_FUNC 1 -#elif (RTE_UART1_DSR_ID == 2) - #define RTE_UART1_DSR_PORT 5 - #define RTE_UART1_DSR_BIT 0 - #define RTE_UART1_DSR_FUNC 4 -#elif (RTE_UART1_DSR_ID == 3) - #define RTE_UART1_DSR_PORT 0xC - #define RTE_UART1_DSR_BIT 10 - #define RTE_UART1_DSR_FUNC 2 -#elif (RTE_UART1_DSR_ID == 4) - #define RTE_UART1_DSR_PORT 0xE - #define RTE_UART1_DSR_BIT 8 - #define RTE_UART1_DSR_FUNC 2 -#else - #error "Invalid UART1_DSR Pin Configuration!" -#endif -#ifndef RTE_UART1_DSR_PIN_EN - #define RTE_UART1_DSR_PIN_EN 1 -#endif -// DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10 -#define RTE_UART1_DTR_ID 0 -#if (RTE_UART1_DTR_ID == 0) - #define RTE_UART1_DTR_PIN_EN 0 -#elif (RTE_UART1_DTR_ID == 1) - #define RTE_UART1_DTR_PORT 1 - #define RTE_UART1_DTR_BIT 8 - #define RTE_UART1_DTR_FUNC 1 -#elif (RTE_UART1_DTR_ID == 2) - #define RTE_UART1_DTR_PORT 5 - #define RTE_UART1_DTR_BIT 1 - #define RTE_UART1_DTR_FUNC 4 -#elif (RTE_UART1_DTR_ID == 3) - #define RTE_UART1_DTR_PORT 0xC - #define RTE_UART1_DTR_BIT 12 - #define RTE_UART1_DTR_FUNC 2 -#elif (RTE_UART1_DTR_ID == 4) - #define RTE_UART1_DTR_PORT 0xE - #define RTE_UART1_DTR_BIT 10 - #define RTE_UART1_DTR_FUNC 2 -#else - #error "Invalid UART1_DTR Pin Configuration!" -#endif -#ifndef RTE_UART1_DTR_PIN_EN - #define RTE_UART1_DTR_PIN_EN 1 -#endif -// RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6 -#define RTE_UART1_RI_ID 0 -#if (RTE_UART1_RI_ID == 0) - #define RTE_UART1_RI_PIN_EN 0 -#elif (RTE_UART1_RI_ID == 1) - #define RTE_UART1_RI_PORT 1 - #define RTE_UART1_RI_BIT 10 - #define RTE_UART1_RI_FUNC 1 -#elif (RTE_UART1_RI_ID == 2) - #define RTE_UART1_RI_PORT 5 - #define RTE_UART1_RI_BIT 3 - #define RTE_UART1_RI_FUNC 4 -#elif (RTE_UART1_RI_ID == 3) - #define RTE_UART1_RI_PORT 0xC - #define RTE_UART1_RI_BIT 1 - #define RTE_UART1_RI_FUNC 2 -#elif (RTE_UART1_RI_ID == 4) - #define RTE_UART1_RI_PORT 0xE - #define RTE_UART1_RI_BIT 6 - #define RTE_UART1_RI_FUNC 2 -#else - #error "Invalid UART1_RI Pin Configuration!" -#endif -#ifndef RTE_UART1_RI_PIN_EN - #define RTE_UART1_RI_PIN_EN 1 -#endif -// Modem Lines -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) -// -#define RTE_UART1_DMA_TX_EN 0 -#define RTE_UART1_DMA_TX_CH 0 -#define RTE_UART1_DMA_TX_PERI_ID 0 -#if (RTE_UART1_DMA_TX_PERI_ID == 0) - #define RTE_UART1_DMA_TX_PERI 3 - #define RTE_UART1_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) -// -#define RTE_UART1_DMA_RX_EN 1 -#define RTE_UART1_DMA_RX_CH 1 -#define RTE_UART1_DMA_RX_PERI_ID 0 -#if (RTE_UART1_DMA_RX_PERI_ID == 0) - #define RTE_UART1_DMA_RX_PERI 4 - #define RTE_UART1_DMA_RX_PERI_SEL 1 -#endif -// DMA -// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -#define RTE_USART2 0 - -// Pin Configuration -// TX <0=>Not used <1=>P1_15 <2=>P2_10 <3=>P7_1 <4=>PA_1 -// USART2 Serial Output pin -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) - #define RTE_USART2_TX_PIN_EN 0 -#elif (RTE_USART2_TX_ID == 1) - #define RTE_USART2_TX_PORT 1 - #define RTE_USART2_TX_BIT 15 - #define RTE_USART2_TX_FUNC 1 -#elif (RTE_USART2_TX_ID == 2) - #define RTE_USART2_TX_PORT 2 - #define RTE_USART2_TX_BIT 10 - #define RTE_USART2_TX_FUNC 2 -#elif (RTE_USART2_TX_ID == 3) - #define RTE_USART2_TX_PORT 7 - #define RTE_USART2_TX_BIT 1 - #define RTE_USART2_TX_FUNC 6 -#elif (RTE_USART2_TX_ID == 4) - #define RTE_USART2_TX_PORT 0xA - #define RTE_USART2_TX_BIT 1 - #define RTE_USART2_TX_FUNC 3 -#else - #error "Invalid USART2_TX Pin Configuration!" -#endif -#ifndef RTE_USART2_TX_PIN_EN - #define RTE_USART2_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P1_16 <2=>P2_11 <3=>P7_2 <4=>PA_2 -// USART2 Serial Input pin -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) - #define RTE_USART2_RX_PIN_EN 0 -#elif (RTE_USART2_RX_ID == 1) - #define RTE_USART2_RX_PORT 1 - #define RTE_USART2_RX_BIT 16 - #define RTE_USART2_RX_FUNC 1 -#elif (RTE_USART2_RX_ID == 2) - #define RTE_USART2_RX_PORT 2 - #define RTE_USART2_RX_BIT 11 - #define RTE_USART2_RX_FUNC 2 -#elif (RTE_USART2_RX_ID == 3) - #define RTE_USART2_RX_PORT 7 - #define RTE_USART2_RX_BIT 2 - #define RTE_USART2_RX_FUNC 6 -#elif (RTE_USART2_RX_ID == 4) - #define RTE_USART2_RX_PORT 0xA - #define RTE_USART2_RX_BIT 2 - #define RTE_USART2_RX_FUNC 3 -#else - #error "Invalid USART2_RX Pin Configuration!" -#endif -#ifndef RTE_USART2_RX_PIN_EN - #define RTE_USART2_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12 -// USART2 Serial Clock input/output synchronous mode -#define RTE_USART2_UCLK_ID 0 -#if (RTE_USART2_UCLK_ID == 0) - #define RTE_USART2_UCLK_PIN_EN 0 -#elif (RTE_USART2_UCLK_ID == 1) - #define RTE_USART2_UCLK_PORT 1 - #define RTE_USART2_UCLK_BIT 17 - #define RTE_USART2_UCLK_FUNC 1 -#elif (RTE_USART2_UCLK_ID == 2) - #define RTE_USART2_UCLK_PORT 2 - #define RTE_USART2_UCLK_BIT 12 - #define RTE_USART2_UCLK_FUNC 7 -#else - #error "Invalid USART2_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART2_UCLK_PIN_EN - #define RTE_USART2_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>5 (DMAMUXPER5) -// -#define RTE_USART2_DMA_TX_EN 0 -#define RTE_USART2_DMA_TX_CH 0 -#define RTE_USART2_DMA_TX_PERI_ID 0 -#if (RTE_USART2_DMA_TX_PERI_ID == 0) - #define RTE_USART2_DMA_TX_PERI 5 - #define RTE_USART2_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>6 (DMAMUXPER6) -// -#define RTE_USART2_DMA_RX_EN 0 -#define RTE_USART2_DMA_RX_CH 1 -#define RTE_USART2_DMA_RX_PERI_ID 0 -#if (RTE_USART2_DMA_RX_PERI_ID == 0) - #define RTE_USART2_DMA_RX_PERI 6 - #define RTE_USART2_DMA_RX_PERI_SEL 1 -#endif -// DMA -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -#define RTE_USART3 0 - -// Pin Configuration -// TX <0=>Not used <1=>P2_3 <2=>P4_1 <3=>P9_3 <4=>PF_2 -// USART3 Serial Output pin -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) - #define RTE_USART3_TX_PIN_EN 0 -#elif (RTE_USART3_TX_ID == 1) - #define RTE_USART3_TX_PORT 2 - #define RTE_USART3_TX_BIT 3 - #define RTE_USART3_TX_FUNC 2 -#elif (RTE_USART3_TX_ID == 2) - #define RTE_USART3_TX_PORT 4 - #define RTE_USART3_TX_BIT 1 - #define RTE_USART3_TX_FUNC 6 -#elif (RTE_USART3_TX_ID == 3) - #define RTE_USART3_TX_PORT 9 - #define RTE_USART3_TX_BIT 3 - #define RTE_USART3_TX_FUNC 7 -#elif (RTE_USART3_TX_ID == 4) - #define RTE_USART3_TX_PORT 0xF - #define RTE_USART3_TX_BIT 2 - #define RTE_USART3_TX_FUNC 1 -#else - #error "Invalid USART3_TX Pin Configuration!" -#endif -#ifndef RTE_USART3_TX_PIN_EN - #define RTE_USART3_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P2_4 <2=>P4_2 <3=>P9_4 <4=>PF_3 -// USART3 Serial Input pin -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) - #define RTE_USART3_RX_PIN_EN 0 -#elif (RTE_USART3_RX_ID == 1) - #define RTE_USART3_RX_PORT 2 - #define RTE_USART3_RX_BIT 4 - #define RTE_USART3_RX_FUNC 2 -#elif (RTE_USART3_RX_ID == 2) - #define RTE_USART3_RX_PORT 4 - #define RTE_USART3_RX_BIT 2 - #define RTE_USART3_RX_FUNC 6 -#elif (RTE_USART3_RX_ID == 3) - #define RTE_USART3_RX_PORT 9 - #define RTE_USART3_RX_BIT 4 - #define RTE_USART3_RX_FUNC 7 -#elif (RTE_USART3_RX_ID == 4) - #define RTE_USART3_RX_PORT 0xF - #define RTE_USART3_RX_BIT 3 - #define RTE_USART3_RX_FUNC 1 -#else - #error "Invalid USART3_RX Pin Configuration!" -#endif -#ifndef RTE_USART3_RX_PIN_EN - #define RTE_USART3_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5 -// USART3 Serial Clock input/output synchronous mode -#define RTE_USART3_UCLK_ID 0 -#if (RTE_USART3_UCLK_ID == 0) - #define RTE_USART3_UCLK_PIN_EN 0 -#elif (RTE_USART3_UCLK_ID == 1) - #define RTE_USART3_UCLK_PORT 2 - #define RTE_USART3_UCLK_BIT 7 - #define RTE_USART3_UCLK_FUNC 2 -#elif (RTE_USART3_UCLK_ID == 2) - #define RTE_USART3_UCLK_PORT 4 - #define RTE_USART3_UCLK_BIT 0 - #define RTE_USART3_UCLK_FUNC 6 -#elif (RTE_USART3_UCLK_ID == 3) - #define RTE_USART3_UCLK_PORT 0xF - #define RTE_USART3_UCLK_BIT 5 - #define RTE_USART3_UCLK_FUNC 1 -#else - #error "Invalid USART3_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART3_UCLK_PIN_EN - #define RTE_USART3_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>7 (DMAMUXPER7) <1=>14 (DMAMUXPER14) -// -#define RTE_USART3_DMA_TX_EN 0 -#define RTE_USART3_DMA_TX_CH 0 -#define RTE_USART3_DMA_TX_PERI_ID 0 -#if (RTE_USART3_DMA_TX_PERI_ID == 0) - #define RTE_USART3_DMA_TX_PERI 7 - #define RTE_USART3_DMA_TX_PERI_SEL 1 -#elif (RTE_USART3_DMA_TX_PERI_ID == 1) - #define RTE_USART3_DMA_TX_PERI 14 - #define RTE_USART3_DMA_TX_PERI_SEL 3 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>8 (DMAMUXPER8) <1=>13 (DMAMUXPER13) -// -#define RTE_USART3_DMA_RX_EN 0 -#define RTE_USART3_DMA_RX_CH 1 -#define RTE_USART3_DMA_RX_PERI_ID 0 -#if (RTE_USART3_DMA_RX_PERI_ID == 0) - #define RTE_USART3_DMA_RX_PERI 8 - #define RTE_USART3_DMA_RX_PERI_SEL 1 -#elif (RTE_USART3_DMA_RX_PERI_ID == 1) - #define RTE_USART3_DMA_RX_PERI 13 - #define RTE_USART3_DMA_RX_PERI_SEL 3 -#endif -// DMA -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] - -// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] -// Configuration settings for Driver_SPI0 in component ::Drivers:SPI -#define RTE_SSP0 0 - -// Pin Configuration -// SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1 -// Slave Select for SSP0 -#define RTE_SSP0_SSEL_PIN_SEL 1 -#if (RTE_SSP0_SSEL_PIN_SEL == 0) -#define RTE_SSP0_SSEL_PIN_EN 0 -#elif (RTE_SSP0_SSEL_PIN_SEL == 1) - #define RTE_SSP0_SSEL_PORT 1 - #define RTE_SSP0_SSEL_BIT 0 - #define RTE_SSP0_SSEL_FUNC 5 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 0 - #define RTE_SSP0_SSEL_GPIO_BIT 4 -#elif (RTE_SSP0_SSEL_PIN_SEL == 2) - #define RTE_SSP0_SSEL_PORT 3 - #define RTE_SSP0_SSEL_BIT 6 - #define RTE_SSP0_SSEL_FUNC 2 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 0 - #define RTE_SSP0_SSEL_GPIO_BIT 6 -#elif (RTE_SSP0_SSEL_PIN_SEL == 3) - #define RTE_SSP0_SSEL_PORT 3 - #define RTE_SSP0_SSEL_BIT 8 - #define RTE_SSP0_SSEL_FUNC 5 - #define RTE_SSP0_SSEL_GPIO_FUNC 4 - #define RTE_SSP0_SSEL_GPIO_PORT 5 - #define RTE_SSP0_SSEL_GPIO_BIT 11 -#elif (RTE_SSP0_SSEL_PIN_SEL == 4) - #define RTE_SSP0_SSEL_PORT 9 - #define RTE_SSP0_SSEL_BIT 0 - #define RTE_SSP0_SSEL_FUNC 7 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 4 - #define RTE_SSP0_SSEL_GPIO_BIT 12 -#elif (RTE_SSP0_SSEL_PIN_SEL == 5) - #define RTE_SSP0_SSEL_PORT 0xF - #define RTE_SSP0_SSEL_BIT 1 - #define RTE_SSP0_SSEL_FUNC 2 - #define RTE_SSP0_SSEL_GPIO_FUNC 4 - #define RTE_SSP0_SSEL_GPIO_PORT 7 - #define RTE_SSP0_SSEL_GPIO_BIT 16 -#else - #error "Invalid SSP0 SSP0_SSEL Pin Configuration!" -#endif -#ifndef RTE_SSP0_SSEL_PIN_EN -#define RTE_SSP0_SSEL_PIN_EN 1 -#endif -// SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0 -// Serial clock for SSP0 -#define RTE_SSP0_SCK_PIN_SEL 0 -#if (RTE_SSP0_SCK_PIN_SEL == 0) - #define RTE_SSP0_SCK_PORT 3 - #define RTE_SSP0_SCK_BIT 0 - #define RTE_SSP0_SCK_FUNC 4 -#elif (RTE_SSP0_SCK_PIN_SEL == 1) - #define RTE_SSP0_SCK_PORT 3 - #define RTE_SSP0_SCK_BIT 3 - #define RTE_SSP0_SCK_FUNC 2 -#elif (RTE_SSP0_SCK_PIN_SEL == 2) - #define RTE_SSP0_SCK_PORT 0xF - #define RTE_SSP0_SCK_BIT 0 - #define RTE_SSP0_SCK_FUNC 0 -#else - #error "Invalid SSP0 SSP0_SCK Pin Configuration!" -#endif -// SSP0_MISO <0=>Not used <1=>P1_1 <2=>P3_6 <3=>P3_7 <4=>P9_1 <5=>PF_2 -// Master In Slave Out for SSP0 -#define RTE_SSP0_MISO_PIN_SEL 0 -#if (RTE_SSP0_MISO_PIN_SEL == 0) - #define RTE_SSP0_MISO_PIN_EN 0 -#elif (RTE_SSP0_MISO_PIN_SEL == 1) - #define RTE_SSP0_MISO_PORT 1 - #define RTE_SSP0_MISO_BIT 1 - #define RTE_SSP0_MISO_FUNC 5 -#elif (RTE_SSP0_MISO_PIN_SEL == 2) - #define RTE_SSP0_MISO_PORT 3 - #define RTE_SSP0_MISO_BIT 6 - #define RTE_SSP0_MISO_FUNC 5 -#elif (RTE_SSP0_MISO_PIN_SEL == 3) - #define RTE_SSP0_MISO_PORT 3 - #define RTE_SSP0_MISO_BIT 7 - #define RTE_SSP0_MISO_FUNC 2 -#elif (RTE_SSP0_MISO_PIN_SEL == 4) - #define RTE_SSP0_MISO_PORT 9 - #define RTE_SSP0_MISO_BIT 1 - #define RTE_SSP0_MISO_FUNC 7 -#elif (RTE_SSP0_MISO_PIN_SEL == 5) - #define RTE_SSP0_MISO_PORT 0xF - #define RTE_SSP0_MISO_BIT 2 - #define RTE_SSP0_MISO_FUNC 2 -#else - #error "Invalid SSP0 SSP0_MISO Pin Configuration!" -#endif -#ifndef RTE_SSP0_MISO_PIN_EN - #define RTE_SSP0_MISO_PIN_EN 1 -#endif -// SSP0_MOSI <0=>Not used <1=>P1_2 <2=>P3_7 <3=>P3_8 <4=>P9_2 <5=>PF_3 -// Master Out Slave In for SSP0 -#define RTE_SSP0_MOSI_PIN_SEL 0 -#if (RTE_SSP0_MOSI_PIN_SEL == 0) - #define RTE_SSP0_MOSI_PIN_EN 0 -#elif (RTE_SSP0_MOSI_PIN_SEL == 1) - #define RTE_SSP0_MOSI_PORT 1 - #define RTE_SSP0_MOSI_BIT 2 - #define RTE_SSP0_MOSI_FUNC 5 -#elif (RTE_SSP0_MOSI_PIN_SEL == 2) - #define RTE_SSP0_MOSI_PORT 3 - #define RTE_SSP0_MOSI_BIT 7 - #define RTE_SSP0_MOSI_FUNC 5 -#elif (RTE_SSP0_MOSI_PIN_SEL == 3) - #define RTE_SSP0_MOSI_PORT 3 - #define RTE_SSP0_MOSI_BIT 8 - #define RTE_SSP0_MOSI_FUNC 2 -#elif (RTE_SSP0_MOSI_PIN_SEL == 4) - #define RTE_SSP0_MOSI_PORT 9 - #define RTE_SSP0_MOSI_BIT 2 - #define RTE_SSP0_MOSI_FUNC 7 -#elif (RTE_SSP0_MOSI_PIN_SEL == 5) - #define RTE_SSP0_MOSI_PORT 0xF - #define RTE_SSP0_MOSI_BIT 3 - #define RTE_SSP0_MOSI_FUNC 2 -#else - #error "Invalid SSP0 SSP0_MOSI Pin Configuration!" -#endif -#ifndef RTE_SSP0_MOSI_PIN_EN - #define RTE_SSP0_MOSI_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>10 (DMAMUXPER10) -// -#define RTE_SSP0_DMA_TX_EN 0 -#define RTE_SSP0_DMA_TX_CH 0 -#define RTE_SSP0_DMA_TX_PERI_ID 0 -#if (RTE_SSP0_DMA_TX_PERI_ID == 0) - #define RTE_SSP0_DMA_TX_PERI 10 - #define RTE_SSP0_DMA_TX_PERI_SEL 0 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>9 (DMAMUXPER9) -// -#define RTE_SSP0_DMA_RX_EN 0 -#define RTE_SSP0_DMA_RX_CH 1 -#define RTE_SSP0_DMA_RX_PERI_ID 0 -#if (RTE_SSP0_DMA_RX_PERI_ID == 0) - #define RTE_SSP0_DMA_RX_PERI 9 - #define RTE_SSP0_DMA_RX_PERI_SEL 0 -#endif -// DMA -// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] - -// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SSP1 0 - -// Pin Configuration -// SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5 -// Slave Select for SSP1 -#define RTE_SSP1_SSEL_PIN_SEL 1 -#if (RTE_SSP1_SSEL_PIN_SEL == 0) - #define RTE_SSP1_SSEL_PIN_EN 0 -#elif (RTE_SSP1_SSEL_PIN_SEL == 1) - #define RTE_SSP1_SSEL_PORT 1 - #define RTE_SSP1_SSEL_BIT 5 - #define RTE_SSP1_SSEL_FUNC 5 - #define RTE_SSP1_SSEL_GPIO_FUNC 0 - #define RTE_SSP1_SSEL_GPIO_PORT 1 - #define RTE_SSP1_SSEL_GPIO_BIT 8 -#elif (RTE_SSP1_SSEL_PIN_SEL == 2) - #define RTE_SSP1_SSEL_PORT 1 - #define RTE_SSP1_SSEL_BIT 20 - #define RTE_SSP1_SSEL_FUNC 1 - #define RTE_SSP1_SSEL_GPIO_FUNC 0 - #define RTE_SSP1_SSEL_GPIO_PORT 0 - #define RTE_SSP1_SSEL_GPIO_BIT 15 -#elif (RTE_SSP1_SSEL_PIN_SEL == 3) - #define RTE_SSP1_SSEL_PORT 0xF - #define RTE_SSP1_SSEL_BIT 5 - #define RTE_SSP1_SSEL_FUNC 2 - #define RTE_SSP1_SSEL_GPIO_FUNC 4 - #define RTE_SSP1_SSEL_GPIO_PORT 7 - #define RTE_SSP1_SSEL_GPIO_BIT 19 -#else - #error "Invalid SSP1 SSP1_SSEL Pin Configuration!" -#endif -#ifndef RTE_SSP1_SSEL_PIN_EN -#define RTE_SSP1_SSEL_PIN_EN 1 -#endif -// SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0 -// Serial clock for SSP1 -#define RTE_SSP1_SCK_PIN_SEL 0 -#if (RTE_SSP1_SCK_PIN_SEL == 0) - #define RTE_SSP1_SCK_PORT 1 - #define RTE_SSP1_SCK_BIT 19 - #define RTE_SSP1_SCK_FUNC 1 -#elif (RTE_SSP1_SCK_PIN_SEL == 1) - #define RTE_SSP1_SCK_PORT 0xF - #define RTE_SSP1_SCK_BIT 4 - #define RTE_SSP1_SCK_FUNC 0 -#elif (RTE_SSP1_SCK_PIN_SEL == 2) - #define RTE_SSP1_SCK_PORT 0x10 - #define RTE_SSP1_SCK_BIT 0 - #define RTE_SSP1_SCK_FUNC 6 -#else - #error "Invalid SSP1 SSP1_SCK Pin Configuration!" -#endif -// SSP1_MISO <0=>Not used <1=>P0_0 <2=>P1_3 <3=>PF_6 -// Master In Slave Out for SSP1 -#define RTE_SSP1_MISO_PIN_SEL 0 -#if (RTE_SSP1_MISO_PIN_SEL == 0) - #define RTE_SSP1_MISO_PIN_EN 0 -#elif (RTE_SSP1_MISO_PIN_SEL == 1) - #define RTE_SSP1_MISO_PORT 0 - #define RTE_SSP1_MISO_BIT 0 - #define RTE_SSP1_MISO_FUNC 1 -#elif (RTE_SSP1_MISO_PIN_SEL == 2) - #define RTE_SSP1_MISO_PORT 1 - #define RTE_SSP1_MISO_BIT 3 - #define RTE_SSP1_MISO_FUNC 5 -#elif (RTE_SSP1_MISO_PIN_SEL == 3) - #define RTE_SSP1_MISO_PORT 0xF - #define RTE_SSP1_MISO_BIT 6 - #define RTE_SSP1_MISO_FUNC 2 -#else - #error "Invalid SSP1 SSP1_MISO Pin Configuration!" -#endif -#ifndef RTE_SSP1_MISO_PIN_EN - #define RTE_SSP1_MISO_PIN_EN 1 -#endif -// SSP1_MOSI <0=>Not used <1=>P0_1 <2=>P1_4 <3=>PF_7 -// Master Out Slave In for SSP1 -#define RTE_SSP1_MOSI_PIN_SEL 0 -#if (RTE_SSP1_MOSI_PIN_SEL == 0) - #define RTE_SSP1_MOSI_PIN_EN 0 -#elif (RTE_SSP1_MOSI_PIN_SEL == 1) - #define RTE_SSP1_MOSI_PORT 0 - #define RTE_SSP1_MOSI_BIT 1 - #define RTE_SSP1_MOSI_FUNC 1 -#elif (RTE_SSP1_MOSI_PIN_SEL == 2) - #define RTE_SSP1_MOSI_PORT 1 - #define RTE_SSP1_MOSI_BIT 4 - #define RTE_SSP1_MOSI_FUNC 5 -#elif (RTE_SSP1_MOSI_PIN_SEL == 3) - #define RTE_SSP1_MOSI_PORT 0xF - #define RTE_SSP1_MOSI_BIT 7 - #define RTE_SSP1_MOSI_FUNC 2 -#else - #error "Invalid SSP1 SSP1_MOSI Pin Configuration!" -#endif -#ifndef RTE_SSP1_MOSI_PIN_EN - #define RTE_SSP1_MOSI_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14) -// -#define RTE_SSP1_DMA_TX_EN 0 -#define RTE_SSP1_DMA_TX_CH 0 -#define RTE_SSP1_DMA_TX_PERI_ID 0 -#if (RTE_SSP1_DMA_TX_PERI_ID == 0) - #define RTE_SSP1_DMA_TX_PERI 3 - #define RTE_SSP1_DMA_TX_PERI_SEL 3 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 1) - #define RTE_SSP1_DMA_TX_PERI 5 - #define RTE_SSP1_DMA_TX_PERI_SEL 2 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 2) - #define RTE_SSP1_DMA_TX_PERI 12 - #define RTE_SSP1_DMA_TX_PERI_SEL 0 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 3) - #define RTE_SSP1_DMA_TX_PERI 14 - #define RTE_SSP1_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13) -// -#define RTE_SSP1_DMA_RX_EN 0 -#define RTE_SSP1_DMA_RX_CH 1 -#define RTE_SSP1_DMA_RX_PERI_ID 0 -#if (RTE_SSP1_DMA_RX_PERI_ID == 0) - #define RTE_SSP1_DMA_RX_PERI 4 - #define RTE_SSP1_DMA_RX_PERI_SEL 3 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 1) - #define RTE_SSP1_DMA_RX_PERI 6 - #define RTE_SSP1_DMA_RX_PERI_SEL 2 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 2) - #define RTE_SSP1_DMA_RX_PERI 11 - #define RTE_SSP1_DMA_RX_PERI_SEL 0 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 3) - #define RTE_SSP1_DMA_RX_PERI 13 - #define RTE_SSP1_DMA_RX_PERI_SEL 2 -#endif -// DMA -// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] - -// SPI (Serial Peripheral Interface) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI 0 - -// Pin Configuration -// SPI_SSEL <0=>Not used <1=>P3_8 -// Slave Select for SPI -#define RTE_SPI_SSEL_PIN_SEL 0 -#if (RTE_SPI_SSEL_PIN_SEL == 0) -#define RTE_SPI_SSEL_PIN_EN 0 -#elif (RTE_SPI_SSEL_PIN_SEL == 1) - #define RTE_SPI_SSEL_PORT 3 - #define RTE_SPI_SSEL_BIT 8 - #define RTE_SPI_SSEL_FUNC 1 - #define RTE_SPI_SSEL_GPIO_FUNC 4 - #define RTE_SPI_SSEL_GPIO_PORT 5 - #define RTE_SPI_SSEL_GPIO_BIT 11 -#else - #error "Invalid SPI SPI_SSEL Pin Configuration!" -#endif -#ifndef RTE_SPI_SSEL_PIN_EN -#define RTE_SPI_SSEL_PIN_EN 1 -#endif -// SPI_SCK <0=>P3_3 -// Serial clock for SPI -#define RTE_SPI_SCK_PIN_SEL 0 -#if (RTE_SPI_SCK_PIN_SEL == 0) - #define RTE_SPI_SCK_PORT 3 - #define RTE_SPI_SCK_BIT 3 - #define RTE_SPI_SCK_FUNC 1 -#else - #error "Invalid SPI SPI_SCK Pin Configuration!" -#endif -// SPI_MISO <0=>Not used <1=>P3_6 -// Master In Slave Out for SPI -#define RTE_SPI_MISO_PIN_SEL 0 -#if (RTE_SPI_MISO_PIN_SEL == 0) - #define RTE_SPI_MISO_PIN_EN 0 -#elif (RTE_SPI_MISO_PIN_SEL == 1) - #define RTE_SPI_MISO_PORT 3 - #define RTE_SPI_MISO_BIT 6 - #define RTE_SPI_MISO_FUNC 1 -#else - #error "Invalid SPI SPI_MISO Pin Configuration!" -#endif -#ifndef RTE_SPI_MISO_PIN_EN - #define RTE_SPI_MISO_PIN_EN 1 -#endif -// SPI_MOSI <0=>Not used <1=>P3_7 -// Master Out Slave In for SPI -#define RTE_SPI_MOSI_PIN_SEL 0 -#if (RTE_SPI_MOSI_PIN_SEL == 0) - #define RTE_SPI_MOSI_PIN_EN 0 -#elif (RTE_SPI_MOSI_PIN_SEL == 1) - #define RTE_SPI_MOSI_PORT 3 - #define RTE_SPI_MOSI_BIT 7 - #define RTE_SPI_MOSI_FUNC 1 -#else - #error "Invalid SPI SPI_MOSI Pin Configuration!" -#endif -#ifndef RTE_SPI_MOSI_PIN_EN - #define RTE_SPI_MOSI_PIN_EN 1 -#endif -// Pin Configuration -// SPI (Serial Peripheral Interface) [Driver_SPI2] - -// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] -// Configuration settings for Driver_SAI0 in component ::Drivers:SAI -#define RTE_I2S0 0 - -// Pin Configuration -// I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4 -// Receive clock for I2S0 -#define RTE_I2S0_RX_SCK_PIN_SEL 2 -#if (RTE_I2S0_RX_SCK_PIN_SEL == 0) -#define RTE_I2S0_RX_SCK_PIN_EN 0 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 1) - #define RTE_I2S0_RX_SCK_PORT 3 - #define RTE_I2S0_RX_SCK_BIT 0 - #define RTE_I2S0_RX_SCK_FUNC 0 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 2) - #define RTE_I2S0_RX_SCK_PORT 6 - #define RTE_I2S0_RX_SCK_BIT 0 - #define RTE_I2S0_RX_SCK_FUNC 4 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 3) - #define RTE_I2S0_RX_SCK_PORT 0xF - #define RTE_I2S0_RX_SCK_BIT 4 - #define RTE_I2S0_RX_SCK_FUNC 7 -#else - #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_SCK_PIN_EN -#define RTE_I2S0_RX_SCK_PIN_EN 1 -#endif -// I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1 -// Receive word select for I2S0 -#define RTE_I2S0_RX_WS_PIN_SEL 2 -#if (RTE_I2S0_RX_WS_PIN_SEL == 0) -#define RTE_I2S0_RX_WS_PIN_EN 0 -#elif (RTE_I2S0_RX_WS_PIN_SEL == 1) - #define RTE_I2S0_RX_WS_PORT 3 - #define RTE_I2S0_RX_WS_BIT 1 - #define RTE_I2S0_RX_WS_FUNC 1 -#elif (RTE_I2S0_RX_WS_PIN_SEL == 2) - #define RTE_I2S0_RX_WS_PORT 6 - #define RTE_I2S0_RX_WS_BIT 1 - #define RTE_I2S0_RX_WS_FUNC 3 -#else - #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_WS_PIN_EN -#define RTE_I2S0_RX_WS_PIN_EN 1 -#endif -// I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2 -// Receive master clock for I2S0 -#define RTE_I2S0_RX_SDA_PIN_SEL 2 -#if (RTE_I2S0_RX_SDA_PIN_SEL == 0) -#define RTE_I2S0_RX_SDA_PIN_EN 0 -#elif (RTE_I2S0_RX_SDA_PIN_SEL == 1) - #define RTE_I2S0_RX_SDA_PORT 3 - #define RTE_I2S0_RX_SDA_BIT 2 - #define RTE_I2S0_RX_SDA_FUNC 1 -#elif (RTE_I2S0_RX_SDA_PIN_SEL == 2) - #define RTE_I2S0_RX_SDA_PORT 6 - #define RTE_I2S0_RX_SDA_BIT 2 - #define RTE_I2S0_RX_SDA_FUNC 3 -#else - #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_SDA_PIN_EN -#define RTE_I2S0_RX_SDA_PIN_EN 1 -#endif -// I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0 -// Receive master clock for I2S0 -#define RTE_I2S0_RX_MCLK_PIN_SEL 0 -#if (RTE_I2S0_RX_MCLK_PIN_SEL == 0) -#define RTE_I2S0_RX_MCLK_PIN_EN 0 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1) - #define RTE_I2S0_RX_MCLK_PORT 1 - #define RTE_I2S0_RX_MCLK_BIT 19 - #define RTE_I2S0_RX_MCLK_FUNC 6 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 2) - #define RTE_I2S0_RX_MCLK_PORT 3 - #define RTE_I2S0_RX_MCLK_BIT 0 - #define RTE_I2S0_RX_MCLK_FUNC 1 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 3) - #define RTE_I2S0_RX_MCLK_PORT 6 - #define RTE_I2S0_RX_MCLK_BIT 0 - #define RTE_I2S0_RX_MCLK_FUNC 1 -#else - #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_MCLK_PIN_EN -#define RTE_I2S0_RX_MCLK_PIN_EN 1 -#endif -// I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7 -// Transmit clock for I2S0 -#define RTE_I2S0_TX_SCK_PIN_SEL 1 -#if (RTE_I2S0_TX_SCK_PIN_SEL == 0) -#define RTE_I2S0_TX_SCK_PIN_EN 0 -#elif (RTE_I2S0_TX_SCK_PIN_SEL == 1) - #define RTE_I2S0_TX_SCK_PORT 3 - #define RTE_I2S0_TX_SCK_BIT 0 - #define RTE_I2S0_TX_SCK_FUNC 2 -#elif (RTE_I2S0_TX_SCK_PIN_SEL == 2) - #define RTE_I2S0_TX_SCK_PORT 4 - #define RTE_I2S0_TX_SCK_BIT 7 - #define RTE_I2S0_TX_SCK_FUNC 7 -#else - #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_SCK_PIN_EN -#define RTE_I2S0_TX_SCK_PIN_EN 1 -#endif -// I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13 -// Transmit word select for I2S0 -#define RTE_I2S0_TX_WS_PIN_SEL 4 -#if (RTE_I2S0_TX_WS_PIN_SEL == 0) -#define RTE_I2S0_TX_WS_PIN_EN 0 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 1) - #define RTE_I2S0_TX_WS_PORT 0 - #define RTE_I2S0_TX_WS_BIT 0 - #define RTE_I2S0_TX_WS_FUNC 6 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 2) - #define RTE_I2S0_TX_WS_PORT 3 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 0 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 3) - #define RTE_I2S0_TX_WS_PORT 3 - #define RTE_I2S0_TX_WS_BIT 4 - #define RTE_I2S0_TX_WS_FUNC 5 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 4) - #define RTE_I2S0_TX_WS_PORT 7 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 2 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 5) - #define RTE_I2S0_TX_WS_PORT 9 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 4 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 6) - #define RTE_I2S0_TX_WS_PORT 0xC - #define RTE_I2S0_TX_WS_BIT 13 - #define RTE_I2S0_TX_WS_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_WS_PIN_EN -#define RTE_I2S0_TX_WS_PIN_EN 1 -#endif -// I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2 <5=>PC_12 -// Transmit data for I2S0 -#define RTE_I2S0_TX_SDA_PIN_SEL 3 -#if (RTE_I2S0_TX_SDA_PIN_SEL == 0) -#define RTE_I2S0_TX_SDA_PIN_EN 0 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 1) - #define RTE_I2S0_TX_SDA_PORT 3 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 0 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 2) - #define RTE_I2S0_TX_SDA_PORT 3 - #define RTE_I2S0_TX_SDA_BIT 5 - #define RTE_I2S0_TX_SDA_FUNC 5 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 3) - #define RTE_I2S0_TX_SDA_PORT 7 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 2 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 4) - #define RTE_I2S0_TX_SDA_PORT 9 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 4 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 5) - #define RTE_I2S0_TX_SDA_PORT 0xC - #define RTE_I2S0_TX_SDA_BIT 12 - #define RTE_I2S0_TX_SDA_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_SDA_PIN_EN -#define RTE_I2S0_TX_SDA_PIN_EN 1 -#endif -// I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2 -// Transmit master clock for I2S0 -#define RTE_I2S0_TX_MCLK_PIN_SEL 2 -#if (RTE_I2S0_TX_MCLK_PIN_SEL == 0) -#define RTE_I2S0_TX_MCLK_PIN_EN 0 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1) - #define RTE_I2S0_TX_MCLK_PORT 3 - #define RTE_I2S0_TX_MCLK_BIT 0 - #define RTE_I2S0_TX_MCLK_FUNC 3 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 2) - #define RTE_I2S0_TX_MCLK_PORT 3 - #define RTE_I2S0_TX_MCLK_BIT 3 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 3) - #define RTE_I2S0_TX_MCLK_PORT 0xf - #define RTE_I2S0_TX_MCLK_BIT 4 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 4) - #define RTE_I2S0_TX_MCLK_PORT 0x10 - #define RTE_I2S0_TX_MCLK_BIT 2 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_MCLK_PIN_EN -#define RTE_I2S0_TX_MCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>9 (DMAMUXPER9) -// -#define RTE_I2S0_DMA_TX_EN 0 -#define RTE_I2S0_DMA_TX_CH 0 -#define RTE_I2S0_DMA_TX_PERI_ID 0 -#if (RTE_I2S0_DMA_TX_PERI_ID == 0) - #define RTE_I2S0_DMA_TX_PERI 9 - #define RTE_I2S0_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>10 (DMAMUXPER10) -// -#define RTE_I2S0_DMA_RX_EN 0 -#define RTE_I2S0_DMA_RX_CH 1 -#define RTE_I2S0_DMA_RX_PERI_ID 0 -#if (RTE_I2S0_DMA_RX_PERI_ID == 0) - #define RTE_I2S0_DMA_RX_PERI 10 - #define RTE_I2S0_DMA_RX_PERI_SEL 1 -#endif -// DMA -// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] - -// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] -// Configuration settings for Driver_I2S1 in component ::Drivers:SAI -#define RTE_I2S1 0 - -// Pin Configuration -// I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3 -// Receive clock for I2S1 -#define RTE_I2S1_RX_SCK_PIN_SEL 0 -#if (RTE_I2S1_RX_SCK_PIN_SEL == 0) -#define RTE_I2S1_RX_SCK_PIN_EN 0 -#elif (RTE_I2S1_RX_SCK_PIN_SEL == 1) - #define RTE_I2S1_RX_SCK_PORT 0x10 - #define RTE_I2S1_RX_SCK_BIT 2 - #define RTE_I2S1_RX_SCK_FUNC 7 -#elif (RTE_I2S1_RX_SCK_PIN_SEL == 2) - #define RTE_I2S1_RX_SCK_PORT 0x10 - #define RTE_I2S1_RX_SCK_BIT 3 - #define RTE_I2S1_RX_SCK_FUNC 7 -#else - #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_SCK_PIN_EN -#define RTE_I2S1_RX_SCK_PIN_EN 1 -#endif -// I2S1_RX_WS <0=>Not used <1=>P3_5 -// Receive word select for I2S1 -#define RTE_I2S1_RX_WS_PIN_SEL 0 -#if (RTE_I2S1_RX_WS_PIN_SEL == 0) -#define RTE_I2S1_RX_WS_PIN_EN 0 -#elif (RTE_I2S1_RX_WS_PIN_SEL == 1) - #define RTE_I2S1_RX_WS_PORT 3 - #define RTE_I2S1_RX_WS_BIT 5 - #define RTE_I2S1_RX_WS_FUNC 6 -#else - #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_WS_PIN_EN -#define RTE_I2S1_RX_WS_PIN_EN 1 -#endif -// I2S1_RX_SDA <0=>Not used <1=>P3_4 -// Receive master clock for I2S1 -#define RTE_I2S1_RX_SDA_PIN_SEL 0 -#if (RTE_I2S1_RX_SDA_PIN_SEL == 0) -#define RTE_I2S1_RX_SDA_PIN_EN 0 -#elif (RTE_I2S1_RX_SDA_PIN_SEL == 1) - #define RTE_I2S1_RX_SDA_PORT 3 - #define RTE_I2S1_RX_SDA_BIT 4 - #define RTE_I2S1_RX_SDA_FUNC 6 -#else - #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_SDA_PIN_EN -#define RTE_I2S1_RX_SDA_PIN_EN 1 -#endif -// I2S1_RX_MCLK <0=>Not used <1=>PA_0 -// Receive master clock for I2S1 -#define RTE_I2S1_RX_MCLK_PIN_SEL 0 -#if (RTE_I2S1_RX_MCLK_PIN_SEL == 0) -#define RTE_I2S1_RX_MCLK_PIN_EN 0 -#elif (RTE_I2S1_RX_MCLK_PIN_SEL == 1) - #define RTE_I2S1_RX_MCLK_PORT 0x0A - #define RTE_I2S1_RX_MCLK_BIT 0 - #define RTE_I2S1_RX_MCLK_FUNC 5 -#else - #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_MCLK_PIN_EN -#define RTE_I2S1_RX_MCLK_PIN_EN 1 -#endif -// I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7 -// Transmit clock for I2S1 -#define RTE_I2S1_TX_SCK_PIN_SEL 0 -#if (RTE_I2S1_TX_SCK_PIN_SEL == 0) -#define RTE_I2S1_TX_SCK_PIN_EN 0 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 1) - #define RTE_I2S1_TX_SCK_PORT 1 - #define RTE_I2S1_TX_SCK_BIT 19 - #define RTE_I2S1_TX_SCK_FUNC 7 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 2) - #define RTE_I2S1_TX_SCK_PORT 3 - #define RTE_I2S1_TX_SCK_BIT 3 - #define RTE_I2S1_TX_SCK_FUNC 7 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 3) - #define RTE_I2S1_TX_SCK_PORT 4 - #define RTE_I2S1_TX_SCK_BIT 7 - #define RTE_I2S1_TX_SCK_FUNC 6 -#else - #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_SCK_PIN_EN -#define RTE_I2S1_TX_SCK_PIN_EN 1 -#endif -// I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7 -// Transmit word select for I2S1 -#define RTE_I2S1_TX_WS_PIN_SEL 0 -#if (RTE_I2S1_TX_WS_PIN_SEL == 0) -#define RTE_I2S1_TX_WS_PIN_EN 0 -#elif (RTE_I2S1_TX_WS_PIN_SEL == 1) - #define RTE_I2S1_TX_WS_PORT 0 - #define RTE_I2S1_TX_WS_BIT 0 - #define RTE_I2S1_TX_WS_FUNC 7 -#elif (RTE_I2S1_TX_WS_PIN_SEL == 2) - #define RTE_I2S1_TX_WS_PORT 0x0F - #define RTE_I2S1_TX_WS_BIT 7 - #define RTE_I2S1_TX_WS_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_WS_PIN_EN -#define RTE_I2S1_TX_WS_PIN_EN 1 -#endif -// I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6 -// Transmit data for I2S -#define RTE_I2S1_TX_SDA_PIN_SEL 0 -#if (RTE_I2S1_TX_SDA_PIN_SEL == 0) -#define RTE_I2S1_TX_SDA_PIN_EN 0 -#elif (RTE_I2S1_TX_SDA_PIN_SEL == 1) - #define RTE_I2S1_TX_SDA_PORT 0 - #define RTE_I2S1_TX_SDA_BIT 1 - #define RTE_I2S1_TX_SDA_FUNC 7 -#elif (RTE_I2S1_TX_SDA_PIN_SEL == 2) - #define RTE_I2S1_TX_SDA_PORT 0x0F - #define RTE_I2S1_TX_SDA_BIT 6 - #define RTE_I2S1_TX_SDA_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_SDA_PIN_EN -#define RTE_I2S1_TX_SDA_PIN_EN 1 -#endif -// I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1 -// Transmit master clock for I2S1 -#define RTE_I2S1_TX_MCLK_PIN_SEL 0 -#if (RTE_I2S1_TX_MCLK_PIN_SEL == 0) -#define RTE_I2S1_TX_MCLK_PIN_EN 0 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 1) - #define RTE_I2S1_TX_MCLK_PORT 8 - #define RTE_I2S1_TX_MCLK_BIT 8 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 2) - #define RTE_I2S1_TX_MCLK_PORT 0x0F - #define RTE_I2S1_TX_MCLK_BIT 0 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 3) - #define RTE_I2S1_TX_MCLK_PORT 0x10 - #define RTE_I2S1_TX_MCLK_BIT 1 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_MCLK_PIN_EN -#define RTE_I2S1_TX_MCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) -// -#define RTE_I2S1_DMA_TX_EN 0 -#define RTE_I2S1_DMA_TX_CH 0 -#define RTE_I2S1_DMA_TX_PERI_ID 0 -#if (RTE_I2S1_DMA_TX_PERI_ID == 0) - #define RTE_I2S1_DMA_TX_PERI 3 - #define RTE_I2S1_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) -// -#define RTE_I2S1_DMA_RX_EN 0 -#define RTE_I2S1_DMA_RX_CH 1 -#define RTE_I2S1_DMA_RX_PERI_ID 0 -#if (RTE_I2S1_DMA_RX_PERI_ID == 0) - #define RTE_I2S1_DMA_RX_PERI 4 - #define RTE_I2S1_DMA_RX_PERI_SEL 2 -#endif -// DMA -// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] - -// CAN0 Controller [Driver_CAN0] -// Configuration settings for Driver_CAN0 in component ::Drivers:CAN -#define RTE_CAN_CAN0 0 - -// Pin Configuration -// CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2 -// CAN0 receiver input. -#define RTE_CAN0_RD_ID 0 -#if (RTE_CAN0_RD_ID == 0) - #define RTE_CAN0_RD_PIN_EN 0 -#elif (RTE_CAN0_RD_ID == 1) - #define RTE_CAN0_RD_PORT 3 - #define RTE_CAN0_RD_BIT 1 - #define RTE_CAN0_RD_FUNC 2 -#elif (RTE_CAN0_RD_ID == 2) - #define RTE_CAN0_RD_PORT 0xE - #define RTE_CAN0_RD_BIT 2 - #define RTE_CAN0_RD_FUNC 1 -#else - #error "Invalid RTE_CAN0_RD Pin Configuration!" -#endif -#ifndef RTE_CAN0_RD_PIN_EN - #define RTE_CAN0_RD_PIN_EN 1 -#endif -// CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3 -// CAN0 transmitter output. -#define RTE_CAN0_TD_ID 0 -#if (RTE_CAN0_TD_ID == 0) - #define RTE_CAN0_TD_PIN_EN 0 -#elif (RTE_CAN0_TD_ID == 1) - #define RTE_CAN0_TD_PORT 3 - #define RTE_CAN0_TD_BIT 2 - #define RTE_CAN0_TD_FUNC 2 -#elif (RTE_CAN0_TD_ID == 2) - #define RTE_CAN0_TD_PORT 0xE - #define RTE_CAN0_TD_BIT 3 - #define RTE_CAN0_TD_FUNC 1 -#else - #error "Invalid RTE_CAN0_TD Pin Configuration!" -#endif -#ifndef RTE_CAN0_TD_PIN_EN - #define RTE_CAN0_TD_PIN_EN 1 -#endif -// Pin Configuration -// CAN0 Controller [Driver_CAN0] - -// CAN1 Controller [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::Drivers:CAN -#define RTE_CAN_CAN1 0 - -// Pin Configuration -// CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1 -// CAN1 receiver input. -#define RTE_CAN1_RD_ID 0 -#if (RTE_CAN1_RD_ID == 0) - #define RTE_CAN1_RD_PIN_EN 0 -#elif (RTE_CAN1_RD_ID == 1) - #define RTE_CAN1_RD_PORT 1 - #define RTE_CAN1_RD_BIT 18 - #define RTE_CAN1_RD_FUNC 5 -#elif (RTE_CAN1_RD_ID == 2) - #define RTE_CAN1_RD_PORT 4 - #define RTE_CAN1_RD_BIT 9 - #define RTE_CAN1_RD_FUNC 6 -#elif (RTE_CAN1_RD_ID == 3) - #define RTE_CAN1_RD_PORT 0xE - #define RTE_CAN1_RD_BIT 1 - #define RTE_CAN1_RD_FUNC 5 -#else - #error "Invalid RTE_CAN1_RD Pin Configuration!" -#endif -#ifndef RTE_CAN1_RD_PIN_EN - #define RTE_CAN1_RD_PIN_EN 1 -#endif -// CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0 -// CAN1 transmitter output. -#define RTE_CAN1_TD_ID 0 -#if (RTE_CAN1_TD_ID == 0) - #define RTE_CAN1_TD_PIN_EN 0 -#elif (RTE_CAN1_TD_ID == 1) - #define RTE_CAN1_TD_PORT 1 - #define RTE_CAN1_TD_BIT 17 - #define RTE_CAN1_TD_FUNC 5 -#elif (RTE_CAN1_TD_ID == 2) - #define RTE_CAN1_TD_PORT 4 - #define RTE_CAN1_TD_BIT 8 - #define RTE_CAN1_TD_FUNC 6 -#elif (RTE_CAN1_TD_ID == 3) - #define RTE_CAN1_TD_PORT 0xE - #define RTE_CAN1_TD_BIT 0 - #define RTE_CAN1_TD_FUNC 5 -#else - #error "Invalid RTE_CAN1_TD Pin Configuration!" -#endif -#ifndef RTE_CAN1_TD_PIN_EN - #define RTE_CAN1_TD_PIN_EN 1 -#endif -// Pin Configuration -// CAN1 Controller [Driver_CAN1] - - -#endif /* __RTE_DEVICE_H */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s deleted file mode 100644 index 19eac6d..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s +++ /dev/null @@ -1,333 +0,0 @@ -;/**************************************************************************//** -; * @file LPC43xx.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * NXP LPC43xxDevice Series -; * @version V1.00 -; * @date 03. September 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; * <<< Use Configuration Wizard in Context Menu >>> -; ******************************************************************************/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -Sign_Value EQU 0x5A5A5A5A - -__Vectors DCD __initial_sp ; 0 Top of Stack - DCD Reset_Handler ; 1 Reset Handler - DCD NMI_Handler ; 2 NMI Handler - DCD HardFault_Handler ; 3 Hard Fault Handler - DCD MemManage_Handler ; 4 MPU Fault Handler - DCD BusFault_Handler ; 5 Bus Fault Handler - DCD UsageFault_Handler ; 6 Usage Fault Handler - DCD Sign_Value ; 7 Reserved - DCD 0 ; 8 Reserved - DCD 0 ; 9 Reserved - DCD 0 ; 10 Reserved - DCD SVC_Handler ; 11 SVCall Handler - DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD 0 ; 13 Reserved - DCD PendSV_Handler ; 14 PendSV Handler - DCD SysTick_Handler ; 15 SysTick Handler - - ; External LPC43xx/M4 Interrupts - DCD DAC_IRQHandler ; 0 DAC interrupt - DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication - DCD DMA_IRQHandler ; 2 DMA interrupt - DCD 0 ; 3 Reserved - DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt - DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt - DCD SDIO_IRQHandler ; 6 SD/MMC interrupt - DCD LCD_IRQHandler ; 7 LCD interrupt - DCD USB0_IRQHandler ; 8 OTG interrupt - DCD USB1_IRQHandler ; 9 USB1 interrupt - DCD SCT_IRQHandler ; 10 SCT combined interrupt - DCD RITIMER_IRQHandler ; 11 RI Timer interrupt - DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt - DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt - DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt - DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt - DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt - DCD ADC0_IRQHandler ; 17 ADC0 interrupt - DCD I2C0_IRQHandler ; 18 I2C0 interrupt - DCD I2C1_IRQHandler ; 19 I2C1 interrupt - DCD SPI_IRQHandler ; 20 SPI interrupt - DCD ADC1_IRQHandler ; 21 ADC1 interrupt - DCD SSP0_IRQHandler ; 22 SSP0 interrupt - DCD SSP1_IRQHandler ; 23 SSP1 interrupt - DCD USART0_IRQHandler ; 24 USART0 interrupt - DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt - DCD USART2_IRQHandler ; 26 USART2 interrupt - DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt - DCD I2S0_IRQHandler ; 28 I2S0 interrupt - DCD I2S1_IRQHandler ; 29 I2S1 interrupt - DCD SPIFI_IRQHandler ; 30 SPISI interrupt - DCD SGPIO_IRQHandler ; 31 SGPIO interrupt - DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0 - DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1 - DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2 - DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3 - DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4 - DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5 - DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6 - DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7 - DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0 - DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1 - DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt - DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt - DCD 0 ; 44 Reserved - DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt - DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt - DCD RTC_IRQHandler ; 47 RTC interrupt - DCD 0 ; 48 Reserved - DCD WWDT_IRQHandler ; 49 WWDT interrupt - DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt - DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt - DCD QEI_IRQHandler ; 52 QEI interrupt - - -;CRP address at offset 0x2FC relative to the BOOT Bank address - IF :LNOT::DEF:NO_CRP - SPACE (0x2FC - (. - __Vectors)) -; EXPORT CRP_Key -CRP_Key DCD 0xFFFFFFFF -; 0xFFFFFFFF => CRP Disabled -; 0x12345678 => CRP Level 1 -; 0x87654321 => CRP Level 2 -; 0x43218765 => CRP Level 3 (ARE YOU SURE?) -; 0x4E697370 => NO ISP (ARE YOU SURE?) - ENDIF - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DAC_IRQHandler [WEAK] - EXPORT M0APP_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT FLASHEEPROM_IRQHandler [WEAK] - EXPORT ETHERNET_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USB1_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT RITIMER_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT I2S1_IRQHandler [WEAK] - EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SGPIO_IRQHandler [WEAK] - EXPORT PIN_INT0_IRQHandler [WEAK] - EXPORT PIN_INT1_IRQHandler [WEAK] - EXPORT PIN_INT2_IRQHandler [WEAK] - EXPORT PIN_INT3_IRQHandler [WEAK] - EXPORT PIN_INT4_IRQHandler [WEAK] - EXPORT PIN_INT5_IRQHandler [WEAK] - EXPORT PIN_INT6_IRQHandler [WEAK] - EXPORT PIN_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT EVENTROUTER_IRQHandler [WEAK] - EXPORT C_CAN1_IRQHandler [WEAK] - EXPORT ADCHS_IRQHandler [WEAK] - EXPORT ATIMER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT WWDT_IRQHandler [WEAK] - EXPORT M0SUB_IRQHandler [WEAK] - EXPORT C_CAN0_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - -DAC_IRQHandler -M0APP_IRQHandler -DMA_IRQHandler -FLASHEEPROM_IRQHandler -ETHERNET_IRQHandler -SDIO_IRQHandler -LCD_IRQHandler -USB0_IRQHandler -USB1_IRQHandler -SCT_IRQHandler -RITIMER_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -MCPWM_IRQHandler -ADC0_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI_IRQHandler -ADC1_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -USART0_IRQHandler -UART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -I2S0_IRQHandler -I2S1_IRQHandler -SPIFI_IRQHandler -SGPIO_IRQHandler -PIN_INT0_IRQHandler -PIN_INT1_IRQHandler -PIN_INT2_IRQHandler -PIN_INT3_IRQHandler -PIN_INT4_IRQHandler -PIN_INT5_IRQHandler -PIN_INT6_IRQHandler -PIN_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -EVENTROUTER_IRQHandler -C_CAN1_IRQHandler -ADCHS_IRQHandler -ATIMER_IRQHandler -RTC_IRQHandler -WWDT_IRQHandler -M0SUB_IRQHandler -C_CAN0_IRQHandler -QEI_IRQHandler - - B . - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c deleted file mode 100644 index 5c46381..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c +++ /dev/null @@ -1,938 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013 - 2017 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 10. September 2018 - * $Revision: V1.0.3 - * - * Project: NXP LPC43xx System initialization - * -------------------------------------------------------------------------- */ - -#include "LPC43xx.h" - -/*---------------------------------------------------------------------------- - This file configures the clocks as follows: - ----------------------------------------------------------------------------- - Clock Unit | Output clock | Source clock | Note - ----------------------------------------------------------------------------- - PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz - ----------------------------------------------------------------------------- - PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz - ----------------------------------------------------------------------------- - CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK - ----------------------------------------------------------------------------- - IDIV A | 60 MHz | PLL1 | To the USB1 peripheral - ----------------------------------------------------------------------------- - IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz - ----------------------------------------------------------------------------- - IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz - ----------------------------------------------------------------------------- - IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz - ----------------------------------------------------------------------------- - IDIV E | 5.3 MHz | PLL1 | To the LCD controller - -----------------------------------------------------------------------------*/ - - -/*---------------------------------------------------------------------------- - Clock source selection definitions (do not change) - *----------------------------------------------------------------------------*/ -#define CLK_SRC_32KHZ 0x00 -#define CLK_SRC_IRC 0x01 -#define CLK_SRC_ENET_RX 0x02 -#define CLK_SRC_ENET_TX 0x03 -#define CLK_SRC_GP_CLKIN 0x04 -#define CLK_SRC_XTAL 0x06 -#define CLK_SRC_PLL0U 0x07 -#define CLK_SRC_PLL0A 0x08 -#define CLK_SRC_PLL1 0x09 -#define CLK_SRC_IDIVA 0x0C -#define CLK_SRC_IDIVB 0x0D -#define CLK_SRC_IDIVC 0x0E -#define CLK_SRC_IDIVD 0x0F -#define CLK_SRC_IDIVE 0x10 - - -/*---------------------------------------------------------------------------- - Define external input frequency values - *----------------------------------------------------------------------------*/ -#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */ -#define CLK_IRC 12000000UL /* Internal oscillator frequency */ -#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */ -#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */ -#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */ -#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */ - - -/*---------------------------------------------------------------------------- - Define clock sources - *----------------------------------------------------------------------------*/ -#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */ -#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */ -#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */ -#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */ -#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */ -#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */ -#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */ - - -/*---------------------------------------------------------------------------- - Configure integer divider values - *----------------------------------------------------------------------------*/ -#define IDIVA_IDIV 2 /* Divide input clock by 3 */ -#define IDIVB_IDIV 1 /* Divide input clock by 2 */ -#define IDIVC_IDIV 0 /* Divide input clock by 1 */ -#define IDIVD_IDIV 0 /* Divide input clock by 1 */ -#define IDIVE_IDIV 33 /* Divide input clock by 34 */ - - -/*---------------------------------------------------------------------------- - Define CPU clock input - *----------------------------------------------------------------------------*/ -#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */ - - -/*---------------------------------------------------------------------------- - Configure external memory controller options - *----------------------------------------------------------------------------*/ -#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */ -#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */ - - -/*---------------------------------------------------------------------------- - * Configure PLL1 - *---------------------------------------------------------------------------- - * Integer mode: - * - PLL1_DIRECT = 0 (Post divider enabled) - * - PLL1_FBSEL = 1 (Feedback divider runs from PLL output) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M - * FCCO = FCLKOUT * 2 * P - * - * Non-integer: - * - PLL1_DIRECT = 0 (Post divider enabled) - * - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M / (2 * P) - * FCCO = FCLKOUT * 2 * P - * - * Direct mode: - * - PLL1_DIRECT = 1 (Post divider disabled) - * - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M - * FCCO = FCLKOUT - * - *---------------------------------------------------------------------------- - * PLL1 requirements: - * | Frequency | Minimum | Maximum | Note | - * | FCLKIN | 1MHz | 25MHz | Clock source is external crystal | - * | FCLKIN | 1MHz | 50MHz | | - * | FCCO | 156MHz | 320MHz | | - * | FCLKOUT | 9.75MHz | 320MHz | | - *---------------------------------------------------------------------------- - * Configuration examples: - * | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS | - * | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 | - * | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 | - * | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 | - * | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 | - * | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 | - * | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 | - * | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 | - *---------------------------------------------------------------------------- - * Relations beetwen PLL dividers and definitions: - * N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL - *----------------------------------------------------------------------------*/ - -/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */ -#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */ -#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */ -#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */ - -#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ -#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */ -#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */ - /* 1: FCLKOUT is used as PLL feedback */ - -/*---------------------------------------------------------------------------- - * Configure Flash Accelerator - *---------------------------------------------------------------------------- - * Flash acces time: - * | CPU clock | FLASHTIM | - * | up to 21MHz | 0 | - * | up to 43MHz | 1 | - * | up to 64MHz | 2 | - * | up to 86MHz | 3 | - * | up to 107MHz | 4 | - * | up to 129MHz | 5 | - * | up to 150MHz | 6 | - * | up to 172MHz | 7 | - * | up to 193MHz | 8 | - * | up to 204MHz | 9 | - *----------------------------------------------------------------------------*/ -#define FLASHCFG_FLASHTIM 9 - - -/*---------------------------------------------------------------------------- - * Configure PLL0USB - *---------------------------------------------------------------------------- - * - * Normal operating mode without post-divider and without pre-divider - * - PLL0USB_DIRECTI = 1 - * - PLL0USB_DIRECTO = 1 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * 2 * M - * FCCO = FOUT - * - * Normal operating mode with post-divider and without pre-divider - * - PLL0USB_DIRECTI = 1 - * - PLL0USB_DIRECTO = 0 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * (M / P) - * FCCO = FOUT * 2 * P - * - * Normal operating mode without post-divider and with pre-divider - * - PLL0USB_DIRECTI = 0 - * - PLL0USB_DIRECTO = 1 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * 2 * M / N - * FCCO = FOUT - * - * Normal operating mode with post-divider and with pre-divider - * - PLL0USB_DIRECTI = 0 - * - PLL0USB_DIRECTO = 0 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * M / (P * N) - * FCCO = FOUT * 2 * P - *---------------------------------------------------------------------------- - * PLL0 requirements: - * | Frequency | Minimum | Maximum | Note | - * | FCLKIN | 14kHz | 25MHz | Clock source is external crystal | - * | FCLKIN | 14kHz | 150MHz | | - * | FCCO | 275MHz | 550MHz | | - * | FCLKOUT | 4.3MHz | 550MHz | | - *---------------------------------------------------------------------------- - * Configuration examples: - * | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS | - * | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 | - * | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 | - *----------------------------------------------------------------------------*/ - -/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */ -#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */ -#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */ -#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */ - -#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */ -#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */ -#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ - - -/*---------------------------------------------------------------------------- - End of configuration - *----------------------------------------------------------------------------*/ - -/* PLL0 Setting Check */ -#if (PLL0USB_BYPASS == 0) - #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL) - #define PLL0USB_CLKIN CLK_XTAL - #else - #define PLL0USB_CLKIN CLK_IRC - #endif - - #if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M) - #define PLL0USB_FCCO (PLL0USB_FOUT) - #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P) - #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) - #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N) - #define PLL0USB_FCCO (PLL0USB_FOUT) - #else /* Mode 1d */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N)) - #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) - #endif - - #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL) - #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)" - #endif - #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL) - #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)" - #endif -#endif - -/* PLL1 Setting Check */ -#if (PLL1_BYPASS == 0) - #if (PLL1_CLK_SEL == CLK_SRC_XTAL) - #define PLL1_CLKIN CLK_XTAL - #else - #define PLL1_CLKIN CLK_IRC - #endif - - #if (PLL1_DIRECT == 1) /* Direct Mode */ - #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #elif (PLL1_FBSEL == 1) /* Integer Mode */ - #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #else /* Noninteger Mode */ - #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL))) - #endif - #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL) - #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)" - #endif - #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL) - #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)" - #endif -#endif - - -/*---------------------------------------------------------------------------- - System Core Clock variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */ - - -/****************************************************************************** - * SetClock - ******************************************************************************/ -void SetClock (void) { - uint32_t x, i; - uint32_t selp, seli; - - - /* Set flash accelerator configuration for bank A and B to reset value */ - LPC_CREG->FLASHCFGA |= (0xF << 12); - LPC_CREG->FLASHCFGB |= (0xF << 12); - - /* Set flash wait states to maximum */ - LPC_EMC->STATICWAITRD0 = 0x1F; - - /* Switch BASE_M4_CLOCK to IRC */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (CLK_SRC_IRC << 24) ; /* Set clock source */ - - /* Configure input to crystal oscilator */ - LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */ - (0 << 1) | /* Operation with crystal connected */ - (0 << 2) ; /* Low-frequency mode */ - - /* Wait ~250us @ 12MHz */ - for (i = 1500; i; i--); - -#if (USE_SPIFI) -/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */ - LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ - (0 << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (CLK_SRC_IRC << 24) ; /* Clock source */ - - LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */ - (0 << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (CLK_SRC_IDIVA << 24) ; /* Clock source */ -#endif - -/*---------------------------------------------------------------------------- - PLL1 Setup - *----------------------------------------------------------------------------*/ - /* Power down PLL */ - LPC_CGU->PLL1_CTRL |= 1; - -#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1)) - /* To run at full speed, CPU must first run at an intermediate speed */ - LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ - (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ - (PLL1_FBSEL << 6) | /* PLL output used as feedback */ - (0 << 7) | /* Direct on/off */ - (PLL1_PSEL << 8) | /* PSEL */ - (0 << 11)| /* Autoblock Disabled */ - (PLL1_NSEL << 12)| /* NSEL */ - (PLL1_MSEL << 16)| /* MSEL */ - (PLL1_CLK_SEL << 24); /* Clock source */ - /* Wait for lock */ - while (!(LPC_CGU->PLL1_STAT & 1)); - - /* CPU base clock is in the mid frequency range before final clock set */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (0x09 << 24) ; /* Clock source: PLL1 */ - - /* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */ - for (i = 1050; i; i--); /* Wait minimum 2100 cycles */ -#endif - /* Configure PLL1 */ - LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ - (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ - (PLL1_FBSEL << 6) | /* PLL output used as feedback */ - (PLL1_DIRECT << 7) | /* Direct on/off */ - (PLL1_PSEL << 8) | /* PSEL */ - (1 << 11)| /* Autoblock En */ - (PLL1_NSEL << 12)| /* NSEL */ - (PLL1_MSEL << 16)| /* MSEL */ - (PLL1_CLK_SEL << 24); /* Clock source */ - - /* Wait for lock */ - while (!(LPC_CGU->PLL1_STAT & 1)); - - /* Set CPU base clock source */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (CPU_CLK_SEL << 24) ; /* Set clock source */ - - /* Set flash accelerator configuration for internal flash bank A and B */ - LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12); - LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12); - -/*---------------------------------------------------------------------------- - PLL0USB Setup - *----------------------------------------------------------------------------*/ - - /* Power down PLL0USB */ - LPC_CGU->PLL0USB_CTRL |= 1; - - /* M divider */ - x = 0x00004000; - switch (PLL0USB_M) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00018003; - break; - case 2: x = 0x00010003; - break; - default: - for (i = PLL0USB_M; i <= 0x8000; i++) { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - } - } - - if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1; - else selp = 31; - - if (PLL0USB_M > 16384) seli = 1; - else if (PLL0USB_M > 8192) seli = 2; - else if (PLL0USB_M > 2048) seli = 4; - else if (PLL0USB_M >= 501) seli = 8; - else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9)); - else seli = (PLL0USB_M & 0x3C) + 4; - LPC_CGU->PLL0USB_MDIV = (selp << 17) | - (seli << 22) | - (x << 0); - - /* N divider */ - x = 0x80; - switch (PLL0USB_N) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00000302; - break; - case 2: x = 0x00000202; - break; - default: - for (i = PLL0USB_N; i <= 0x0100; i++) { - x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - } - } - LPC_CGU->PLL0USB_NP_DIV = (x << 12); - - /* P divider */ - x = 0x10; - switch (PLL0USB_P) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00000062; - break; - case 2: x = 0x00000042; - break; - default: - for (i = PLL0USB_P; i <= 0x200; i++) { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F); - } - } - LPC_CGU->PLL0USB_NP_DIV |= x; - - LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */ - (1 << 11) | /* Autoblock En */ - (1 << 4 ) | /* PLL0USB clock en */ - (PLL0USB_DIRECTO << 3 ) | /* Direct output */ - (PLL0USB_DIRECTI << 2 ) | /* Direct input */ - (PLL0USB_BYPASS << 1 ) | /* PLL bypass */ - (0 << 0 ) ; /* PLL0USB Enabled */ - while (!(LPC_CGU->PLL0USB_STAT & 1)); - - -/*---------------------------------------------------------------------------- - Integer divider Setup - *----------------------------------------------------------------------------*/ - - /* Configure integer dividers */ - LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVA_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVA_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVB_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVB_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVC_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVC_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVD_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVD_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVE_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVE_CLK_SEL << 24) ; /* Clock source */ -} - - -/*---------------------------------------------------------------------------- - Approximate delay function (must be used after SystemCoreClockUpdate() call) - *----------------------------------------------------------------------------*/ -#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000) - -static void WaitUs (uint32_t us) { - uint32_t cyc = us * CPU_NANOSEC(1000)/4; - while(cyc--); -} - - -/*---------------------------------------------------------------------------- - External Memory Controller Definitions - *----------------------------------------------------------------------------*/ -#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */ -/* Write Mode register macro */ -#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x)))) - -/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */ -#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)) -#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000) - -#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */ -#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */ - -typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg); - -const uint16_t emcdivby2_opc[] = { - 0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */ - 0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */ - 0x6003, /* STR R3,[R0,#0] ; Store CREG6 */ - 0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */ - 0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */ - 0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */ - 0xD0FC, /* BEQ loop ; Jump if 0 */ - 0x4770, /* BX LR ; Exit */ - 0, -}; - -#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4) -#define emcdivby2_ram 0x10000000 - -/*---------------------------------------------------------------------------- - Initialize external memory controller - *----------------------------------------------------------------------------*/ - -void SystemInit_ExtMemCtl (void) { - uint32_t emcdivby2_buf[emcdivby2_szw]; - uint32_t div, n; - - /* Select and enable EMC branch clock */ - LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1; - while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1)); - - /* Set EMC clock output delay */ - if (SystemCoreClock < 80000000UL) { - LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */ - } - else { - LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */ - } - - /* Configure EMC port pins */ - LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */ - LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */ - LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */ - LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */ - LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */ - LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */ - LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */ - LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */ - LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */ - LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */ - LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */ - LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */ - LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */ - LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */ - LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */ - - LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */ - LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */ - LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */ - LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */ - LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */ - LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */ - LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */ - LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */ - LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */ - LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */ - LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */ - - LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */ - LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */ - LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */ - LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */ - LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */ - LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */ - LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */ - LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */ - - LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */ - LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */ - LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */ - LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */ - LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */ - LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */ - LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */ - LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */ - LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */ - LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */ - LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */ - LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */ - - LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */ - - LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */ - LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */ - LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */ - LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */ - LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */ - LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */ - LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */ - LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */ - LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */ - LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */ - LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */ - LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */ - LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */ - LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */ - LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */ - LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */ - LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */ - - LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */ - LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */ - LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */ - LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */ - LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */ - LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */ - LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */ - LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */ - LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */ - LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */ - LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */ - LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */ - LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */ - LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */ - LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */ - LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */ - - LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */ - LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */ - - div = 0; - if (SystemCoreClock > 120000000UL) { - /* Use EMC clock divider and EMC clock output delay */ - div = 1; - /* Following code must be executed in RAM to ensure stable operation */ - /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */ - /* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */ - /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */ - - /* This code configures EMC clock divider and is executed in RAM */ - for (n = 0; n < emcdivby2_szw; n++) { - emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n); - *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n); - } - __ISB(); - ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1); - for (n = 0; n < emcdivby2_szw; n++) { - *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n]; - } - } - - /* Configure EMC clock-out pins */ - LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */ - LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */ - LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */ - LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */ - - /* Static memory configuration (chip select 0) */ -#if (USE_EXT_STAT_MEM_CS0) - LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */ - (2 << 0) | /* Memory width 32-bit */ - (1 << 3); /* Async page mode enable */ - - LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */ - - LPC_EMC->STATICWAITPAGE0 = 2; - - /* Set Static Memory Read Delay for 90ns External NOR Flash */ - LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div); - LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */ -#endif - - /* Dynamic memory configuration (chip select 0) */ -#if (USE_EXT_DYN_MEM_CS0) - - /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */ - LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */ - (0 << 12) | /* AM[12] = 0 */ - (2 << 9) | /* AM[11:9] = 2 */ - (2 << 7) ; /* AM[8:7] = 2 */ - - LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/ - LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */ - - LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div); - LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div); - LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div); - LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div); - LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div); - LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div); - LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div); - - WaitUs (100); - LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */ - WaitUs (1); - LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ - WaitUs (1); - LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1; - WaitUs (10); - LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1; - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */ - - /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */ - WR_MODE(((3 << 4) | 2) << 12); - - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */ - LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */ -#endif -} - - -/*---------------------------------------------------------------------------- - Measure frequency using frequency monitor - *----------------------------------------------------------------------------*/ -uint32_t MeasureFreq (uint32_t clk_sel) { - uint32_t fcnt, rcnt, fout; - - /* Set register values */ - LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */ - LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */ - LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */ - while (LPC_CGU->FREQ_MON & (1 << 23)) { - fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; - rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF; - if (fcnt == 0 && rcnt == 0) { - return (0); /* No input clock present */ - } - } - fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; - fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */ - - return (fout); -} - - -/*---------------------------------------------------------------------------- - Get PLL1 (divider and multiplier) parameters - *----------------------------------------------------------------------------*/ -static __inline uint32_t GetPLL1Param (void) { - uint32_t ctrl; - uint32_t p; - uint32_t div, mul; - - ctrl = LPC_CGU->PLL1_CTRL; - div = ((ctrl >> 12) & 0x03) + 1; - mul = ((ctrl >> 16) & 0xFF) + 1; - p = 1 << ((ctrl >> 8) & 0x03); - - if (ctrl & (1 << 1)) { - /* Bypass = 1, PLL1 input clock sent to post-dividers */ - if (ctrl & (1 << 7)) { - div *= (2*p); - } - } - else { - /* Direct and integer mode */ - if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) { - /* Non-integer mode */ - div *= (2*p); - } - } - return ((div << 8) | (mul)); -} - - -/*---------------------------------------------------------------------------- - Get input clock source for specified clock generation block - *----------------------------------------------------------------------------*/ -int32_t GetClkSel (uint32_t clk_src) { - uint32_t reg; - int32_t clk_sel = -1; - - switch (clk_src) { - case CLK_SRC_IRC: - case CLK_SRC_ENET_RX: - case CLK_SRC_ENET_TX: - case CLK_SRC_GP_CLKIN: - return (clk_src); - - case CLK_SRC_32KHZ: - return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ); - case CLK_SRC_XTAL: - return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL); - - case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break; - case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break; - case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break; - - case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break; - case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break; - case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break; - case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break; - case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break; - - default: - return (clk_sel); - } - if (!(reg & 1)) { - clk_sel = (reg >> 24) & 0x1F; - } - return (clk_sel); -} - - -/*---------------------------------------------------------------------------- - Get clock frequency for specified clock source - *----------------------------------------------------------------------------*/ -uint32_t GetClockFreq (uint32_t clk_src) { - uint32_t tmp; - uint32_t mul = 1; - uint32_t div = 1; - uint32_t main_freq = 0; - int32_t clk_sel = clk_src; - - do { - switch (clk_sel) { - case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break; - case CLK_SRC_IRC: main_freq = CLK_IRC; break; - case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break; - case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break; - case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break; - case CLK_SRC_XTAL: main_freq = CLK_XTAL; break; - - case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break; - case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break; - - case CLK_SRC_PLL0U: /* Not implemented */ break; - case CLK_SRC_PLL0A: /* Not implemented */ break; - - case CLK_SRC_PLL1: - tmp = GetPLL1Param (); - mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */ - div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */ - break; - - default: - return (0); /* Clock not running or not supported */ - } - if (main_freq == 0) { - clk_sel = GetClkSel (clk_sel); - } - } - while (main_freq == 0); - - return ((main_freq * mul) / div); -} - - -/*---------------------------------------------------------------------------- - System Core Clock update - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) { - /* Check BASE_M4_CLK connection */ - uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F; - - /* Update core clock frequency */ - SystemCoreClock = GetClockFreq (base_src); -} - - -extern uint32_t __Vectors; /* see startup_LPC43xx.s */ - -/*---------------------------------------------------------------------------- - Initialize the system - *----------------------------------------------------------------------------*/ -void SystemInit (void) { - - #if (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ - #endif - - /* Stop CM0 core */ - LPC_RGU->RESET_CTRL1 = (1 << 24); - - /* Disable SysTick timer */ - SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); - - /* Set vector table pointer */ - SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL; - - /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */ - SetClock(); - - /* Update SystemCoreClock variable */ - SystemCoreClockUpdate(); - - /* Configure External Memory Controller */ -//SystemInit_ExtMemCtl (); -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_0.c deleted file mode 100644 index a541cb9..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_0.c +++ /dev/null @@ -1,206 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_Config_0.c - * Purpose: USB Device Configuration - * Rev.: V5.2.0 - *------------------------------------------------------------------------------ - * Use the following configuration settings in the Device Class configuration - * files to assign a Device Class to this USB Device 0. - * - * Configuration Setting Value - * --------------------- ----- - * Assign Device Class to USB Device # = 0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// USB Device 0 -// Connect to hardware via Driver_USBD# <0-255> -// Select driver control block for hardware interface. -#define USBD0_PORT 0 - -// High-speed -// Enable High-speed functionality (if device supports it). -#define USBD0_HS 1 - -// Device Settings -// These settings are used to create the Device Descriptor -// Max Endpoint 0 Packet Size -// Maximum packet size for Endpoint 0 (bMaxPacketSize0). -// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes -#define USBD0_MAX_PACKET0 64 - -// Vendor ID <0x0000-0xFFFF> -// Vendor ID assigned by USB-IF (idVendor). -#define USBD0_DEV_DESC_IDVENDOR 0xC251 - -// Product ID <0x0000-0xFFFF> -// Product ID assigned by manufacturer (idProduct). -#define USBD0_DEV_DESC_IDPRODUCT 0xF00A - -// Device Release Number <0x0000-0xFFFF> -// Device Release Number in binary-coded decimal (bcdDevice) -#define USBD0_DEV_DESC_BCDDEVICE 0x0100 - -// - -// Configuration Settings -// These settings are used to create the Configuration Descriptor. -// Power -// Default Power Setting (D6: of bmAttributes). -// <0=>Bus-powered -// <1=>Self-powered -// Remote Wakeup -// Configuration support for Remote Wakeup (D5: of bmAttributes). -#define USBD0_CFG_DESC_BMATTRIBUTES 0x80 - -// Maximum Power Consumption (in mA) <0-510><#/2> -// Maximum Power Consumption of USB Device from bus in this -// specific configuration when device is fully operational (bMaxPower). -#define USBD0_CFG_DESC_BMAXPOWER 250 - -// - -// String Settings -// These settings are used to create the String Descriptor. -// Language ID <0x0000-0xFCFF> -// English (United States) = 0x0409. -#define USBD0_STR_DESC_LANGID 0x0409 - -// Manufacturer String -// String Descriptor describing Manufacturer. -#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM" - -// Product String -// String Descriptor describing Product. -#define USBD0_STR_DESC_PROD L"LPC-Link2" - -// Serial Number String -// Enable Serial Number String. -// If disabled Serial Number String will not be assigned to USB Device. -#define USBD0_STR_DESC_SER_EN 1 - -// Default value -// Default device's Serial Number String. -#define USBD0_STR_DESC_SER L"0001A0000000" - -// Maximum Length (in characters) <0-126> -// Specifies the maximum number of Serial Number String characters that can be set at run-time. -// Maximum value is 126. Use value 0 to disable RAM allocation for string. -#define USBD0_STR_DESC_SER_MAX_LEN 16 - -// -// - -// Microsoft OS Descriptors Settings -// These settings are used to create the Microsoft OS Descriptors. -// OS String -// Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors. -#define USBD0_OS_DESC_EN 1 - -// Vendor Code <0x01-0xFF> -// Specifies Vendor Code used to retrieve OS Feature Descriptors. -#define USBD0_OS_DESC_VENDOR_CODE 0x01 - -// -// - -// Control Transfer Buffer Size <64-65536:64> -// Specifies size of buffer used for Control Transfers. -// It should be at least as big as maximum packet size for Endpoint 0. -#define USBD0_EP0_BUF_SIZE 128 - -// OS Resources Settings -// These settings are used to optimize usage of OS resources. -// Core Thread Stack Size <64-65536> -#define USBD0_CORE_THREAD_STACK_SIZE 1024 - -// Core Thread Priority -#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal - -// -// - - -#include "RTE_Components.h" - -#ifdef RTE_USB_Device_CustomClass_0 -#include "USBD_Config_CustomClass_0.h" -#endif -#ifdef RTE_USB_Device_CustomClass_1 -#include "USBD_Config_CustomClass_1.h" -#endif -#ifdef RTE_USB_Device_CustomClass_2 -#include "USBD_Config_CustomClass_2.h" -#endif -#ifdef RTE_USB_Device_CustomClass_3 -#include "USBD_Config_CustomClass_3.h" -#endif - -#ifdef RTE_USB_Device_HID_0 -#include "USBD_Config_HID_0.h" -#endif -#ifdef RTE_USB_Device_HID_1 -#include "USBD_Config_HID_1.h" -#endif -#ifdef RTE_USB_Device_HID_2 -#include "USBD_Config_HID_2.h" -#endif -#ifdef RTE_USB_Device_HID_3 -#include "USBD_Config_HID_3.h" -#endif - -#ifdef RTE_USB_Device_MSC_0 -#include "USBD_Config_MSC_0.h" -#endif -#ifdef RTE_USB_Device_MSC_1 -#include "USBD_Config_MSC_1.h" -#endif -#ifdef RTE_USB_Device_MSC_2 -#include "USBD_Config_MSC_2.h" -#endif -#ifdef RTE_USB_Device_MSC_3 -#include "USBD_Config_MSC_3.h" -#endif - -#ifdef RTE_USB_Device_CDC_0 -#include "USBD_Config_CDC_0.h" -#endif -#ifdef RTE_USB_Device_CDC_1 -#include "USBD_Config_CDC_1.h" -#endif -#ifdef RTE_USB_Device_CDC_2 -#include "USBD_Config_CDC_2.h" -#endif -#ifdef RTE_USB_Device_CDC_3 -#include "USBD_Config_CDC_3.h" -#endif -#ifdef RTE_USB_Device_CDC_4 -#include "USBD_Config_CDC_4.h" -#endif -#ifdef RTE_USB_Device_CDC_5 -#include "USBD_Config_CDC_5.h" -#endif -#ifdef RTE_USB_Device_CDC_6 -#include "USBD_Config_CDC_6.h" -#endif -#ifdef RTE_USB_Device_CDC_7 -#include "USBD_Config_CDC_7.h" -#endif - -#ifdef RTE_USB_Device_ADC_0 -#include "USBD_Config_ADC_0.h" -#endif -#ifdef RTE_USB_Device_ADC_1 -#include "USBD_Config_ADC_1.h" -#endif -#ifdef RTE_USB_Device_ADC_2 -#include "USBD_Config_ADC_2.h" -#endif -#ifdef RTE_USB_Device_ADC_3 -#include "USBD_Config_ADC_3.h" -#endif - -#include "usbd_config.h" diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_CDC_0.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_CDC_0.h deleted file mode 100644 index 7cf68d1..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_CDC_0.h +++ /dev/null @@ -1,364 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_Config_CDC_0.h - * Purpose: USB Device Communication Device Class (CDC) Configuration - * Rev.: V5.2.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// USB Device: Communication Device Class (CDC) 0 -// Assign Device Class to USB Device # <0-3> -// Select USB Device that is used for this Device Class instance -#define USBD_CDC0_DEV 0 - -// Communication Class Subclass -// Specifies the model used by the CDC class. -// <2=>Abstract Control Model (ACM) -// <13=>Network Control Model (NCM) -#define USBD_CDC0_SUBCLASS 2 - -// Communication Class Protocol -// Specifies the protocol used by the CDC class. -// <0=>No protocol (Virtual COM) -// <255=>Vendor-specific (RNDIS) -#define USBD_CDC0_PROTOCOL 0 - -// Interrupt Endpoint Settings -// By default, the settings match the first USB Class instance in a USB Device. -// Endpoint conflicts are flagged by compile-time error messages. - -// Interrupt IN Endpoint Number -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -#define USBD_CDC0_EP_INT_IN 3 - - -// Endpoint Settings -// Parameters are used to create Endpoint Descriptors -// and for memory allocation in the USB component. - -// Full/Low-speed (High-speed disabled) -// Parameters apply when High-speed is disabled in USBD_Config_n.c -// Maximum Endpoint Packet Size (in bytes) <0-64> -// Specifies the physical packet size used for information exchange. -// Maximum value is 64. -#define USBD_CDC0_WMAXPACKETSIZE 16 - -// Endpoint polling Interval (in ms) <1-255> -// Specifies the frequency of requests initiated by USB Host for -// getting the notification. -#define USBD_CDC0_BINTERVAL 2 - -// - -// High-speed -// Parameters apply when High-speed is enabled in USBD_Config_n.c -// -// Maximum Endpoint Packet Size (in bytes) <0-1024> -// Specifies the physical packet size used for information exchange. -// Maximum value is 1024. -// Additional transactions per microframe -// Additional transactions improve communication performance. -// <0=>None <1=>1 additional <2=>2 additional -#define USBD_CDC0_HS_WMAXPACKETSIZE 16 - -// Endpoint polling Interval (in 125 us intervals) -// Specifies the frequency of requests initiated by USB Host for -// getting the notification. -// <1=> 1 <2=> 2 <3=> 4 <4=> 8 -// <5=> 16 <6=> 32 <7=> 64 <8=> 128 -// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 -// <13=>4096 <14=>8192 <15=>16384 <16=>32768 -#define USBD_CDC0_HS_BINTERVAL 2 - -// -// -// - - -// Bulk Endpoint Settings -// By default, the settings match the first USB Class instance in a USB Device. -// Endpoint conflicts are flagged by compile-time error messages. - -// Bulk IN Endpoint Number -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -#define USBD_CDC0_EP_BULK_IN 4 - -// Bulk OUT Endpoint Number -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -#define USBD_CDC0_EP_BULK_OUT 4 - - -// Endpoint Settings -// Parameters are used to create USB Descriptors and for memory -// allocation in the USB component. -// -// Full/Low-speed (High-speed disabled) -// Parameters apply when High-speed is disabled in USBD_Config_n.c -// Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64 -// Specifies the physical packet size used for information exchange. -// Maximum value is 64. -#define USBD_CDC0_WMAXPACKETSIZE1 64 - -// - -// High-speed -// Parameters apply when High-speed is enabled in USBD_Config_n.c -// -// Maximum Endpoint Packet Size (in bytes) <512=>512 -// Specifies the physical packet size used for information exchange. -// Only available value is 512. -#define USBD_CDC0_HS_WMAXPACKETSIZE1 512 - -// Maximum NAK Rate <0-255> -// Specifies the interval in which Bulk Endpoint can NAK. -// Value of 0 indicates that Bulk Endpoint never NAKs. -#define USBD_CDC0_HS_BINTERVAL1 0 - -// -// -// - -// Communication Device Class Settings -// Parameters are used to create USB Descriptors and for memory allocation -// in the USB component. -// -// Communication Class Interface String -#define USBD_CDC0_CIF_STR_DESC L"USB_CDC0_0" - -// Data Class Interface String -#define USBD_CDC0_DIF_STR_DESC L"USB_CDC0_1" - -// Abstract Control Model Settings - -// Call Management Capabilities -// Specifies which call management functionality is supported. -// Call Management channel -// <0=>Communication Class Interface only -// <1=>Communication and Data Class Interface -// Device Call Management handling -// <0=>None -// <1=>All -// -#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03 - -// Abstract Control Management Capabilities -// Specifies which abstract control management functionality is supported. -// D3 bit -// Enabled = Supports the notification Network_Connection -// D2 bit -// Enabled = Supports the request Send_Break -// D1 bit -// Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding, -// Set_Control_Line_State, and notification Serial_State -// D0 bit -// Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature -// -#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06 - -// Maximum Communication Device Send Buffer Size -// Specifies size of buffer used for sending of data to USB Host. -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes -// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes -#define USBD_CDC0_ACM_SEND_BUF_SIZE 1024 - -// Maximum Communication Device Receive Buffer Size -// Specifies size of buffer used for receiving of data from USB Host. -// Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint. -// Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint. -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes -// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes -#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE 2048 - -// - -// Network Control Model Settings - -// MAC Address String -// Specifies 48-bit Ethernet MAC address. -#define USBD_CDC0_NCM_MAC_ADDRESS L"1E306CA2455E" - -// Ethernet Statistics -// Specifies Ethernet statistic functions supported. -// XMIT_OK -// Frames transmitted without errors -// RVC_OK -// Frames received without errors -// XMIT_ERROR -// Frames not transmitted, or transmitted with errors -// RCV_ERROR -// Frames received with errors that are not delivered to the USB host. -// RCV_NO_BUFFER -// Frame missed, no buffers -// DIRECTED_BYTES_XMIT -// Directed bytes transmitted without errors -// DIRECTED_FRAMES_XMIT -// Directed frames transmitted without errors -// MULTICAST_BYTES_XMIT -// Multicast bytes transmitted without errors -// MULTICAST_FRAMES_XMIT -// Multicast frames transmitted without errors -// BROADCAST_BYTES_XMIT -// Broadcast bytes transmitted without errors -// BROADCAST_FRAMES_XMIT -// Broadcast frames transmitted without errors -// DIRECTED_BYTES_RCV -// Directed bytes received without errors -// DIRECTED_FRAMES_RCV -// Directed frames received without errors -// MULTICAST_BYTES_RCV -// Multicast bytes received without errors -// MULTICAST_FRAMES_RCV -// Multicast frames received without errors -// BROADCAST_BYTES_RCV -// Broadcast bytes received without errors -// BROADCAST_FRAMES_RCV -// Broadcast frames received without errors -// RCV_CRC_ERROR -// Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error -// TRANSMIT_QUEUE_LENGTH -// Length of transmit queue -// RCV_ERROR_ALIGNMENT -// Frames received with alignment error -// XMIT_ONE_COLLISION -// Frames transmitted with one collision -// XMIT_MORE_COLLISIONS -// Frames transmitted with more than one collision -// XMIT_DEFERRED -// Frames transmitted after deferral -// XMIT_MAX_COLLISIONS -// Frames not transmitted due to collisions -// RCV_OVERRUN -// Frames not received due to overrun -// XMIT_UNDERRUN -// Frames not transmitted due to underrun -// XMIT_HEARTBEAT_FAILURE -// Frames transmitted with heartbeat failure -// XMIT_TIMES_CRS_LOST -// Times carrier sense signal lost during transmission -// XMIT_LATE_COLLISIONS -// Late collisions detected -// -#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS 0x00000003 - -// Maximum Segment Size -// Specifies maximum segment size that Ethernet device is capable of supporting. -// Typically 1514 bytes. -#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE 1514 - -// Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing) -// Specifies multicast filtering type. -// Number of Multicast Filters -// Specifies number of multicast filters that can be configured by the USB Host. -#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS 1 - -// Number of Power Filters -// Specifies number of pattern filters that are available for causing wake-up of the USB Host. -#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS 0 - -// Network Capabilities -// Specifies which functions are supported. -// SetCrcMode/GetCrcMode -// SetMaxDatagramSize/GetMaxDatagramSize -// SetNetAddress/GetNetAddress -// SetEthernetPacketFilter -// -#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES 0x1B - -// NTB Parameters -// Specifies NTB parameters reported by GetNtbParameters function. - -// NTB Formats Supported (bmNtbFormatsSupported) -// Specifies NTB formats supported. -// 16-bit NTB (always supported) -// 32-bit NTB -// -#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED 0x0001 - -// IN Data Pipe -// -// Maximum NTB Size (dwNtbInMaxSize) -// Specifies maximum IN NTB size in bytes. -#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE 4096 - -// NTB Datagram Payload Alignment Divisor (wNdpInDivisor) -// Specifies divisor used for IN NTB Datagram payload alignment. -#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR 4 - -// NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder) -// Specifies remainder used to align input datagram payload within the NTB. -// (Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder -#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER 0 - -// NDP Alignment Modulus in NTB (wNdpInAlignment) -// Specifies NDP alignment modulus for NTBs on the IN pipe. -// Shall be power of 2, and shall be at least 4. -#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT 4 - -// - -// OUT Data Pipe -// -// Maximum NTB Size (dwNtbOutMaxSize) -// Specifies maximum OUT NTB size in bytes. -#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE 4096 - -// NTB Datagram Payload Alignment Divisor (wNdpOutDivisor) -// Specifies divisor used for OUT NTB Datagram payload alignment. -#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR 4 - -// NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder) -// Specifies remainder used to align output datagram payload within the NTB. -// (Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder -#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0 - -// NDP Alignment Modulus in NTB (wNdpOutAlignment) -// Specifies NDP alignment modulus for NTBs on the IN pipe. -// Shall be power of 2, and shall be at least 4. -#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT 4 - -// - -// - -// Raw Data Access API -// Enables or disables Raw Data Access API. -#define USBD_CDC0_NCM_RAW_ENABLE 0 - -// IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer -// Specifies buffering used for sending data to USB Host. -// Not used when RAW Data Access API is enabled. -#define USBD_CDC0_NCM_NTB_IN_BUF_CNT 1 - -// OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer -// Specifies buffering used for receiving data from USB Host. -// Not used when RAW Data Access API is enabled. -#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT 1 - -// - -// - -// OS Resources Settings -// These settings are used to optimize usage of OS resources. -// Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536> -#define USBD_CDC0_INT_THREAD_STACK_SIZE 512 - -// Communication Device Class Interrupt Endpoint Thread Priority -#define USBD_CDC0_INT_THREAD_PRIORITY osPriorityAboveNormal - -// Communication Device Class Bulk Endpoints Thread Stack Size <64-65536> -#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512 - -// Communication Device Class Bulk Endpoints Thread Priority -#define USBD_CDC0_BULK_THREAD_PRIORITY osPriorityAboveNormal - -// -// diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_CustomClass_0.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_CustomClass_0.h deleted file mode 100644 index c576037..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_CustomClass_0.h +++ /dev/null @@ -1,3771 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2017 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_Config_CustomClass_0.h - * Purpose: USB Device Custom Class Configuration - * Rev.: V5.2.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// USB Device: Custom Class 0 -// Custom Class can be used to make support for Standard or Vendor-Specific Class -// Assign Device Class to USB Device # <0-3> -// Select USB Device that is used for this Device Class instance -#define USBD_CUSTOM_CLASS0_DEV 0 - -// Interface Association -// Used for grouping of multiple interfaces to a single class. -#define USBD_CUSTOM_CLASS0_IAD_EN 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IAD_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IAD_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IAD_PROTOCOL 0x00 - -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF0_EN 1 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF0_NUM 0 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF0_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF0_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF0_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF0_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP0_EN 1 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP1_EN 1 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP2_EN 1 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP2_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP2_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 0. -#define USBD_CUSTOM_CLASS0_IF0_STR_EN 1 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF0_STR L"LPC-Link2 CMSIS-DAP" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID_EN 1 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_EN 1 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_STR L"{CDB3B5AD-293B-4663-AA36-1AAE46463776}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF1_EN 0 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF1_NUM 1 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF1_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF1_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF1_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF1_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP0_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP1_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP2_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP2_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP2_BENDPOINTADDRESS 0x02 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 1. -#define USBD_CUSTOM_CLASS0_IF1_STR_EN 0 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF1_STR L"USB_CUSTOM_CLASS0_IF1" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID_EN 0 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF2_EN 0 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF2_NUM 2 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF2_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF2_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF2_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF2_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP0_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP1_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP2_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP2_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP2_BENDPOINTADDRESS 0x02 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 2. -#define USBD_CUSTOM_CLASS0_IF2_STR_EN 0 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF2_STR L"USB_CUSTOM_CLASS0_IF2" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID_EN 0 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF3_EN 0 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF3_NUM 3 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF3_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF3_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF3_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF3_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP0_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP1_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP2_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP2_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP2_BENDPOINTADDRESS 0x02 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 3. -#define USBD_CUSTOM_CLASS0_IF3_STR_EN 0 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF3_STR L"USB_CUSTOM_CLASS0_IF3" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID_EN 0 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// OS Resources Settings -// These settings are used to optimize usage of OS resources. -// Endpoint 1 Thread Stack Size <64-65536> -// This setting is used if Endpoint 1 is enabled. -#define USBD_CUSTOM_CLASS0_EP1_THREAD_STACK_SIZE 512 - -// Endpoint 1 Thread Priority -#define USBD_CUSTOM_CLASS0_EP1_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 2 Thread Stack Size <64-65536> -// This setting is used if Endpoint 2 is enabled. -#define USBD_CUSTOM_CLASS0_EP2_THREAD_STACK_SIZE 512 - -// Endpoint 2 Thread Priority -#define USBD_CUSTOM_CLASS0_EP2_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 3 Thread Stack Size <64-65536> -// This setting is used if Endpoint 3 is enabled. -#define USBD_CUSTOM_CLASS0_EP3_THREAD_STACK_SIZE 512 - -// Endpoint 3 Thread Priority -#define USBD_CUSTOM_CLASS0_EP3_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 4 Thread Stack Size <64-65536> -// This setting is used if Endpoint 4 is enabled. -#define USBD_CUSTOM_CLASS0_EP4_THREAD_STACK_SIZE 512 - -// Endpoint 4 Thread Priority -#define USBD_CUSTOM_CLASS0_EP4_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 5 Thread Stack Size <64-65536> -// This setting is used if Endpoint 5 is enabled. -#define USBD_CUSTOM_CLASS0_EP5_THREAD_STACK_SIZE 512 - -// Endpoint 5 Thread Priority -#define USBD_CUSTOM_CLASS0_EP5_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 6 Thread Stack Size <64-65536> -// This setting is used if Endpoint 6 is enabled. -#define USBD_CUSTOM_CLASS0_EP6_THREAD_STACK_SIZE 512 - -// Endpoint 6 Thread Priority -#define USBD_CUSTOM_CLASS0_EP6_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 7 Thread Stack Size <64-65536> -// This setting is used if Endpoint 7 is enabled. -#define USBD_CUSTOM_CLASS0_EP7_THREAD_STACK_SIZE 512 - -// Endpoint 7 Thread Priority -#define USBD_CUSTOM_CLASS0_EP7_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 8 Thread Stack Size <64-65536> -// This setting is used if Endpoint 8 is enabled. -#define USBD_CUSTOM_CLASS0_EP8_THREAD_STACK_SIZE 512 - -// Endpoint 8 Thread Priority -#define USBD_CUSTOM_CLASS0_EP8_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 9 Thread Stack Size <64-65536> -// This setting is used if Endpoint 9 is enabled. -#define USBD_CUSTOM_CLASS0_EP9_THREAD_STACK_SIZE 512 - -// Endpoint 9 Thread Priority -#define USBD_CUSTOM_CLASS0_EP9_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 10 Thread Stack Size <64-65536> -// This setting is used if Endpoint 10 is enabled. -#define USBD_CUSTOM_CLASS0_EP10_THREAD_STACK_SIZE 512 - -// Endpoint 10 Thread Priority -#define USBD_CUSTOM_CLASS0_EP10_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 11 Thread Stack Size <64-65536> -// This setting is used if Endpoint 11 is enabled. -#define USBD_CUSTOM_CLASS0_EP11_THREAD_STACK_SIZE 512 - -// Endpoint 11 Thread Priority -#define USBD_CUSTOM_CLASS0_EP11_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 12 Thread Stack Size <64-65536> -// This setting is used if Endpoint 12 is enabled. -#define USBD_CUSTOM_CLASS0_EP12_THREAD_STACK_SIZE 512 - -// Endpoint 12 Thread Priority -#define USBD_CUSTOM_CLASS0_EP12_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 13 Thread Stack Size <64-65536> -// This setting is used if Endpoint 13 is enabled. -#define USBD_CUSTOM_CLASS0_EP13_THREAD_STACK_SIZE 512 - -// Endpoint 13 Thread Priority -#define USBD_CUSTOM_CLASS0_EP13_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 14 Thread Stack Size <64-65536> -// This setting is used if Endpoint 14 is enabled. -#define USBD_CUSTOM_CLASS0_EP14_THREAD_STACK_SIZE 512 - -// Endpoint 14 Thread Priority -#define USBD_CUSTOM_CLASS0_EP14_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 15 Thread Stack Size <64-65536> -// This setting is used if Endpoint 15 is enabled. -#define USBD_CUSTOM_CLASS0_EP15_THREAD_STACK_SIZE 512 - -// Endpoint 15 Thread Priority -#define USBD_CUSTOM_CLASS0_EP15_THREAD_PRIORITY osPriorityAboveNormal - -// -// diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/USBD_User_CDC_ACM_UART_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/USBD_User_CDC_ACM_UART_0.c deleted file mode 100644 index 7f12203..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/USBD_User_CDC_ACM_UART_0.c +++ /dev/null @@ -1,381 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device:CDC - * Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_User_CDC_ACM_UART_0.c - * Purpose: USB Device Communication Device Class (CDC) - * Abstract Control Model (ACM) USB <-> UART Bridge User module - * Rev.: V1.0.8 - *----------------------------------------------------------------------------*/ -/** - * \addtogroup usbd_cdcFunctions - * - * USBD_User_CDC_ACM_UART_0.c implements the application specific - * functionality of the CDC ACM class and is used to demonstrate a USB <-> UART - * bridge. All data received on USB is transmitted on UART and all data - * received on UART is transmitted on USB. - * - * Details of operation: - * UART -> USB: - * Initial reception on UART is started after the USB Host sets line coding - * with SetLineCoding command. Having received a full UART buffer, any - * new reception is restarted on the same buffer. Any data received on - * the UART is sent over USB using the CDC0_ACM_UART_to_USB_Thread thread. - * USB -> UART: - * While the UART transmit is not busy, data transmission on the UART is - * started in the USBD_CDC0_ACM_DataReceived callback as soon as data is - * received on the USB. Further data received on USB is transmitted on - * UART in the UART callback routine until there is no more data available. - * In this case, the next UART transmit is restarted from the - * USBD_CDC0_ACM_DataReceived callback as soon as new data is received - * on the USB. - * - * The following constants in this module affect the module functionality: - * - * - UART_PORT: specifies UART Port - * default value: 0 (=UART0) - * - UART_BUFFER_SIZE: specifies UART data Buffer Size - * default value: 512 - * - * Notes: - * If the USB is slower than the UART, data can get lost. This may happen - * when USB is pausing during data reception because of the USB Host being - * too loaded with other tasks and not polling the Bulk IN Endpoint often - * enough (up to 2 seconds of gap in polling Bulk IN Endpoint may occur). - * This problem can be solved by using a large enough UART buffer to - * compensate up to a few seconds of received UART data or by using UART - * flow control. - * If the device that receives the UART data (usually a PC) is too loaded - * with other tasks it can also loose UART data. This problem can only be - * solved by using UART flow control. - * - * This file has to be adapted in case of UART flow control usage. - */ - - -//! [code_USBD_User_CDC_ACM] -#include -#include - -#include "rl_usb.h" - -#include "Driver_USART.h" - -#include "DAP_config.h" -#include "DAP.h" - -// UART Configuration ---------------------------------------------------------- - -#define UART_BUFFER_SIZE (512) // UART Buffer Size - -//------------------------------------------------------------------------------ - -#define _UART_Driver_(n) Driver_USART##n -#define UART_Driver_(n) _UART_Driver_(n) -extern ARM_DRIVER_USART UART_Driver_(DAP_UART_DRIVER); -#define ptrUART (&UART_Driver_(DAP_UART_DRIVER)) - -// Local Variables -static uint8_t uart_rx_buf[UART_BUFFER_SIZE]; -static uint8_t uart_tx_buf[UART_BUFFER_SIZE]; - -static volatile int32_t uart_rx_cnt = 0; -static volatile int32_t usb_tx_cnt = 0; - -static void *cdc_acm_bridge_tid = 0U; -static CDC_LINE_CODING cdc_acm_line_coding = { 0U, 0U, 0U, 0U }; - -static uint8_t cdc_acm_active = 1U; -static osMutexId_t cdc_acm_mutex_id = NULL; - -// Acquire mutex -__STATIC_INLINE void CDC_ACM_Lock (void) { - if (cdc_acm_mutex_id == NULL) { - cdc_acm_mutex_id = osMutexNew(NULL); - } - osMutexAcquire(cdc_acm_mutex_id, osWaitForever); -} - -// Release mutex -__STATIC_INLINE void CDC_ACM_Unlock (void) { - osMutexRelease(cdc_acm_mutex_id); -} - -// Change communication settings. -// \param[in] line_coding pointer to CDC_LINE_CODING structure. -// \return true set line coding request processed. -// \return false set line coding request not supported or not processed. -static bool CDC_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) { - uint32_t data_bits = 0U, parity = 0U, stop_bits = 0U; - int32_t status; - - (void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U); - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); - (void)ptrUART->Control (ARM_USART_CONTROL_TX, 0U); - (void)ptrUART->Control (ARM_USART_CONTROL_RX, 0U); - - switch (line_coding->bCharFormat) { - case 0: // 1 Stop bit - stop_bits = ARM_USART_STOP_BITS_1; - break; - case 1: // 1.5 Stop bits - stop_bits = ARM_USART_STOP_BITS_1_5; - break; - case 2: // 2 Stop bits - stop_bits = ARM_USART_STOP_BITS_2; - break; - default: - return false; - } - - switch (line_coding->bParityType) { - case 0: // None - parity = ARM_USART_PARITY_NONE; - break; - case 1: // Odd - parity = ARM_USART_PARITY_ODD; - break; - case 2: // Even - parity = ARM_USART_PARITY_EVEN; - break; - default: - return false; - } - - switch (line_coding->bDataBits) { - case 5: - data_bits = ARM_USART_DATA_BITS_5; - break; - case 6: - data_bits = ARM_USART_DATA_BITS_6; - break; - case 7: - data_bits = ARM_USART_DATA_BITS_7; - break; - case 8: - data_bits = ARM_USART_DATA_BITS_8; - break; - default: - return false; - } - - status = ptrUART->Control(ARM_USART_MODE_ASYNCHRONOUS | - data_bits | - parity | - stop_bits , - line_coding->dwDTERate ); - - if (status != ARM_DRIVER_OK) { - return false; - } - - // Store requested settings to local variable - memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding)); - - uart_rx_cnt = 0; - usb_tx_cnt = 0; - - (void)ptrUART->Control (ARM_USART_CONTROL_TX, 1U); - (void)ptrUART->Control (ARM_USART_CONTROL_RX, 1U); - - (void)ptrUART->Receive (uart_rx_buf, UART_BUFFER_SIZE); - - return true; -} - -// Activate or Deactivate USBD COM PORT -// \param[in] cmd 0=deactivate, 1=activate -// \return 0=Ok, 0xFF=Error -uint8_t USB_COM_PORT_Activate (uint32_t cmd) { - switch (cmd) { - case 0U: - cdc_acm_active = 0U; - USBD_CDC0_ACM_Uninitialize(); - break; - case 1U: - USBD_CDC0_ACM_Initialize(); - CDC_ACM_Lock(); - CDC_ACM_SetLineCoding(&cdc_acm_line_coding); - cdc_acm_active = 1U; - CDC_ACM_Unlock(); - break; - } - - return 0U; -} - -// Called when UART has transmitted or received requested number of bytes. -// \param[in] event UART event -// - ARM_USART_EVENT_SEND_COMPLETE: all requested data was sent -// - ARM_USART_EVENT_RECEIVE_COMPLETE: all requested data was received -static void UART_Callback (uint32_t event) { - int32_t cnt; - - if (cdc_acm_active == 0U) { - return; - } - - if (event & ARM_USART_EVENT_SEND_COMPLETE) { - // USB -> UART - cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE); - if (cnt > 0) { - (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt)); - } - } - - if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { - // UART data received, restart new reception - uart_rx_cnt += UART_BUFFER_SIZE; - (void)ptrUART->Receive(uart_rx_buf, UART_BUFFER_SIZE); - } -} - -// Thread: Sends data received on UART to USB -// \param[in] arg not used. -__NO_RETURN static void CDC0_ACM_UART_to_USB_Thread (void *arg) { - int32_t cnt, cnt_to_wrap; - - (void)(arg); - - for (;;) { - // UART - > USB - if (ptrUART->GetStatus().rx_busy != 0U) { - cnt = uart_rx_cnt; - cnt += (int32_t)ptrUART->GetRxCount(); - cnt -= usb_tx_cnt; - if (cnt >= (UART_BUFFER_SIZE - 32)) { - // Dump old data in UART receive buffer if USB is not consuming fast enough - cnt = (UART_BUFFER_SIZE - 32); - usb_tx_cnt = uart_rx_cnt - (UART_BUFFER_SIZE - 32); - } - if (cnt > 0) { - cnt_to_wrap = (int32_t)(UART_BUFFER_SIZE - ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))); - if (cnt > cnt_to_wrap) { - cnt = cnt_to_wrap; - } - cnt = USBD_CDC_ACM_WriteData(0U, (uart_rx_buf + ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))), cnt); - if (cnt > 0) { - usb_tx_cnt += cnt; - } - } - } - (void)osDelay(10U); - } -} - -static osRtxThread_t cdc0_acm_uart_to_usb_thread_cb_mem __SECTION(.bss.os.thread.cb); -static uint64_t cdc0_acm_uart_to_usb_thread_stack_mem[512U / 8U] __SECTION(.bss.os.thread.cdc.stack); -static const osThreadAttr_t cdc0_acm_uart_to_usb_thread_attr = { - "CDC0_ACM_UART_to_USB_Thread", - 0U, - &cdc0_acm_uart_to_usb_thread_cb_mem, - sizeof(osRtxThread_t), - &cdc0_acm_uart_to_usb_thread_stack_mem[0], - sizeof(cdc0_acm_uart_to_usb_thread_stack_mem), - osPriorityNormal, - 0U, - 0U -}; - - -// CDC ACM Callbacks ----------------------------------------------------------- - -// Called when new data was received from the USB Host. -// \param[in] len number of bytes available to read. -void USBD_CDC0_ACM_DataReceived (uint32_t len) { - int32_t cnt; - - (void)(len); - - if (cdc_acm_active == 0U) { - return; - } - - if (ptrUART->GetStatus().tx_busy == 0U) { - // Start USB -> UART - cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE); - if (cnt > 0) { - (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt)); - } - } -} - -// Called during USBD_Initialize to initialize the USB CDC class instance (ACM). -void USBD_CDC0_ACM_Initialize (void) { - (void)ptrUART->Initialize (UART_Callback); - (void)ptrUART->PowerControl (ARM_POWER_FULL); - - cdc_acm_bridge_tid = osThreadNew (CDC0_ACM_UART_to_USB_Thread, NULL, &cdc0_acm_uart_to_usb_thread_attr); -} - - -// Called during USBD_Uninitialize to de-initialize the USB CDC class instance (ACM). -void USBD_CDC0_ACM_Uninitialize (void) { - if (osThreadTerminate (cdc_acm_bridge_tid) == osOK) { - cdc_acm_bridge_tid = NULL; - } - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); - (void)ptrUART->PowerControl (ARM_POWER_OFF); - (void)ptrUART->Uninitialize (); -} - - -// Called upon USB Bus Reset Event. -void USBD_CDC0_ACM_Reset (void) { - if (cdc_acm_active == 0U ) { - return; - } - (void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U); - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); -} - - -// Called upon USB Host request to change communication settings. -// \param[in] line_coding pointer to CDC_LINE_CODING structure. -// \return true set line coding request processed. -// \return false set line coding request not supported or not processed. -bool USBD_CDC0_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) { - bool ret = false; - - CDC_ACM_Lock(); - if (cdc_acm_active == 0U) { - // Store requested settings to local variable - memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding)); - ret = true; - } else { - ret = CDC_ACM_SetLineCoding(line_coding); - } - CDC_ACM_Unlock(); - - return ret; -} - - -// Called upon USB Host request to retrieve communication settings. -// \param[out] line_coding pointer to CDC_LINE_CODING structure. -// \return true get line coding request processed. -// \return false get line coding request not supported or not processed. -bool USBD_CDC0_ACM_GetLineCoding (CDC_LINE_CODING *line_coding) { - - // Load settings from ones stored on USBD_CDC0_ACM_SetLineCoding callback - *line_coding = cdc_acm_line_coding; - - return true; -} - - -// Called upon USB Host request to set control line states. -// \param [in] state control line settings bitmap. -// - bit 0: DTR state -// - bit 1: RTS state -// \return true set control line state request processed. -// \return false set control line state request not supported or not processed. -bool USBD_CDC0_ACM_SetControlLineState (uint16_t state) { - // Add code for set control line state - - (void)(state); - - return true; -} - -//! [code_USBD_User_CDC_ACM] diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/USBD_User_CustomClass_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/USBD_User_CustomClass_0.c deleted file mode 100644 index 186c7b9..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/USBD_User_CustomClass_0.c +++ /dev/null @@ -1,358 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2016 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_User_CustomClass_0.c - * Purpose: USB Device Custom Class User module - * Rev.: V6.7.3 - *----------------------------------------------------------------------------*/ -/* - * USBD_User_CustomClass_0.c is a code template for the Custom Class 0 - * class request handling. It allows user to handle all Custom Class class - * requests. - * - * Uncomment "Example code" lines to see example that receives data on - * Endpoint 1 OUT and echoes it back on Endpoint 1 IN. - * To try the example you also have to enable Bulk Endpoint 1 IN/OUT in Custom - * Class configuration in USBD_Config_CustomClass_0.h file. - */ - -/** - * \addtogroup usbd_custom_classFunctions - * - */ - - -//! [code_USBD_User_CustomClass] - -#include -#include -#include -#include "cmsis_os2.h" -#define osObjectsExternal -#include "osObjects.h" -#include "rl_usb.h" -#include "Driver_USBD.h" -#include "DAP_config.h" -#include "DAP.h" - -static volatile uint16_t USB_RequestIndexI; // Request Index In -static volatile uint16_t USB_RequestIndexO; // Request Index Out -static volatile uint16_t USB_RequestCountI; // Request Count In -static volatile uint16_t USB_RequestCountO; // Request Count Out -static volatile uint8_t USB_RequestIdle; // Request Idle Flag - -static volatile uint16_t USB_ResponseIndexI; // Response Index In -static volatile uint16_t USB_ResponseIndexO; // Response Index Out -static volatile uint16_t USB_ResponseCountI; // Response Count In -static volatile uint16_t USB_ResponseCountO; // Response Count Out -static volatile uint8_t USB_ResponseIdle; // Response Idle Flag - -static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Request Buffer -static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Response Buffer -static uint16_t USB_RespSize[DAP_PACKET_COUNT]; // Response Size - -// \brief Callback function called during USBD_Initialize to initialize the USB Custom class instance -void USBD_CustomClass0_Initialize (void) { - // Handle Custom Class Initialization - - // Initialize variables - USB_RequestIndexI = 0U; - USB_RequestIndexO = 0U; - USB_RequestCountI = 0U; - USB_RequestCountO = 0U; - USB_RequestIdle = 1U; - USB_ResponseIndexI = 0U; - USB_ResponseIndexO = 0U; - USB_ResponseCountI = 0U; - USB_ResponseCountO = 0U; - USB_ResponseIdle = 1U; -} - -// \brief Callback function called during USBD_Uninitialize to de-initialize the USB Custom class instance -void USBD_CustomClass0_Uninitialize (void) { - // Handle Custom Class De-initialization -} - -// \brief Callback function called upon USB Bus Reset signaling -void USBD_CustomClass0_Reset (void) { - // Handle USB Bus Reset Event -} - -// \brief Callback function called when Endpoint Start was requested (by activating interface or configuration) -// \param[in] ep_addr endpoint address. -void USBD_CustomClass0_EndpointStart (uint8_t ep_addr) { - // Start communication on Endpoint - if (ep_addr == USB_ENDPOINT_OUT(1U)) { - USB_RequestIdle = 0U; - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[0], DAP_PACKET_SIZE); - } -} - -// \brief Callback function called when Endpoint Stop was requested (by de-activating interface or activating configuration 0) -// \param[in] ep_addr endpoint address. -void USBD_CustomClass0_EndpointStop (uint8_t ep_addr) { - // Handle Endpoint communication stopped - (void)ep_addr; -} - -// \brief Callback function called when Custom Class 0 received SETUP PACKET on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] setup_packet pointer to received setup packet. -// \param[out] buf pointer to data buffer used for data stage requested by setup packet. -// \param[out] len pointer to number of data bytes in data stage requested by setup packet. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet if no data stage) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -usbdRequestStatus USBD_CustomClass0_Endpoint0_SetupPacketReceived (const USB_SETUP_PACKET *setup_packet, uint8_t **buf, uint32_t *len) { - (void)setup_packet; - (void)buf; - (void)len; - - switch (setup_packet->bmRequestType.Recipient) { - case USB_REQUEST_TO_DEVICE: - break; - case USB_REQUEST_TO_INTERFACE: - break; - case USB_REQUEST_TO_ENDPOINT: - break; - default: - break; - } - - return usbdRequestNotProcessed; -} - -// \brief Callback function called when SETUP PACKET was processed by USB library -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback nor by Custom Class callback) -// \param[in] setup_packet pointer to processed setup packet. -void USBD_CustomClass0_Endpoint0_SetupPacketProcessed (const USB_SETUP_PACKET *setup_packet) { - (void)setup_packet; - - switch (setup_packet->bmRequestType.Recipient) { - case USB_REQUEST_TO_DEVICE: - break; - case USB_REQUEST_TO_INTERFACE: - break; - case USB_REQUEST_TO_ENDPOINT: - break; - default: - break; - } -} - -// \brief Callback function called when Custom Class 0 received OUT DATA on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] len number of received data bytes. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -// \return usbdRequestNAK: request was processed but the device is busy (return NAK) -usbdRequestStatus USBD_CustomClass0_Endpoint0_OutDataReceived (uint32_t len) { - (void)len; - return usbdRequestNotProcessed; -} - -// \brief Callback function called when Custom Class 0 sent IN DATA on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] len number of sent data bytes. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (return ACK) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -// \return usbdRequestNAK: request was processed but the device is busy (return NAK) -usbdRequestStatus USBD_CustomClass0_Endpoint0_InDataSent (uint32_t len) { - (void)len; - return usbdRequestNotProcessed; -} - -// \brief Callback function called when DATA was sent or received on Endpoint n -// \param[in] event event on Endpoint: -// - ARM_USBD_EVENT_OUT = data OUT received -// - ARM_USBD_EVENT_IN = data IN sent -void USBD_CustomClass0_Endpoint1_Event (uint32_t event) { - // Handle Endpoint 1 events - uint32_t n; - - if (event & ARM_USBD_EVENT_OUT) { - n = USBD_EndpointReadGetResult(0U, USB_ENDPOINT_OUT(1U)); - if (n != 0U) { - if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) { - DAP_TransferAbort = 1U; - } else { - USB_RequestIndexI++; - if (USB_RequestIndexI == DAP_PACKET_COUNT) { - USB_RequestIndexI = 0U; - } - USB_RequestCountI++; - osThreadFlagsSet(DAP_ThreadId, 0x01); - } - } - // Start reception of next request packet - if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); - } else { - USB_RequestIdle = 1U; - } - } - if (event & ARM_USBD_EVENT_IN) { - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]); - USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - } else { - USB_ResponseIdle = 1U; - } - } -} -void USBD_CustomClass0_Endpoint2_Event (uint32_t event) { - // Handle Endpoint 2 events - if (event & ARM_USBD_EVENT_IN) { - SWO_TransferComplete(); - } -} -void USBD_CustomClass0_Endpoint3_Event (uint32_t event) { - // Handle Endpoint 3 events - (void)event; -} -void USBD_CustomClass0_Endpoint4_Event (uint32_t event) { - // Handle Endpoint 4 events - (void)event; -} -void USBD_CustomClass0_Endpoint5_Event (uint32_t event) { - // Handle Endpoint 5 events - (void)event; -} -void USBD_CustomClass0_Endpoint6_Event (uint32_t event) { - // Handle Endpoint 6 events - (void)event; -} -void USBD_CustomClass0_Endpoint7_Event (uint32_t event) { - // Handle Endpoint 7 events - (void)event; -} -void USBD_CustomClass0_Endpoint8_Event (uint32_t event) { - // Handle Endpoint 8 events - (void)event; -} -void USBD_CustomClass0_Endpoint9_Event (uint32_t event) { - // Handle Endpoint 9 events - (void)event; -} -void USBD_CustomClass0_Endpoint10_Event (uint32_t event) { - // Handle Endpoint 10 events - (void)event; -} -void USBD_CustomClass0_Endpoint11_Event (uint32_t event) { - // Handle Endpoint 11 events - (void)event; -} -void USBD_CustomClass0_Endpoint12_Event (uint32_t event) { - // Handle Endpoint 12 events - (void)event; -} -void USBD_CustomClass0_Endpoint13_Event (uint32_t event) { - // Handle Endpoint 13 events - (void)event; -} -void USBD_CustomClass0_Endpoint14_Event (uint32_t event) { - // Handle Endpoint 14 events - (void)event; -} -void USBD_CustomClass0_Endpoint15_Event (uint32_t event) { - // Handle Endpoint 15 events - (void)event; -} - -// DAP Thread. -__NO_RETURN void DAP_Thread (void *argument) { - uint32_t flags; - uint32_t n; - (void) argument; - - for (;;) { - osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - - // Process pending requests - while (USB_RequestCountI != USB_RequestCountO) { - - // Handle Queue Commands - n = USB_RequestIndexO; - while (USB_Request[n][0] == ID_DAP_QueueCommands) { - USB_Request[n][0] = ID_DAP_ExecuteCommands; - n++; - if (n == DAP_PACKET_COUNT) { - n = 0U; - } - if (n == USB_RequestIndexI) { - flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - if (flags & 0x80U) { - break; - } - } - } - - // Execute DAP Command (process request and prepare response) - USB_RespSize[USB_ResponseIndexI] = - (uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]); - - // Update Request Index and Count - USB_RequestIndexO++; - if (USB_RequestIndexO == DAP_PACKET_COUNT) { - USB_RequestIndexO = 0U; - } - USB_RequestCountO++; - - if (USB_RequestIdle) { - if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { - USB_RequestIdle = 0U; - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); - } - } - - // Update Response Index and Count - USB_ResponseIndexI++; - if (USB_ResponseIndexI == DAP_PACKET_COUNT) { - USB_ResponseIndexI = 0U; - } - USB_ResponseCountI++; - - if (USB_ResponseIdle) { - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - n = USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - USB_ResponseIdle = 0U; - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[n], USB_RespSize[n]); - } - } - } - } -} - -// SWO Data Queue Transfer -// buf: pointer to buffer with data -// num: number of bytes to transfer -void SWO_QueueTransfer (uint8_t *buf, uint32_t num) { - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(2U), buf, num); -} - -// SWO Data Abort Transfer -void SWO_AbortTransfer (void) { - USBD_EndpointAbort(0U, USB_ENDPOINT_IN(2U)); -} - -//! [code_USBD_User_CustomClass] diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/main.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/main.c deleted file mode 100644 index ea90b4a..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/main.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2013-2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 21. May 2021 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Examples LPC-Link2 - * Title: main.c CMSIS-DAP Main module for LPC-Link2 - * - *---------------------------------------------------------------------------*/ - -#include "cmsis_os2.h" -#include "osObjects.h" -#include "rl_usb.h" -#include "DAP_config.h" -#include "DAP.h" - -// Application Main program -__NO_RETURN void app_main (void *argument) { - (void)argument; - - DAP_Setup(); // DAP Setup - - USBD_Initialize(0U); // USB Device Initialization -#ifdef LPC_LINK2_ONBOARD - char *ser_num; - ser_num = GetSerialNum(); - if (ser_num != NULL) { - USBD_SetSerialNumber(0U, ser_num); // Update Serial Number - } -#endif - USBD_Connect(0U); // USB Device Connect - - while (!USBD_Configured(0U)); // Wait for USB Device to configure - - LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED - LED_RUNNING_OUT(1U); // Turn on Target Running LED - Delayms(500U); // Wait for 500ms - LED_RUNNING_OUT(0U); // Turn off Target Running LED - LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED - - // Create DAP Thread - DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr); - - // Create SWO Thread - SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr); - - osDelay(osWaitForever); - for (;;) {} -} - -int main (void) { - - SystemCoreClockUpdate(); - osKernelInitialize(); // Initialize CMSIS-RTOS - osThreadNew(app_main, NULL, NULL); // Create application main thread - if (osKernelGetState() == osKernelReady) { - osKernelStart(); // Start thread execution - } - - for (;;) {} -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/osObjects.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/osObjects.h deleted file mode 100644 index 6619bb9..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/osObjects.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 11. June 2021 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Examples LPC-Link2 - * Title: osObjects.h CMSIS-DAP RTOS2 Objects for LPC-Link2 - * - *---------------------------------------------------------------------------*/ - -#ifndef __osObjects_h__ -#define __osObjects_h__ - -#include "cmsis_os2.h" - -#ifdef osObjectsExternal -extern osThreadId_t DAP_ThreadId; -extern osThreadId_t SWO_ThreadId; -#else -static const osThreadAttr_t DAP_ThreadAttr = { - .priority = osPriorityNormal -}; -static const osThreadAttr_t SWO_ThreadAttr = { - .priority = osPriorityAboveNormal -}; -extern osThreadId_t DAP_ThreadId; - osThreadId_t DAP_ThreadId; -extern osThreadId_t SWO_ThreadId; - osThreadId_t SWO_ThreadId; -#endif - -extern void DAP_Thread (void *argument); -extern void SWO_Thread (void *argument); - -extern void app_main (void *argument); - -#endif /* __osObjects_h__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.c deleted file mode 100644 index cc76f74..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 27. May 2021 - * $Revision: V1.0.0 - * - * Project: CMSIS-DAP Examples LPC-Link2 - * Title: ser_num.c CMSIS-DAP Serial Number module for LPC-Link2 - * - *---------------------------------------------------------------------------*/ - -#include -#include -#include - -#include "ser_num.h" - -// Serial Number -#define SER_NUM_PREFIX "00A1" -static char SerialNum[32]; - -#define IAP_LOCATION *(volatile unsigned int *)(0x10400100) -#define IAP_READ_DEVICE_SERIAL_NUMBER 58U -typedef void (*IAP)(unsigned int [],unsigned int[]); - -/** - \brief Calculate 32-bit CRC (polynom: 0x04C11DB7, init value: 0xFFFFFFFF) - \param[in] data pointer to data - \param[in] len data length (in bytes) - \return CRC32 value -*/ -static uint32_t crc32 (const uint8_t *data, uint32_t len) { - uint32_t crc32; - uint32_t n; - - crc32 = 0xFFFFFFFFU; - while (len != 0U) { - crc32 ^= ((uint32_t)*data++) << 24U; - for (n = 8U; n; n--) { - if (crc32 & 0x80000000U) { - crc32 <<= 1U; - crc32 ^= 0x04C11DB7U; - } else { - crc32 <<= 1U; - } - } - len--; - } - return (crc32); -} - -/** - \brief Get serial number string. First characters are fixed. Last eight - characters are Unique (calculated from devices's unique ID) - \return Serial number string or NULL (callculation of unique ID failed) -*/ -char *GetSerialNum (void) { - uint32_t command_param[5]; - uint32_t status_result[5]; - uint32_t uid; - char *str; - IAP iap_entry; - - memset(command_param, 0, sizeof(command_param)); - memset(status_result, 0, sizeof(status_result)); - iap_entry = (IAP)IAP_LOCATION; - command_param[0] = IAP_READ_DEVICE_SERIAL_NUMBER; - iap_entry(command_param, status_result); - str = NULL; - if (status_result[0] == 0U) { - uid = crc32 ((uint8_t *)&status_result[1], 16U); - snprintf(SerialNum, sizeof(SerialNum), "%s%08X", SER_NUM_PREFIX, uid); - str = SerialNum; - } - - return (str); -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.h deleted file mode 100644 index 6370739..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 27. May 2021 - * $Revision: V1.0.0 - * - * Project: CMSIS-DAP Examples LPC-Link2 - * Title: ser_num.h CMSIS-DAP Serial Number module for LPC-Link2 - * - *---------------------------------------------------------------------------*/ - -#ifndef __SER_NUM_H__ -#define __SER_NUM_H__ - -char *GetSerialNum (void); - -#endif /* __SER_NUM_H__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/target.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/target.c deleted file mode 100644 index 5a82aea..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/target.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 16. June 2021 - * $Revision: V1.0.0 - * - * Project: CMSIS-DAP Examples LPC-Link2 - * Title: target.c CMSIS-DAP Target Device/Board information (patchable) - * - *---------------------------------------------------------------------------*/ - -#include "DAP_config.h" - -#if TARGET_FIXED != 0 -const char TargetDeviceVendor [64] = TARGET_DEVICE_VENDOR; -const char TargetDeviceName [64] = TARGET_DEVICE_NAME; -const char TargetBoardVendor [64] = TARGET_BOARD_VENDOR; -const char TargetBoardName [64] = TARGET_BOARD_NAME; -#endif diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvguix b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvguix deleted file mode 100644 index ee3e6e5..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvguix +++ /dev/null @@ -1,3619 +0,0 @@ - - - - -6.1 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
- - - - MCU-LINK - 0x4 - ARM-ADS - 6160000::V6.16::ARMCLANG - 1 - - - LPC55S69JBD64:cm33_core0 - NXP - NXP.LPC55S69_DFP.13.1.0 - https://mcuxpresso.nxp.com/cmsis_pack/repo/ - IRAM(0x20000000,0x040000) IRAM2(0x20040000,0x4000) IROM(0x00000000,0x098000) XRAM(0x04000000,0x8000) XRAM2(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE - - - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM)) - 0 - $$Device:LPC55S69JBD64$fsl_device_registers.h - - - - - - - - - - $$Device:LPC55S69JBD64$LPC55S69_cm33_core0.xml - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - CMSIS_DAP - 1 - 0 - 1 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - - - - SARMV8M.DLL - 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- - - - - - - RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash.scf - - - - - - - - RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash_ns.scf - - - - - - - - RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash_s.scf - - - - - - - - RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_ram.scf - - - - - - - - RTE\Device\LPC55S69JBD64_cm33_core0\RTE_Device.h - - - - - - - - RTE\Device\LPC55S69JBD64_cm33_core0\startup_LPC55S69_cm33_core0.S - - - - - - - - RTE\USB\USBD_Config_0.c - - - - - - - - RTE\USB\USBD_Config_CDC_0.h - - - - - - - - RTE\USB\USBD_Config_CustomClass_0.h - - - - - - - - - - - - - CMSIS_DAP - 1 - - - - - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DAP_config.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DAP_config.h deleted file mode 100644 index 573d725..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DAP_config.h +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Copyright (c) 2013-2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 15. September 2021 - * $Revision: V2.1.0 - * - * Project: CMSIS-DAP Examples MCU-LINK - * Title: DAP_config.h CMSIS-DAP Configuration File for MCU-LINK - * - *---------------------------------------------------------------------------*/ - -#ifndef __DAP_CONFIG_H__ -#define __DAP_CONFIG_H__ - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information -\ingroup DAP_ConfigIO_gr -@{ -Provides definitions about the hardware and configuration of the Debug Unit. - -This information includes: - - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. - - Debug Unit Identification strings (Vendor, Product, Serial Number). - - Debug Unit communication packet size. - - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - - Optional information about a connected Target Device (for Evaluation Boards). -*/ - -#ifdef _RTE_ -#include "RTE_Components.h" -#include CMSIS_device_header -#else -#include "device.h" // Debug Unit Cortex-M Processor Header File -#endif - -#include "pin_mux.h" -#include "fsl_gpio.h" - -#include "ser_num.h" - -/// Processor Clock of the Cortex-M MCU used in the Debug Unit. -/// This value is used to calculate the SWD/JTAG clock speed. -#define CPU_CLOCK 150000000U ///< Specifies the CPU Clock in Hz. - -/// Number of processor cycles for I/O Port write operations. -/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O -/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses -/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// required. -#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. - -/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. - -/// Indicate that JTAG communication mode is available at the Debug Port. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. - -/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. -/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. -#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. - -/// Default communication mode on the Debug Access Port. -/// Used for the command \ref DAP_Connect when Port Default mode is selected. -#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. - -/// Default communication speed on the Debug Access Port for SWD and JTAG mode. -/// Used to initialize the default SWD/JTAG clock frequency. -/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. -#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. - -/// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimize the communication performance with the -/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, -/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. -#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes. - -/// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimize the communication performance with the -/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the -/// setting can be reduced (valid range is 1 .. 255). -#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered. - -/// Indicate that UART Serial Wire Output (SWO) trace is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available. - -/// USART Driver instance number for the UART SWO. -#define SWO_UART_DRIVER 3 ///< USART Driver instance number (Driver_USART#). - -/// Maximum SWO UART Baudrate. -#define SWO_UART_MAX_BAUDRATE 9000000U ///< SWO UART Maximum Baudrate in Hz. - -/// Indicate that Manchester Serial Wire Output (SWO) trace is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. - -/// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n). - -/// SWO Streaming Trace. -#define SWO_STREAM 1 ///< SWO Streaming Trace: 1 = available, 0 = not available. - -/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. -#define TIMESTAMP_CLOCK 150000000U ///< Timestamp clock in Hz (0 = timestamps not supported). - -/// Indicate that UART Communication Port is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available. - -/// USART Driver instance number for the UART Communication Port. -#define DAP_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). - -/// UART Receive Buffer Size. -#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). - -/// UART Transmit Buffer Size. -#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). - -/// Indicate that UART Communication via USB COM Port is available. -/// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. - -/// Debug Unit is connected to fixed Target Device. -/// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings -/// are stored and may be used by the debugger or IDE to configure device parameters. -#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; - -#define TARGET_DEVICE_VENDOR "NXP" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device -#define TARGET_BOARD_VENDOR "NXP" ///< String indicating the Board Vendor -#define TARGET_BOARD_NAME "NXP board" ///< String indicating the Board Name - -#if TARGET_FIXED != 0 -#include -static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR; -static const char TargetDeviceName [] = TARGET_DEVICE_NAME; -static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR; -static const char TargetBoardName [] = TARGET_BOARD_NAME; -#endif - -/** Get Vendor Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { - (void)str; - return (0U); -} - -/** Get Product Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { - (void)str; - return (0U); -} - -/** Get Serial Number string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { - uint8_t len = 0U; - char *ser_num; - - ser_num = GetSerialNum(); - if (ser_num != NULL) { - strcpy(str, ser_num); - len = (uint8_t)(strlen(ser_num) + 1U); - } - - return (len); -} - -/** Get Target Device Vendor string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceVendor); - len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Device Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceName); - len = (uint8_t)(strlen(TargetDeviceName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Board Vendor string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardVendor); - len = (uint8_t)(strlen(TargetBoardVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Target Board Name string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardName); - len = (uint8_t)(strlen(TargetBoardName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif -} - -/** Get Product Firmware Version string. -\param str Pointer to buffer to store the string (max 60 characters). -\return String length (including terminating NULL character) or 0 (no string). -*/ -__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { - (void)str; - return (0U); -} - -///@} - -// Debug Port I/O Pins -//SWO/TDO -#define PIN_SWO_TDO_PORT (0U) -#define PIN_SWO_TDO_PIN (3U) - -//************************************************************************************************** -/** -\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access -\ingroup DAP_ConfigIO_gr -@{ - -Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode -and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug -interface of a device. The following I/O Pins are provided: - -JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode ----------------------------- | -------------------- | --------------------------------------------- -TCK: Test Clock | SWCLK: Clock | Output Push/Pull -TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) -TDI: Test Data Input | | Output Push/Pull -TDO: Test Data Output | | Input -nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor -nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor - - -DAP Hardware I/O Pin Access Functions -------------------------------------- -The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to -these I/O Pins. - -For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. -This functions are provided to achieve faster I/O that is possible with some advanced GPIO -peripherals that can independently write/read a single I/O pin without affecting any other pins -of the same I/O port. The following SWDIO I/O Pin functions are provided: - - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. - - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. - - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. - - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. -*/ - - -// Configure DAP I/O pins ------------------------------ - -/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. -Configures the DAP Hardware I/O pins for JTAG mode: - - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. - - TDO to input mode. -*/ -__STATIC_INLINE void PORT_JTAG_SETUP (void) { - - // TCK - DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN); - DBGIF_TCK_SWCLK_GPIO->DIRSET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN); - - // TDI - DBGIF_TDI_GPIO->SET[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN); - DBGIF_TDI_GPIO->DIRSET[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN); - - // TMS - DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); - DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); - DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN); - - // nRESET - DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN); - - // TDO - GPIO->DIRCLR[PIN_SWO_TDO_PORT] = (1U << PIN_SWO_TDO_PIN); -} - -/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. -Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - - SWCLK, SWDIO, nRESET to output mode and set to default high level. - - TDI, nTRST to HighZ mode (pins are unused in SWD mode). -*/ -__STATIC_INLINE void PORT_SWD_SETUP (void) { - - // SWCLK - DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN); - DBGIF_TCK_SWCLK_GPIO->DIRSET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN); - - // SWDIO - DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); - DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); - DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN); - - // nRESET - DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN); - - // TDI - DBGIF_TDI_GPIO->DIRCLR[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN); -} - -/** Disable JTAG/SWD I/O Pins. -Disables the DAP Hardware I/O pins which configures: - - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. -*/ -__STATIC_INLINE void PORT_OFF (void) { - - // TCK/SWCLK - DBGIF_TCK_SWCLK_GPIO->DIRCLR[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN); - - // TMS/SWDIO - DBGIF_TMS_SWDIO_TXEN_GPIO->CLR[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN); - DBGIF_TMS_SWDIO_GPIO->DIRCLR[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); - - // nRESET - DBGIF_RESET_TXEN_GPIO->CLR[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN); - DBGIF_RESET_GPIO->DIRCLR[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - - // TDI - DBGIF_TDI_GPIO->DIRCLR[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN); - - // TDO - GPIO->DIRCLR[PIN_SWO_TDO_PORT] = (1U << PIN_SWO_TDO_PIN); -} - - -// SWCLK/TCK I/O pin ------------------------------------- - -/** SWCLK/TCK I/O pin: Get Input. -\return Current status of the SWCLK/TCK DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { - return ((DBGIF_TCK_SWCLK_GPIO->PIN[DBGIF_TCK_SWCLK_PORT] >> DBGIF_TCK_SWCLK_PIN) & 1U); -} - -/** SWCLK/TCK I/O pin: Set Output to High. -Set the SWCLK/TCK DAP hardware I/O pin to high level. -*/ -__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { - DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN); -} - -/** SWCLK/TCK I/O pin: Set Output to Low. -Set the SWCLK/TCK DAP hardware I/O pin to low level. -*/ -__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { - DBGIF_TCK_SWCLK_GPIO->CLR[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN); -} - - -// SWDIO/TMS Pin I/O -------------------------------------- - -/** SWDIO/TMS I/O pin: Get Input. -\return Current status of the SWDIO/TMS DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { - return ((DBGIF_TMS_SWDIO_GPIO->PIN[DBGIF_TMS_SWDIO_PORT] >> DBGIF_TMS_SWDIO_PIN) & 1U); -} - -/** SWDIO/TMS I/O pin: Set Output to High. -Set the SWDIO/TMS DAP hardware I/O pin to high level. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { - DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); -} - -/** SWDIO/TMS I/O pin: Set Output to Low. -Set the SWDIO/TMS DAP hardware I/O pin to low level. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { - DBGIF_TMS_SWDIO_GPIO->CLR[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); -} - -/** SWDIO I/O pin: Get Input (used in SWD mode only). -\return Current status of the SWDIO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { - return (DBGIF_TMS_SWDIO_GPIO->B[DBGIF_TMS_SWDIO_PORT][DBGIF_TMS_SWDIO_PIN]); -} - -/** SWDIO I/O pin: Set Output (used in SWD mode only). -\param bit Output value for the SWDIO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { - DBGIF_TMS_SWDIO_GPIO->B[DBGIF_TMS_SWDIO_PORT][DBGIF_TMS_SWDIO_PIN] = bit; -} - -/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). -Configure the SWDIO DAP hardware I/O pin to output mode. This function is -called prior \ref PIN_SWDIO_OUT function calls. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { - DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); - DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN); -} - -/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). -Configure the SWDIO DAP hardware I/O pin to input mode. This function is -called prior \ref PIN_SWDIO_IN function calls. -*/ -__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { - DBGIF_TMS_SWDIO_TXEN_GPIO->CLR[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN); - DBGIF_TMS_SWDIO_GPIO->DIRCLR[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN); -} - - -// TDI Pin I/O --------------------------------------------- - -/** TDI I/O pin: Get Input. -\return Current status of the TDI DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { - return (DBGIF_TDI_GPIO->B[DBGIF_TDI_PORT][DBGIF_TDI_PIN]); -} - -/** TDI I/O pin: Set Output. -\param bit Output value for the TDI DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { - DBGIF_TDI_GPIO->B[DBGIF_TDI_PORT][DBGIF_TDI_PIN] = bit; -} - - -// TDO Pin I/O --------------------------------------------- - -/** TDO I/O pin: Get Input. -\return Current status of the TDO DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { - return (GPIO->B[PIN_SWO_TDO_PORT][PIN_SWO_TDO_PIN]); - -} - - -// nTRST Pin I/O ------------------------------------------- - -/** nTRST I/O pin: Get Input. -\return Current status of the nTRST DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { - return (0U); // Not available -} - -/** nTRST I/O pin: Set Output. -\param bit JTAG TRST Test Reset pin status: - - 0: issue a JTAG TRST Test Reset. - - 1: release JTAG TRST Test Reset. -*/ -__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { - (void) bit; - // Not available -} - -// nRESET Pin I/O------------------------------------------ - -/** nRESET I/O pin: Get Input. -\return Current status of the nRESET DAP hardware I/O pin. -*/ -__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { - return ((DBGIF_RESET_GPIO->PIN[DBGIF_RESET_PORT] >> DBGIF_RESET_PIN) & 1U); -} - -/** nRESET I/O pin: Set Output. -\param bit target device hardware reset pin status: - - 0: issue a device hardware reset. - - 1: release device hardware reset. -*/ -__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { - if (bit) { - DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - DBGIF_RESET_TXEN_GPIO->CLR[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN); - DBGIF_RESET_GPIO->DIRCLR[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - } else { - DBGIF_RESET_GPIO->CLR[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT] = (1U << DBGIF_RESET_PIN); - DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN); - } -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs -\ingroup DAP_ConfigIO_gr -@{ - -CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. - -It is recommended to provide the following LEDs for status indication: - - Connect LED: is active when the DAP hardware is connected to a debugger. - - Running LED: is active when the debugger has put the target device into running state. -*/ - -/** Debug Unit: Set status of Connected LED. -\param bit status of the Connect LED. - - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. - - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. -*/ -__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { - if (bit) { - LED1_GPIO->CLR[LED1_PORT] = (1U << LED1_PIN); - } else { - LED1_GPIO->SET[LED1_PORT] = (1U << LED1_PIN); - } -} - -/** Debug Unit: Set status Target Running LED. -\param bit status of the Target Running LED. - - 1: Target Running LED ON: program execution in target started. - - 0: Target Running LED OFF: program execution in target stopped. -*/ -__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) { - (void) bit; - // Not available -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp -\ingroup DAP_ConfigIO_gr -@{ -Access function for Test Domain Timer. - -The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By -default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. - -*/ - -/** Get timestamp of Test Domain Timer. -\return Current timestamp value. -*/ -__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { - return (DWT->CYCCNT); -} - -///@} - - -//************************************************************************************************** -/** -\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization -\ingroup DAP_ConfigIO_gr -@{ - -CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. -*/ - -/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). -This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the -Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: - - I/O clock system enabled. - - all I/O pins: input buffer enabled, output pins are set to HighZ mode. - - for nTRST, nRESET a weak pull-up (if available) is enabled. - - LED output pins are enabled and LEDs are turned off. -*/ -__STATIC_INLINE void DAP_SETUP (void) { - BOARD_InitBootPins(); -} - -/** Reset Target Device with custom specific I/O pin or command sequence. -This function allows the optional implementation of a device specific reset sequence. -It is called when the command \ref DAP_ResetTarget and is for example required -when a device needs a time-critical unlock sequence that enables the debug port. -\return 0 = no device specific reset sequence is implemented.\n - 1 = a device specific reset sequence is implemented. -*/ -__STATIC_INLINE uint8_t RESET_TARGET (void) { - return (0U); // change to '1' when a device reset sequence is implemented -} - -///@} - - -#endif /* __DAP_CONFIG_H__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DebugConfig/MCU-Link_LPC55S69JBD64_cm33_core0.dbgconf b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DebugConfig/MCU-Link_LPC55S69JBD64_cm33_core0.dbgconf deleted file mode 100644 index 1cc3a2a..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/DebugConfig/MCU-Link_LPC55S69JBD64_cm33_core0.dbgconf +++ /dev/null @@ -1,18 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO pin -// The SWO (Serial Wire Output) pin optionally provides data from the ITM -// for an external debug tool to evaluate. -// <0=> PIO0_10 -// <1=> PIO0_8 -SWO_Pin = 0; -// - -// Debug Configuration -// StopAfterBootloader Stop after Bootloader -// -Dbg_CR = 0x00000001; -// - - -// <<< end of configuration section >>> \ No newline at end of file diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/MCU-Link.mex b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/MCU-Link.mex deleted file mode 100644 index 1788595..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/MCU-Link.mex +++ /dev/null @@ -1,743 +0,0 @@ - - - - LPC55S69 - LPC55S69JBD64 - ksdk2_0 - - - - - - - - true - false - false - - - - - - - - - 9.0.3 - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - - cm33_core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9.0.3 - - - - - - - - - true - - - - - INPUT - - - - - true - - - - - OUTPUT - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - true - - - - - - - 0.0.0 - - - - - - - - - - 9.0.3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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-:0400000500000201F4 -:00000001FF diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/README.md b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/README.md deleted file mode 100644 index f8d4dbf..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/README.md +++ /dev/null @@ -1,13 +0,0 @@ -CMSIS-DAP v2 firmware for NXP MCU-LINK debug probe. - -CMSIS-DAP v2 uses USB bulk endpoints for the communication with the host PC and is therefore faster. -Optionally, support for streaming SWO trace is provided via an additional USB endpoint. - -Instructions for programing CMSIS_DAP firmware on MCU-LINK: -- download and install MCU-LINK_installer from https://www.nxp.com/design/microcontrollers-developer-resources/mcu-link-debug-probe:MCU-LINK -- disconnect MCU-LINK from USB (J1), set "firmware update" jumper (J3), connect MCU-LINK to USB (J1) -- open a Command Window -- navigate to the MCU-LINK_installer installation (default C:\nxp\MCU-LINK_installer\) and go to the scripts sub-directory -- copy pre-built firmware hex file ..\CMSIS\DAP\Firmware\Examples\MCU-LINK\Objects\CMSIS_DAP.hex to scripts directory -- run the command: programm_CMSIS.cmd CMSIS_DAP.hex -- follow the instructions in command window diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.c deleted file mode 100644 index 737078a..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2013-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.1.1 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration - * - * ----------------------------------------------------------------------------- - */ - -#include "cmsis_compiler.h" -#include "rtx_os.h" - -// OS Idle Thread -__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { - (void)argument; - - for (;;) {} -} - -// OS Error Callback function -__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { - (void)object_id; - - switch (code) { - case osRtxErrorStackOverflow: - // Stack overflow detected for thread (thread_id=object_id) - break; - case osRtxErrorISRQueueOverflow: - // ISR Queue overflow detected when inserting object (object_id) - break; - case osRtxErrorTimerQueueOverflow: - // User Timer Callback Queue overflow detected for timer (timer_id=object_id) - break; - case osRtxErrorClibSpace: - // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM - break; - case osRtxErrorClibMutex: - // Standard C/C++ library mutex initialization failed - break; - default: - // Reserved - break; - } - for (;;) {} -//return 0U; -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.h deleted file mode 100644 index 3c70db6..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.h +++ /dev/null @@ -1,580 +0,0 @@ -/* - * Copyright (c) 2013-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.5.2 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration definitions - * - * ----------------------------------------------------------------------------- - */ - -#ifndef RTX_CONFIG_H_ -#define RTX_CONFIG_H_ - -#ifdef _RTE_ -#include "RTE_Components.h" -#ifdef RTE_RTX_CONFIG_H -#include RTE_RTX_CONFIG_H -#endif -#endif - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Configuration -// ======================= - -// Global Dynamic Memory size [bytes] <0-1073741824:8> -// Defines the combined global dynamic memory size. -// Default: 32768 -#ifndef OS_DYNAMIC_MEM_SIZE -#define OS_DYNAMIC_MEM_SIZE 4096 -#endif - -// Kernel Tick Frequency [Hz] <1-1000000> -// Defines base time unit for delays and timeouts. -// Default: 1000 (1ms tick) -#ifndef OS_TICK_FREQ -#define OS_TICK_FREQ 1000 -#endif - -// Round-Robin Thread switching -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN_ENABLE -#define OS_ROBIN_ENABLE 1 -#endif - -// Round-Robin Timeout <1-1000> -// Defines how many ticks a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBIN_TIMEOUT -#define OS_ROBIN_TIMEOUT 5 -#endif - -// - -// ISR FIFO Queue -// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries -// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries -// RTOS Functions called from ISR store requests to this buffer. -// Default: 16 entries -#ifndef OS_ISR_FIFO_QUEUE -#define OS_ISR_FIFO_QUEUE 32 -#endif - -// Object Memory usage counters -// Enables object memory usage counters (requires RTX source variant). -#ifndef OS_OBJ_MEM_USAGE -#define OS_OBJ_MEM_USAGE 0 -#endif - -// - -// Thread Configuration -// ======================= - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_THREAD_OBJ_MEM -#define OS_THREAD_OBJ_MEM 0 -#endif - -// Number of user Threads <1-1000> -// Defines maximum number of user threads that can be active at the same time. -// Applies to user threads with system provided memory for control blocks. -#ifndef OS_THREAD_NUM -#define OS_THREAD_NUM 1 -#endif - -// Number of user Threads with default Stack size <0-1000> -// Defines maximum number of user threads with default stack size. -// Applies to user threads with zero stack size specified. -#ifndef OS_THREAD_DEF_STACK_NUM -#define OS_THREAD_DEF_STACK_NUM 0 -#endif - -// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> -// Defines the combined stack size for user threads with user-provided stack size. -// Applies to user threads with user-provided stack size and system provided memory for stack. -// Default: 0 -#ifndef OS_THREAD_USER_STACK_SIZE -#define OS_THREAD_USER_STACK_SIZE 0 -#endif - -// - -// Default Thread Stack size [bytes] <96-1073741824:8> -// Defines stack size for threads with zero stack size specified. -// Default: 3072 -#ifndef OS_STACK_SIZE -#define OS_STACK_SIZE 1024 -#endif - -// Idle Thread Stack size [bytes] <72-1073741824:8> -// Defines stack size for Idle thread. -// Default: 512 -#ifndef OS_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE 512 -#endif - -// Idle Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_IDLE_THREAD_TZ_MOD_ID -#define OS_IDLE_THREAD_TZ_MOD_ID 0 -#endif - -// Stack overrun checking -// Enables stack overrun check at thread switch (requires RTX source variant). -// Enabling this option increases slightly the execution time of a thread switch. -#ifndef OS_STACK_CHECK -#define OS_STACK_CHECK 0 -#endif - -// Stack usage watermark -// Initializes thread stack with watermark pattern for analyzing stack usage. -// Enabling this option increases significantly the execution time of thread creation. -#ifndef OS_STACK_WATERMARK -#define OS_STACK_WATERMARK 0 -#endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_PRIVILEGE_MODE -#define OS_PRIVILEGE_MODE 1 -#endif - -// - -// Timer Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_TIMER_OBJ_MEM -#define OS_TIMER_OBJ_MEM 0 -#endif - -// Number of Timer objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_TIMER_NUM -#define OS_TIMER_NUM 1 -#endif - -// - -// Timer Thread Priority -// <8=> Low -// <16=> Below Normal <24=> Normal <32=> Above Normal -// <40=> High -// <48=> Realtime -// Defines priority for timer thread -// Default: High -#ifndef OS_TIMER_THREAD_PRIO -#define OS_TIMER_THREAD_PRIO 40 -#endif - -// Timer Thread Stack size [bytes] <0-1073741824:8> -// Defines stack size for Timer thread. -// May be set to 0 when timers are not used. -// Default: 512 -#ifndef OS_TIMER_THREAD_STACK_SIZE -#define OS_TIMER_THREAD_STACK_SIZE 512 -#endif - -// Timer Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_TIMER_THREAD_TZ_MOD_ID -#define OS_TIMER_THREAD_TZ_MOD_ID 0 -#endif - -// Timer Callback Queue entries <0-256> -// Number of concurrent active timer callback functions. -// May be set to 0 when timers are not used. -// Default: 4 -#ifndef OS_TIMER_CB_QUEUE -#define OS_TIMER_CB_QUEUE 4 -#endif - -// - -// Event Flags Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_EVFLAGS_OBJ_MEM -#define OS_EVFLAGS_OBJ_MEM 0 -#endif - -// Number of Event Flags objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_EVFLAGS_NUM -#define OS_EVFLAGS_NUM 1 -#endif - -// - -// - -// Mutex Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MUTEX_OBJ_MEM -#define OS_MUTEX_OBJ_MEM 0 -#endif - -// Number of Mutex objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MUTEX_NUM -#define OS_MUTEX_NUM 1 -#endif - -// - -// - -// Semaphore Configuration -// ========================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_SEMAPHORE_OBJ_MEM -#define OS_SEMAPHORE_OBJ_MEM 0 -#endif - -// Number of Semaphore objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_SEMAPHORE_NUM -#define OS_SEMAPHORE_NUM 1 -#endif - -// - -// - -// Memory Pool Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MEMPOOL_OBJ_MEM -#define OS_MEMPOOL_OBJ_MEM 0 -#endif - -// Number of Memory Pool objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MEMPOOL_NUM -#define OS_MEMPOOL_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MEMPOOL_DATA_SIZE -#define OS_MEMPOOL_DATA_SIZE 0 -#endif - -// - -// - -// Message Queue Configuration -// ============================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MSGQUEUE_OBJ_MEM -#define OS_MSGQUEUE_OBJ_MEM 0 -#endif - -// Number of Message Queue objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MSGQUEUE_NUM -#define OS_MSGQUEUE_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MSGQUEUE_DATA_SIZE -#define OS_MSGQUEUE_DATA_SIZE 0 -#endif - -// - -// - -// Event Recorder Configuration -// =============================== - -// Global Initialization -// Initialize Event Recorder during 'osKernelInitialize'. -#ifndef OS_EVR_INIT -#define OS_EVR_INIT 0 -#endif - -// Start recording -// Start event recording after initialization. -#ifndef OS_EVR_START -#define OS_EVR_START 1 -#endif - -// Global Event Filter Setup -// Initial recording level applied to all components. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_LEVEL -#define OS_EVR_LEVEL 0x00U -#endif - -// RTOS Event Filter Setup -// Recording levels for RTX components. -// Only applicable if events for the respective component are generated. - -// Memory Management -// Recording level for Memory Management events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMORY_LEVEL -#define OS_EVR_MEMORY_LEVEL 0x81U -#endif - -// Kernel -// Recording level for Kernel events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_KERNEL_LEVEL -#define OS_EVR_KERNEL_LEVEL 0x81U -#endif - -// Thread -// Recording level for Thread events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THREAD_LEVEL -#define OS_EVR_THREAD_LEVEL 0x85U -#endif - -// Generic Wait -// Recording level for Generic Wait events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_WAIT_LEVEL -#define OS_EVR_WAIT_LEVEL 0x81U -#endif - -// Thread Flags -// Recording level for Thread Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THFLAGS_LEVEL -#define OS_EVR_THFLAGS_LEVEL 0x81U -#endif - -// Event Flags -// Recording level for Event Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_EVFLAGS_LEVEL -#define OS_EVR_EVFLAGS_LEVEL 0x81U -#endif - -// Timer -// Recording level for Timer events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_TIMER_LEVEL -#define OS_EVR_TIMER_LEVEL 0x81U -#endif - -// Mutex -// Recording level for Mutex events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MUTEX_LEVEL -#define OS_EVR_MUTEX_LEVEL 0x81U -#endif - -// Semaphore -// Recording level for Semaphore events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_SEMAPHORE_LEVEL -#define OS_EVR_SEMAPHORE_LEVEL 0x81U -#endif - -// Memory Pool -// Recording level for Memory Pool events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMPOOL_LEVEL -#define OS_EVR_MEMPOOL_LEVEL 0x81U -#endif - -// Message Queue -// Recording level for Message Queue events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MSGQUEUE_LEVEL -#define OS_EVR_MSGQUEUE_LEVEL 0x81U -#endif - -// - -// - -// RTOS Event Generation -// Enables event generation for RTX components (requires RTX source variant). - -// Memory Management -// Enables Memory Management event generation. -#ifndef OS_EVR_MEMORY -#define OS_EVR_MEMORY 1 -#endif - -// Kernel -// Enables Kernel event generation. -#ifndef OS_EVR_KERNEL -#define OS_EVR_KERNEL 1 -#endif - -// Thread -// Enables Thread event generation. -#ifndef OS_EVR_THREAD -#define OS_EVR_THREAD 1 -#endif - -// Generic Wait -// Enables Generic Wait event generation. -#ifndef OS_EVR_WAIT -#define OS_EVR_WAIT 1 -#endif - -// Thread Flags -// Enables Thread Flags event generation. -#ifndef OS_EVR_THFLAGS -#define OS_EVR_THFLAGS 1 -#endif - -// Event Flags -// Enables Event Flags event generation. -#ifndef OS_EVR_EVFLAGS -#define OS_EVR_EVFLAGS 1 -#endif - -// Timer -// Enables Timer event generation. -#ifndef OS_EVR_TIMER -#define OS_EVR_TIMER 1 -#endif - -// Mutex -// Enables Mutex event generation. -#ifndef OS_EVR_MUTEX -#define OS_EVR_MUTEX 1 -#endif - -// Semaphore -// Enables Semaphore event generation. -#ifndef OS_EVR_SEMAPHORE -#define OS_EVR_SEMAPHORE 1 -#endif - -// Memory Pool -// Enables Memory Pool event generation. -#ifndef OS_EVR_MEMPOOL -#define OS_EVR_MEMPOOL 1 -#endif - -// Message Queue -// Enables Message Queue event generation. -#ifndef OS_EVR_MSGQUEUE -#define OS_EVR_MSGQUEUE 1 -#endif - -// - -// - -// Number of Threads which use standard C/C++ library libspace -// (when thread specific memory allocation is not used). -#if (OS_THREAD_OBJ_MEM == 0) -#ifndef OS_THREAD_LIBSPACE_NUM -#define OS_THREAD_LIBSPACE_NUM 4 -#endif -#else -#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM -#endif - -//------------- <<< end of configuration section >>> --------------------------- - -#endif // RTX_CONFIG_H_ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash.scf b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash.scf deleted file mode 100644 index 1af7a54..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash.scf +++ /dev/null @@ -1,105 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00000200 -#define m_text_size 0x00071E00 - -#define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x00026000 - -#if (defined(__use_shmem__)) - #define m_data_start 0x20000000 - #define m_data_size 0x00031800 - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x20000000 - #define m_data_size 0x00033000 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_ns.scf b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_ns.scf deleted file mode 100644 index 56067ac..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_ns.scf +++ /dev/null @@ -1,107 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190923 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -/* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */ -#define m_interrupts_start 0x00010000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00010200 -#define m_text_size 0x00061E00 - -#define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x00026000 - -/* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */ -#if (defined(__use_shmem__)) - #define m_data_start 0x20008000 - #define m_data_size 0x00029000 - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x20008000 - #define m_data_size 0x0002B000 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_s.scf b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_s.scf deleted file mode 100644 index f4ea3e7..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_s.scf +++ /dev/null @@ -1,116 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190923 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -/* Only the first 64kB of flash is used as secure memory. */ -#define m_interrupts_start 0x10000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x10000200 -#define m_text_size 0x0000FC00 - -#define m_core1_image_start 0x10072000 -#define m_core1_image_size 0x00026000 - -/* Only first 32kB of data RAM is used as secure memory. */ -#if (defined(__use_shmem__)) - #define m_data_start 0x30000000 - #define m_data_size 0x00008000 - #define m_rpmsg_sh_mem_start 0x30031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x30000000 - #define m_data_size 0x00008000 -#endif - -/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ -#define m_veneer_table_start 0x1000FE00 -#define m_veneer_table_size 0x200 - - -#define m_usb_sram_start 0x50100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table - *(Veneer$$CMSE) - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_ram.scf b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_ram.scf deleted file mode 100644 index 7974430..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_ram.scf +++ /dev/null @@ -1,105 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x04000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x04000200 -#define m_text_size 0x00007E00 - -#define m_core1_image_start 0x20033000 -#define m_core1_image_size 0x0000C800 - -#if (defined(__use_shmem__)) - #define m_data_start 0x20000000 - #define m_data_size 0x00031800 - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x20000000 - #define m_data_size 0x00033000 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/RTE_Device.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/RTE_Device.h deleted file mode 100644 index 7e71d12..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/RTE_Device.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _RTE_DEVICE_H -#define _RTE_DEVICE_H - -#include "pin_mux.h" - -/* UART Select, UART0-UART7. */ -/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART - * instance. */ -#define RTE_USART0 1 -#define RTE_USART0_DMA_EN 1 -#define RTE_USART1 0 -#define RTE_USART1_DMA_EN 0 -#define RTE_USART2 0 -#define RTE_USART2_DMA_EN 0 -#define RTE_USART3 1 -#define RTE_USART3_DMA_EN 1 -#define RTE_USART4 0 -#define RTE_USART4_DMA_EN 0 -#define RTE_USART5 0 -#define RTE_USART5_DMA_EN 0 -#define RTE_USART6 0 -#define RTE_USART6_DMA_EN 0 -#define RTE_USART7 0 -#define RTE_USART7_DMA_EN 0 - -/* USART configuration. */ -#define USART_RX_BUFFER_LEN 64 -#define USART0_RX_BUFFER_ENABLE 1 -#define USART1_RX_BUFFER_ENABLE 0 -#define USART2_RX_BUFFER_ENABLE 0 -#define USART3_RX_BUFFER_ENABLE 1 -#define USART4_RX_BUFFER_ENABLE 0 -#define USART5_RX_BUFFER_ENABLE 0 -#define USART6_RX_BUFFER_ENABLE 0 -#define USART7_RX_BUFFER_ENABLE 0 - -#define RTE_USART0_DMA_TX_CH 5 -#define RTE_USART0_DMA_TX_DMA_BASE DMA0 -#define RTE_USART0_DMA_RX_CH 4 -#define RTE_USART0_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART1_DMA_TX_CH 7 -#define RTE_USART1_DMA_TX_DMA_BASE DMA0 -#define RTE_USART1_DMA_RX_CH 6 -#define RTE_USART1_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART2_DMA_TX_CH 8 -#define RTE_USART2_DMA_TX_DMA_BASE DMA0 -#define RTE_USART2_DMA_RX_CH 9 -#define RTE_USART2_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART3_DMA_TX_CH 9 -#define RTE_USART3_DMA_TX_DMA_BASE DMA0 -#define RTE_USART3_DMA_RX_CH 8 -#define RTE_USART3_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART4_DMA_TX_CH 13 -#define RTE_USART4_DMA_TX_DMA_BASE DMA0 -#define RTE_USART4_DMA_RX_CH 12 -#define RTE_USART4_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART5_DMA_TX_CH 15 -#define RTE_USART5_DMA_TX_DMA_BASE DMA0 -#define RTE_USART5_DMA_RX_CH 14 -#define RTE_USART5_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART6_DMA_TX_CH 17 -#define RTE_USART6_DMA_TX_DMA_BASE DMA0 -#define RTE_USART6_DMA_RX_CH 16 -#define RTE_USART6_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART7_DMA_TX_CH 19 -#define RTE_USART7_DMA_TX_DMA_BASE DMA0 -#define RTE_USART7_DMA_RX_CH 18 -#define RTE_USART7_DMA_RX_DMA_BASE DMA0 - -/* I2C Select, I2C0 -I2C7*/ -/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. - */ -#define RTE_I2C0 0 -#define RTE_I2C0_DMA_EN 0 -#define RTE_I2C1 0 -#define RTE_I2C1_DMA_EN 0 -#define RTE_I2C2 0 -#define RTE_I2C2_DMA_EN 0 -#define RTE_I2C3 0 -#define RTE_I2C3_DMA_EN 0 -#define RTE_I2C4 0 -#define RTE_I2C4_DMA_EN 0 -#define RTE_I2C5 0 -#define RTE_I2C5_DMA_EN 0 -#define RTE_I2C6 0 -#define RTE_I2C6_DMA_EN 0 -#define RTE_I2C7 0 -#define RTE_I2C7_DMA_EN 0 - -/*I2C configuration*/ -#define RTE_I2C0_Master_DMA_BASE DMA0 -#define RTE_I2C0_Master_DMA_CH 1 - -#define RTE_I2C1_Master_DMA_BASE DMA0 -#define RTE_I2C1_Master_DMA_CH 3 - -#define RTE_I2C2_Master_DMA_BASE DMA0 -#define RTE_I2C2_Master_DMA_CH 5 - -#define RTE_I2C3_Master_DMA_BASE DMA0 -#define RTE_I2C3_Master_DMA_CH 7 - -#define RTE_I2C4_Master_DMA_BASE DMA0 -#define RTE_I2C4_Master_DMA_CH 9 - -#define RTE_I2C5_Master_DMA_BASE DMA0 -#define RTE_I2C5_Master_DMA_CH 11 - -#define RTE_I2C6_Master_DMA_BASE DMA0 -#define RTE_I2C6_Master_DMA_CH 13 - -#define RTE_I2C7_Master_DMA_BASE DMA0 -#define RTE_I2C7_Master_DMA_CH 15 - -/* SPI select, SPI0 - SPI7.*/ -/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. - */ -#define RTE_SPI0 0 -#define RTE_SPI0_DMA_EN 0 -#define RTE_SPI1 0 -#define RTE_SPI1_DMA_EN 0 -#define RTE_SPI2 0 -#define RTE_SPI2_DMA_EN 0 -#define RTE_SPI3 0 -#define RTE_SPI3_DMA_EN 0 -#define RTE_SPI4 0 -#define RTE_SPI4_DMA_EN 0 -#define RTE_SPI5 0 -#define RTE_SPI5_DMA_EN 0 -#define RTE_SPI6 0 -#define RTE_SPI6_DMA_EN 0 -#define RTE_SPI7 0 -#define RTE_SPI7_DMA_EN 0 - -/* SPI configuration. */ -#define RTE_SPI0_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI0_PIN_INIT SPI0_InitPins -#define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins -#define RTE_SPI0_DMA_TX_CH 1 -#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI0_DMA_RX_CH 0 -#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI1_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI1_PIN_INIT SPI1_InitPins -#define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins -#define RTE_SPI1_DMA_TX_CH 3 -#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI1_DMA_RX_CH 2 -#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI2_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI2_PIN_INIT SPI2_InitPins -#define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins -#define RTE_SPI2_DMA_TX_CH 5 -#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI2_DMA_RX_CH 4 -#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI3_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI3_PIN_INIT SPI3_InitPins -#define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins -#define RTE_SPI3_DMA_TX_CH 7 -#define RTE_SPI3_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI3_DMA_RX_CH 6 -#define RTE_SPI3_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI4_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI4_PIN_INIT SPI4_InitPins -#define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins -#define RTE_SPI4_DMA_TX_CH 9 -#define RTE_SPI4_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI4_DMA_RX_CH 8 -#define RTE_SPI4_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI5_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI5_PIN_INIT SPI5_InitPins -#define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins -#define RTE_SPI5_DMA_TX_CH 11 -#define RTE_SPI5_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI5_DMA_RX_CH 10 -#define RTE_SPI5_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI6_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI6_PIN_INIT SPI6_InitPins -#define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins -#define RTE_SPI6_DMA_TX_CH 13 -#define RTE_SPI6_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI6_DMA_RX_CH 12 -#define RTE_SPI6_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI7_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI7_PIN_INIT SPI7_InitPins -#define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins -#define RTE_SPI7_DMA_TX_CH 15 -#define RTE_SPI7_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI7_DMA_RX_CH 14 -#define RTE_SPI7_DMA_RX_DMA_BASE DMA0 - -#endif /* _RTE_DEVICE_H */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/startup_LPC55S69_cm33_core0.S b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/startup_LPC55S69_cm33_core0.S deleted file mode 100644 index 9a573e0..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/startup_LPC55S69_cm33_core0.S +++ /dev/null @@ -1,801 +0,0 @@ -/* --------------------------------------------------------------------------------------- - * @file: startup_LPC55S69_cm33_core0.s - * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0 - * @version: 1.1 - * @date: 2019-5-16 - * ---------------------------------------------------------------------------------------*/ -/* - * Copyright 1997-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - .syntax unified - .arch armv8-m.main - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors - -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base - msr msplim, R0 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ - def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ - def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ - def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ - def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ - def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ - def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ - def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */ - def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ - def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ - def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */ - def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .end diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c deleted file mode 100644 index 9c3cbd7..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c +++ /dev/null @@ -1,206 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_Config_0.c - * Purpose: USB Device Configuration - * Rev.: V5.2.0 - *------------------------------------------------------------------------------ - * Use the following configuration settings in the Device Class configuration - * files to assign a Device Class to this USB Device 0. - * - * Configuration Setting Value - * --------------------- ----- - * Assign Device Class to USB Device # = 0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// USB Device 0 -// Connect to hardware via Driver_USBD# <0-255> -// Select driver control block for hardware interface. -#define USBD0_PORT 1 - -// High-speed -// Enable High-speed functionality (if device supports it). -#define USBD0_HS 1 - -// Device Settings -// These settings are used to create the Device Descriptor -// Max Endpoint 0 Packet Size -// Maximum packet size for Endpoint 0 (bMaxPacketSize0). -// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes -#define USBD0_MAX_PACKET0 64 - -// Vendor ID <0x0000-0xFFFF> -// Vendor ID assigned by USB-IF (idVendor). -#define USBD0_DEV_DESC_IDVENDOR 0xC251 - -// Product ID <0x0000-0xFFFF> -// Product ID assigned by manufacturer (idProduct). -#define USBD0_DEV_DESC_IDPRODUCT 0xF00B - -// Device Release Number <0x0000-0xFFFF> -// Device Release Number in binary-coded decimal (bcdDevice) -#define USBD0_DEV_DESC_BCDDEVICE 0x0100 - -// - -// Configuration Settings -// These settings are used to create the Configuration Descriptor. -// Power -// Default Power Setting (D6: of bmAttributes). -// <0=>Bus-powered -// <1=>Self-powered -// Remote Wakeup -// Configuration support for Remote Wakeup (D5: of bmAttributes). -#define USBD0_CFG_DESC_BMATTRIBUTES 0x80 - -// Maximum Power Consumption (in mA) <0-510><#/2> -// Maximum Power Consumption of USB Device from bus in this -// specific configuration when device is fully operational (bMaxPower). -#define USBD0_CFG_DESC_BMAXPOWER 250 - -// - -// String Settings -// These settings are used to create the String Descriptor. -// Language ID <0x0000-0xFCFF> -// English (United States) = 0x0409. -#define USBD0_STR_DESC_LANGID 0x0409 - -// Manufacturer String -// String Descriptor describing Manufacturer. -#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM" - -// Product String -// String Descriptor describing Product. -#define USBD0_STR_DESC_PROD L"MCU-LINK" - -// Serial Number String -// Enable Serial Number String. -// If disabled Serial Number String will not be assigned to USB Device. -#define USBD0_STR_DESC_SER_EN 1 - -// Default value -// Default device's Serial Number String. -#define USBD0_STR_DESC_SER L"0001A0000000" - -// Maximum Length (in characters) <0-126> -// Specifies the maximum number of Serial Number String characters that can be set at run-time. -// Maximum value is 126. Use value 0 to disable RAM allocation for string. -#define USBD0_STR_DESC_SER_MAX_LEN 16 - -// -// - -// Microsoft OS Descriptors Settings -// These settings are used to create the Microsoft OS Descriptors. -// OS String -// Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors. -#define USBD0_OS_DESC_EN 1 - -// Vendor Code <0x01-0xFF> -// Specifies Vendor Code used to retrieve OS Feature Descriptors. -#define USBD0_OS_DESC_VENDOR_CODE 0x01 - -// -// - -// Control Transfer Buffer Size <64-65536:64> -// Specifies size of buffer used for Control Transfers. -// It should be at least as big as maximum packet size for Endpoint 0. -#define USBD0_EP0_BUF_SIZE 128 - -// OS Resources Settings -// These settings are used to optimize usage of OS resources. -// Core Thread Stack Size <64-65536> -#define USBD0_CORE_THREAD_STACK_SIZE 1024 - -// Core Thread Priority -#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal - -// -// - - -#include "RTE_Components.h" - -#ifdef RTE_USB_Device_CustomClass_0 -#include "USBD_Config_CustomClass_0.h" -#endif -#ifdef RTE_USB_Device_CustomClass_1 -#include "USBD_Config_CustomClass_1.h" -#endif -#ifdef RTE_USB_Device_CustomClass_2 -#include "USBD_Config_CustomClass_2.h" -#endif -#ifdef RTE_USB_Device_CustomClass_3 -#include "USBD_Config_CustomClass_3.h" -#endif - -#ifdef RTE_USB_Device_HID_0 -#include "USBD_Config_HID_0.h" -#endif -#ifdef RTE_USB_Device_HID_1 -#include "USBD_Config_HID_1.h" -#endif -#ifdef RTE_USB_Device_HID_2 -#include "USBD_Config_HID_2.h" -#endif -#ifdef RTE_USB_Device_HID_3 -#include "USBD_Config_HID_3.h" -#endif - -#ifdef RTE_USB_Device_MSC_0 -#include "USBD_Config_MSC_0.h" -#endif -#ifdef RTE_USB_Device_MSC_1 -#include "USBD_Config_MSC_1.h" -#endif -#ifdef RTE_USB_Device_MSC_2 -#include "USBD_Config_MSC_2.h" -#endif -#ifdef RTE_USB_Device_MSC_3 -#include "USBD_Config_MSC_3.h" -#endif - -#ifdef RTE_USB_Device_CDC_0 -#include "USBD_Config_CDC_0.h" -#endif -#ifdef RTE_USB_Device_CDC_1 -#include "USBD_Config_CDC_1.h" -#endif -#ifdef RTE_USB_Device_CDC_2 -#include "USBD_Config_CDC_2.h" -#endif -#ifdef RTE_USB_Device_CDC_3 -#include "USBD_Config_CDC_3.h" -#endif -#ifdef RTE_USB_Device_CDC_4 -#include "USBD_Config_CDC_4.h" -#endif -#ifdef RTE_USB_Device_CDC_5 -#include "USBD_Config_CDC_5.h" -#endif -#ifdef RTE_USB_Device_CDC_6 -#include "USBD_Config_CDC_6.h" -#endif -#ifdef RTE_USB_Device_CDC_7 -#include "USBD_Config_CDC_7.h" -#endif - -#ifdef RTE_USB_Device_ADC_0 -#include "USBD_Config_ADC_0.h" -#endif -#ifdef RTE_USB_Device_ADC_1 -#include "USBD_Config_ADC_1.h" -#endif -#ifdef RTE_USB_Device_ADC_2 -#include "USBD_Config_ADC_2.h" -#endif -#ifdef RTE_USB_Device_ADC_3 -#include "USBD_Config_ADC_3.h" -#endif - -#include "usbd_config.h" diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h deleted file mode 100644 index 7cf68d1..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h +++ /dev/null @@ -1,364 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_Config_CDC_0.h - * Purpose: USB Device Communication Device Class (CDC) Configuration - * Rev.: V5.2.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// USB Device: Communication Device Class (CDC) 0 -// Assign Device Class to USB Device # <0-3> -// Select USB Device that is used for this Device Class instance -#define USBD_CDC0_DEV 0 - -// Communication Class Subclass -// Specifies the model used by the CDC class. -// <2=>Abstract Control Model (ACM) -// <13=>Network Control Model (NCM) -#define USBD_CDC0_SUBCLASS 2 - -// Communication Class Protocol -// Specifies the protocol used by the CDC class. -// <0=>No protocol (Virtual COM) -// <255=>Vendor-specific (RNDIS) -#define USBD_CDC0_PROTOCOL 0 - -// Interrupt Endpoint Settings -// By default, the settings match the first USB Class instance in a USB Device. -// Endpoint conflicts are flagged by compile-time error messages. - -// Interrupt IN Endpoint Number -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -#define USBD_CDC0_EP_INT_IN 3 - - -// Endpoint Settings -// Parameters are used to create Endpoint Descriptors -// and for memory allocation in the USB component. - -// Full/Low-speed (High-speed disabled) -// Parameters apply when High-speed is disabled in USBD_Config_n.c -// Maximum Endpoint Packet Size (in bytes) <0-64> -// Specifies the physical packet size used for information exchange. -// Maximum value is 64. -#define USBD_CDC0_WMAXPACKETSIZE 16 - -// Endpoint polling Interval (in ms) <1-255> -// Specifies the frequency of requests initiated by USB Host for -// getting the notification. -#define USBD_CDC0_BINTERVAL 2 - -// - -// High-speed -// Parameters apply when High-speed is enabled in USBD_Config_n.c -// -// Maximum Endpoint Packet Size (in bytes) <0-1024> -// Specifies the physical packet size used for information exchange. -// Maximum value is 1024. -// Additional transactions per microframe -// Additional transactions improve communication performance. -// <0=>None <1=>1 additional <2=>2 additional -#define USBD_CDC0_HS_WMAXPACKETSIZE 16 - -// Endpoint polling Interval (in 125 us intervals) -// Specifies the frequency of requests initiated by USB Host for -// getting the notification. -// <1=> 1 <2=> 2 <3=> 4 <4=> 8 -// <5=> 16 <6=> 32 <7=> 64 <8=> 128 -// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 -// <13=>4096 <14=>8192 <15=>16384 <16=>32768 -#define USBD_CDC0_HS_BINTERVAL 2 - -// -// -// - - -// Bulk Endpoint Settings -// By default, the settings match the first USB Class instance in a USB Device. -// Endpoint conflicts are flagged by compile-time error messages. - -// Bulk IN Endpoint Number -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -#define USBD_CDC0_EP_BULK_IN 4 - -// Bulk OUT Endpoint Number -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -#define USBD_CDC0_EP_BULK_OUT 4 - - -// Endpoint Settings -// Parameters are used to create USB Descriptors and for memory -// allocation in the USB component. -// -// Full/Low-speed (High-speed disabled) -// Parameters apply when High-speed is disabled in USBD_Config_n.c -// Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64 -// Specifies the physical packet size used for information exchange. -// Maximum value is 64. -#define USBD_CDC0_WMAXPACKETSIZE1 64 - -// - -// High-speed -// Parameters apply when High-speed is enabled in USBD_Config_n.c -// -// Maximum Endpoint Packet Size (in bytes) <512=>512 -// Specifies the physical packet size used for information exchange. -// Only available value is 512. -#define USBD_CDC0_HS_WMAXPACKETSIZE1 512 - -// Maximum NAK Rate <0-255> -// Specifies the interval in which Bulk Endpoint can NAK. -// Value of 0 indicates that Bulk Endpoint never NAKs. -#define USBD_CDC0_HS_BINTERVAL1 0 - -// -// -// - -// Communication Device Class Settings -// Parameters are used to create USB Descriptors and for memory allocation -// in the USB component. -// -// Communication Class Interface String -#define USBD_CDC0_CIF_STR_DESC L"USB_CDC0_0" - -// Data Class Interface String -#define USBD_CDC0_DIF_STR_DESC L"USB_CDC0_1" - -// Abstract Control Model Settings - -// Call Management Capabilities -// Specifies which call management functionality is supported. -// Call Management channel -// <0=>Communication Class Interface only -// <1=>Communication and Data Class Interface -// Device Call Management handling -// <0=>None -// <1=>All -// -#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03 - -// Abstract Control Management Capabilities -// Specifies which abstract control management functionality is supported. -// D3 bit -// Enabled = Supports the notification Network_Connection -// D2 bit -// Enabled = Supports the request Send_Break -// D1 bit -// Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding, -// Set_Control_Line_State, and notification Serial_State -// D0 bit -// Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature -// -#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06 - -// Maximum Communication Device Send Buffer Size -// Specifies size of buffer used for sending of data to USB Host. -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes -// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes -#define USBD_CDC0_ACM_SEND_BUF_SIZE 1024 - -// Maximum Communication Device Receive Buffer Size -// Specifies size of buffer used for receiving of data from USB Host. -// Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint. -// Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint. -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes -// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes -#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE 2048 - -// - -// Network Control Model Settings - -// MAC Address String -// Specifies 48-bit Ethernet MAC address. -#define USBD_CDC0_NCM_MAC_ADDRESS L"1E306CA2455E" - -// Ethernet Statistics -// Specifies Ethernet statistic functions supported. -// XMIT_OK -// Frames transmitted without errors -// RVC_OK -// Frames received without errors -// XMIT_ERROR -// Frames not transmitted, or transmitted with errors -// RCV_ERROR -// Frames received with errors that are not delivered to the USB host. -// RCV_NO_BUFFER -// Frame missed, no buffers -// DIRECTED_BYTES_XMIT -// Directed bytes transmitted without errors -// DIRECTED_FRAMES_XMIT -// Directed frames transmitted without errors -// MULTICAST_BYTES_XMIT -// Multicast bytes transmitted without errors -// MULTICAST_FRAMES_XMIT -// Multicast frames transmitted without errors -// BROADCAST_BYTES_XMIT -// Broadcast bytes transmitted without errors -// BROADCAST_FRAMES_XMIT -// Broadcast frames transmitted without errors -// DIRECTED_BYTES_RCV -// Directed bytes received without errors -// DIRECTED_FRAMES_RCV -// Directed frames received without errors -// MULTICAST_BYTES_RCV -// Multicast bytes received without errors -// MULTICAST_FRAMES_RCV -// Multicast frames received without errors -// BROADCAST_BYTES_RCV -// Broadcast bytes received without errors -// BROADCAST_FRAMES_RCV -// Broadcast frames received without errors -// RCV_CRC_ERROR -// Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error -// TRANSMIT_QUEUE_LENGTH -// Length of transmit queue -// RCV_ERROR_ALIGNMENT -// Frames received with alignment error -// XMIT_ONE_COLLISION -// Frames transmitted with one collision -// XMIT_MORE_COLLISIONS -// Frames transmitted with more than one collision -// XMIT_DEFERRED -// Frames transmitted after deferral -// XMIT_MAX_COLLISIONS -// Frames not transmitted due to collisions -// RCV_OVERRUN -// Frames not received due to overrun -// XMIT_UNDERRUN -// Frames not transmitted due to underrun -// XMIT_HEARTBEAT_FAILURE -// Frames transmitted with heartbeat failure -// XMIT_TIMES_CRS_LOST -// Times carrier sense signal lost during transmission -// XMIT_LATE_COLLISIONS -// Late collisions detected -// -#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS 0x00000003 - -// Maximum Segment Size -// Specifies maximum segment size that Ethernet device is capable of supporting. -// Typically 1514 bytes. -#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE 1514 - -// Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing) -// Specifies multicast filtering type. -// Number of Multicast Filters -// Specifies number of multicast filters that can be configured by the USB Host. -#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS 1 - -// Number of Power Filters -// Specifies number of pattern filters that are available for causing wake-up of the USB Host. -#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS 0 - -// Network Capabilities -// Specifies which functions are supported. -// SetCrcMode/GetCrcMode -// SetMaxDatagramSize/GetMaxDatagramSize -// SetNetAddress/GetNetAddress -// SetEthernetPacketFilter -// -#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES 0x1B - -// NTB Parameters -// Specifies NTB parameters reported by GetNtbParameters function. - -// NTB Formats Supported (bmNtbFormatsSupported) -// Specifies NTB formats supported. -// 16-bit NTB (always supported) -// 32-bit NTB -// -#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED 0x0001 - -// IN Data Pipe -// -// Maximum NTB Size (dwNtbInMaxSize) -// Specifies maximum IN NTB size in bytes. -#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE 4096 - -// NTB Datagram Payload Alignment Divisor (wNdpInDivisor) -// Specifies divisor used for IN NTB Datagram payload alignment. -#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR 4 - -// NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder) -// Specifies remainder used to align input datagram payload within the NTB. -// (Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder -#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER 0 - -// NDP Alignment Modulus in NTB (wNdpInAlignment) -// Specifies NDP alignment modulus for NTBs on the IN pipe. -// Shall be power of 2, and shall be at least 4. -#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT 4 - -// - -// OUT Data Pipe -// -// Maximum NTB Size (dwNtbOutMaxSize) -// Specifies maximum OUT NTB size in bytes. -#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE 4096 - -// NTB Datagram Payload Alignment Divisor (wNdpOutDivisor) -// Specifies divisor used for OUT NTB Datagram payload alignment. -#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR 4 - -// NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder) -// Specifies remainder used to align output datagram payload within the NTB. -// (Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder -#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0 - -// NDP Alignment Modulus in NTB (wNdpOutAlignment) -// Specifies NDP alignment modulus for NTBs on the IN pipe. -// Shall be power of 2, and shall be at least 4. -#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT 4 - -// - -// - -// Raw Data Access API -// Enables or disables Raw Data Access API. -#define USBD_CDC0_NCM_RAW_ENABLE 0 - -// IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer -// Specifies buffering used for sending data to USB Host. -// Not used when RAW Data Access API is enabled. -#define USBD_CDC0_NCM_NTB_IN_BUF_CNT 1 - -// OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer -// Specifies buffering used for receiving data from USB Host. -// Not used when RAW Data Access API is enabled. -#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT 1 - -// - -// - -// OS Resources Settings -// These settings are used to optimize usage of OS resources. -// Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536> -#define USBD_CDC0_INT_THREAD_STACK_SIZE 512 - -// Communication Device Class Interrupt Endpoint Thread Priority -#define USBD_CDC0_INT_THREAD_PRIORITY osPriorityAboveNormal - -// Communication Device Class Bulk Endpoints Thread Stack Size <64-65536> -#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512 - -// Communication Device Class Bulk Endpoints Thread Priority -#define USBD_CDC0_BULK_THREAD_PRIORITY osPriorityAboveNormal - -// -// diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CustomClass_0.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CustomClass_0.h deleted file mode 100644 index 1c47124..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CustomClass_0.h +++ /dev/null @@ -1,3771 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_Config_CustomClass_0.h - * Purpose: USB Device Custom Class Configuration - * Rev.: V5.2.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// USB Device: Custom Class 0 -// Custom Class can be used to make support for Standard or Vendor-Specific Class -// Assign Device Class to USB Device # <0-3> -// Select USB Device that is used for this Device Class instance -#define USBD_CUSTOM_CLASS0_DEV 0 - -// Interface Association -// Used for grouping of multiple interfaces to a single class. -#define USBD_CUSTOM_CLASS0_IAD_EN 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IAD_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IAD_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IAD_PROTOCOL 0x00 - -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF0_EN 1 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF0_NUM 0 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF0_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF0_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF0_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF0_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP0_EN 1 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP1_EN 1 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP2_EN 1 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP2_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP2_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF0_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF0_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF0_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 0. -#define USBD_CUSTOM_CLASS0_IF0_STR_EN 1 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF0_STR L"MCU-LINK CMSIS-DAP" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID_EN 1 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_EN 1 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_STR L"{CDB3B5AD-293B-4663-AA36-1AAE46463776}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF1_EN 0 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF1_NUM 1 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF1_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF1_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF1_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF1_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP0_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP1_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP2_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP2_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP2_BENDPOINTADDRESS 0x02 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF1_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF1_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF1_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 1. -#define USBD_CUSTOM_CLASS0_IF1_STR_EN 0 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF1_STR L"USB_CUSTOM_CLASS0_IF1" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID_EN 0 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF2_EN 0 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF2_NUM 2 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF2_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF2_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF2_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF2_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP0_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP1_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP2_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP2_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP2_BENDPOINTADDRESS 0x02 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF2_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF2_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF2_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 2. -#define USBD_CUSTOM_CLASS0_IF2_STR_EN 0 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF2_STR L"USB_CUSTOM_CLASS0_IF2" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID_EN 0 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// Interface -#define USBD_CUSTOM_CLASS0_IF3_EN 0 - -// Interface Settings -// The Interface Settings are used to create the Interface Descriptor. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about the Interface Descriptor. - -// Interface Number <0-255> -// Defines the value for bInterfaceNumber -// Each USB Device Interface has a sequential Interface Number starting with 0. -// Several Interfaces may have the same Interface Number; in this case the value -// of Alternate Setting is used to differ between the Interfaces. For a -// composite device the Interface Numbers of the custom classes must be contiguous. -#define USBD_CUSTOM_CLASS0_IF3_NUM 3 - -// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 -// Defines the value for bAlternateSetting -// A sequential number starting with 0 to identify the Interface Descriptors -// that share the same value for Interface Number. -#define USBD_CUSTOM_CLASS0_IF3_ALT 0 - -// Class Code -// Class Codes are defined by USB-IF. For more information refer to -// http://www.usb.org/developers/defined_class. -// <0x00=>0x00: Indicate a Null Class Code triple -// <0x01=>0x01: Audio -// <0x02=>0x02: Communications and CDC Control -// <0x03=>0x03: HID (Human Interface Device) -// <0x05=>0x05: Physical -// <0x06=>0x06: Image -// <0x07=>0x07: Printer -// <0x08=>0x08: Mass Storage -// <0x0A=>0x0A: CDC-Data -// <0x0B=>0x0B: Smart Card -// <0x0D=>0x0D: Content Security -// <0x0E=>0x0E: Video -// <0x0F=>0x0F: Personal Healthcare -// <0x10=>0x10: Audio/Video Devices -// <0xDC=>0xDC: Diagnostic Device -// <0xE0=>0xE0: Wireless Controller -// <0xEF=>0xEF: Miscellaneous -// <0xFE=>0xFE: Application Specific -// <0xFF=>0xFF: Vendor Specific -#define USBD_CUSTOM_CLASS0_IF3_CLASS 0xFF - -// Subclass Code <0x00-0xFF> -// The possible values depend on the Class Code: -// Class Code 0x00: Subclass Code must be 0 -// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF -// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF -#define USBD_CUSTOM_CLASS0_IF3_SUBCLASS 0x00 - -// Protocol Code <0x00-0xFF> -// The Protocol Code value defines the protocol used on this interface: -// Protocol Code 0x00: class-specific protocol not used -// Protocol Code 0x01 .. 0xFE: class-specific protocol used -// Protocol Code 0xFF: vendor-specific protocol used -#define USBD_CUSTOM_CLASS0_IF3_PROTOCOL 0x00 - -// - -// Endpoint Settings -// Following settings are used to create the Endpoint Descriptors. -// Refer to USB - USB Concepts - USB Descriptor in the MDK Components -// User's Guide for more information about Endpoint Descriptors. - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP0_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP0_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP0_BENDPOINTADDRESS 0x01 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP1_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP1_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP1_BENDPOINTADDRESS 0x81 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP2_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP2_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP2_BENDPOINTADDRESS 0x02 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP3_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP3_BMATTRIBUTES 0x03 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP3_BENDPOINTADDRESS 0x82 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP4_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP4_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP4_BENDPOINTADDRESS 0x03 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP5_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP5_BMATTRIBUTES 0x01 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP5_BENDPOINTADDRESS 0x83 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_WMAXPACKETSIZE 1023 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_BINTERVAL 1 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_WMAXPACKETSIZE 1024 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_BINTERVAL 1 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP6_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP6_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP6_BENDPOINTADDRESS 0x04 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_BINTERVAL 0 - -// -// -// - -// Endpoint -// Enable Endpoint for this interface. -#define USBD_CUSTOM_CLASS0_IF3_EP7_EN 0 - -// Type -// Select Endpoint Type. -// Endpoint Descriptor: bmAttributes field bits 0 .. 1. -// If required, for Isochronous Endpoint, Synchronization and Usage Type -// can be set by manually editing define value of BMATTRIBUTES. -// <2=>Bulk -// <3=>Interrupt -// <1=>Isochronous -#define USBD_CUSTOM_CLASS0_IF3_EP7_BMATTRIBUTES 0x02 - -// Number -// Select Endpoint Number. -// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. -// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 -// Direction -// Select Endpoint Direction. -// Endpoint Descriptor: bEndpointAddress field bit 7. -// <0=>OUT -// <1=>IN -#define USBD_CUSTOM_CLASS0_IF3_EP7_BENDPOINTADDRESS 0x84 - -// Speed Settings -// Settings that are different depending on device operating speed. -// -// Full/Low-speed -// Parameters apply when device operates in Full/Low-speed. -// -// Maximum Packet Size <0-1023> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 8, 16, 32 or 64. -// For Interrupt Endpoint set value to 1 .. 64. -// For Isochronous Endpoint set value to 1 .. 1023. -#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_WMAXPACKETSIZE 64 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in ms). -// Endpoint Descriptor: bInterval field. -// Setting is not used for Bulk Endpoint (set value to 0). -// For Interrupt Endpoint set value to 1 .. 255 (polling interval). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_BINTERVAL 0 - -// - -// High-speed -// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c -// (n is the index of device on which this interface will be used) and when -// device operates in High-speed. -// -// Maximum Packet Size <0-1024> -// Specifies the physical packet size used for information exchange (in bytes). -// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. -// For Bulk Endpoint set value to 512. -// For Interrupt Endpoint set value to 1 .. 1024. -// For Isochronous Endpoint set value to 1 .. 1024. -// Additional Transactions per Microframe -// Specifies additional transactions per microframe to improve communication performance. -// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. -// Relevant only if Endpoint Type is Isochronous or Interrupt. -// Value: None = 1 transaction per microframe -// Value: 1 additional = 2 transaction per microframe -// Value: 2 additional = 3 transaction per microframe -// <0=>None -// <1=>1 additional -// <2=>2 additional -#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_WMAXPACKETSIZE 512 - -// Endpoint Polling Interval <0-255> -// Specifies the frequency of requests initiated by USB Host (in 125 us units). -// Endpoint Descriptor: bInterval field. -// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. -// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). -#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_BINTERVAL 0 - -// -// -// -// - -// String Settings -// Following settings are used to create String Descriptor(s) - -// Interface String Enable -// Enable Interface String. -// If disabled Interface String will not be assigned to USB Device Custom Class Interface 3. -#define USBD_CUSTOM_CLASS0_IF3_STR_EN 0 - -// Interface String -#define USBD_CUSTOM_CLASS0_IF3_STR L"USB_CUSTOM_CLASS0_IF3" - -// -// - -// Microsoft OS Descriptor Settings -// Following settings are used to create Extended Compat ID OS Feature Descriptor - -// Extended Compat ID OS Feature Descriptor Function Section -// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID_EN 0 - -// compatibleID -// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID "WINUSB" - -// subCompatibleID -// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_SUBCOMPAT_ID "" - -// - -// Extended Properties OS Feature Descriptor -// Custom Property Section 0 -// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_INT 0 - -// -// - -// Custom Property Section 1 -// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_INT 0 - -// -// - -// Custom Property Section 2 -// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_INT 0 - -// -// - -// Custom Property Section 3 -// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_EN 0 - -// Data Type -// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. -// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. -// <1=>Unicode String (REG_SZ) -// <2=>Unicode String with environment variables (REG_EXPAND_SZ) -// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// <6=>Unicode String with symbolic link (REG_LINK) -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_TYP 1 - -// Name -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_NAME L"" - -// Data -// Unicode String -// Property Data in case Data Type is selected as Unicode String. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_STR L"" - -// 32-bit Integer -// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. -#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_INT 0 - -// -// -// -// -// - - -// OS Resources Settings -// These settings are used to optimize usage of OS resources. -// Endpoint 1 Thread Stack Size <64-65536> -// This setting is used if Endpoint 1 is enabled. -#define USBD_CUSTOM_CLASS0_EP1_THREAD_STACK_SIZE 512 - -// Endpoint 1 Thread Priority -#define USBD_CUSTOM_CLASS0_EP1_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 2 Thread Stack Size <64-65536> -// This setting is used if Endpoint 2 is enabled. -#define USBD_CUSTOM_CLASS0_EP2_THREAD_STACK_SIZE 512 - -// Endpoint 2 Thread Priority -#define USBD_CUSTOM_CLASS0_EP2_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 3 Thread Stack Size <64-65536> -// This setting is used if Endpoint 3 is enabled. -#define USBD_CUSTOM_CLASS0_EP3_THREAD_STACK_SIZE 512 - -// Endpoint 3 Thread Priority -#define USBD_CUSTOM_CLASS0_EP3_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 4 Thread Stack Size <64-65536> -// This setting is used if Endpoint 4 is enabled. -#define USBD_CUSTOM_CLASS0_EP4_THREAD_STACK_SIZE 512 - -// Endpoint 4 Thread Priority -#define USBD_CUSTOM_CLASS0_EP4_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 5 Thread Stack Size <64-65536> -// This setting is used if Endpoint 5 is enabled. -#define USBD_CUSTOM_CLASS0_EP5_THREAD_STACK_SIZE 512 - -// Endpoint 5 Thread Priority -#define USBD_CUSTOM_CLASS0_EP5_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 6 Thread Stack Size <64-65536> -// This setting is used if Endpoint 6 is enabled. -#define USBD_CUSTOM_CLASS0_EP6_THREAD_STACK_SIZE 512 - -// Endpoint 6 Thread Priority -#define USBD_CUSTOM_CLASS0_EP6_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 7 Thread Stack Size <64-65536> -// This setting is used if Endpoint 7 is enabled. -#define USBD_CUSTOM_CLASS0_EP7_THREAD_STACK_SIZE 512 - -// Endpoint 7 Thread Priority -#define USBD_CUSTOM_CLASS0_EP7_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 8 Thread Stack Size <64-65536> -// This setting is used if Endpoint 8 is enabled. -#define USBD_CUSTOM_CLASS0_EP8_THREAD_STACK_SIZE 512 - -// Endpoint 8 Thread Priority -#define USBD_CUSTOM_CLASS0_EP8_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 9 Thread Stack Size <64-65536> -// This setting is used if Endpoint 9 is enabled. -#define USBD_CUSTOM_CLASS0_EP9_THREAD_STACK_SIZE 512 - -// Endpoint 9 Thread Priority -#define USBD_CUSTOM_CLASS0_EP9_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 10 Thread Stack Size <64-65536> -// This setting is used if Endpoint 10 is enabled. -#define USBD_CUSTOM_CLASS0_EP10_THREAD_STACK_SIZE 512 - -// Endpoint 10 Thread Priority -#define USBD_CUSTOM_CLASS0_EP10_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 11 Thread Stack Size <64-65536> -// This setting is used if Endpoint 11 is enabled. -#define USBD_CUSTOM_CLASS0_EP11_THREAD_STACK_SIZE 512 - -// Endpoint 11 Thread Priority -#define USBD_CUSTOM_CLASS0_EP11_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 12 Thread Stack Size <64-65536> -// This setting is used if Endpoint 12 is enabled. -#define USBD_CUSTOM_CLASS0_EP12_THREAD_STACK_SIZE 512 - -// Endpoint 12 Thread Priority -#define USBD_CUSTOM_CLASS0_EP12_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 13 Thread Stack Size <64-65536> -// This setting is used if Endpoint 13 is enabled. -#define USBD_CUSTOM_CLASS0_EP13_THREAD_STACK_SIZE 512 - -// Endpoint 13 Thread Priority -#define USBD_CUSTOM_CLASS0_EP13_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 14 Thread Stack Size <64-65536> -// This setting is used if Endpoint 14 is enabled. -#define USBD_CUSTOM_CLASS0_EP14_THREAD_STACK_SIZE 512 - -// Endpoint 14 Thread Priority -#define USBD_CUSTOM_CLASS0_EP14_THREAD_PRIORITY osPriorityAboveNormal - -// Endpoint 15 Thread Stack Size <64-65536> -// This setting is used if Endpoint 15 is enabled. -#define USBD_CUSTOM_CLASS0_EP15_THREAD_STACK_SIZE 512 - -// Endpoint 15 Thread Priority -#define USBD_CUSTOM_CLASS0_EP15_THREAD_PRIORITY osPriorityAboveNormal - -// -// diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD1_LPC55xxx.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD1_LPC55xxx.c deleted file mode 100644 index 69f94c1..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD1_LPC55xxx.c +++ /dev/null @@ -1,984 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2021 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 28. June 2021 - * $Revision: V1.0 - * - * Driver: Driver_USBD1 - * Project: USB1 High-Speed Device Driver for NXP LPC55xxx - * -------------------------------------------------------------------------- - * Use the following configuration settings in the middleware component - * to connect to this driver. - * - * Configuration Setting Value - * --------------------- ----- - * Connect to hardware via Driver_USBD# = 1 - * -------------------------------------------------------------------------- - * Defines used for driver configuration (at compile time): - * - * USBD1_MAX_ENDPOINT_NUM: defines maximum number of IN/OUT Endpoint pairs - * that driver will support with Control Endpoint 0 - * not included, this value impacts driver memory - * requirements - * - default value: 5 - * - maximum value: 5 - * - * USBD1_OUT_EP0_BUF_SZ: defines Out Endpoint0 buffer size (in Bytes) - * USBD1_IN_EP0_BUF_SZ: defines In Endpoint0 buffer size (in Bytes) - * USBD1_OUT_EP1_BUF_SZ: defines Out Endpoint1 buffer size (in Bytes) - * USBD1_IN_EP1_BUF_SZ: defines In Endpoint1 buffer size (in Bytes) - * USBD1_OUT_EP2_BUF_SZ: defines Out Endpoint2 buffer size (in Bytes) - * USBD1_IN_EP2_BUF_SZ: defines In Endpoint2 buffer size (in Bytes) - * USBD1_OUT_EP3_BUF_SZ: defines Out Endpoint3 buffer size (in Bytes) - * USBD1_IN_EP3_BUF_SZ: defines In Endpoint3 buffer size (in Bytes) - * USBD1_OUT_EP4_BUF_SZ: defines Out Endpoint4 buffer size (in Bytes) - * USBD1_IN_EP4_BUF_SZ: defines In Endpoint4 buffer size (in Bytes) - * USBD1_OUT_EP5_BUF_SZ: defines Out Endpoint5 buffer size (in Bytes) - * USBD1_IN_EP5_BUF_SZ: defines In Endpoint5 buffer size (in Bytes) - * -------------------------------------------------------------------------- */ - -/* History: - * Version 1.0 - * Initial release - */ - -#include -#include - -#include "Driver_USBD.h" - -#include "RTE_Device.h" -#include "RTE_Components.h" - -#include "fsl_common.h" -#include "fsl_power.h" -#include "fsl_clock.h" -#include "fsl_reset.h" - -#include "USB_LPC55xxx.h" - -// Endpoint buffer must be 64Byte aligned -#define ALIGN_64(n) (n == 0U ? (0U) : (64U * (((n - 1U) / 64U) + 1U))) - -#ifndef USBD1_MAX_ENDPOINT_NUM -#define USBD1_MAX_ENDPOINT_NUM (5U) -#endif -#if (USBD1_MAX_ENDPOINT_NUM > 5) -#error Too many Endpoints, maximum IN/OUT Endpoint pairs that this driver supports is 5 !!! -#endif - -// Endpoint Bufer size definitions -#ifndef USBD1_OUT_EP0_BUF_SZ -#define USBD1_OUT_EP0_BUF_SZ (64U) -#endif -#ifndef USBD1_IN_EP0_BUF_SZ -#define USBD1_IN_EP0_BUF_SZ (64U) -#endif -#define USBD1_OUT_EP0_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP0_BUF_SZ)) -#define USBD1_IN_EP0_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP0_BUF_SZ)) - -#if (USBD1_MAX_ENDPOINT_NUM > 0) -#ifndef USBD1_OUT_EP1_BUF_SZ -#define USBD1_OUT_EP1_BUF_SZ (1024U) -#endif -#ifndef USBD1_IN_EP1_BUF_SZ -#define USBD1_IN_EP1_BUF_SZ (1024U) -#endif -#else -#define USBD1_OUT_EP1_BUF_SZ (0U) -#define USBD1_IN_EP1_BUF_SZ (0U) -#endif -#define USBD1_OUT_EP1_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP1_BUF_SZ)) -#define USBD1_IN_EP1_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP1_BUF_SZ)) - -#if (USBD1_MAX_ENDPOINT_NUM > 1) -#ifndef USBD1_OUT_EP2_BUF_SZ -#define USBD1_OUT_EP2_BUF_SZ (1024U) -#endif -#ifndef USBD1_IN_EP2_BUF_SZ -#define USBD1_IN_EP2_BUF_SZ (1024U) -#endif -#else -#define USBD1_OUT_EP2_BUF_SZ (0U) -#define USBD1_IN_EP2_BUF_SZ (0U) -#endif -#define USBD1_OUT_EP2_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP2_BUF_SZ)) -#define USBD1_IN_EP2_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP2_BUF_SZ)) - -#if (USBD1_MAX_ENDPOINT_NUM > 2) -#ifndef USBD1_OUT_EP3_BUF_SZ -#define USBD1_OUT_EP3_BUF_SZ (1024U) -#endif -#ifndef USBD1_IN_EP3_BUF_SZ -#define USBD1_IN_EP3_BUF_SZ (1024U) -#endif -#else -#define USBD1_OUT_EP3_BUF_SZ (0U) -#define USBD1_IN_EP3_BUF_SZ (0U) -#endif -#define USBD1_OUT_EP3_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP3_BUF_SZ)) -#define USBD1_IN_EP3_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP3_BUF_SZ)) - -#if (USBD1_MAX_ENDPOINT_NUM > 3) -#ifndef USBD1_OUT_EP4_BUF_SZ -#define USBD1_OUT_EP4_BUF_SZ (1024U) -#endif -#ifndef USBD1_IN_EP4_BUF_SZ -#define USBD1_IN_EP4_BUF_SZ (1024U) -#endif -#else -#define USBD1_OUT_EP4_BUF_SZ (0U) -#define USBD1_IN_EP4_BUF_SZ (0U) -#endif -#define USBD1_OUT_EP4_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP4_BUF_SZ)) -#define USBD1_IN_EP4_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP4_BUF_SZ)) - -#if (USBD1_MAX_ENDPOINT_NUM > 4) -#ifndef USBD1_OUT_EP5_BUF_SZ -#define USBD1_OUT_EP5_BUF_SZ (1024U) -#endif -#ifndef USBD1_IN_EP5_BUF_SZ -#define USBD1_IN_EP5_BUF_SZ (1024U) -#endif -#else -#define USBD1_OUT_EP5_BUF_SZ (0U) -#define USBD1_IN_EP5_BUF_SZ (0U) -#endif -#define USBD1_OUT_EP5_BUF_SZ_64 (ALIGN_64(USBD1_OUT_EP5_BUF_SZ)) -#define USBD1_IN_EP5_BUF_SZ_64 (ALIGN_64(USBD1_IN_EP5_BUF_SZ)) - -#define USBD1_OUT_EP0_BUF_OFFSET (0U) -#define USBD1_IN_EP0_BUF_OFFSET (USBD1_OUT_EP0_BUF_SZ_64) -#define USBD1_OUT_EP1_BUF_OFFSET (USBD1_IN_EP0_BUF_OFFSET + USBD1_IN_EP0_BUF_SZ_64) -#define USBD1_IN_EP1_BUF_OFFSET (USBD1_OUT_EP1_BUF_OFFSET + USBD1_OUT_EP1_BUF_SZ_64) -#define USBD1_OUT_EP2_BUF_OFFSET (USBD1_IN_EP1_BUF_OFFSET + USBD1_IN_EP1_BUF_SZ_64) -#define USBD1_IN_EP2_BUF_OFFSET (USBD1_OUT_EP2_BUF_OFFSET + USBD1_OUT_EP2_BUF_SZ_64) -#define USBD1_OUT_EP3_BUF_OFFSET (USBD1_IN_EP2_BUF_OFFSET + USBD1_IN_EP2_BUF_SZ_64) -#define USBD1_IN_EP3_BUF_OFFSET (USBD1_OUT_EP3_BUF_OFFSET + USBD1_OUT_EP3_BUF_SZ_64) -#define USBD1_OUT_EP4_BUF_OFFSET (USBD1_IN_EP3_BUF_OFFSET + USBD1_IN_EP3_BUF_SZ_64) -#define USBD1_IN_EP4_BUF_OFFSET (USBD1_OUT_EP4_BUF_OFFSET + USBD1_OUT_EP4_BUF_SZ_64) -#define USBD1_OUT_EP5_BUF_OFFSET (USBD1_IN_EP4_BUF_OFFSET + USBD1_IN_EP4_BUF_SZ_64) -#define USBD1_IN_EP5_BUF_OFFSET (USBD1_OUT_EP5_BUF_OFFSET + USBD1_OUT_EP5_BUF_SZ_64) - -#define USBD_EP_BUFFER_SZ (USBD1_OUT_EP0_BUF_SZ_64 + USBD1_IN_EP0_BUF_SZ_64 + \ - USBD1_OUT_EP1_BUF_SZ_64 + USBD1_IN_EP1_BUF_SZ_64 + \ - USBD1_OUT_EP2_BUF_SZ_64 + USBD1_IN_EP2_BUF_SZ_64 + \ - USBD1_OUT_EP3_BUF_SZ_64 + USBD1_IN_EP3_BUF_SZ_64 + \ - USBD1_OUT_EP4_BUF_SZ_64 + USBD1_IN_EP4_BUF_SZ_64 + \ - USBD1_OUT_EP5_BUF_SZ_64 + USBD1_IN_EP5_BUF_SZ_64 ) - -#if (USBD_EP_BUFFER_SZ > 0x3C00U) - #error "Endpoint buffers do not fit into RAMx!" -#endif - -#define EP_NUM(ep_addr) (ep_addr & ARM_USB_ENDPOINT_NUMBER_MASK) -#define EP_IDX(ep_addr) ((ep_addr & 0x80U) ? ((EP_NUM(ep_addr)) * 2U + 1U) : (ep_addr * 2U)) -#define CMD_IDX(ep_addr) ((ep_addr & 0x80U) ? ((EP_NUM(ep_addr)) * 4U + 2U) : (ep_addr * 4U)) - -// Resource allocation -static uint8_t ep_buf[USBD_EP_BUFFER_SZ] __attribute__((section(".bss.ARM.__at_0x40100000"))); -static EP_CMD ep_cmd[(USBD1_MAX_ENDPOINT_NUM + 1) * 4] __attribute__((section(".bss.ARM.__at_0x40103C00"))); -static EP_TRANSFER ep_transfer[(USBD1_MAX_ENDPOINT_NUM + 1) * 2]; - -// Global variables -static ARM_USBD_STATE usbd_state; -static uint8_t usbd_flags; - -static uint8_t setup_packet[8]; // Setup packet data -static volatile uint8_t setup_received; // Setup packet received - -static ARM_USBD_SignalDeviceEvent_t SignalDeviceEvent; -static ARM_USBD_SignalEndpointEvent_t SignalEndpointEvent; - -static const EP endpoint[] = { - // Endpoint 0 - { &(ep_cmd[0]), &(ep_buf[USBD1_OUT_EP0_BUF_OFFSET]), &(ep_transfer[0]), USBD1_OUT_EP0_BUF_OFFSET, }, - { &(ep_cmd[2]), &(ep_buf[USBD1_IN_EP0_BUF_OFFSET]), &(ep_transfer[1]), USBD1_IN_EP0_BUF_OFFSET, }, - -#if (USBD1_MAX_ENDPOINT_NUM > 0U) - // Endpoint 1 - { &(ep_cmd[4]), &(ep_buf[USBD1_OUT_EP1_BUF_OFFSET]), &(ep_transfer[2]), USBD1_OUT_EP1_BUF_OFFSET, }, - { &(ep_cmd[6]), &(ep_buf[USBD1_IN_EP1_BUF_OFFSET]), &(ep_transfer[3]), USBD1_IN_EP1_BUF_OFFSET, }, -#endif - -#if (USBD1_MAX_ENDPOINT_NUM > 1U) - // Endpoint 2 - { &(ep_cmd[8]), &(ep_buf[USBD1_OUT_EP2_BUF_OFFSET]), &(ep_transfer[4]), USBD1_OUT_EP2_BUF_OFFSET, }, - { &(ep_cmd[10]), &(ep_buf[USBD1_IN_EP2_BUF_OFFSET]), &(ep_transfer[5]), USBD1_IN_EP2_BUF_OFFSET, }, -#endif - -#if (USBD1_MAX_ENDPOINT_NUM > 2U) - // Endpoint 3 - { &(ep_cmd[12]), &(ep_buf[USBD1_OUT_EP3_BUF_OFFSET]), &(ep_transfer[6]), USBD1_OUT_EP3_BUF_OFFSET, }, - { &(ep_cmd[14]), &(ep_buf[USBD1_IN_EP3_BUF_OFFSET]), &(ep_transfer[7]), USBD1_IN_EP3_BUF_OFFSET, }, -#endif - -#if (USBD1_MAX_ENDPOINT_NUM > 3U) - // Endpoint 4 - { &(ep_cmd[16]), &(ep_buf[USBD1_OUT_EP4_BUF_OFFSET]), &(ep_transfer[8]), USBD1_OUT_EP4_BUF_OFFSET, }, - { &(ep_cmd[18]), &(ep_buf[USBD1_IN_EP4_BUF_OFFSET]), &(ep_transfer[9]), USBD1_IN_EP4_BUF_OFFSET, }, -#endif -#if (USBD1_MAX_ENDPOINT_NUM > 4U) - // Endpoint 5 - { &(ep_cmd[16]), &(ep_buf[USBD1_OUT_EP5_BUF_OFFSET]), &(ep_transfer[8]), USBD1_OUT_EP5_BUF_OFFSET, }, - { &(ep_cmd[18]), &(ep_buf[USBD1_IN_EP5_BUF_OFFSET]), &(ep_transfer[9]), USBD1_IN_EP5_BUF_OFFSET, }, -#endif -}; - - -// USBD Driver ***************************************************************** - -#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) - -// Driver Version -static const ARM_DRIVER_VERSION usbd_driver_version = { ARM_USBD_API_VERSION, ARM_USBD_DRV_VERSION }; - -// Driver Capabilities -static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = { -#if (USBD_VBUS_DETECT == 1) - 1U, // VBUS Detection - 1U, // Event VBUS On - 1U, // Event VBUS Off -#else - 0U, // VBUS Detection - 0U, // Event VBUS On - 0U // Event VBUS Off -#endif -}; - -/** - \fn void USBD_Reset (void) - \brief Reset USB Endpoint settings and variables. -*/ -static void USBD_Reset (void) { - // Clear USB Endpoint command/status list - memset((void *)ep_cmd, 0, sizeof(ep_cmd)); - - memset((void *)&usbd_state, 0, sizeof(usbd_state)); -} - -// USBD Driver functions - -/** - \fn ARM_DRIVER_VERSION USBD_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -static ARM_DRIVER_VERSION USBD_GetVersion (void) { return usbd_driver_version; } - -/** - \fn ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_USBD_CAPABILITIES -*/ -static ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) { return usbd_driver_capabilities; } - -/** - \fn int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) - \brief Initialize USB Device Interface. - \param[in] cb_device_event Pointer to \ref ARM_USBD_SignalDeviceEvent - \param[in] cb_endpoint_event Pointer to \ref ARM_USBD_SignalEndpointEvent - \return \ref execution_status -*/ -static int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) { - - if ((usbd_flags & USBD_DRIVER_FLAG_INITIALIZED) != 0U) { return ARM_DRIVER_OK; } - - SignalDeviceEvent = cb_device_event; - SignalEndpointEvent = cb_endpoint_event; - - usbd_flags = USBD_DRIVER_FLAG_INITIALIZED; - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_Uninitialize (void) - \brief De-initialize USB Device Interface. - \return \ref execution_status -*/ -static int32_t USBD_Uninitialize (void) { - - usbd_flags &= ~USBD_DRIVER_FLAG_INITIALIZED; - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_PowerControl (ARM_POWER_STATE state) - \brief Control USB Device Interface Power. - \param[in] state Power state - \return \ref execution_status -*/ -static int32_t USBD_PowerControl (ARM_POWER_STATE state) { - - switch (state) { - case ARM_POWER_OFF: - NVIC_DisableIRQ (USB1_IRQn); // Disable interrupt - NVIC_ClearPendingIRQ (USB1_IRQn); // Clear pending interrupt - - usbd_flags &= ~USBD_DRIVER_FLAG_POWERED; // Clear powered flag - - RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn); // Reset USB1 Device controller - RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn); // Reset USB1 PHY - RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); // Reset USB1 RAM controller - - // Disable USB IP clock - SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_DEV(1); - SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_PHY(1); - - // Clear USB Endpoint command/status list - memset((void *)ep_cmd, 0, sizeof(ep_cmd)); - - // Clear Endpoint transfer structure - memset((void *)ep_transfer, 0, sizeof(ep_transfer)); - break; - - case ARM_POWER_FULL: - if ((usbd_flags & USBD_DRIVER_FLAG_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; } - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) != 0U) { return ARM_DRIVER_OK; } - - // Enable USB IP clock - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, 16000000U); - CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); - - // Enable device operation (through USB1 Host PORTMODE register) - CLOCK_EnableClock(kCLOCK_Usbh1); - USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbh1); - - // Setup PHY - USBPHY->PWD = 0U; - USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; - USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; - - // Clear USB RAM - memset((void *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM); - - // Reset variables and endpoint settings - USBD_Reset (); - - // Set Endpoint list start address - USBHSD->EPLISTSTART = (uint32_t)ep_cmd; - - // Set USB Data buffer start address - USBHSD->DATABUFSTART = (uint32_t)ep_buf; - - // Enable device status interrupt - USBHSD->INTEN = USB_INTSTAT_DEV_INT_MASK; - - usbd_flags |= USBD_DRIVER_FLAG_POWERED; - - // Enable USB interrupt - NVIC_EnableIRQ (USB1_IRQn); - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_DeviceConnect (void) - \brief Connect USB Device. - \return \ref execution_status -*/ -static int32_t USBD_DeviceConnect (void) { - - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - // Attach Device - USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DCON_MASK; - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_DeviceDisconnect (void) - \brief Disconnect USB Device. - \return \ref execution_status -*/ -static int32_t USBD_DeviceDisconnect (void) { - - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - // Detach Device - USBHSD->DEVCMDSTAT &= ~USB_DEVCMDSTAT_DCON_MASK; - - return ARM_DRIVER_OK; -} - -/** - \fn ARM_USBD_STATE USBD_DeviceGetState (void) - \brief Get current USB Device State. - \return Device State \ref ARM_USBD_STATE -*/ -static ARM_USBD_STATE USBD_DeviceGetState (void) { - ARM_USBD_STATE dev_state = { 0U, 0U, 0U }; - - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return dev_state; } - - - return usbd_state; -} - -/** - \fn int32_t USBD_DeviceRemoteWakeup (void) - \brief Trigger USB Remote Wakeup. - \return \ref execution_status -*/ -static int32_t USBD_DeviceRemoteWakeup (void) { - - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - // Force remote wakeup - USBHSD->DEVCMDSTAT &= ~USB_DEVCMDSTAT_DSUS_MASK; - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_DeviceSetAddress (uint8_t dev_addr) - \brief Set USB Device Address. - \param[in] dev_addr Device Address - \return \ref execution_status -*/ -static int32_t USBD_DeviceSetAddress (uint8_t dev_addr) { - - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_ReadSetupPacket (uint8_t *setup) - \brief Read setup packet received over Control Endpoint. - \param[out] setup Pointer to buffer for setup packet - \return \ref execution_status -*/ -static int32_t USBD_ReadSetupPacket (uint8_t *setup) { - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - if (setup_received == 0U) { return ARM_DRIVER_ERROR; } - - setup_received = 0U; - memcpy(setup, setup_packet, 8); - - if (setup_received != 0U) { // If new setup packet was received while this was being read - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_EndpointConfigure (uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size) - \brief Configure USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx) - \param[in] ep_max_packet_size Endpoint Maximum Packet Size - \return \ref execution_status -*/ -static int32_t USBD_EndpointConfigure (uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size) { - uint8_t ep_num, ep_idx; - EP const * ep; - volatile uint32_t DBG1 = 0; - volatile uint32_t DBG2 = 0; - volatile uint32_t DBG3 = 0; - volatile uint32_t DBG4 = 0; - volatile uint32_t DBG5 = ep_addr; - volatile uint32_t DBG6 = ep_type; - volatile uint32_t DBG7 = ep_max_packet_size; - - ep_num = EP_NUM(ep_addr); - ep_idx = EP_IDX(ep_addr); - ep = &endpoint[ep_idx]; - - if (ep_num > USBD1_MAX_ENDPOINT_NUM) { - DBG1++; - return ARM_DRIVER_ERROR; - } - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { - DBG2++; - return ARM_DRIVER_ERROR; - } - - if (ep->cmd->active == 1U) { - // Endpoint is "owned" by hardware - DBG3++; - return ARM_DRIVER_ERROR_BUSY; - } - - if (ep_max_packet_size > ((ep+1)->buf_offset - ep->buf_offset)) { - // Configured Endpoint buffer size is too small - DBG4++; - return ARM_DRIVER_ERROR; - } - - // Clear Endpoint command/status - memset((void *)ep->cmd, 0, sizeof(EP_CMD) * 2U); - - // Clear Endpoint transfer structure - memset((void *)ep->transfer, 0, sizeof(EP_TRANSFER)); - - ep_transfer[ep_idx].max_packet_sz = ep_max_packet_size & ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK; - - ep->cmd->buff_addr_offset = ep->buf_offset >> 6; - - if (ep_num != 0U) { - ep->cmd->ep_disabled = 1U; - - // Reset data toggle - ep->cmd->ep_type_periodic = 0U; - ep->cmd->toggle_value = 0U; - ep->cmd->toggle_reset = 1U; - - switch (ep_type) { - case ARM_USB_ENDPOINT_CONTROL: - break; - case ARM_USB_ENDPOINT_ISOCHRONOUS: - ep->cmd->toggle_value = 0U; - ep->cmd->ep_type_periodic = 1U; - break; - case ARM_USB_ENDPOINT_BULK: - ep->cmd->toggle_value = 0U; - ep->cmd->ep_type_periodic = 0U; - break; - case ARM_USB_ENDPOINT_INTERRUPT: - ep->cmd->toggle_value = 1U; - ep->cmd->ep_type_periodic = 1U; - break; - default: // Unknown endpoint type - return ARM_DRIVER_ERROR; - } - ep->cmd->ep_disabled = 0U; - - /* Double-buffering not configured/used */ - ep->cmd[1].buff_addr_offset = ep->buf_offset >> 6; - ep->cmd[1].ep_disabled = 1U; - } - - // Clear Endpoint Interrupt - USBHSD->INTSTAT = USB_INT_EP(ep_idx); - - // Enable endpoint interrupt - USBHSD->INTEN |= USB_INT_EP(ep_idx); - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) - \brief Unconfigure USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return \ref execution_status -*/ -static int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) { - uint8_t ep_num, ep_idx; - EP const * ep; - - ep_num = EP_NUM(ep_addr); - ep_idx = EP_IDX(ep_addr); - ep = &endpoint[ep_idx]; - - if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - if (ep->cmd->active == 1U) { - // Endpoint is "owned" by hardware - return ARM_DRIVER_ERROR_BUSY; - } - - // Disable endpoint interrupt - USBHSD->INTEN &= ~USB_INT_EP(ep_idx); - - if (ep->cmd->active) { - USBHSD->EPSKIP |= (1U << ep_idx); - while (USBHSD->EPSKIP & (1U << ep_idx)); - } - - // Clear Endpoint command/status - memset((void *)ep->cmd, 0, sizeof(EP_CMD) * 2U); - - ep->cmd->ep_disabled = 1U; - - // Clear Endpoint Interrupt - USBHSD->INTSTAT = USB_INT_EP(ep_idx); - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) - \brief Set/Clear Stall for USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] stall Operation - - \b false Clear - - \b true Set - \return \ref execution_status -*/ -static int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) { - uint8_t ep_num; - EP const * ep; - - ep_num = EP_NUM(ep_addr); - ep = &endpoint[EP_IDX(ep_addr)]; - - if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - if (ep->cmd->active == 1U) { - // Endpoint is "owned" by hardware - return ARM_DRIVER_ERROR_BUSY; - } - - if (stall != 0U) { - // Set Endpoint stall - ep->cmd->stall = 1U; - } else { - ep->cmd->toggle_value = 0U; - ep->cmd->toggle_reset = 1U; - - // Clear Stall - ep->cmd->stall = 0U; - } - - return ARM_DRIVER_OK; -} - -/** - \fn int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) - \brief Read data from or Write data to USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[out] data Pointer to buffer for data to read or with data to write - \param[in] num Number of data bytes to transfer - \return \ref execution_status -*/ -static int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) { - uint8_t ep_num, ep_idx; - EP const * ep; - - ep_num = EP_NUM(ep_addr); - ep_idx = EP_IDX(ep_addr); - ep = &endpoint[ep_idx]; - - if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - if (ep->cmd->active == 1U) { - // Endpoint is "owned" by hardware - return ARM_DRIVER_ERROR_BUSY; - } - - ep->transfer->num = num; - ep->transfer->buf = data; - ep->transfer->num_transferred_total = 0U; - if (num > ep->transfer->max_packet_sz) { num = ep->transfer->max_packet_sz; } - - if (ep_addr & ARM_USB_ENDPOINT_DIRECTION_MASK) { - // Copy data into IN Endpoint buffer - memcpy (ep->buf, ep->transfer->buf, num); - } - - ep->cmd->buff_addr_offset = ep->buf_offset >> 6; - - ep->transfer->num_transferring = num; - - // Set number of bytes to send/receive - ep->cmd->NBytes = num; - - // Activate endpoint - ep->cmd->active |= 1U; - - return ARM_DRIVER_OK; -} - -/** - \fn uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) - \brief Get result of USB Endpoint transfer. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return number of successfully transferred data bytes -*/ -static uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) { - - if (EP_NUM(ep_addr) > USBD1_MAX_ENDPOINT_NUM) { return 0U; } - - return (ep_transfer[EP_IDX(ep_addr)].num_transferred_total); -} - -/** - \fn int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) - \brief Abort current USB Endpoint transfer. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return \ref execution_status -*/ -static int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) { - uint8_t ep_num, ep_idx; - EP const * ep; - - ep_num = EP_NUM(ep_addr); - ep_idx = EP_IDX(ep_addr); - ep = &endpoint[ep_idx]; - - if (ep_num > USBD1_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; } - - // Disable endpoint interrupt - USBHSD->INTEN &= ~USB_INT_EP(ep_idx); - - if (ep->cmd->active == 1U) { - USBHSD->EPSKIP |= (1U << EP_IDX(ep_addr)); - while (USBHSD->EPSKIP & (1U << EP_IDX(ep_addr))); - ep->cmd->active = 0U; - } - - // Clear transfer info - ep->transfer->num = 0U; - ep->transfer->num_transferred_total = 0U; - ep->transfer->num_transferring = 0U; - - // Clear Endpoint Interrupt - USBHSD->INTSTAT = USB_INT_EP(ep_idx); - - // Enable endpoint interrupt - USBHSD->INTEN |= USB_INT_EP(ep_idx); - - return ARM_DRIVER_OK; -} - -/** - \fn uint16_t USBD_GetFrameNumber (void) - \brief Get current USB Frame Number. - \return Frame Number -*/ -static uint16_t USBD_GetFrameNumber (void) { - - if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return 0; } - - return ((USBHSD->INFO & USB_INFO_FRAME_NR_MASK) >> USB_INFO_FRAME_NR_SHIFT); -} - -/** - \fn void USB1_IRQHandler (void) - \brief USB1 Device Interrupt Routine (IRQ). -*/ -void USB1_IRQHandler (void) { - uint32_t num, ep_idx, intstat, cmdstat, dev_evt = 0U; - uint16_t val; - EP const * ep; - - intstat = USBHSD->INTSTAT & USBHSD->INTEN; - cmdstat = USBHSD->DEVCMDSTAT; - - // Clear interrupt flags - USBHSD->INTSTAT = intstat; - - // Device Status interrupt - if (intstat & USB_INTSTAT_DEV_INT_MASK) { - - // Reset - if (cmdstat & USB_DEVCMDSTAT_DRES_C_MASK) { - USBD_Reset (); - usbd_state.active = 1U; - usbd_state.speed = ARM_USB_SPEED_FULL; - USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DRES_C_MASK | USB_DEVCMDSTAT_DEV_EN_MASK; - SignalDeviceEvent(ARM_USBD_EVENT_RESET); - - if (((USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >> USBHSD_DEVCMDSTAT_Speed_SHIFT) == 2U) { - SignalDeviceEvent(ARM_USBD_EVENT_HIGH_SPEED); - } - } - - // Suspend - if (cmdstat & USB_DEVCMDSTAT_DSUS_MASK) { - usbd_state.active = 0U; - USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DSUS_MASK; - SignalDeviceEvent(ARM_USBD_EVENT_SUSPEND); - } - -#if (USBD_VBUS_DETECT == 1) - // Disconnect - if (cmdstat & USB_DEVCMDSTAT_DCON_C) { - usbd_state.active = 0U; - usbd_state.vbus = 0U; - LPC_USB->DEVCMDSTAT |= USB_DEVCMDSTAT_DCON_C; - SignalDeviceEvent(ARM_USBD_EVENT_VBUS_OFF); - } - - // VBUS De-bounced - if (cmdstat & USB_DEVCMDSTAT_VBUS_DEBOUNCED) { - usbd_state.vbus = 1U; - SignalDeviceEvent(ARM_USBD_EVENT_VBUS_ON); - } -#endif - } - - // Endpoint interrupt - if (intstat & USB_INT_EP_MSK) { - for (ep_idx = 0; ep_idx <= USBD1_MAX_ENDPOINT_NUM * 2U; ep_idx += 2U) { - - if (intstat & (USB_INT_EP(ep_idx))) { - - // Clear Interrupt status - USBHSD->INTSTAT = (1 << ep_idx); - // Setup Packet - if ((ep_idx == 0U) && ((cmdstat & USB_DEVCMDSTAT_SETUP_MASK) != 0U)) { - ep_cmd[0].stall = 0U; - ep_cmd[1].stall = 0U; - ep_cmd[2].stall = 0U; - ep_cmd[3].stall = 0U; - - USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_SETUP_MASK; - memcpy(setup_packet, ep_buf, 8); - - // Analyze Setup packet for SetAddress - val = setup_packet[0] | (setup_packet[1] << 8); - if (val == 0x0500U) { - val = (setup_packet[2] | (setup_packet[3] << 8)) & USB_DEVCMDSTAT_DEV_ADDR_MASK; - // Set device address - USBHSD->DEVCMDSTAT = (USBHSD->DEVCMDSTAT & ~USB_DEVCMDSTAT_DEV_ADDR_MASK) | - USB_DEVCMDSTAT_DEV_ADDR(val) | USB_DEVCMDSTAT_DEV_EN_MASK; - } - - setup_received = 1U; - if (SignalEndpointEvent != NULL) { - SignalEndpointEvent(0U, ARM_USBD_EVENT_SETUP); - } - } else { - // OUT Packet - ep = &endpoint[ep_idx]; - - num = ep->transfer->num_transferring - ep->cmd->NBytes; - - // Copy EP data - memcpy (ep->transfer->buf, ep->buf, num); - - ep->transfer->buf += num; - ep->transfer->num_transferred_total += num; - - // Check if all OUT data received: - // - data terminated with ZLP or short packet or - // - all required data received - if ((ep->transfer->num_transferred_total == ep->transfer->num) || - (num == 0U) || (num != ep->transfer->max_packet_sz)) { - - if (SignalEndpointEvent != NULL) { - SignalEndpointEvent(ep_idx / 2U, ARM_USBD_EVENT_OUT); - } - } else { - // Remaining data to transfer - num = ep->transfer->num - ep->transfer->num_transferred_total; - if (num > ep->transfer->max_packet_sz) { num = ep->transfer->max_packet_sz; } - - ep->transfer->num_transferring = num; - ep->cmd->NBytes = num; - ep->cmd->buff_addr_offset = ep->buf_offset >> 6; - - // Activate EP to receive next packet - ep->cmd->active = 1U; - } - } - } - } - - // IN Packet - for (ep_idx = 1; ep_idx <= USBD1_MAX_ENDPOINT_NUM * 2U; ep_idx += 2U) { - - if (intstat & (USB_INT_EP(ep_idx))) { - // Clear Interrupt status - USBHSD->INTSTAT = (1 << ep_idx); - - ep = &endpoint[ep_idx]; - - ep->transfer->buf += ep->transfer->num_transferring; - ep->transfer->num_transferred_total += ep->transfer->num_transferring; - - if (ep->transfer->num_transferred_total == ep->transfer->num) { - // All data has been transfered - if (SignalEndpointEvent != NULL) { - SignalEndpointEvent(0x80 | (ep_idx / 2), ARM_USBD_EVENT_IN); - } - } else { - // Still data to transfer - num = ep->transfer->num - ep->transfer->num_transferred_total; - if (num > ep->transfer->max_packet_sz) { - // Remaining data bigger than max packet - num = ep->transfer->max_packet_sz; - } - - ep->transfer->num_transferring = num; - - // Copy data into IN Endpoint buffer - memcpy (ep->buf, ep->transfer->buf, num); - - ep->cmd->buff_addr_offset = ep->buf_offset >> 6; - - // Set number of bytes to send - ep->cmd->NBytes = num; - - // Activate EP to send next packet - ep->cmd->active = 1U; - } - } - } - } -} - -ARM_DRIVER_USBD Driver_USBD1 = { - USBD_GetVersion, - USBD_GetCapabilities, - USBD_Initialize, - USBD_Uninitialize, - USBD_PowerControl, - USBD_DeviceConnect, - USBD_DeviceDisconnect, - USBD_DeviceGetState, - USBD_DeviceRemoteWakeup, - USBD_DeviceSetAddress, - USBD_ReadSetupPacket, - USBD_EndpointConfigure, - USBD_EndpointUnconfigure, - USBD_EndpointStall, - USBD_EndpointTransfer, - USBD_EndpointTransferGetResult, - USBD_EndpointTransferAbort, - USBD_GetFrameNumber -}; diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CDC_ACM_UART_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CDC_ACM_UART_0.c deleted file mode 100644 index 7f12203..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CDC_ACM_UART_0.c +++ /dev/null @@ -1,381 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device:CDC - * Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_User_CDC_ACM_UART_0.c - * Purpose: USB Device Communication Device Class (CDC) - * Abstract Control Model (ACM) USB <-> UART Bridge User module - * Rev.: V1.0.8 - *----------------------------------------------------------------------------*/ -/** - * \addtogroup usbd_cdcFunctions - * - * USBD_User_CDC_ACM_UART_0.c implements the application specific - * functionality of the CDC ACM class and is used to demonstrate a USB <-> UART - * bridge. All data received on USB is transmitted on UART and all data - * received on UART is transmitted on USB. - * - * Details of operation: - * UART -> USB: - * Initial reception on UART is started after the USB Host sets line coding - * with SetLineCoding command. Having received a full UART buffer, any - * new reception is restarted on the same buffer. Any data received on - * the UART is sent over USB using the CDC0_ACM_UART_to_USB_Thread thread. - * USB -> UART: - * While the UART transmit is not busy, data transmission on the UART is - * started in the USBD_CDC0_ACM_DataReceived callback as soon as data is - * received on the USB. Further data received on USB is transmitted on - * UART in the UART callback routine until there is no more data available. - * In this case, the next UART transmit is restarted from the - * USBD_CDC0_ACM_DataReceived callback as soon as new data is received - * on the USB. - * - * The following constants in this module affect the module functionality: - * - * - UART_PORT: specifies UART Port - * default value: 0 (=UART0) - * - UART_BUFFER_SIZE: specifies UART data Buffer Size - * default value: 512 - * - * Notes: - * If the USB is slower than the UART, data can get lost. This may happen - * when USB is pausing during data reception because of the USB Host being - * too loaded with other tasks and not polling the Bulk IN Endpoint often - * enough (up to 2 seconds of gap in polling Bulk IN Endpoint may occur). - * This problem can be solved by using a large enough UART buffer to - * compensate up to a few seconds of received UART data or by using UART - * flow control. - * If the device that receives the UART data (usually a PC) is too loaded - * with other tasks it can also loose UART data. This problem can only be - * solved by using UART flow control. - * - * This file has to be adapted in case of UART flow control usage. - */ - - -//! [code_USBD_User_CDC_ACM] -#include -#include - -#include "rl_usb.h" - -#include "Driver_USART.h" - -#include "DAP_config.h" -#include "DAP.h" - -// UART Configuration ---------------------------------------------------------- - -#define UART_BUFFER_SIZE (512) // UART Buffer Size - -//------------------------------------------------------------------------------ - -#define _UART_Driver_(n) Driver_USART##n -#define UART_Driver_(n) _UART_Driver_(n) -extern ARM_DRIVER_USART UART_Driver_(DAP_UART_DRIVER); -#define ptrUART (&UART_Driver_(DAP_UART_DRIVER)) - -// Local Variables -static uint8_t uart_rx_buf[UART_BUFFER_SIZE]; -static uint8_t uart_tx_buf[UART_BUFFER_SIZE]; - -static volatile int32_t uart_rx_cnt = 0; -static volatile int32_t usb_tx_cnt = 0; - -static void *cdc_acm_bridge_tid = 0U; -static CDC_LINE_CODING cdc_acm_line_coding = { 0U, 0U, 0U, 0U }; - -static uint8_t cdc_acm_active = 1U; -static osMutexId_t cdc_acm_mutex_id = NULL; - -// Acquire mutex -__STATIC_INLINE void CDC_ACM_Lock (void) { - if (cdc_acm_mutex_id == NULL) { - cdc_acm_mutex_id = osMutexNew(NULL); - } - osMutexAcquire(cdc_acm_mutex_id, osWaitForever); -} - -// Release mutex -__STATIC_INLINE void CDC_ACM_Unlock (void) { - osMutexRelease(cdc_acm_mutex_id); -} - -// Change communication settings. -// \param[in] line_coding pointer to CDC_LINE_CODING structure. -// \return true set line coding request processed. -// \return false set line coding request not supported or not processed. -static bool CDC_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) { - uint32_t data_bits = 0U, parity = 0U, stop_bits = 0U; - int32_t status; - - (void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U); - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); - (void)ptrUART->Control (ARM_USART_CONTROL_TX, 0U); - (void)ptrUART->Control (ARM_USART_CONTROL_RX, 0U); - - switch (line_coding->bCharFormat) { - case 0: // 1 Stop bit - stop_bits = ARM_USART_STOP_BITS_1; - break; - case 1: // 1.5 Stop bits - stop_bits = ARM_USART_STOP_BITS_1_5; - break; - case 2: // 2 Stop bits - stop_bits = ARM_USART_STOP_BITS_2; - break; - default: - return false; - } - - switch (line_coding->bParityType) { - case 0: // None - parity = ARM_USART_PARITY_NONE; - break; - case 1: // Odd - parity = ARM_USART_PARITY_ODD; - break; - case 2: // Even - parity = ARM_USART_PARITY_EVEN; - break; - default: - return false; - } - - switch (line_coding->bDataBits) { - case 5: - data_bits = ARM_USART_DATA_BITS_5; - break; - case 6: - data_bits = ARM_USART_DATA_BITS_6; - break; - case 7: - data_bits = ARM_USART_DATA_BITS_7; - break; - case 8: - data_bits = ARM_USART_DATA_BITS_8; - break; - default: - return false; - } - - status = ptrUART->Control(ARM_USART_MODE_ASYNCHRONOUS | - data_bits | - parity | - stop_bits , - line_coding->dwDTERate ); - - if (status != ARM_DRIVER_OK) { - return false; - } - - // Store requested settings to local variable - memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding)); - - uart_rx_cnt = 0; - usb_tx_cnt = 0; - - (void)ptrUART->Control (ARM_USART_CONTROL_TX, 1U); - (void)ptrUART->Control (ARM_USART_CONTROL_RX, 1U); - - (void)ptrUART->Receive (uart_rx_buf, UART_BUFFER_SIZE); - - return true; -} - -// Activate or Deactivate USBD COM PORT -// \param[in] cmd 0=deactivate, 1=activate -// \return 0=Ok, 0xFF=Error -uint8_t USB_COM_PORT_Activate (uint32_t cmd) { - switch (cmd) { - case 0U: - cdc_acm_active = 0U; - USBD_CDC0_ACM_Uninitialize(); - break; - case 1U: - USBD_CDC0_ACM_Initialize(); - CDC_ACM_Lock(); - CDC_ACM_SetLineCoding(&cdc_acm_line_coding); - cdc_acm_active = 1U; - CDC_ACM_Unlock(); - break; - } - - return 0U; -} - -// Called when UART has transmitted or received requested number of bytes. -// \param[in] event UART event -// - ARM_USART_EVENT_SEND_COMPLETE: all requested data was sent -// - ARM_USART_EVENT_RECEIVE_COMPLETE: all requested data was received -static void UART_Callback (uint32_t event) { - int32_t cnt; - - if (cdc_acm_active == 0U) { - return; - } - - if (event & ARM_USART_EVENT_SEND_COMPLETE) { - // USB -> UART - cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE); - if (cnt > 0) { - (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt)); - } - } - - if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { - // UART data received, restart new reception - uart_rx_cnt += UART_BUFFER_SIZE; - (void)ptrUART->Receive(uart_rx_buf, UART_BUFFER_SIZE); - } -} - -// Thread: Sends data received on UART to USB -// \param[in] arg not used. -__NO_RETURN static void CDC0_ACM_UART_to_USB_Thread (void *arg) { - int32_t cnt, cnt_to_wrap; - - (void)(arg); - - for (;;) { - // UART - > USB - if (ptrUART->GetStatus().rx_busy != 0U) { - cnt = uart_rx_cnt; - cnt += (int32_t)ptrUART->GetRxCount(); - cnt -= usb_tx_cnt; - if (cnt >= (UART_BUFFER_SIZE - 32)) { - // Dump old data in UART receive buffer if USB is not consuming fast enough - cnt = (UART_BUFFER_SIZE - 32); - usb_tx_cnt = uart_rx_cnt - (UART_BUFFER_SIZE - 32); - } - if (cnt > 0) { - cnt_to_wrap = (int32_t)(UART_BUFFER_SIZE - ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))); - if (cnt > cnt_to_wrap) { - cnt = cnt_to_wrap; - } - cnt = USBD_CDC_ACM_WriteData(0U, (uart_rx_buf + ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))), cnt); - if (cnt > 0) { - usb_tx_cnt += cnt; - } - } - } - (void)osDelay(10U); - } -} - -static osRtxThread_t cdc0_acm_uart_to_usb_thread_cb_mem __SECTION(.bss.os.thread.cb); -static uint64_t cdc0_acm_uart_to_usb_thread_stack_mem[512U / 8U] __SECTION(.bss.os.thread.cdc.stack); -static const osThreadAttr_t cdc0_acm_uart_to_usb_thread_attr = { - "CDC0_ACM_UART_to_USB_Thread", - 0U, - &cdc0_acm_uart_to_usb_thread_cb_mem, - sizeof(osRtxThread_t), - &cdc0_acm_uart_to_usb_thread_stack_mem[0], - sizeof(cdc0_acm_uart_to_usb_thread_stack_mem), - osPriorityNormal, - 0U, - 0U -}; - - -// CDC ACM Callbacks ----------------------------------------------------------- - -// Called when new data was received from the USB Host. -// \param[in] len number of bytes available to read. -void USBD_CDC0_ACM_DataReceived (uint32_t len) { - int32_t cnt; - - (void)(len); - - if (cdc_acm_active == 0U) { - return; - } - - if (ptrUART->GetStatus().tx_busy == 0U) { - // Start USB -> UART - cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE); - if (cnt > 0) { - (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt)); - } - } -} - -// Called during USBD_Initialize to initialize the USB CDC class instance (ACM). -void USBD_CDC0_ACM_Initialize (void) { - (void)ptrUART->Initialize (UART_Callback); - (void)ptrUART->PowerControl (ARM_POWER_FULL); - - cdc_acm_bridge_tid = osThreadNew (CDC0_ACM_UART_to_USB_Thread, NULL, &cdc0_acm_uart_to_usb_thread_attr); -} - - -// Called during USBD_Uninitialize to de-initialize the USB CDC class instance (ACM). -void USBD_CDC0_ACM_Uninitialize (void) { - if (osThreadTerminate (cdc_acm_bridge_tid) == osOK) { - cdc_acm_bridge_tid = NULL; - } - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); - (void)ptrUART->PowerControl (ARM_POWER_OFF); - (void)ptrUART->Uninitialize (); -} - - -// Called upon USB Bus Reset Event. -void USBD_CDC0_ACM_Reset (void) { - if (cdc_acm_active == 0U ) { - return; - } - (void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U); - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); -} - - -// Called upon USB Host request to change communication settings. -// \param[in] line_coding pointer to CDC_LINE_CODING structure. -// \return true set line coding request processed. -// \return false set line coding request not supported or not processed. -bool USBD_CDC0_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) { - bool ret = false; - - CDC_ACM_Lock(); - if (cdc_acm_active == 0U) { - // Store requested settings to local variable - memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding)); - ret = true; - } else { - ret = CDC_ACM_SetLineCoding(line_coding); - } - CDC_ACM_Unlock(); - - return ret; -} - - -// Called upon USB Host request to retrieve communication settings. -// \param[out] line_coding pointer to CDC_LINE_CODING structure. -// \return true get line coding request processed. -// \return false get line coding request not supported or not processed. -bool USBD_CDC0_ACM_GetLineCoding (CDC_LINE_CODING *line_coding) { - - // Load settings from ones stored on USBD_CDC0_ACM_SetLineCoding callback - *line_coding = cdc_acm_line_coding; - - return true; -} - - -// Called upon USB Host request to set control line states. -// \param [in] state control line settings bitmap. -// - bit 0: DTR state -// - bit 1: RTS state -// \return true set control line state request processed. -// \return false set control line state request not supported or not processed. -bool USBD_CDC0_ACM_SetControlLineState (uint16_t state) { - // Add code for set control line state - - (void)(state); - - return true; -} - -//! [code_USBD_User_CDC_ACM] diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CustomClass_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CustomClass_0.c deleted file mode 100644 index 186c7b9..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CustomClass_0.c +++ /dev/null @@ -1,358 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2016 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_User_CustomClass_0.c - * Purpose: USB Device Custom Class User module - * Rev.: V6.7.3 - *----------------------------------------------------------------------------*/ -/* - * USBD_User_CustomClass_0.c is a code template for the Custom Class 0 - * class request handling. It allows user to handle all Custom Class class - * requests. - * - * Uncomment "Example code" lines to see example that receives data on - * Endpoint 1 OUT and echoes it back on Endpoint 1 IN. - * To try the example you also have to enable Bulk Endpoint 1 IN/OUT in Custom - * Class configuration in USBD_Config_CustomClass_0.h file. - */ - -/** - * \addtogroup usbd_custom_classFunctions - * - */ - - -//! [code_USBD_User_CustomClass] - -#include -#include -#include -#include "cmsis_os2.h" -#define osObjectsExternal -#include "osObjects.h" -#include "rl_usb.h" -#include "Driver_USBD.h" -#include "DAP_config.h" -#include "DAP.h" - -static volatile uint16_t USB_RequestIndexI; // Request Index In -static volatile uint16_t USB_RequestIndexO; // Request Index Out -static volatile uint16_t USB_RequestCountI; // Request Count In -static volatile uint16_t USB_RequestCountO; // Request Count Out -static volatile uint8_t USB_RequestIdle; // Request Idle Flag - -static volatile uint16_t USB_ResponseIndexI; // Response Index In -static volatile uint16_t USB_ResponseIndexO; // Response Index Out -static volatile uint16_t USB_ResponseCountI; // Response Count In -static volatile uint16_t USB_ResponseCountO; // Response Count Out -static volatile uint8_t USB_ResponseIdle; // Response Idle Flag - -static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Request Buffer -static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Response Buffer -static uint16_t USB_RespSize[DAP_PACKET_COUNT]; // Response Size - -// \brief Callback function called during USBD_Initialize to initialize the USB Custom class instance -void USBD_CustomClass0_Initialize (void) { - // Handle Custom Class Initialization - - // Initialize variables - USB_RequestIndexI = 0U; - USB_RequestIndexO = 0U; - USB_RequestCountI = 0U; - USB_RequestCountO = 0U; - USB_RequestIdle = 1U; - USB_ResponseIndexI = 0U; - USB_ResponseIndexO = 0U; - USB_ResponseCountI = 0U; - USB_ResponseCountO = 0U; - USB_ResponseIdle = 1U; -} - -// \brief Callback function called during USBD_Uninitialize to de-initialize the USB Custom class instance -void USBD_CustomClass0_Uninitialize (void) { - // Handle Custom Class De-initialization -} - -// \brief Callback function called upon USB Bus Reset signaling -void USBD_CustomClass0_Reset (void) { - // Handle USB Bus Reset Event -} - -// \brief Callback function called when Endpoint Start was requested (by activating interface or configuration) -// \param[in] ep_addr endpoint address. -void USBD_CustomClass0_EndpointStart (uint8_t ep_addr) { - // Start communication on Endpoint - if (ep_addr == USB_ENDPOINT_OUT(1U)) { - USB_RequestIdle = 0U; - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[0], DAP_PACKET_SIZE); - } -} - -// \brief Callback function called when Endpoint Stop was requested (by de-activating interface or activating configuration 0) -// \param[in] ep_addr endpoint address. -void USBD_CustomClass0_EndpointStop (uint8_t ep_addr) { - // Handle Endpoint communication stopped - (void)ep_addr; -} - -// \brief Callback function called when Custom Class 0 received SETUP PACKET on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] setup_packet pointer to received setup packet. -// \param[out] buf pointer to data buffer used for data stage requested by setup packet. -// \param[out] len pointer to number of data bytes in data stage requested by setup packet. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet if no data stage) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -usbdRequestStatus USBD_CustomClass0_Endpoint0_SetupPacketReceived (const USB_SETUP_PACKET *setup_packet, uint8_t **buf, uint32_t *len) { - (void)setup_packet; - (void)buf; - (void)len; - - switch (setup_packet->bmRequestType.Recipient) { - case USB_REQUEST_TO_DEVICE: - break; - case USB_REQUEST_TO_INTERFACE: - break; - case USB_REQUEST_TO_ENDPOINT: - break; - default: - break; - } - - return usbdRequestNotProcessed; -} - -// \brief Callback function called when SETUP PACKET was processed by USB library -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback nor by Custom Class callback) -// \param[in] setup_packet pointer to processed setup packet. -void USBD_CustomClass0_Endpoint0_SetupPacketProcessed (const USB_SETUP_PACKET *setup_packet) { - (void)setup_packet; - - switch (setup_packet->bmRequestType.Recipient) { - case USB_REQUEST_TO_DEVICE: - break; - case USB_REQUEST_TO_INTERFACE: - break; - case USB_REQUEST_TO_ENDPOINT: - break; - default: - break; - } -} - -// \brief Callback function called when Custom Class 0 received OUT DATA on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] len number of received data bytes. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -// \return usbdRequestNAK: request was processed but the device is busy (return NAK) -usbdRequestStatus USBD_CustomClass0_Endpoint0_OutDataReceived (uint32_t len) { - (void)len; - return usbdRequestNotProcessed; -} - -// \brief Callback function called when Custom Class 0 sent IN DATA on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] len number of sent data bytes. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (return ACK) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -// \return usbdRequestNAK: request was processed but the device is busy (return NAK) -usbdRequestStatus USBD_CustomClass0_Endpoint0_InDataSent (uint32_t len) { - (void)len; - return usbdRequestNotProcessed; -} - -// \brief Callback function called when DATA was sent or received on Endpoint n -// \param[in] event event on Endpoint: -// - ARM_USBD_EVENT_OUT = data OUT received -// - ARM_USBD_EVENT_IN = data IN sent -void USBD_CustomClass0_Endpoint1_Event (uint32_t event) { - // Handle Endpoint 1 events - uint32_t n; - - if (event & ARM_USBD_EVENT_OUT) { - n = USBD_EndpointReadGetResult(0U, USB_ENDPOINT_OUT(1U)); - if (n != 0U) { - if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) { - DAP_TransferAbort = 1U; - } else { - USB_RequestIndexI++; - if (USB_RequestIndexI == DAP_PACKET_COUNT) { - USB_RequestIndexI = 0U; - } - USB_RequestCountI++; - osThreadFlagsSet(DAP_ThreadId, 0x01); - } - } - // Start reception of next request packet - if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); - } else { - USB_RequestIdle = 1U; - } - } - if (event & ARM_USBD_EVENT_IN) { - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]); - USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - } else { - USB_ResponseIdle = 1U; - } - } -} -void USBD_CustomClass0_Endpoint2_Event (uint32_t event) { - // Handle Endpoint 2 events - if (event & ARM_USBD_EVENT_IN) { - SWO_TransferComplete(); - } -} -void USBD_CustomClass0_Endpoint3_Event (uint32_t event) { - // Handle Endpoint 3 events - (void)event; -} -void USBD_CustomClass0_Endpoint4_Event (uint32_t event) { - // Handle Endpoint 4 events - (void)event; -} -void USBD_CustomClass0_Endpoint5_Event (uint32_t event) { - // Handle Endpoint 5 events - (void)event; -} -void USBD_CustomClass0_Endpoint6_Event (uint32_t event) { - // Handle Endpoint 6 events - (void)event; -} -void USBD_CustomClass0_Endpoint7_Event (uint32_t event) { - // Handle Endpoint 7 events - (void)event; -} -void USBD_CustomClass0_Endpoint8_Event (uint32_t event) { - // Handle Endpoint 8 events - (void)event; -} -void USBD_CustomClass0_Endpoint9_Event (uint32_t event) { - // Handle Endpoint 9 events - (void)event; -} -void USBD_CustomClass0_Endpoint10_Event (uint32_t event) { - // Handle Endpoint 10 events - (void)event; -} -void USBD_CustomClass0_Endpoint11_Event (uint32_t event) { - // Handle Endpoint 11 events - (void)event; -} -void USBD_CustomClass0_Endpoint12_Event (uint32_t event) { - // Handle Endpoint 12 events - (void)event; -} -void USBD_CustomClass0_Endpoint13_Event (uint32_t event) { - // Handle Endpoint 13 events - (void)event; -} -void USBD_CustomClass0_Endpoint14_Event (uint32_t event) { - // Handle Endpoint 14 events - (void)event; -} -void USBD_CustomClass0_Endpoint15_Event (uint32_t event) { - // Handle Endpoint 15 events - (void)event; -} - -// DAP Thread. -__NO_RETURN void DAP_Thread (void *argument) { - uint32_t flags; - uint32_t n; - (void) argument; - - for (;;) { - osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - - // Process pending requests - while (USB_RequestCountI != USB_RequestCountO) { - - // Handle Queue Commands - n = USB_RequestIndexO; - while (USB_Request[n][0] == ID_DAP_QueueCommands) { - USB_Request[n][0] = ID_DAP_ExecuteCommands; - n++; - if (n == DAP_PACKET_COUNT) { - n = 0U; - } - if (n == USB_RequestIndexI) { - flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - if (flags & 0x80U) { - break; - } - } - } - - // Execute DAP Command (process request and prepare response) - USB_RespSize[USB_ResponseIndexI] = - (uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]); - - // Update Request Index and Count - USB_RequestIndexO++; - if (USB_RequestIndexO == DAP_PACKET_COUNT) { - USB_RequestIndexO = 0U; - } - USB_RequestCountO++; - - if (USB_RequestIdle) { - if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { - USB_RequestIdle = 0U; - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); - } - } - - // Update Response Index and Count - USB_ResponseIndexI++; - if (USB_ResponseIndexI == DAP_PACKET_COUNT) { - USB_ResponseIndexI = 0U; - } - USB_ResponseCountI++; - - if (USB_ResponseIdle) { - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - n = USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - USB_ResponseIdle = 0U; - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[n], USB_RespSize[n]); - } - } - } - } -} - -// SWO Data Queue Transfer -// buf: pointer to buffer with data -// num: number of bytes to transfer -void SWO_QueueTransfer (uint8_t *buf, uint32_t num) { - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(2U), buf, num); -} - -// SWO Data Abort Transfer -void SWO_AbortTransfer (void) { - USBD_EndpointAbort(0U, USB_ENDPOINT_IN(2U)); -} - -//! [code_USBD_User_CustomClass] diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USB_LPC55xxx.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USB_LPC55xxx.h deleted file mode 100644 index bb29db4..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/USB_LPC55xxx.h +++ /dev/null @@ -1,70 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2021 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 28. June 2021 - * $Revision: V1.0 - * - * Project: USB Driver Definitions for NXP LPC55xxx - * -------------------------------------------------------------------------- */ - -#ifndef __USB_LPC55XXX_H -#define __USB_LPC55XXX_H - -#include - -// USB Device Endpoint Interrupt definitions -#define USB_INT_EP_MSK (0x0FFFU) -#define USB_INT_EP(ep_idx) ((1U << (ep_idx)) & USB_INT_EP_MSK) - -// USB Driver State Flags -// Device State Flags -#define USBD_DRIVER_FLAG_INITIALIZED (1U ) -#define USBD_DRIVER_FLAG_POWERED (1U << 1 ) - -// Transfer information structure -typedef struct { - uint32_t max_packet_sz; - uint32_t num; - uint32_t num_transferred_total; - uint32_t num_transferring; - uint8_t *buf; -} EP_TRANSFER; - -// Endpoint command/status -typedef struct { - uint32_t buff_addr_offset : 11; - uint32_t NBytes : 15; - uint32_t ep_type_periodic : 1; - uint32_t toggle_value : 1; - uint32_t toggle_reset : 1; - uint32_t stall : 1; - uint32_t ep_disabled : 1; - uint32_t active : 1; -} EP_CMD; - -// Endpoint structure -typedef struct __EP { - EP_CMD * const cmd; - uint8_t * const buf; - EP_TRANSFER * const transfer; - uint16_t buf_offset; -} EP; - -#endif /* __USB_LPC55XXX_H */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.c deleted file mode 100644 index d7fd979..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.c +++ /dev/null @@ -1,150 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ -/* - * How to set up clock using clock driver functions: - * - * 1. Setup clock sources. - * - * 2. Set up wait states of the flash. - * - * 3. Set up all dividers. - * - * 4. Set up all selectors to provide selected clocks. - */ - -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v7.0 -processor: LPC55S69 -package_id: LPC55S69JBD64 -mcu_data: ksdk2_0 -processor_version: 9.0.3 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -#include "fsl_power.h" -#include "fsl_clock.h" -#include "clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: FXCOM0_clock.outFreq, value: 48 MHz} -- {id: FXCOM3_clock.outFreq, value: 48 MHz} -- {id: System_clock.outFreq, value: 150 MHz, locked: true, accuracy: '0.001'} -- {id: USB1_PHY_clock.outFreq, value: 16 MHz} -settings: -- {id: PLL0_Mode, value: Normal} -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -- {id: ENABLE_CLKIN_ENA, value: Enabled} -- {id: ENABLE_PLL_USB_OUT, value: Enabled} -- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} -- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.FROHFDIV} -- {id: SYSCON.FCCLKSEL3.sel, value: SYSCON.FROHFDIV} -- {id: SYSCON.FRGCTRL3_DIV.scale, value: '256', locked: true} -- {id: SYSCON.FROHFDIV.scale, value: '2', locked: true} -- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} -- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} -- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} -- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} -- {id: SYSCON.PLL0_PDEC.scale, value: '2'} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} -- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ -#ifndef SDK_SECONDARY_CORE - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ - - POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up PLL */ - CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - const pll_setup_t pll0Setup = { - .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), - .pllndec = SYSCON_PLL0NDEC_NDIV(8U), - .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), - .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, - .pllRate = 150000000U, - .flags = PLL_SETUPFLAG_WAITLOCK - }; - CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ - - /*!< Set up dividers */ - #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) - CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 0U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */ - #else - CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 256U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */ - #endif - #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) - CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 0U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */ - #else - CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 256U, false); /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */ - #endif - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClkDiv(kCLOCK_DivFrohfClk, 0U, true); /*!< Reset FROHFDIV divider counter and halt it */ - CLOCK_SetClkDiv(kCLOCK_DivFrohfClk, 2U, false); /*!< Set FROHFDIV divider to value 2 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ - CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to FRO_HF_DIV */ - CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to FRO_HF_DIV */ - - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -#endif -} - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.h deleted file mode 100644 index c196f14..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.c deleted file mode 100644 index 6ee35ef..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.c +++ /dev/null @@ -1,77 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Peripherals v9.0 -processor: LPC55S69 -package_id: LPC55S69JBD64 -mcu_data: ksdk2_0 -processor_version: 9.0.3 -functionalGroups: -- name: BOARD_InitPeripherals - UUID: 85f4cd0c-3b58-4e23-a413-239f6952f139 - called_from_default_init: true - selectedCore: cm33_core0 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -component: -- type: 'system' -- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' -- global_system_definitions: - - user_definitions: '' - - user_includes: '' - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/*********************************************************************************************************************** - * Included files - **********************************************************************************************************************/ -#include "peripherals.h" - -/*********************************************************************************************************************** - * BOARD_InitPeripherals functional group - **********************************************************************************************************************/ -/*********************************************************************************************************************** - * NVIC initialization code - **********************************************************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -instance: -- name: 'NVIC' -- type: 'nvic' -- mode: 'general' -- custom_name_enabled: 'false' -- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67' -- functional_group: 'BOARD_InitPeripherals' -- peripheral: 'NVIC' -- config_sets: - - nvic: - - interrupt_table: [] - - interrupts: [] - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/* Empty initialization function (commented out) -static void NVIC_init(void) { -} */ - -/*********************************************************************************************************************** - * Initialization functions - **********************************************************************************************************************/ -void BOARD_InitPeripherals(void) -{ - /* Initialize components */ -} - -/*********************************************************************************************************************** - * BOARD_InitBootPeripherals function - **********************************************************************************************************************/ -void BOARD_InitBootPeripherals(void) -{ - BOARD_InitPeripherals(); -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.h deleted file mode 100644 index 2a75809..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.h +++ /dev/null @@ -1,33 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PERIPHERALS_H_ -#define _PERIPHERALS_H_ - -/*********************************************************************************************************************** - * Included files - **********************************************************************************************************************/ -#include "fsl_common.h" - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*********************************************************************************************************************** - * Initialization functions - **********************************************************************************************************************/ - -void BOARD_InitPeripherals(void); - -/*********************************************************************************************************************** - * BOARD_InitBootPeripherals function - **********************************************************************************************************************/ -void BOARD_InitBootPeripherals(void); - -#if defined(__cplusplus) -} -#endif - -#endif /* _PERIPHERALS_H_ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.c deleted file mode 100644 index 19d4184..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.c +++ /dev/null @@ -1,337 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* clang-format off */ -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v9.0 -processor: LPC55S69 -package_id: LPC55S69JBD64 -mcu_data: ksdk2_0 -processor_version: 9.0.3 -pin_labels: -- {pin_num: '36', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A, label: _DBGIF_TCK_SWCLK, identifier: DBGIF_TCK_SWCLK} -- {pin_num: '2', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: _DBGIF_TDI, identifier: DBGIF_TDI} -- {pin_num: '52', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, label: _DBGIF_TMS_SWDIO, identifier: DBGIF_TMS_SWDIO} -- {pin_num: '44', pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, label: _DBGIF_TMS_SWDIO_TXEN, identifier: DBGIF_TMS_SWDIO_TXEN} -- {pin_num: '58', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, label: _DBGIF_RESET, identifier: DBG_IF_RESET;DBGIF_RESET} -- {pin_num: '46', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13, label: _DBGIF_RESET_TXEN, identifier: DBG_IF_RESET_TXEN;DBGIF_RESET_TXEN} -- {pin_num: '53', pin_signal: PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3, label: _DBGIF_TDO_SWO, identifier: DBG_IF_TDO_SWO;DBGIF_TDO_SWO} -- {pin_num: '45', pin_signal: PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24, label: _FC0_TARGET_RXD, identifier: FC0_TARGET_RXD} -- {pin_num: '51', pin_signal: PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25, label: _FC0_TARGET_TXD, identifier: FC0_TARGET_TXD} -- {pin_num: '56', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, label: _LED1, identifier: LED1} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ -/* clang-format on */ - -#include "fsl_common.h" -#include "fsl_gpio.h" -#include "pin_mux.h" - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) -{ - MCU_LINK_InitPins(); -} - -/* clang-format off */ -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -MCU_LINK_InitPins: -- options: {callFromInitBoot: 'true', prefix: '', coreID: cm33_core0, enableClock: 'true'} -- pin_list: - - {pin_num: '36', peripheral: GPIO, signal: 'PIO0, 0', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A, direction: INPUT, - slew_rate: fast} - - {pin_num: '2', peripheral: GPIO, signal: 'PIO0, 1', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, direction: INPUT, slew_rate: fast} - - {pin_num: '52', peripheral: GPIO, signal: 'PIO0, 2', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, direction: INPUT, mode: inactive, - slew_rate: fast} - - {pin_num: '44', peripheral: GPIO, signal: 'PIO0, 28', pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, direction: OUTPUT, - gpio_init_state: 'false', slew_rate: fast} - - {pin_num: '58', peripheral: GPIO, signal: 'PIO0, 19', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, - identifier: DBGIF_RESET, direction: INPUT, slew_rate: fast} - - {pin_num: '46', peripheral: GPIO, signal: 'PIO0, 13', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13, - identifier: DBGIF_RESET_TXEN, direction: OUTPUT, gpio_init_state: 'false'} - - {pin_num: '53', peripheral: FLEXCOMM3, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3, identifier: DBGIF_TDO_SWO, - slew_rate: fast} - - {pin_num: '45', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24, slew_rate: fast} - - {pin_num: '51', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25, slew_rate: fast} - - {pin_num: '23', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} - - {pin_num: '24', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} - - {pin_num: '25', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} - - {pin_num: '22', peripheral: USBHSH, signal: USB_VSS, pin_signal: USB1_VSS22} - - {pin_num: '26', peripheral: USBHSH, signal: USB_VSS, pin_signal: USB1_VSS26} - - {pin_num: '41', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5} - - {pin_num: '56', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: OUTPUT, - gpio_init_state: 'true', mode: pullUp} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ -/* clang-format on */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : MCU_LINK_InitPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -/* Function assigned for the Cortex-M33 (Core #0) */ -void MCU_LINK_InitPins(void) -{ - /* Enables the clock for the I/O controller.: Enable Clock. */ - CLOCK_EnableClock(kCLOCK_Iocon); - - /* Enables the clock for the GPIO0 module */ - CLOCK_EnableClock(kCLOCK_Gpio0); - - gpio_pin_config_t DBGIF_TCK_SWCLK_config = { - .pinDirection = kGPIO_DigitalInput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO0_0 (pin 36) */ - GPIO_PinInit(DBGIF_TCK_SWCLK_GPIO, DBGIF_TCK_SWCLK_PORT, DBGIF_TCK_SWCLK_PIN, &DBGIF_TCK_SWCLK_config); - - gpio_pin_config_t DBGIF_TDI_config = { - .pinDirection = kGPIO_DigitalInput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO0_1 (pin 2) */ - GPIO_PinInit(DBGIF_TDI_GPIO, DBGIF_TDI_PORT, DBGIF_TDI_PIN, &DBGIF_TDI_config); - - gpio_pin_config_t DBGIF_TMS_SWDIO_config = { - .pinDirection = kGPIO_DigitalInput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO0_2 (pin 52) */ - GPIO_PinInit(DBGIF_TMS_SWDIO_GPIO, DBGIF_TMS_SWDIO_PORT, DBGIF_TMS_SWDIO_PIN, &DBGIF_TMS_SWDIO_config); - - gpio_pin_config_t LED1_config = { - .pinDirection = kGPIO_DigitalOutput, - .outputLogic = 1U - }; - /* Initialize GPIO functionality on pin PIO0_5 (pin 56) */ - GPIO_PinInit(LED1_GPIO, LED1_PORT, LED1_PIN, &LED1_config); - - gpio_pin_config_t DBGIF_RESET_TXEN_config = { - .pinDirection = kGPIO_DigitalOutput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO0_13 (pin 46) */ - GPIO_PinInit(DBGIF_RESET_TXEN_GPIO, DBGIF_RESET_TXEN_PORT, DBGIF_RESET_TXEN_PIN, &DBGIF_RESET_TXEN_config); - - gpio_pin_config_t DBGIF_RESET_config = { - .pinDirection = kGPIO_DigitalInput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO0_19 (pin 58) */ - GPIO_PinInit(DBGIF_RESET_GPIO, DBGIF_RESET_PORT, DBGIF_RESET_PIN, &DBGIF_RESET_config); - - gpio_pin_config_t DBGIF_TMS_SWDIO_TXEN_config = { - .pinDirection = kGPIO_DigitalOutput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO0_28 (pin 44) */ - GPIO_PinInit(DBGIF_TMS_SWDIO_TXEN_GPIO, DBGIF_TMS_SWDIO_TXEN_PORT, DBGIF_TMS_SWDIO_TXEN_PIN, &DBGIF_TMS_SWDIO_TXEN_config); - - IOCON->PIO[0][0] = ((IOCON->PIO[0][0] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT00 (pin 36) is configured as PIO0_0. */ - | IOCON_PIO_FUNC(PIO0_0_FUNC_ALT0) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_0_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_0_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][1] = ((IOCON->PIO[0][1] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT01 (pin 2) is configured as PIO0_1. */ - | IOCON_PIO_FUNC(PIO0_1_FUNC_ALT0) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_1_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_1_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][13] = ((IOCON->PIO[0][13] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT013 (pin 46) is configured as PIO0_13. */ - | IOCON_PIO_FUNC(PIO0_13_FUNC_ALT0) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_13_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][19] = ((IOCON->PIO[0][19] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT019 (pin 58) is configured as PIO0_19. */ - | IOCON_PIO_FUNC(PIO0_19_FUNC_ALT0) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_19_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_19_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][2] = ((IOCON->PIO[0][2] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT02 (pin 52) is configured as PIO0_2. */ - | IOCON_PIO_FUNC(PIO0_2_FUNC_ALT0) - - /* Selects function mode (on-chip pull-up/pull-down resistor control). - * : Inactive. - * Inactive (no pull-down/pull-up resistor enabled). */ - | IOCON_PIO_MODE(PIO0_2_MODE_INACTIVE) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_2_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_2_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT024 (pin 45) is configured as FC0_RXD_SDA_MOSI_DATA. */ - | IOCON_PIO_FUNC(PIO0_24_FUNC_ALT1) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_24_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_24_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][25] = ((IOCON->PIO[0][25] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT025 (pin 51) is configured as FC0_TXD_SCL_MISO_WS. */ - | IOCON_PIO_FUNC(PIO0_25_FUNC_ALT1) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_25_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_25_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT028 (pin 44) is configured as PIO0_28. */ - | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT0) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_28_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][3] = ((IOCON->PIO[0][3] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT03 (pin 53) is configured as FC3_RXD_SDA_MOSI_DATA. */ - | IOCON_PIO_FUNC(PIO0_3_FUNC_ALT1) - - /* Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. */ - | IOCON_PIO_SLEW(PIO0_3_SLEW_FAST) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_3_DIGIMODE_DIGITAL)); - - IOCON->PIO[0][5] = ((IOCON->PIO[0][5] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT05 (pin 56) is configured as PIO0_5. */ - | IOCON_PIO_FUNC(PIO0_5_FUNC_ALT0) - - /* Selects function mode (on-chip pull-up/pull-down resistor control). - * : Pull-up. - * Pull-up resistor enabled. */ - | IOCON_PIO_MODE(PIO0_5_MODE_PULL_UP) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO0_5_DIGIMODE_DIGITAL)); - - IOCON->PIO[1][2] = ((IOCON->PIO[1][2] & - /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) - - /* Selects pin function. - * : PORT12 (pin 41) is configured as USB1_PORTPWRN. */ - | IOCON_PIO_FUNC(PIO1_2_FUNC_ALT7) - - /* Select Digital mode. - * : Enable Digital mode. - * Digital input is enabled. */ - | IOCON_PIO_DIGIMODE(PIO1_2_DIGIMODE_DIGITAL)); -} -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.h deleted file mode 100644 index 1a12c66..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.h +++ /dev/null @@ -1,276 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -/*! - * @addtogroup pin_mux - * @{ - */ - -/*********************************************************************************************************************** - * API - **********************************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_0_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 0. */ -#define PIO0_0_FUNC_ALT0 0x00u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_0_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_13_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 0. */ -#define PIO0_13_FUNC_ALT0 0x00u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_19_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 0. */ -#define PIO0_19_FUNC_ALT0 0x00u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_19_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_1_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 0. */ -#define PIO0_1_FUNC_ALT0 0x00u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_1_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_24_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 1. */ -#define PIO0_24_FUNC_ALT1 0x01u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_24_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_25_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 1. */ -#define PIO0_25_FUNC_ALT1 0x01u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_25_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_28_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 0. */ -#define PIO0_28_FUNC_ALT0 0x00u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_28_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_2_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 0. */ -#define PIO0_2_FUNC_ALT0 0x00u -/*! - * @brief - * Selects function mode (on-chip pull-up/pull-down resistor control). - * : Inactive. - * Inactive (no pull-down/pull-up resistor enabled). - */ -#define PIO0_2_MODE_INACTIVE 0x00u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_2_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_3_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 1. */ -#define PIO0_3_FUNC_ALT1 0x01u -/*! - * @brief - * Driver slew rate. - * : Fast-mode, output slew rate is faster. - * Refer to the appropriate specific device data sheet for details. - */ -#define PIO0_3_SLEW_FAST 0x01u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO0_5_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 0. */ -#define PIO0_5_FUNC_ALT0 0x00u -/*! - * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ -#define PIO0_5_MODE_PULL_UP 0x02u -/*! - * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ -#define PIO1_2_DIGIMODE_DIGITAL 0x01u -/*! - * @brief Selects pin function.: Alternative connection 7. */ -#define PIO1_2_FUNC_ALT7 0x07u - -/*! @name PIO0_0 (number 36), _DBGIF_TCK_SWCLK - @{ */ - -/* Symbols to be used with GPIO driver */ -#define DBGIF_TCK_SWCLK_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define DBGIF_TCK_SWCLK_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */ -#define DBGIF_TCK_SWCLK_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define DBGIF_TCK_SWCLK_PIN 0U /*!<@brief PORT pin number */ -#define DBGIF_TCK_SWCLK_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_1 (number 2), _DBGIF_TDI - @{ */ - -/* Symbols to be used with GPIO driver */ -#define DBGIF_TDI_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define DBGIF_TDI_GPIO_PIN_MASK (1U << 1U) /*!<@brief GPIO pin mask */ -#define DBGIF_TDI_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define DBGIF_TDI_PIN 1U /*!<@brief PORT pin number */ -#define DBGIF_TDI_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_2 (number 52), _DBGIF_TMS_SWDIO - @{ */ - -/* Symbols to be used with GPIO driver */ -#define DBGIF_TMS_SWDIO_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define DBGIF_TMS_SWDIO_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */ -#define DBGIF_TMS_SWDIO_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define DBGIF_TMS_SWDIO_PIN 2U /*!<@brief PORT pin number */ -#define DBGIF_TMS_SWDIO_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_28 (number 44), _DBGIF_TMS_SWDIO_TXEN - @{ */ - -/* Symbols to be used with GPIO driver */ -#define DBGIF_TMS_SWDIO_TXEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define DBGIF_TMS_SWDIO_TXEN_GPIO_PIN_MASK (1U << 28U) /*!<@brief GPIO pin mask */ -#define DBGIF_TMS_SWDIO_TXEN_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define DBGIF_TMS_SWDIO_TXEN_PIN 28U /*!<@brief PORT pin number */ -#define DBGIF_TMS_SWDIO_TXEN_PIN_MASK (1U << 28U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_19 (number 58), _DBGIF_RESET - @{ */ - -/* Symbols to be used with GPIO driver */ -#define DBGIF_RESET_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define DBGIF_RESET_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ -#define DBGIF_RESET_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define DBGIF_RESET_PIN 19U /*!<@brief PORT pin number */ -#define DBGIF_RESET_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_13 (number 46), _DBGIF_RESET_TXEN - @{ */ - -/* Symbols to be used with GPIO driver */ -#define DBGIF_RESET_TXEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define DBGIF_RESET_TXEN_GPIO_PIN_MASK (1U << 13U) /*!<@brief GPIO pin mask */ -#define DBGIF_RESET_TXEN_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define DBGIF_RESET_TXEN_PIN 13U /*!<@brief PORT pin number */ -#define DBGIF_RESET_TXEN_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_3 (number 53), _DBGIF_TDO_SWO - @{ */ -#define DBGIF_TDO_SWO_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define DBGIF_TDO_SWO_PIN 3U /*!<@brief PORT pin number */ -#define DBGIF_TDO_SWO_PIN_MASK (1U << 3U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_24 (number 45), _FC0_TARGET_RXD - @{ */ -#define FC0_TARGET_RXD_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define FC0_TARGET_RXD_PIN 24U /*!<@brief PORT pin number */ -#define FC0_TARGET_RXD_PIN_MASK (1U << 24U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_25 (number 51), _FC0_TARGET_TXD - @{ */ -#define FC0_TARGET_TXD_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define FC0_TARGET_TXD_PIN 25U /*!<@brief PORT pin number */ -#define FC0_TARGET_TXD_PIN_MASK (1U << 25U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! @name PIO0_5 (number 56), _LED1 - @{ */ - -/* Symbols to be used with GPIO driver */ -#define LED1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define LED1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ -#define LED1_PORT 0U /*!<@brief PORT peripheral base pointer */ -#define LED1_PIN 5U /*!<@brief PORT pin number */ -#define LED1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ - /* @} */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void MCU_LINK_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c deleted file mode 100644 index 40d56a3..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c +++ /dev/null @@ -1,1284 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - /* - * Modified by Arm - */ -#define FSL_USART_MODIFIED_BY_ARM 1U - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -/*! - * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` - */ -typedef union usart_to_flexcomm -{ - flexcomm_usart_irq_handler_t usart_master_handler; - flexcomm_irq_handler_t flexcomm_handler; -} usart_to_flexcomm_t; - -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - uint32_t i; - - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); - return i; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - uint16_t rxRingBufferHead = handle->rxRingBufferHead; - uint16_t rxRingBufferTail = handle->rxRingBufferTail; - - if (rxRingBufferTail > rxRingBufferHead) - { - size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; - } - else - { - size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == (uint8_t)kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | - USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; - - /* Setup baudrate */ - if (config->enableMode32k) - { - if ((9600U % config->baudRate_Bps) == 0U) - { - base->BRG = 9600U / config->baudRate_Bps; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - /* Setting continuous Clock configuration. used for synchronous mode. */ - USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); - - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->enableMode32k = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; - config->enableHardwareFlowControl = false; -} - -#ifdef FSL_USART_MODIFIED_BY_ARM -#define FRACT_BITS 12U -#define BAUDRATE_DIVIDER_MAX_ERROR 3U - /*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. - * - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ (not used) - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - * - * Requirement: - * FlexComm input clock must be set 48MHz (fro_hf / 2). - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t flexcomm_idx; - uint32_t flexcomm_clock; - uint32_t div, div_calc; /* divider, 12 LSBs are fractonal part */ - uint8_t ovs, ovs_best; /* oversampling */ - uint32_t br_div, br_div_best; /* baudate divider */ - uint8_t mul; - uint32_t delta; - - (void)srcClock_Hz; - - flexcomm_idx = FLEXCOMM_GetInstance(base); - flexcomm_clock = CLOCK_GetFlexCommInputClock(flexcomm_idx); - if (flexcomm_clock != CPU_CLOCK_HZ) - { - /* FlexComm input clock must be 48000000 */ - return kStatus_USART_BaudrateNotSupport; - } - - /* Calculate fixed point divider (12 LSBs are fractional part) */ - div = (uint32_t)(((uint64_t)flexcomm_clock << FRACT_BITS) / (uint64_t)baudrate_Bps); - - if ((div >> FRACT_BITS) < 5U) - { - return kStatus_USART_BaudrateNotSupport; - } - - br_div_best = 0U; - if ((div & ((1 << FRACT_BITS) - 1U)) == 0U) - { - /* Divider has no fractional part */ - for (ovs = 16; ovs > 8U; ovs--) - { - br_div = div / ovs; - if ((br_div & ((1 << FRACT_BITS) - 1U)) == 0U) - { - ovs_best = ovs; - br_div_best = br_div >> FRACT_BITS; - mul = 0U; - break; - } - } - } - - if (br_div_best == 0U) - { - /* Divider has fractional part */ - if ((div >> FRACT_BITS) > 16) - { - /* Oversampling is fixed to 16 */ - ovs_best = 16U; - br_div = (div / ovs_best)>> FRACT_BITS; - if (br_div <= 0xFFFFU) - { - br_div_best = br_div; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - /* div = (1 + (mul / 256)) * (ovs * br_div) => mul = (256 * div) / (ovs * br_div) - 256 */ - mul = ((((uint64_t)div * (uint64_t)256U) / ((uint64_t)ovs_best * (uint64_t)br_div_best)) >> FRACT_BITS) - 256U; - - } - else - { - /* Baudrate divider is fixed to 1. */ - br_div_best = 1U; - ovs_best = div >> FRACT_BITS; - mul = ((((uint64_t)div * (uint64_t)256U) / ((uint64_t)ovs_best * (uint64_t)br_div_best)) >> FRACT_BITS) - 256U; - } - } - - div_calc = (uint32_t)(((uint64_t)ovs_best * (uint64_t)br_div_best * (uint64_t)mul) << FRACT_BITS) / 256U + (((uint64_t)ovs_best * (uint64_t)br_div_best) << FRACT_BITS); - delta = (div < div_calc) ? (div_calc - div) : (div - div_calc); - if (((delta * 100U) / div) > BAUDRATE_DIVIDER_MAX_ERROR) - { - return kStatus_USART_BaudrateNotSupport; - } - - CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0 + flexcomm_idx, mul, false); - base->OSR = ovs_best - 1U; - base->BRG = br_div_best - 1U; - - return kStatus_Success; -} -#else -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* If synchronous master mode is enabled, only configure the BRG value. */ - if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) - { - if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) - { - brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1U; - } - } - else - { - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8U; osrval--) - { - brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; - if (brgval > 0xFFFFU) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculated OSR and BRG value */ - baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff > ((baudrate_Bps / 100U) * 3U)) - { - return kStatus_USART_BaudrateNotSupport; - } - - /* value over range */ - if (best_brgval > 0xFFFFU) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - } - - return kStatus_Success; -} -#endif - -/*! - * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * param base USART peripheral base address. - * param baudRate_Bps USART baudrate to be set.. - * param enableMode32k true is 32k mode, false is normal mode. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) -{ -#ifdef FSL_USART_MODIFIED_BY_ARM - (void)base; - (void)baudRate_Bps; - (void)enableMode32k; - (void)srcClock_Hz; - - return kStatus_USART_BaudrateNotSupport; -#else - status_t result = kStatus_Success; - base->CFG &= ~(USART_CFG_ENABLE_MASK); - if (enableMode32k) - { - base->CFG |= USART_CFG_MODE32K_MASK; - if ((9600U % baudRate_Bps) == 0U) - { - base->BRG = 9600U / baudRate_Bps - 1U; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - base->CFG &= ~(USART_CFG_MODE32K_MASK); - result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - base->CFG |= USART_CFG_ENABLE_MASK; - return result; -#endif -} - -/*! - * brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * param base USART peripheral base address. - * param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable) -{ - assert(base != NULL); - - uint32_t temp = 0U; - - if (enable) - { - /* Set USART 9-bit mode, disable parity. */ - temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); - temp |= (uint32_t)USART_CFG_DATALEN(0x2U); - base->CFG = temp; - } - else - { - /* Set USART to 8-bit mode. */ - base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); - base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); - } -} - -/*! - * brief Transmit an address frame in 9-bit data mode. - * - * param base USART peripheral base address. - * param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address) -{ - assert(base != NULL); - base->FIFOWR = ((uint32_t)address | 0x100UL); -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_InvalidArgument Invalid argument. - * retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - /* Check whether txFIFO is enabled */ - if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return kStatus_InvalidArgument; - } - for (; length > 0U; length--) - { - /* Loop until txFIFO get some space for new data */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t statusFlag; - status_t status = kStatus_Success; -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) - { - return kStatus_Fail; - } - for (; length > 0U; length--) - { - /* loop until rxFIFO have some data to read */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) -#else - while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) -#endif - { - } -#if UART_RETRY_TIMES - if (waitTimes == 0U) - { - status = kStatus_USART_Timeout; - break; - } -#endif - /* check rxFIFO statusFlag */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - status = kStatus_USART_RxError; - break; - } - /* check receive statusFlag */ - statusFlag = base->STAT; - /* Clear all status flags */ - base->STAT |= statusFlag; - if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) - { - status = kStatus_USART_ParityError; - } - if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) - { - status = kStatus_USART_FramingError; - } - if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) - { - status = kStatus_USART_NoiseError; - } - - if (kStatus_Success == status) - { - *data = (uint8_t)base->FIFORD; - data++; - } - else - { - break; - } - } - return status; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - - uint32_t instance = 0; - usart_to_flexcomm_t handler; - handler.usart_master_handler = USART_TransferHandleIRQ; - - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Enable interrupt in NVIC. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); - if ((0U == xfer->dataSize) || (NULL == xfer->txData)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the - * handle value. */ - uint32_t interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->txData = xfer->txData; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = (uint8_t)kUSART_TxBusy; - /* Enable transmiter interrupt and the previously disabled interrupt. */ - USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0U; - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize - - ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t interruptMask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); - if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) - { - return kStatus_InvalidArgument; - } - - /* Enable address detect when address match is enabled. */ - if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) - { - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer != NULL) - { - /* Disable IRQ, protect ring buffer. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy != 0U) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive != 0U) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = xfer->dataSize; - handle->rxState = (uint8_t)kUSART_RxBusy; - } - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - /* Call user callback since all data are received. */ - if (0U == bytesToReceive) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up - * the handle value. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = (uint8_t)kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - } - /* Return the how many bytes have read. */ - if (receivedBytes != NULL) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (NULL == handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - bool sendEnabled = (handle->txDataSize != 0U); - uint8_t rxdata; - size_t tmpsize; - - /* If RX overrun. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || - (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) - { - /* Receive data */ - if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) - { - /* Clear address detect when RXFIFO has data. */ - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize != 0U) - { - rxdata = (uint8_t)base->FIFORD; - *handle->rxData = rxdata; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - if (0U == handle->rxDataSize) - { - if (NULL == handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = (uint8_t)kUSART_RxIdle; - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer != NULL) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overridden. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - rxdata = (uint8_t)base->FIFORD; - handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; - /* Increase handle->rxRingBufferHead. */ - if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0U; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - - base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; - } - } - } - - /* Tx idle and the interrupt is enabled. */ - if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) - { - /* Set txState to idle only when all data has been sent out to bus. */ - handle->txState = (uint8_t)kUSART_TxIdle; - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - tmpsize = handle->rxDataSize; - - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) - { - base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); - } - } -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/main.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/main.c deleted file mode 100644 index 649d096..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/main.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2013-2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 15. September 2021 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Examples MCU-LINK - * Title: main.c CMSIS-DAP Main module for MCU-LINK - * - *---------------------------------------------------------------------------*/ - -#include "cmsis_os2.h" -#include "osObjects.h" -#include "rl_usb.h" -#include "DAP_config.h" -#include "DAP.h" - -#include "clock_config.h" -#include "pin_mux.h" -#include "fsl_dma.h" - -// Callbacks for USART0 Driver -uint32_t USART0_GetFreq (void) { return CLOCK_GetFlexCommClkFreq(0); } -void USART0_InitPins (void) { /* Done in BOARD_InitBootPins function */ } -void USART0_DeinitPins (void) { /* Not implemented */ } - -// Callbacks for USART3 Driver -uint32_t USART3_GetFreq (void) { return CLOCK_GetFlexCommClkFreq(3); } -void USART3_InitPins (void) { /* Done in BOARD_InitBootPins function */ } -void USART3_DeinitPins (void) { /* Not implemented */ } - -// Application Main program -__NO_RETURN void app_main (void *argument) { - (void)argument; - - BOARD_InitBootPins(); - BOARD_InitBootClocks(); - - DMA_Init(DMA0); - - DAP_Setup(); // DAP Setup - - USBD_Initialize(0U); // USB Device Initialization - char *ser_num; - ser_num = GetSerialNum(); - if (ser_num != NULL) { - USBD_SetSerialNumber(0U, ser_num); // Update Serial Number - } - - USBD_Connect(0U); // USB Device Connect - - while (!USBD_Configured(0U)); // Wait for USB Device to configure - - LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED - LED_RUNNING_OUT(1U); // Turn on Target Running LED - Delayms(500U); // Wait for 500ms - LED_RUNNING_OUT(0U); // Turn off Target Running LED - LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED - - // Create DAP Thread - DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr); - - // Create SWO Thread - SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr); - - osDelay(osWaitForever); - for (;;) {} -} - -int main (void) { - - SystemCoreClockUpdate(); - osKernelInitialize(); // Initialize CMSIS-RTOS - osThreadNew(app_main, NULL, NULL); // Create application main thread - if (osKernelGetState() == osKernelReady) { - osKernelStart(); // Start thread execution - } - - for (;;) {} -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/osObjects.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/osObjects.h deleted file mode 100644 index c2be7a4..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/osObjects.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 15. September 2021 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Examples MCU-LINK - * Title: osObjects.h CMSIS-DAP RTOS2 Objects for MCU-LINK - * - *---------------------------------------------------------------------------*/ - -#ifndef __osObjects_h__ -#define __osObjects_h__ - -#include "cmsis_os2.h" - -#ifdef osObjectsExternal -extern osThreadId_t DAP_ThreadId; -extern osThreadId_t SWO_ThreadId; -#else -static const osThreadAttr_t DAP_ThreadAttr = { - .priority = osPriorityNormal -}; -static const osThreadAttr_t SWO_ThreadAttr = { - .priority = osPriorityAboveNormal -}; -extern osThreadId_t DAP_ThreadId; - osThreadId_t DAP_ThreadId; -extern osThreadId_t SWO_ThreadId; - osThreadId_t SWO_ThreadId; -#endif - -extern void DAP_Thread (void *argument); -extern void SWO_Thread (void *argument); - -extern void app_main (void *argument); - -#endif /* __osObjects_h__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.c deleted file mode 100644 index 53513c2..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 15. September 2021 - * $Revision: V1.0.0 - * - * Project: CMSIS-DAP Examples MCU-LINK - * Title: ser_num.c CMSIS-DAP Serial Number module for MCU-LINK - * - *---------------------------------------------------------------------------*/ - -#include -#include -#include - -#include "ser_num.h" -#include "fsl_iap_ffr.h" - -// Serial Number -#define SER_NUM_PREFIX "00A1" -static char SerialNum[32]; - -/** - \brief Calculate 32-bit CRC (polynom: 0x04C11DB7, init value: 0xFFFFFFFF) - \param[in] data pointer to data - \param[in] len data length (in bytes) - \return CRC32 value -*/ -static uint32_t crc32 (const uint8_t *data, uint32_t len) { - uint32_t crc32; - uint32_t n; - - crc32 = 0xFFFFFFFFU; - while (len != 0U) { - crc32 ^= ((uint32_t)*data++) << 24U; - for (n = 8U; n; n--) { - if (crc32 & 0x80000000U) { - crc32 <<= 1U; - crc32 ^= 0x04C11DB7U; - } else { - crc32 <<= 1U; - } - } - len--; - } - return (crc32); -} - -/** - \brief Get serial number string. First characters are fixed. Last eight - characters are Unique (calculated from devices's unique ID) - \return Serial number string or NULL (callculation of unique ID failed) -*/ -char *GetSerialNum (void) { - flash_config_t flash_config; - uint8_t uuid_buf[16]; - uint32_t uid; - char *str; - - str = NULL; - if (FFR_Init(&flash_config) == kStatus_Success) { - if (FFR_GetUUID(&flash_config, uuid_buf) == kStatus_Success) { - uid = crc32(uuid_buf, 16U); - snprintf(SerialNum, sizeof(SerialNum), "%s%08X", SER_NUM_PREFIX, uid); - str = SerialNum; - } - } - - return (str); -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.h deleted file mode 100644 index 92586a1..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 15. September 2021 - * $Revision: V1.0.0 - * - * Project: CMSIS-DAP Examples MCU-LINK - * Title: ser_num.h CMSIS-DAP Serial Number module for MCU-LINK - * - *---------------------------------------------------------------------------*/ - -#ifndef __SER_NUM_H__ -#define __SER_NUM_H__ - -char *GetSerialNum (void); - -#endif /* __SER_NUM_H__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Include/DAP.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Include/DAP.h deleted file mode 100644 index f226dd5..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Include/DAP.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - * Copyright (c) 2013-2022 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 5. December 2022 - * $Revision: V2.1.2 - * - * Project: CMSIS-DAP Include - * Title: DAP.h Definitions - * - *---------------------------------------------------------------------------*/ - -#ifndef __DAP_H__ -#define __DAP_H__ - - -// DAP Firmware Version -#ifdef DAP_FW_V1 -#define DAP_FW_VER "1.3.0" -#else -#define DAP_FW_VER "2.1.2" -#endif - -// DAP Command IDs -#define ID_DAP_Info 0x00U -#define ID_DAP_HostStatus 0x01U -#define ID_DAP_Connect 0x02U -#define ID_DAP_Disconnect 0x03U -#define ID_DAP_TransferConfigure 0x04U -#define ID_DAP_Transfer 0x05U -#define ID_DAP_TransferBlock 0x06U -#define ID_DAP_TransferAbort 0x07U -#define ID_DAP_WriteABORT 0x08U -#define ID_DAP_Delay 0x09U -#define ID_DAP_ResetTarget 0x0AU -#define ID_DAP_SWJ_Pins 0x10U -#define ID_DAP_SWJ_Clock 0x11U -#define ID_DAP_SWJ_Sequence 0x12U -#define ID_DAP_SWD_Configure 0x13U -#define ID_DAP_SWD_Sequence 0x1DU -#define ID_DAP_JTAG_Sequence 0x14U -#define ID_DAP_JTAG_Configure 0x15U -#define ID_DAP_JTAG_IDCODE 0x16U -#define ID_DAP_SWO_Transport 0x17U -#define ID_DAP_SWO_Mode 0x18U -#define ID_DAP_SWO_Baudrate 0x19U -#define ID_DAP_SWO_Control 0x1AU -#define ID_DAP_SWO_Status 0x1BU -#define ID_DAP_SWO_ExtendedStatus 0x1EU -#define ID_DAP_SWO_Data 0x1CU -#define ID_DAP_UART_Transport 0x1FU -#define ID_DAP_UART_Configure 0x20U -#define ID_DAP_UART_Control 0x22U -#define ID_DAP_UART_Status 0x23U -#define ID_DAP_UART_Transfer 0x21U - -#define ID_DAP_QueueCommands 0x7EU -#define ID_DAP_ExecuteCommands 0x7FU - -// DAP Vendor Command IDs -#define ID_DAP_Vendor0 0x80U -#define ID_DAP_Vendor1 0x81U -#define ID_DAP_Vendor2 0x82U -#define ID_DAP_Vendor3 0x83U -#define ID_DAP_Vendor4 0x84U -#define ID_DAP_Vendor5 0x85U -#define ID_DAP_Vendor6 0x86U -#define ID_DAP_Vendor7 0x87U -#define ID_DAP_Vendor8 0x88U -#define ID_DAP_Vendor9 0x89U -#define ID_DAP_Vendor10 0x8AU -#define ID_DAP_Vendor11 0x8BU -#define ID_DAP_Vendor12 0x8CU -#define ID_DAP_Vendor13 0x8DU -#define ID_DAP_Vendor14 0x8EU -#define ID_DAP_Vendor15 0x8FU -#define ID_DAP_Vendor16 0x90U -#define ID_DAP_Vendor17 0x91U -#define ID_DAP_Vendor18 0x92U -#define ID_DAP_Vendor19 0x93U -#define ID_DAP_Vendor20 0x94U -#define ID_DAP_Vendor21 0x95U -#define ID_DAP_Vendor22 0x96U -#define ID_DAP_Vendor23 0x97U -#define ID_DAP_Vendor24 0x98U -#define ID_DAP_Vendor25 0x99U -#define ID_DAP_Vendor26 0x9AU -#define ID_DAP_Vendor27 0x9BU -#define ID_DAP_Vendor28 0x9CU -#define ID_DAP_Vendor29 0x9DU -#define ID_DAP_Vendor30 0x9EU -#define ID_DAP_Vendor31 0x9FU - -#define ID_DAP_Invalid 0xFFU - -// DAP Status Code -#define DAP_OK 0U -#define DAP_ERROR 0xFFU - -// DAP ID -#define DAP_ID_VENDOR 1U -#define DAP_ID_PRODUCT 2U -#define DAP_ID_SER_NUM 3U -#define DAP_ID_DAP_FW_VER 4U -#define DAP_ID_DEVICE_VENDOR 5U -#define DAP_ID_DEVICE_NAME 6U -#define DAP_ID_BOARD_VENDOR 7U -#define DAP_ID_BOARD_NAME 8U -#define DAP_ID_PRODUCT_FW_VER 9U -#define DAP_ID_CAPABILITIES 0xF0U -#define DAP_ID_TIMESTAMP_CLOCK 0xF1U -#define DAP_ID_UART_RX_BUFFER_SIZE 0xFBU -#define DAP_ID_UART_TX_BUFFER_SIZE 0xFCU -#define DAP_ID_SWO_BUFFER_SIZE 0xFDU -#define DAP_ID_PACKET_COUNT 0xFEU -#define DAP_ID_PACKET_SIZE 0xFFU - -// DAP Host Status -#define DAP_DEBUGGER_CONNECTED 0U -#define DAP_TARGET_RUNNING 1U - -// DAP Port -#define DAP_PORT_AUTODETECT 0U // Autodetect Port -#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z) -#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET -#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET - -// DAP SWJ Pins -#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK -#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS -#define DAP_SWJ_TDI 2 // TDI -#define DAP_SWJ_TDO 3 // TDO -#define DAP_SWJ_nTRST 5 // nTRST -#define DAP_SWJ_nRESET 7 // nRESET - -// DAP Transfer Request -#define DAP_TRANSFER_APnDP (1U<<0) -#define DAP_TRANSFER_RnW (1U<<1) -#define DAP_TRANSFER_A2 (1U<<2) -#define DAP_TRANSFER_A3 (1U<<3) -#define DAP_TRANSFER_MATCH_VALUE (1U<<4) -#define DAP_TRANSFER_MATCH_MASK (1U<<5) -#define DAP_TRANSFER_TIMESTAMP (1U<<7) - -// DAP Transfer Response -#define DAP_TRANSFER_OK (1U<<0) -#define DAP_TRANSFER_WAIT (1U<<1) -#define DAP_TRANSFER_FAULT (1U<<2) -#define DAP_TRANSFER_ERROR (1U<<3) -#define DAP_TRANSFER_MISMATCH (1U<<4) - -// DAP SWO Trace Mode -#define DAP_SWO_OFF 0U -#define DAP_SWO_UART 1U -#define DAP_SWO_MANCHESTER 2U - -// DAP SWO Trace Status -#define DAP_SWO_CAPTURE_ACTIVE (1U<<0) -#define DAP_SWO_CAPTURE_PAUSED (1U<<1) -#define DAP_SWO_STREAM_ERROR (1U<<6) -#define DAP_SWO_BUFFER_OVERRUN (1U<<7) - -// DAP UART Transport -#define DAP_UART_TRANSPORT_NONE 0U -#define DAP_UART_TRANSPORT_USB_COM_PORT 1U -#define DAP_UART_TRANSPORT_DAP_COMMAND 2U - -// DAP UART Control -#define DAP_UART_CONTROL_RX_ENABLE (1U<<0) -#define DAP_UART_CONTROL_RX_DISABLE (1U<<1) -#define DAP_UART_CONTROL_RX_BUF_FLUSH (1U<<2) -#define DAP_UART_CONTROL_TX_ENABLE (1U<<4) -#define DAP_UART_CONTROL_TX_DISABLE (1U<<5) -#define DAP_UART_CONTROL_TX_BUF_FLUSH (1U<<6) - -// DAP UART Status -#define DAP_UART_STATUS_RX_ENABLED (1U<<0) -#define DAP_UART_STATUS_RX_DATA_LOST (1U<<1) -#define DAP_UART_STATUS_FRAMING_ERROR (1U<<2) -#define DAP_UART_STATUS_PARITY_ERROR (1U<<3) -#define DAP_UART_STATUS_TX_ENABLED (1U<<4) - -// DAP UART Configure Error -#define DAP_UART_CFG_ERROR_DATA_BITS (1U<<0) -#define DAP_UART_CFG_ERROR_PARITY (1U<<1) -#define DAP_UART_CFG_ERROR_STOP_BITS (1U<<2) - -// Debug Port Register Addresses -#define DP_IDCODE 0x00U // IDCODE Register (SW Read only) -#define DP_ABORT 0x00U // Abort Register (SW Write only) -#define DP_CTRL_STAT 0x04U // Control & Status -#define DP_WCR 0x04U // Wire Control Register (SW Only) -#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W) -#define DP_RESEND 0x08U // Resend (SW Read Only) -#define DP_RDBUFF 0x0CU // Read Buffer (Read Only) - -// JTAG IR Codes -#define JTAG_ABORT 0x08U -#define JTAG_DPACC 0x0AU -#define JTAG_APACC 0x0BU -#define JTAG_IDCODE 0x0EU -#define JTAG_BYPASS 0x0FU - -// JTAG Sequence Info -#define JTAG_SEQUENCE_TCK 0x3FU // TCK count -#define JTAG_SEQUENCE_TMS 0x40U // TMS value -#define JTAG_SEQUENCE_TDO 0x80U // TDO capture - -// SWD Sequence Info -#define SWD_SEQUENCE_CLK 0x3FU // SWCLK count -#define SWD_SEQUENCE_DIN 0x80U // SWDIO capture - - -#include -#include -#include "cmsis_compiler.h" - -// DAP Data structure -typedef struct { - uint8_t debug_port; // Debug Port - uint8_t fast_clock; // Fast Clock Flag - uint8_t padding[2]; - uint32_t clock_delay; // Clock Delay - uint32_t timestamp; // Last captured Timestamp - struct { // Transfer Configuration - uint8_t idle_cycles; // Idle cycles after transfer - uint8_t padding[3]; - uint16_t retry_count; // Number of retries after WAIT response - uint16_t match_retry; // Number of retries if read value does not match - uint32_t match_mask; // Match Mask - } transfer; -#if (DAP_SWD != 0) - struct { // SWD Configuration - uint8_t turnaround; // Turnaround period - uint8_t data_phase; // Always generate Data Phase - } swd_conf; -#endif -#if (DAP_JTAG != 0) - struct { // JTAG Device Chain - uint8_t count; // Number of devices - uint8_t index; // Device index (device at TDO has index 0) -#if (DAP_JTAG_DEV_CNT != 0) - uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits - uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR - uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR -#endif - } jtag_dev; -#endif -} DAP_Data_t; - -extern DAP_Data_t DAP_Data; // DAP Data -extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag - - -#ifdef __cplusplus -extern "C" -{ -#endif - -// Functions -extern void SWJ_Sequence (uint32_t count, const uint8_t *data); -extern void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi); -extern void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo); -extern void JTAG_IR (uint32_t ir); -extern uint32_t JTAG_ReadIDCode (void); -extern void JTAG_WriteAbort (uint32_t data); -extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data); -extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data); - -extern void Delayms (uint32_t delay); - -extern uint32_t SWO_Transport (const uint8_t *request, uint8_t *response); -extern uint32_t SWO_Mode (const uint8_t *request, uint8_t *response); -extern uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response); -extern uint32_t SWO_Control (const uint8_t *request, uint8_t *response); -extern uint32_t SWO_Status (uint8_t *response); -extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response); -extern uint32_t SWO_Data (const uint8_t *request, uint8_t *response); - -extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num); -extern void SWO_AbortTransfer (void); -extern void SWO_TransferComplete (void); - -extern uint32_t SWO_Mode_UART (uint32_t enable); -extern uint32_t SWO_Baudrate_UART (uint32_t baudrate); -extern uint32_t SWO_Control_UART (uint32_t active); -extern void SWO_Capture_UART (uint8_t *buf, uint32_t num); -extern uint32_t SWO_GetCount_UART (void); - -extern uint32_t SWO_Mode_Manchester (uint32_t enable); -extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate); -extern uint32_t SWO_Control_Manchester (uint32_t active); -extern void SWO_Capture_Manchester (uint8_t *buf, uint32_t num); -extern uint32_t SWO_GetCount_Manchester (void); - -extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response); -extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response); -extern uint32_t UART_Control (const uint8_t *request, uint8_t *response); -extern uint32_t UART_Status (uint8_t *response); -extern uint32_t UART_Transfer (const uint8_t *request, uint8_t *response); - -extern uint8_t USB_COM_PORT_Activate (uint32_t cmd); - -extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response); -extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response); -extern uint32_t DAP_ExecuteCommand (const uint8_t *request, uint8_t *response); - -extern void DAP_Setup (void); - -// Configurable delay for clock generation -#ifndef DELAY_SLOW_CYCLES -#define DELAY_SLOW_CYCLES 3U // Number of cycles for one iteration -#endif -#if defined(__CC_ARM) -__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) { - uint32_t count = delay; - while (--count); -} -#else -__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) { - __ASM volatile ( - ".syntax unified\n" - "0:\n\t" - "subs %0,%0,#1\n\t" - "bne 0b\n" - : "+l" (delay) : : "cc" - ); -} -#endif - -// Fixed delay for fast clock generation -#ifndef DELAY_FAST_CYCLES -#define DELAY_FAST_CYCLES 0U // Number of cycles: 0..3 -#endif -__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) { -#if (DELAY_FAST_CYCLES >= 1U) - __NOP(); -#endif -#if (DELAY_FAST_CYCLES >= 2U) - __NOP(); -#endif -#if (DELAY_FAST_CYCLES >= 3U) - __NOP(); -#endif -} - -#ifdef __cplusplus -} -#endif - - -#endif /* __DAP_H__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP.c deleted file mode 100644 index 0e4f319..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP.c +++ /dev/null @@ -1,1816 +0,0 @@ -/* - * Copyright (c) 2013-2022 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 5. December 2022 - * $Revision: V2.1.2 - * - * Project: CMSIS-DAP Source - * Title: DAP.c CMSIS-DAP Commands - * - *---------------------------------------------------------------------------*/ - -#include -#include "DAP_config.h" -#include "DAP.h" - - -#if (DAP_PACKET_SIZE < 64U) -#error "Minimum Packet Size is 64!" -#endif -#if (DAP_PACKET_SIZE > 32768U) -#error "Maximum Packet Size is 32768!" -#endif -#if (DAP_PACKET_COUNT < 1U) -#error "Minimum Packet Count is 1!" -#endif -#if (DAP_PACKET_COUNT > 255U) -#error "Maximum Packet Count is 255!" -#endif - - -// Clock Macros -#define MAX_SWJ_CLOCK(delay_cycles) \ - ((CPU_CLOCK/2U) / (IO_PORT_WRITE_CYCLES + delay_cycles)) - - - DAP_Data_t DAP_Data; // DAP Data -volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag - - -static const char DAP_FW_Ver [] = DAP_FW_VER; - - -// Common clock delay calculation routine -// clock: requested SWJ frequency in Hertz -static void Set_Clock_Delay(uint32_t clock) { - uint32_t delay; - - if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { - DAP_Data.fast_clock = 1U; - DAP_Data.clock_delay = 1U; - } else { - DAP_Data.fast_clock = 0U; - - delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock; - if (delay > IO_PORT_WRITE_CYCLES) { - delay -= IO_PORT_WRITE_CYCLES; - delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; - } else { - delay = 1U; - } - - DAP_Data.clock_delay = delay; - } -} - - -// Get DAP Information -// id: info identifier -// info: pointer to info data -// return: number of bytes in info data -static uint8_t DAP_Info(uint8_t id, uint8_t *info) { - uint8_t length = 0U; - - switch (id) { - case DAP_ID_VENDOR: - length = DAP_GetVendorString((char *)info); - break; - case DAP_ID_PRODUCT: - length = DAP_GetProductString((char *)info); - break; - case DAP_ID_SER_NUM: - length = DAP_GetSerNumString((char *)info); - break; - case DAP_ID_DAP_FW_VER: - length = (uint8_t)sizeof(DAP_FW_Ver); - memcpy(info, DAP_FW_Ver, length); - break; - case DAP_ID_DEVICE_VENDOR: - length = DAP_GetTargetDeviceVendorString((char *)info); - break; - case DAP_ID_DEVICE_NAME: - length = DAP_GetTargetDeviceNameString((char *)info); - break; - case DAP_ID_BOARD_VENDOR: - length = DAP_GetTargetBoardVendorString((char *)info); - break; - case DAP_ID_BOARD_NAME: - length = DAP_GetTargetBoardNameString((char *)info); - break; - case DAP_ID_PRODUCT_FW_VER: - length = DAP_GetProductFirmwareVersionString((char *)info); - break; - case DAP_ID_CAPABILITIES: - info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) | - ((DAP_JTAG != 0) ? (1U << 1) : 0U) | - ((SWO_UART != 0) ? (1U << 2) : 0U) | - ((SWO_MANCHESTER != 0) ? (1U << 3) : 0U) | - /* Atomic Commands */ (1U << 4) | - ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) | - ((SWO_STREAM != 0U) ? (1U << 6) : 0U) | - ((DAP_UART != 0U) ? (1U << 7) : 0U); - - info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U); - length = 2U; - break; - case DAP_ID_TIMESTAMP_CLOCK: -#if (TIMESTAMP_CLOCK != 0U) - info[0] = (uint8_t)(TIMESTAMP_CLOCK >> 0); - info[1] = (uint8_t)(TIMESTAMP_CLOCK >> 8); - info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16); - info[3] = (uint8_t)(TIMESTAMP_CLOCK >> 24); - length = 4U; -#endif - break; - case DAP_ID_UART_RX_BUFFER_SIZE: -#if (DAP_UART != 0) - info[0] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 0); - info[1] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 8); - info[2] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 16); - info[3] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 24); - length = 4U; -#endif - break; - case DAP_ID_UART_TX_BUFFER_SIZE: -#if (DAP_UART != 0) - info[0] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 0); - info[1] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 8); - info[2] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 16); - info[3] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 24); - length = 4U; -#endif - break; - case DAP_ID_SWO_BUFFER_SIZE: -#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) - info[0] = (uint8_t)(SWO_BUFFER_SIZE >> 0); - info[1] = (uint8_t)(SWO_BUFFER_SIZE >> 8); - info[2] = (uint8_t)(SWO_BUFFER_SIZE >> 16); - info[3] = (uint8_t)(SWO_BUFFER_SIZE >> 24); - length = 4U; -#endif - break; - case DAP_ID_PACKET_SIZE: - info[0] = (uint8_t)(DAP_PACKET_SIZE >> 0); - info[1] = (uint8_t)(DAP_PACKET_SIZE >> 8); - length = 2U; - break; - case DAP_ID_PACKET_COUNT: - info[0] = DAP_PACKET_COUNT; - length = 1U; - break; - default: - break; - } - - return (length); -} - - -// Delay for specified time -// delay: delay time in ms -void Delayms(uint32_t delay) { - delay *= ((CPU_CLOCK/1000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; - PIN_DELAY_SLOW(delay); -} - - -// Process Delay command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_Delay(const uint8_t *request, uint8_t *response) { - uint32_t delay; - - delay = (uint32_t)(*(request+0)) | - (uint32_t)(*(request+1) << 8); - delay *= ((CPU_CLOCK/1000000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; - - PIN_DELAY_SLOW(delay); - - *response = DAP_OK; - return ((2U << 16) | 1U); -} - - -// Process Host Status command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_HostStatus(const uint8_t *request, uint8_t *response) { - - switch (*request) { - case DAP_DEBUGGER_CONNECTED: - LED_CONNECTED_OUT((*(request+1) & 1U)); - break; - case DAP_TARGET_RUNNING: - LED_RUNNING_OUT((*(request+1) & 1U)); - break; - default: - *response = DAP_ERROR; - return ((2U << 16) | 1U); - } - - *response = DAP_OK; - return ((2U << 16) | 1U); -} - - -// Process Connect command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_Connect(const uint8_t *request, uint8_t *response) { - uint32_t port; - - if (*request == DAP_PORT_AUTODETECT) { - port = DAP_DEFAULT_PORT; - } else { - port = *request; - } - - switch (port) { -#if (DAP_SWD != 0) - case DAP_PORT_SWD: - DAP_Data.debug_port = DAP_PORT_SWD; - PORT_SWD_SETUP(); - break; -#endif -#if (DAP_JTAG != 0) - case DAP_PORT_JTAG: - DAP_Data.debug_port = DAP_PORT_JTAG; - PORT_JTAG_SETUP(); - break; -#endif - default: - port = DAP_PORT_DISABLED; - break; - } - - *response = (uint8_t)port; - return ((1U << 16) | 1U); -} - - -// Process Disconnect command and prepare response -// response: pointer to response data -// return: number of bytes in response -static uint32_t DAP_Disconnect(uint8_t *response) { - - DAP_Data.debug_port = DAP_PORT_DISABLED; - PORT_OFF(); - - *response = DAP_OK; - return (1U); -} - - -// Process Reset Target command and prepare response -// response: pointer to response data -// return: number of bytes in response -static uint32_t DAP_ResetTarget(uint8_t *response) { - - *(response+1) = RESET_TARGET(); - *(response+0) = DAP_OK; - return (2U); -} - - -// Process SWJ Pins command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) { -#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) - uint32_t value; - uint32_t select; - uint32_t wait; - uint32_t timestamp; - - value = (uint32_t) *(request+0); - select = (uint32_t) *(request+1); - wait = (uint32_t)(*(request+2) << 0) | - (uint32_t)(*(request+3) << 8) | - (uint32_t)(*(request+4) << 16) | - (uint32_t)(*(request+5) << 24); - - if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { - if ((value & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { - PIN_SWCLK_TCK_SET(); - } else { - PIN_SWCLK_TCK_CLR(); - } - } - if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { - if ((value & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { - PIN_SWDIO_TMS_SET(); - } else { - PIN_SWDIO_TMS_CLR(); - } - } - if ((select & (1U << DAP_SWJ_TDI)) != 0U) { - PIN_TDI_OUT(value >> DAP_SWJ_TDI); - } - if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { - PIN_nTRST_OUT(value >> DAP_SWJ_nTRST); - } - if ((select & (1U << DAP_SWJ_nRESET)) != 0U){ - PIN_nRESET_OUT(value >> DAP_SWJ_nRESET); - } - - if (wait != 0U) { -#if (TIMESTAMP_CLOCK != 0U) - if (wait > 3000000U) { - wait = 3000000U; - } -#if (TIMESTAMP_CLOCK >= 1000000U) - wait *= TIMESTAMP_CLOCK / 1000000U; -#else - wait /= 1000000U / TIMESTAMP_CLOCK; -#endif -#else - wait = 1U; -#endif - timestamp = TIMESTAMP_GET(); - do { - if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { - if ((value >> DAP_SWJ_SWCLK_TCK) ^ PIN_SWCLK_TCK_IN()) { - continue; - } - } - if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { - if ((value >> DAP_SWJ_SWDIO_TMS) ^ PIN_SWDIO_TMS_IN()) { - continue; - } - } - if ((select & (1U << DAP_SWJ_TDI)) != 0U) { - if ((value >> DAP_SWJ_TDI) ^ PIN_TDI_IN()) { - continue; - } - } - if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { - if ((value >> DAP_SWJ_nTRST) ^ PIN_nTRST_IN()) { - continue; - } - } - if ((select & (1U << DAP_SWJ_nRESET)) != 0U) { - if ((value >> DAP_SWJ_nRESET) ^ PIN_nRESET_IN()) { - continue; - } - } - break; - } while ((TIMESTAMP_GET() - timestamp) < wait); - } - - value = (PIN_SWCLK_TCK_IN() << DAP_SWJ_SWCLK_TCK) | - (PIN_SWDIO_TMS_IN() << DAP_SWJ_SWDIO_TMS) | - (PIN_TDI_IN() << DAP_SWJ_TDI) | - (PIN_TDO_IN() << DAP_SWJ_TDO) | - (PIN_nTRST_IN() << DAP_SWJ_nTRST) | - (PIN_nRESET_IN() << DAP_SWJ_nRESET); - - *response = (uint8_t)value; -#else - *response = 0U; -#endif - - return ((6U << 16) | 1U); -} - - -// Process SWJ Clock command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) { -#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) - uint32_t clock; - uint32_t delay; - - clock = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - - if (clock == 0U) { - *response = DAP_ERROR; - return ((4U << 16) | 1U); - } - - Set_Clock_Delay(clock); - - *response = DAP_OK; -#else - *response = DAP_ERROR; -#endif - - return ((4U << 16) | 1U); -} - - -// Process SWJ Sequence command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_SWJ_Sequence(const uint8_t *request, uint8_t *response) { - uint32_t count; - - count = *request++; - if (count == 0U) { - count = 256U; - } - -#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) - SWJ_Sequence(count, request); - *response = DAP_OK; -#else - *response = DAP_ERROR; -#endif - - count = (count + 7U) >> 3; - - return (((count + 1U) << 16) | 1U); -} - - -// Process SWD Configure command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_SWD_Configure(const uint8_t *request, uint8_t *response) { -#if (DAP_SWD != 0) - uint8_t value; - - value = *request; - DAP_Data.swd_conf.turnaround = (value & 0x03U) + 1U; - DAP_Data.swd_conf.data_phase = (value & 0x04U) ? 1U : 0U; - - *response = DAP_OK; -#else - *response = DAP_ERROR; -#endif - - return ((1U << 16) | 1U); -} - - -// Process SWD Sequence command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_SWD_Sequence(const uint8_t *request, uint8_t *response) { - uint32_t sequence_info; - uint32_t sequence_count; - uint32_t request_count; - uint32_t response_count; - uint32_t count; - -#if (DAP_SWD != 0) - *response++ = DAP_OK; -#else - *response++ = DAP_ERROR; -#endif - request_count = 1U; - response_count = 1U; - - sequence_count = *request++; - while (sequence_count--) { - sequence_info = *request++; - count = sequence_info & SWD_SEQUENCE_CLK; - if (count == 0U) { - count = 64U; - } - count = (count + 7U) / 8U; -#if (DAP_SWD != 0) - if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { - PIN_SWDIO_OUT_DISABLE(); - } else { - PIN_SWDIO_OUT_ENABLE(); - } - SWD_Sequence(sequence_info, request, response); - if (sequence_count == 0U) { - PIN_SWDIO_OUT_ENABLE(); - } -#endif - if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { - request_count++; -#if (DAP_SWD != 0) - response += count; - response_count += count; -#endif - } else { - request += count; - request_count += count + 1U; - } - } - - return ((request_count << 16) | response_count); -} - - -// Process JTAG Sequence command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_JTAG_Sequence(const uint8_t *request, uint8_t *response) { - uint32_t sequence_info; - uint32_t sequence_count; - uint32_t request_count; - uint32_t response_count; - uint32_t count; - -#if (DAP_JTAG != 0) - *response++ = DAP_OK; -#else - *response++ = DAP_ERROR; -#endif - request_count = 1U; - response_count = 1U; - - sequence_count = *request++; - while (sequence_count--) { - sequence_info = *request++; - count = sequence_info & JTAG_SEQUENCE_TCK; - if (count == 0U) { - count = 64U; - } - count = (count + 7U) / 8U; -#if (DAP_JTAG != 0) - JTAG_Sequence(sequence_info, request, response); -#endif - request += count; - request_count += count + 1U; -#if (DAP_JTAG != 0) - if ((sequence_info & JTAG_SEQUENCE_TDO) != 0U) { - response += count; - response_count += count; - } -#endif - } - - return ((request_count << 16) | response_count); -} - - -// Process JTAG Configure command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_JTAG_Configure(const uint8_t *request, uint8_t *response) { - uint32_t count; -#if (DAP_JTAG != 0) - uint32_t length; - uint32_t bits; - uint32_t n; - - count = *request++; - DAP_Data.jtag_dev.count = (uint8_t)count; - - bits = 0U; - for (n = 0U; n < count; n++) { - length = *request++; - DAP_Data.jtag_dev.ir_length[n] = (uint8_t)length; - DAP_Data.jtag_dev.ir_before[n] = (uint16_t)bits; - bits += length; - } - for (n = 0U; n < count; n++) { - bits -= DAP_Data.jtag_dev.ir_length[n]; - DAP_Data.jtag_dev.ir_after[n] = (uint16_t)bits; - } - - *response = DAP_OK; -#else - count = *request; - *response = DAP_ERROR; -#endif - - return (((count + 1U) << 16) | 1U); -} - - -// Process JTAG IDCODE command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_JTAG_IDCode(const uint8_t *request, uint8_t *response) { -#if (DAP_JTAG != 0) - uint32_t data; - - if (DAP_Data.debug_port != DAP_PORT_JTAG) { - goto id_error; - } - - // Device index (JTAP TAP) - DAP_Data.jtag_dev.index = *request; - if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { - goto id_error; - } - - // Select JTAG chain - JTAG_IR(JTAG_IDCODE); - - // Read IDCODE register - data = JTAG_ReadIDCode(); - - // Store Data - *(response+0) = DAP_OK; - *(response+1) = (uint8_t)(data >> 0); - *(response+2) = (uint8_t)(data >> 8); - *(response+3) = (uint8_t)(data >> 16); - *(response+4) = (uint8_t)(data >> 24); - - return ((1U << 16) | 5U); - -id_error: -#endif - *response = DAP_ERROR; - return ((1U << 16) | 1U); -} - - -// Process Transfer Configure command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_TransferConfigure(const uint8_t *request, uint8_t *response) { - - DAP_Data.transfer.idle_cycles = *(request+0); - DAP_Data.transfer.retry_count = (uint16_t) *(request+1) | - (uint16_t)(*(request+2) << 8); - DAP_Data.transfer.match_retry = (uint16_t) *(request+3) | - (uint16_t)(*(request+4) << 8); - - *response = DAP_OK; - return ((5U << 16) | 1U); -} - - -// Process SWD Transfer command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -#if (DAP_SWD != 0) -static uint32_t DAP_SWD_Transfer(const uint8_t *request, uint8_t *response) { - const - uint8_t *request_head; - uint32_t request_count; - uint32_t request_value; - uint8_t *response_head; - uint32_t response_count; - uint32_t response_value; - uint32_t post_read; - uint32_t check_write; - uint32_t match_value; - uint32_t match_retry; - uint32_t retry; - uint32_t data; -#if (TIMESTAMP_CLOCK != 0U) - uint32_t timestamp; -#endif - - request_head = request; - - response_count = 0U; - response_value = 0U; - response_head = response; - response += 2; - - DAP_TransferAbort = 0U; - - post_read = 0U; - check_write = 0U; - - request++; // Ignore DAP index - - request_count = *request++; - - while (request_count != 0) { - request_count--; - request_value = *request++; - if ((request_value & DAP_TRANSFER_RnW) != 0U) { - // Read register - if (post_read) { - // Read was posted before - retry = DAP_Data.transfer.retry_count; - if ((request_value & (DAP_TRANSFER_APnDP | DAP_TRANSFER_MATCH_VALUE)) == DAP_TRANSFER_APnDP) { - // Read previous AP data and post next AP read - do { - response_value = SWD_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - } else { - // Read previous AP data - do { - response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - post_read = 0U; - } - if (response_value != DAP_TRANSFER_OK) { - break; - } - // Store previous AP data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); -#if (TIMESTAMP_CLOCK != 0U) - if (post_read) { - // Store Timestamp of next AP read - if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { - timestamp = DAP_Data.timestamp; - *response++ = (uint8_t) timestamp; - *response++ = (uint8_t)(timestamp >> 8); - *response++ = (uint8_t)(timestamp >> 16); - *response++ = (uint8_t)(timestamp >> 24); - } - } -#endif - } - if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { - // Read with value match - match_value = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - request += 4; - match_retry = DAP_Data.transfer.match_retry; - if ((request_value & DAP_TRANSFER_APnDP) != 0U) { - // Post AP read - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(request_value, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } - } - do { - // Read register until its value matches or retry counter expires - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } - } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); - if ((data & DAP_Data.transfer.match_mask) != match_value) { - response_value |= DAP_TRANSFER_MISMATCH; - } - if (response_value != DAP_TRANSFER_OK) { - break; - } - } else { - // Normal read - retry = DAP_Data.transfer.retry_count; - if ((request_value & DAP_TRANSFER_APnDP) != 0U) { - // Read AP register - if (post_read == 0U) { - // Post AP read - do { - response_value = SWD_Transfer(request_value, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } -#if (TIMESTAMP_CLOCK != 0U) - // Store Timestamp - if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { - timestamp = DAP_Data.timestamp; - *response++ = (uint8_t) timestamp; - *response++ = (uint8_t)(timestamp >> 8); - *response++ = (uint8_t)(timestamp >> 16); - *response++ = (uint8_t)(timestamp >> 24); - } -#endif - post_read = 1U; - } - } else { - // Read DP register - do { - response_value = SWD_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } -#if (TIMESTAMP_CLOCK != 0U) - // Store Timestamp - if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { - timestamp = DAP_Data.timestamp; - *response++ = (uint8_t) timestamp; - *response++ = (uint8_t)(timestamp >> 8); - *response++ = (uint8_t)(timestamp >> 16); - *response++ = (uint8_t)(timestamp >> 24); - } -#endif - // Store data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); - } - } - check_write = 0U; - } else { - // Write register - if (post_read) { - // Read previous data - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } - // Store previous data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); - post_read = 0U; - } - // Load data - data = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - request += 4; - if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { - // Write match mask - DAP_Data.transfer.match_mask = data; - response_value = DAP_TRANSFER_OK; - } else { - // Write DP/AP register - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } -#if (TIMESTAMP_CLOCK != 0U) - // Store Timestamp - if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { - timestamp = DAP_Data.timestamp; - *response++ = (uint8_t) timestamp; - *response++ = (uint8_t)(timestamp >> 8); - *response++ = (uint8_t)(timestamp >> 16); - *response++ = (uint8_t)(timestamp >> 24); - } -#endif - check_write = 1U; - } - } - response_count++; - if (DAP_TransferAbort) { - break; - } - } - - while (request_count != 0) { - // Process canceled requests - request_count--; - request_value = *request++; - if ((request_value & DAP_TRANSFER_RnW) != 0U) { - // Read register - if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { - // Read with value match - request += 4; - } - } else { - // Write register - request += 4; - } - } - - if (response_value == DAP_TRANSFER_OK) { - if (post_read) { - // Read previous data - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - // Store previous data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); - } else if (check_write) { - // Check last write - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - } - } - -end: - *(response_head+0) = (uint8_t)response_count; - *(response_head+1) = (uint8_t)response_value; - - return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); -} -#endif - - -// Process JTAG Transfer command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -#if (DAP_JTAG != 0) -static uint32_t DAP_JTAG_Transfer(const uint8_t *request, uint8_t *response) { - const - uint8_t *request_head; - uint32_t request_count; - uint32_t request_value; - uint32_t request_ir; - uint8_t *response_head; - uint32_t response_count; - uint32_t response_value; - uint32_t post_read; - uint32_t match_value; - uint32_t match_retry; - uint32_t retry; - uint32_t data; - uint32_t ir; -#if (TIMESTAMP_CLOCK != 0U) - uint32_t timestamp; -#endif - - request_head = request; - - response_count = 0U; - response_value = 0U; - response_head = response; - response += 2; - - DAP_TransferAbort = 0U; - - ir = 0U; - post_read = 0U; - - // Device index (JTAP TAP) - DAP_Data.jtag_dev.index = *request++; - if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { - goto end; - } - - request_count = *request++; - - while (request_count != 0) { - request_count--; - request_value = *request++; - request_ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; - if ((request_value & DAP_TRANSFER_RnW) != 0U) { - // Read register - if (post_read) { - // Read was posted before - retry = DAP_Data.transfer.retry_count; - if ((ir == request_ir) && ((request_value & DAP_TRANSFER_MATCH_VALUE) == 0U)) { - // Read previous data and post next read - do { - response_value = JTAG_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - } else { - // Select JTAG chain - if (ir != JTAG_DPACC) { - ir = JTAG_DPACC; - JTAG_IR(ir); - } - // Read previous data - do { - response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - post_read = 0U; - } - if (response_value != DAP_TRANSFER_OK) { - break; - } - // Store previous data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); -#if (TIMESTAMP_CLOCK != 0U) - if (post_read) { - // Store Timestamp of next AP read - if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { - timestamp = DAP_Data.timestamp; - *response++ = (uint8_t) timestamp; - *response++ = (uint8_t)(timestamp >> 8); - *response++ = (uint8_t)(timestamp >> 16); - *response++ = (uint8_t)(timestamp >> 24); - } - } -#endif - } - if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { - // Read with value match - match_value = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - request += 4; - match_retry = DAP_Data.transfer.match_retry; - // Select JTAG chain - if (ir != request_ir) { - ir = request_ir; - JTAG_IR(ir); - } - // Post DP/AP read - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(request_value, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } - do { - // Read register until its value matches or retry counter expires - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } - } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); - if ((data & DAP_Data.transfer.match_mask) != match_value) { - response_value |= DAP_TRANSFER_MISMATCH; - } - if (response_value != DAP_TRANSFER_OK) { - break; - } - } else { - // Normal read - if (post_read == 0U) { - // Select JTAG chain - if (ir != request_ir) { - ir = request_ir; - JTAG_IR(ir); - } - // Post DP/AP read - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(request_value, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } -#if (TIMESTAMP_CLOCK != 0U) - // Store Timestamp - if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { - timestamp = DAP_Data.timestamp; - *response++ = (uint8_t) timestamp; - *response++ = (uint8_t)(timestamp >> 8); - *response++ = (uint8_t)(timestamp >> 16); - *response++ = (uint8_t)(timestamp >> 24); - } -#endif - post_read = 1U; - } - } - } else { - // Write register - if (post_read) { - // Select JTAG chain - if (ir != JTAG_DPACC) { - ir = JTAG_DPACC; - JTAG_IR(ir); - } - // Read previous data - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } - // Store previous data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); - post_read = 0U; - } - // Load data - data = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - request += 4; - if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { - // Write match mask - DAP_Data.transfer.match_mask = data; - response_value = DAP_TRANSFER_OK; - } else { - // Select JTAG chain - if (ir != request_ir) { - ir = request_ir; - JTAG_IR(ir); - } - // Write DP/AP register - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - break; - } -#if (TIMESTAMP_CLOCK != 0U) - // Store Timestamp - if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { - timestamp = DAP_Data.timestamp; - *response++ = (uint8_t) timestamp; - *response++ = (uint8_t)(timestamp >> 8); - *response++ = (uint8_t)(timestamp >> 16); - *response++ = (uint8_t)(timestamp >> 24); - } -#endif - } - } - response_count++; - if (DAP_TransferAbort) { - break; - } - } - - while (request_count != 0) { - // Process canceled requests - request_count--; - request_value = *request++; - if ((request_value & DAP_TRANSFER_RnW) != 0U) { - // Read register - if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { - // Read with value match - request += 4; - } - } else { - // Write register - request += 4; - } - } - - if (response_value == DAP_TRANSFER_OK) { - // Select JTAG chain - if (ir != JTAG_DPACC) { - ir = JTAG_DPACC; - JTAG_IR(ir); - } - if (post_read) { - // Read previous data - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - // Store previous data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); - } else { - // Check last write - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - } - } - -end: - *(response_head+0) = (uint8_t)response_count; - *(response_head+1) = (uint8_t)response_value; - - return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); -} -#endif - - -// Process Dummy Transfer command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_Dummy_Transfer(const uint8_t *request, uint8_t *response) { - const - uint8_t *request_head; - uint32_t request_count; - uint32_t request_value; - - request_head = request; - - request++; // Ignore DAP index - - request_count = *request++; - - for (; request_count != 0U; request_count--) { - // Process dummy requests - request_value = *request++; - if ((request_value & DAP_TRANSFER_RnW) != 0U) { - // Read register - if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { - // Read with value match - request += 4; - } - } else { - // Write register - request += 4; - } - } - - *(response+0) = 0U; // Response count - *(response+1) = 0U; // Response value - - return (((uint32_t)(request - request_head) << 16) | 2U); -} - - -// Process Transfer command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_Transfer(const uint8_t *request, uint8_t *response) { - uint32_t num; - - switch (DAP_Data.debug_port) { -#if (DAP_SWD != 0) - case DAP_PORT_SWD: - num = DAP_SWD_Transfer(request, response); - break; -#endif -#if (DAP_JTAG != 0) - case DAP_PORT_JTAG: - num = DAP_JTAG_Transfer(request, response); - break; -#endif - default: - num = DAP_Dummy_Transfer(request, response); - break; - } - - return (num); -} - - -// Process SWD Transfer Block command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response -#if (DAP_SWD != 0) -static uint32_t DAP_SWD_TransferBlock(const uint8_t *request, uint8_t *response) { - uint32_t request_count; - uint32_t request_value; - uint32_t response_count; - uint32_t response_value; - uint8_t *response_head; - uint32_t retry; - uint32_t data; - - response_count = 0U; - response_value = 0U; - response_head = response; - response += 3; - - DAP_TransferAbort = 0U; - - request++; // Ignore DAP index - - request_count = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8); - request += 2; - if (request_count == 0U) { - goto end; - } - - request_value = *request++; - if ((request_value & DAP_TRANSFER_RnW) != 0U) { - // Read register block - if ((request_value & DAP_TRANSFER_APnDP) != 0U) { - // Post AP read - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(request_value, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - } - while (request_count--) { - // Read DP/AP register - if ((request_count == 0U) && ((request_value & DAP_TRANSFER_APnDP) != 0U)) { - // Last AP read - request_value = DP_RDBUFF | DAP_TRANSFER_RnW; - } - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - // Store data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); - response_count++; - } - } else { - // Write register block - while (request_count--) { - // Load data - data = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - request += 4; - // Write DP/AP register - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - response_count++; - } - // Check last write - retry = DAP_Data.transfer.retry_count; - do { - response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - } - -end: - *(response_head+0) = (uint8_t)(response_count >> 0); - *(response_head+1) = (uint8_t)(response_count >> 8); - *(response_head+2) = (uint8_t) response_value; - - return ((uint32_t)(response - response_head)); -} -#endif - - -// Process JTAG Transfer Block command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response -#if (DAP_JTAG != 0) -static uint32_t DAP_JTAG_TransferBlock(const uint8_t *request, uint8_t *response) { - uint32_t request_count; - uint32_t request_value; - uint32_t response_count; - uint32_t response_value; - uint8_t *response_head; - uint32_t retry; - uint32_t data; - uint32_t ir; - - response_count = 0U; - response_value = 0U; - response_head = response; - response += 3; - - DAP_TransferAbort = 0U; - - // Device index (JTAP TAP) - DAP_Data.jtag_dev.index = *request++; - if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { - goto end; - } - - request_count = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8); - request += 2; - if (request_count == 0U) { - goto end; - } - - request_value = *request++; - - // Select JTAG chain - ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; - JTAG_IR(ir); - - if ((request_value & DAP_TRANSFER_RnW) != 0U) { - // Post read - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(request_value, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - // Read register block - while (request_count--) { - // Read DP/AP register - if (request_count == 0U) { - // Last read - if (ir != JTAG_DPACC) { - JTAG_IR(JTAG_DPACC); - } - request_value = DP_RDBUFF | DAP_TRANSFER_RnW; - } - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - // Store data - *response++ = (uint8_t) data; - *response++ = (uint8_t)(data >> 8); - *response++ = (uint8_t)(data >> 16); - *response++ = (uint8_t)(data >> 24); - response_count++; - } - } else { - // Write register block - while (request_count--) { - // Load data - data = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - request += 4; - // Write DP/AP register - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(request_value, &data); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - if (response_value != DAP_TRANSFER_OK) { - goto end; - } - response_count++; - } - // Check last write - if (ir != JTAG_DPACC) { - JTAG_IR(JTAG_DPACC); - } - retry = DAP_Data.transfer.retry_count; - do { - response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); - } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); - } - -end: - *(response_head+0) = (uint8_t)(response_count >> 0); - *(response_head+1) = (uint8_t)(response_count >> 8); - *(response_head+2) = (uint8_t) response_value; - - return ((uint32_t)(response - response_head)); -} -#endif - - -// Process Transfer Block command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_TransferBlock(const uint8_t *request, uint8_t *response) { - uint32_t num; - - switch (DAP_Data.debug_port) { -#if (DAP_SWD != 0) - case DAP_PORT_SWD: - num = DAP_SWD_TransferBlock (request, response); - break; -#endif -#if (DAP_JTAG != 0) - case DAP_PORT_JTAG: - num = DAP_JTAG_TransferBlock(request, response); - break; -#endif - default: - *(response+0) = 0U; // Response count [7:0] - *(response+1) = 0U; // Response count[15:8] - *(response+2) = 0U; // Response value - num = 3U; - break; - } - - if ((*(request+3) & DAP_TRANSFER_RnW) != 0U) { - // Read register block - num |= 4U << 16; - } else { - // Write register block - num |= (4U + (((uint32_t)(*(request+1)) | (uint32_t)(*(request+2) << 8)) * 4)) << 16; - } - - return (num); -} - - -// Process SWD Write ABORT command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response -#if (DAP_SWD != 0) -static uint32_t DAP_SWD_WriteAbort(const uint8_t *request, uint8_t *response) { - uint32_t data; - - // Load data (Ignore DAP index) - data = (uint32_t)(*(request+1) << 0) | - (uint32_t)(*(request+2) << 8) | - (uint32_t)(*(request+3) << 16) | - (uint32_t)(*(request+4) << 24); - - // Write Abort register - SWD_Transfer(DP_ABORT, &data); - - *response = DAP_OK; - return (1U); -} -#endif - - -// Process JTAG Write ABORT command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response -#if (DAP_JTAG != 0) -static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) { - uint32_t data; - - // Device index (JTAP TAP) - DAP_Data.jtag_dev.index = *request; - if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { - *response = DAP_ERROR; - return (1U); - } - - // Select JTAG chain - JTAG_IR(JTAG_ABORT); - - // Load data - data = (uint32_t)(*(request+1) << 0) | - (uint32_t)(*(request+2) << 8) | - (uint32_t)(*(request+3) << 16) | - (uint32_t)(*(request+4) << 24); - - // Write Abort register - JTAG_WriteAbort(data); - - *response = DAP_OK; - return (1U); -} -#endif - - -// Process Write ABORT command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -static uint32_t DAP_WriteAbort(const uint8_t *request, uint8_t *response) { - uint32_t num; - - switch (DAP_Data.debug_port) { -#if (DAP_SWD != 0) - case DAP_PORT_SWD: - num = DAP_SWD_WriteAbort (request, response); - break; -#endif -#if (DAP_JTAG != 0) - case DAP_PORT_JTAG: - num = DAP_JTAG_WriteAbort(request, response); - break; -#endif - default: - *response = DAP_ERROR; - num = 1U; - break; - } - return ((5U << 16) | num); -} - - -// Process DAP Vendor command request and prepare response -// Default function (can be overridden) -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -__WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { - (void)request; - *response = ID_DAP_Invalid; - return ((1U << 16) | 1U); -} - - -// Process DAP command request and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) { - uint32_t num; - - if ((*request >= ID_DAP_Vendor0) && (*request <= ID_DAP_Vendor31)) { - return DAP_ProcessVendorCommand(request, response); - } - - *response++ = *request; - - switch (*request++) { - case ID_DAP_Info: - num = DAP_Info(*request, response+1); - *response = (uint8_t)num; - return ((2U << 16) + 2U + num); - - case ID_DAP_HostStatus: - num = DAP_HostStatus(request, response); - break; - - case ID_DAP_Connect: - num = DAP_Connect(request, response); - break; - case ID_DAP_Disconnect: - num = DAP_Disconnect(response); - break; - - case ID_DAP_Delay: - num = DAP_Delay(request, response); - break; - - case ID_DAP_ResetTarget: - num = DAP_ResetTarget(response); - break; - - case ID_DAP_SWJ_Pins: - num = DAP_SWJ_Pins(request, response); - break; - case ID_DAP_SWJ_Clock: - num = DAP_SWJ_Clock(request, response); - break; - case ID_DAP_SWJ_Sequence: - num = DAP_SWJ_Sequence(request, response); - break; - - case ID_DAP_SWD_Configure: - num = DAP_SWD_Configure(request, response); - break; - case ID_DAP_SWD_Sequence: - num = DAP_SWD_Sequence(request, response); - break; - - case ID_DAP_JTAG_Sequence: - num = DAP_JTAG_Sequence(request, response); - break; - case ID_DAP_JTAG_Configure: - num = DAP_JTAG_Configure(request, response); - break; - case ID_DAP_JTAG_IDCODE: - num = DAP_JTAG_IDCode(request, response); - break; - - case ID_DAP_TransferConfigure: - num = DAP_TransferConfigure(request, response); - break; - case ID_DAP_Transfer: - num = DAP_Transfer(request, response); - break; - case ID_DAP_TransferBlock: - num = DAP_TransferBlock(request, response); - break; - - case ID_DAP_WriteABORT: - num = DAP_WriteAbort(request, response); - break; - -#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) - case ID_DAP_SWO_Transport: - num = SWO_Transport(request, response); - break; - case ID_DAP_SWO_Mode: - num = SWO_Mode(request, response); - break; - case ID_DAP_SWO_Baudrate: - num = SWO_Baudrate(request, response); - break; - case ID_DAP_SWO_Control: - num = SWO_Control(request, response); - break; - case ID_DAP_SWO_Status: - num = SWO_Status(response); - break; - case ID_DAP_SWO_ExtendedStatus: - num = SWO_ExtendedStatus(request, response); - break; - case ID_DAP_SWO_Data: - num = SWO_Data(request, response); - break; -#endif - -#if (DAP_UART != 0) - case ID_DAP_UART_Transport: - num = UART_Transport(request, response); - break; - case ID_DAP_UART_Configure: - num = UART_Configure(request, response); - break; - case ID_DAP_UART_Control: - num = UART_Control(request, response); - break; - case ID_DAP_UART_Status: - num = UART_Status(response); - break; - case ID_DAP_UART_Transfer: - num = UART_Transfer(request, response); - break; -#endif - - default: - *(response-1) = ID_DAP_Invalid; - return ((1U << 16) | 1U); - } - - return ((1U << 16) + 1U + num); -} - - -// Execute DAP command (process request and prepare response) -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t DAP_ExecuteCommand(const uint8_t *request, uint8_t *response) { - uint32_t cnt, num, n; - - if (*request == ID_DAP_ExecuteCommands) { - *response++ = *request++; - cnt = *request++; - *response++ = (uint8_t)cnt; - num = (2U << 16) | 2U; - while (cnt--) { - n = DAP_ProcessCommand(request, response); - num += n; - request += (uint16_t)(n >> 16); - response += (uint16_t) n; - } - return (num); - } - - return DAP_ProcessCommand(request, response); -} - - -// Setup DAP -void DAP_Setup(void) { - - // Default settings - DAP_Data.debug_port = 0U; - DAP_Data.transfer.idle_cycles = 0U; - DAP_Data.transfer.retry_count = 100U; - DAP_Data.transfer.match_retry = 0U; - DAP_Data.transfer.match_mask = 0x00000000U; -#if (DAP_SWD != 0) - DAP_Data.swd_conf.turnaround = 1U; - DAP_Data.swd_conf.data_phase = 0U; -#endif -#if (DAP_JTAG != 0) - DAP_Data.jtag_dev.count = 0U; -#endif - - // Sets DAP_Data.fast_clock and DAP_Data.clock_delay. - Set_Clock_Delay(DAP_DEFAULT_SWJ_CLOCK); - - DAP_SETUP(); // Device specific setup -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP_vendor.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP_vendor.c deleted file mode 100644 index 4f2477a..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP_vendor.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 1. December 2017 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Source - * Title: DAP_vendor.c CMSIS-DAP Vendor Commands - * - *---------------------------------------------------------------------------*/ - -#include "DAP_config.h" -#include "DAP.h" - -//************************************************************************************************** -/** -\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands -\ingroup DAP_Vendor_gr -@{ - -The file DAP_vendor.c provides template source code for extension of a Debug Unit with -Vendor Commands. Copy this file to the project folder of the Debug Unit and add the -file to the MDK-ARM project under the file group Configuration. -*/ - -/** Process DAP Vendor Command and prepare Response Data -\param request pointer to request data -\param response pointer to response data -\return number of bytes in response (lower 16 bits) - number of bytes in request (upper 16 bits) -*/ -uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { - uint32_t num = (1U << 16) | 1U; - - *response++ = *request; // copy Command ID - - switch (*request++) { // first byte in request is Command ID - case ID_DAP_Vendor0: -#if 0 // example user command - num += 1U << 16; // increment request count - if (*request == 1U) { // when first command data byte is 1 - *response++ = 'X'; // send 'X' as response - num++; // increment response count - } -#endif - break; - - case ID_DAP_Vendor1: break; - case ID_DAP_Vendor2: break; - case ID_DAP_Vendor3: break; - case ID_DAP_Vendor4: break; - case ID_DAP_Vendor5: break; - case ID_DAP_Vendor6: break; - case ID_DAP_Vendor7: break; - case ID_DAP_Vendor8: break; - case ID_DAP_Vendor9: break; - case ID_DAP_Vendor10: break; - case ID_DAP_Vendor11: break; - case ID_DAP_Vendor12: break; - case ID_DAP_Vendor13: break; - case ID_DAP_Vendor14: break; - case ID_DAP_Vendor15: break; - case ID_DAP_Vendor16: break; - case ID_DAP_Vendor17: break; - case ID_DAP_Vendor18: break; - case ID_DAP_Vendor19: break; - case ID_DAP_Vendor20: break; - case ID_DAP_Vendor21: break; - case ID_DAP_Vendor22: break; - case ID_DAP_Vendor23: break; - case ID_DAP_Vendor24: break; - case ID_DAP_Vendor25: break; - case ID_DAP_Vendor26: break; - case ID_DAP_Vendor27: break; - case ID_DAP_Vendor28: break; - case ID_DAP_Vendor29: break; - case ID_DAP_Vendor30: break; - case ID_DAP_Vendor31: break; - } - - return (num); -} - -///@} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/JTAG_DP.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Source/JTAG_DP.c deleted file mode 100644 index 24b1f3f..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/JTAG_DP.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 1. December 2017 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Source - * Title: JTAG_DP.c CMSIS-DAP JTAG DP I/O - * - *---------------------------------------------------------------------------*/ - -#include "DAP_config.h" -#include "DAP.h" - - -// JTAG Macros - -#define PIN_TCK_SET PIN_SWCLK_TCK_SET -#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR -#define PIN_TMS_SET PIN_SWDIO_TMS_SET -#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR - -#define JTAG_CYCLE_TCK() \ - PIN_TCK_CLR(); \ - PIN_DELAY(); \ - PIN_TCK_SET(); \ - PIN_DELAY() - -#define JTAG_CYCLE_TDI(tdi) \ - PIN_TDI_OUT(tdi); \ - PIN_TCK_CLR(); \ - PIN_DELAY(); \ - PIN_TCK_SET(); \ - PIN_DELAY() - -#define JTAG_CYCLE_TDO(tdo) \ - PIN_TCK_CLR(); \ - PIN_DELAY(); \ - tdo = PIN_TDO_IN(); \ - PIN_TCK_SET(); \ - PIN_DELAY() - -#define JTAG_CYCLE_TDIO(tdi,tdo) \ - PIN_TDI_OUT(tdi); \ - PIN_TCK_CLR(); \ - PIN_DELAY(); \ - tdo = PIN_TDO_IN(); \ - PIN_TCK_SET(); \ - PIN_DELAY() - -#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) - - -#if (DAP_JTAG != 0) - - -// Generate JTAG Sequence -// info: sequence information -// tdi: pointer to TDI generated data -// tdo: pointer to TDO captured data -// return: none -void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) { - uint32_t i_val; - uint32_t o_val; - uint32_t bit; - uint32_t n, k; - - n = info & JTAG_SEQUENCE_TCK; - if (n == 0U) { - n = 64U; - } - - if (info & JTAG_SEQUENCE_TMS) { - PIN_TMS_SET(); - } else { - PIN_TMS_CLR(); - } - - while (n) { - i_val = *tdi++; - o_val = 0U; - for (k = 8U; k && n; k--, n--) { - JTAG_CYCLE_TDIO(i_val, bit); - i_val >>= 1; - o_val >>= 1; - o_val |= bit << 7; - } - o_val >>= k; - if (info & JTAG_SEQUENCE_TDO) { - *tdo++ = (uint8_t)o_val; - } - } -} - - -// JTAG Set IR -// ir: IR value -// return: none -#define JTAG_IR_Function(speed) /**/ \ -static void JTAG_IR_##speed (uint32_t ir) { \ - uint32_t n; \ - \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ - JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \ - PIN_TMS_CLR(); \ - JTAG_CYCLE_TCK(); /* Capture-IR */ \ - JTAG_CYCLE_TCK(); /* Shift-IR */ \ - \ - PIN_TDI_OUT(1U); \ - for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \ - JTAG_CYCLE_TCK(); /* Bypass before data */ \ - } \ - for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \ - JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \ - ir >>= 1; \ - } \ - n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \ - if (n) { \ - JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \ - PIN_TDI_OUT(1U); \ - for (--n; n; n--) { \ - JTAG_CYCLE_TCK(); /* Bypass after data */ \ - } \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \ - } else { \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \ - } \ - \ - JTAG_CYCLE_TCK(); /* Update-IR */ \ - PIN_TMS_CLR(); \ - JTAG_CYCLE_TCK(); /* Idle */ \ - PIN_TDI_OUT(1U); \ -} - - -// JTAG Transfer I/O -// request: A[3:2] RnW APnDP -// data: DATA[31:0] -// return: ACK[2:0] -#define JTAG_TransferFunction(speed) /**/ \ -static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \ - uint32_t ack; \ - uint32_t bit; \ - uint32_t val; \ - uint32_t n; \ - \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ - PIN_TMS_CLR(); \ - JTAG_CYCLE_TCK(); /* Capture-DR */ \ - JTAG_CYCLE_TCK(); /* Shift-DR */ \ - \ - for (n = DAP_Data.jtag_dev.index; n; n--) { \ - JTAG_CYCLE_TCK(); /* Bypass before data */ \ - } \ - \ - JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \ - ack = bit << 1; \ - JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \ - ack |= bit << 0; \ - JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \ - ack |= bit << 2; \ - \ - if (ack != DAP_TRANSFER_OK) { \ - /* Exit on error */ \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TCK(); /* Exit1-DR */ \ - goto exit; \ - } \ - \ - if (request & DAP_TRANSFER_RnW) { \ - /* Read Transfer */ \ - val = 0U; \ - for (n = 31U; n; n--) { \ - JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \ - val |= bit << 31; \ - val >>= 1; \ - } \ - n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ - if (n) { \ - JTAG_CYCLE_TDO(bit); /* Get D31 */ \ - for (--n; n; n--) { \ - JTAG_CYCLE_TCK(); /* Bypass after data */ \ - } \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ - } else { \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \ - } \ - val |= bit << 31; \ - if (data) { *data = val; } \ - } else { \ - /* Write Transfer */ \ - val = *data; \ - for (n = 31U; n; n--) { \ - JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \ - val >>= 1; \ - } \ - n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ - if (n) { \ - JTAG_CYCLE_TDI(val); /* Set D31 */ \ - for (--n; n; n--) { \ - JTAG_CYCLE_TCK(); /* Bypass after data */ \ - } \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ - } else { \ - PIN_TMS_SET(); \ - JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \ - } \ - } \ - \ -exit: \ - JTAG_CYCLE_TCK(); /* Update-DR */ \ - PIN_TMS_CLR(); \ - JTAG_CYCLE_TCK(); /* Idle */ \ - PIN_TDI_OUT(1U); \ - \ - /* Capture Timestamp */ \ - if (request & DAP_TRANSFER_TIMESTAMP) { \ - DAP_Data.timestamp = TIMESTAMP_GET(); \ - } \ - \ - /* Idle cycles */ \ - n = DAP_Data.transfer.idle_cycles; \ - while (n--) { \ - JTAG_CYCLE_TCK(); /* Idle */ \ - } \ - \ - return ((uint8_t)ack); \ -} - - -#undef PIN_DELAY -#define PIN_DELAY() PIN_DELAY_FAST() -JTAG_IR_Function(Fast) -JTAG_TransferFunction(Fast) - -#undef PIN_DELAY -#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) -JTAG_IR_Function(Slow) -JTAG_TransferFunction(Slow) - - -// JTAG Read IDCODE register -// return: value read -uint32_t JTAG_ReadIDCode (void) { - uint32_t bit; - uint32_t val; - uint32_t n; - - PIN_TMS_SET(); - JTAG_CYCLE_TCK(); /* Select-DR-Scan */ - PIN_TMS_CLR(); - JTAG_CYCLE_TCK(); /* Capture-DR */ - JTAG_CYCLE_TCK(); /* Shift-DR */ - - for (n = DAP_Data.jtag_dev.index; n; n--) { - JTAG_CYCLE_TCK(); /* Bypass before data */ - } - - val = 0U; - for (n = 31U; n; n--) { - JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ - val |= bit << 31; - val >>= 1; - } - PIN_TMS_SET(); - JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ - val |= bit << 31; - - JTAG_CYCLE_TCK(); /* Update-DR */ - PIN_TMS_CLR(); - JTAG_CYCLE_TCK(); /* Idle */ - - return (val); -} - - -// JTAG Write ABORT register -// data: value to write -// return: none -void JTAG_WriteAbort (uint32_t data) { - uint32_t n; - - PIN_TMS_SET(); - JTAG_CYCLE_TCK(); /* Select-DR-Scan */ - PIN_TMS_CLR(); - JTAG_CYCLE_TCK(); /* Capture-DR */ - JTAG_CYCLE_TCK(); /* Shift-DR */ - - for (n = DAP_Data.jtag_dev.index; n; n--) { - JTAG_CYCLE_TCK(); /* Bypass before data */ - } - - PIN_TDI_OUT(0U); - JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */ - JTAG_CYCLE_TCK(); /* Set A2=0 */ - JTAG_CYCLE_TCK(); /* Set A3=0 */ - - for (n = 31U; n; n--) { - JTAG_CYCLE_TDI(data); /* Set D0..D30 */ - data >>= 1; - } - n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; - if (n) { - JTAG_CYCLE_TDI(data); /* Set D31 */ - for (--n; n; n--) { - JTAG_CYCLE_TCK(); /* Bypass after data */ - } - PIN_TMS_SET(); - JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ - } else { - PIN_TMS_SET(); - JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */ - } - - JTAG_CYCLE_TCK(); /* Update-DR */ - PIN_TMS_CLR(); - JTAG_CYCLE_TCK(); /* Idle */ - PIN_TDI_OUT(1U); -} - - -// JTAG Set IR -// ir: IR value -// return: none -void JTAG_IR (uint32_t ir) { - if (DAP_Data.fast_clock) { - JTAG_IR_Fast(ir); - } else { - JTAG_IR_Slow(ir); - } -} - - -// JTAG Transfer I/O -// request: A[3:2] RnW APnDP -// data: DATA[31:0] -// return: ACK[2:0] -uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) { - if (DAP_Data.fast_clock) { - return JTAG_TransferFast(request, data); - } else { - return JTAG_TransferSlow(request, data); - } -} - - -#endif /* (DAP_JTAG != 0) */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/SWO.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Source/SWO.c deleted file mode 100644 index 4a850cf..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/SWO.c +++ /dev/null @@ -1,798 +0,0 @@ -/* - * Copyright (c) 2013-2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 29. March 2021 - * $Revision: V2.0.1 - * - * Project: CMSIS-DAP Source - * Title: SWO.c CMSIS-DAP SWO I/O - * - *---------------------------------------------------------------------------*/ - -#include "DAP_config.h" -#include "DAP.h" -#if (SWO_UART != 0) -#include "Driver_USART.h" -#endif -#if (SWO_STREAM != 0) -#include "cmsis_os2.h" -#define osObjectsExternal -#include "osObjects.h" -#endif - -#if (SWO_STREAM != 0) -#ifdef DAP_FW_V1 -#error "SWO Streaming Trace not supported in DAP V1!" -#endif -#endif - -#if (SWO_UART != 0) - -// USART Driver -#define _USART_Driver_(n) Driver_USART##n -#define USART_Driver_(n) _USART_Driver_(n) -extern ARM_DRIVER_USART USART_Driver_(SWO_UART_DRIVER); -#define pUSART (&USART_Driver_(SWO_UART_DRIVER)) - -static uint8_t USART_Ready = 0U; - -#endif /* (SWO_UART != 0) */ - - -#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) - - -#define SWO_STREAM_TIMEOUT 50U /* Stream timeout in ms */ - -#define USB_BLOCK_SIZE 512U /* USB Block Size */ -#define TRACE_BLOCK_SIZE 64U /* Trace Block Size (2^n: 32...512) */ - -// Trace State -static uint8_t TraceTransport = 0U; /* Trace Transport */ -static uint8_t TraceMode = 0U; /* Trace Mode */ -static uint8_t TraceStatus = 0U; /* Trace Status without Errors */ -static uint8_t TraceError[2] = {0U, 0U}; /* Trace Error flags (banked) */ -static uint8_t TraceError_n = 0U; /* Active Trace Error bank */ - -// Trace Buffer -static uint8_t TraceBuf[SWO_BUFFER_SIZE]; /* Trace Buffer (must be 2^n) */ -static volatile uint32_t TraceIndexI = 0U; /* Incoming Trace Index */ -static volatile uint32_t TraceIndexO = 0U; /* Outgoing Trace Index */ -static volatile uint8_t TraceUpdate; /* Trace Update Flag */ -static uint32_t TraceBlockSize; /* Current Trace Block Size */ - -#if (TIMESTAMP_CLOCK != 0U) -// Trace Timestamp -static volatile struct { - uint32_t index; - uint32_t tick; -} TraceTimestamp; -#endif - -// Trace Helper functions -static void ClearTrace (void); -static void ResumeTrace (void); -static uint32_t GetTraceCount (void); -static uint8_t GetTraceStatus (void); -static void SetTraceError (uint8_t flag); - -#if (SWO_STREAM != 0) -extern osThreadId_t SWO_ThreadId; -static volatile uint8_t TransferBusy = 0U; /* Transfer Busy Flag */ -static uint32_t TransferSize; /* Current Transfer Size */ -#endif - - -#if (SWO_UART != 0) - -// USART Driver Callback function -// event: event mask -static void USART_Callback (uint32_t event) { - uint32_t index_i; - uint32_t index_o; - uint32_t count; - uint32_t num; - - if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { -#if (TIMESTAMP_CLOCK != 0U) - TraceTimestamp.tick = TIMESTAMP_GET(); -#endif - index_o = TraceIndexO; - index_i = TraceIndexI; - index_i += TraceBlockSize; - TraceIndexI = index_i; -#if (TIMESTAMP_CLOCK != 0U) - TraceTimestamp.index = index_i; -#endif - num = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U)); - count = index_i - index_o; - if (count <= (SWO_BUFFER_SIZE - num)) { - index_i &= SWO_BUFFER_SIZE - 1U; - TraceBlockSize = num; - pUSART->Receive(&TraceBuf[index_i], num); - } else { - TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED; - } - TraceUpdate = 1U; -#if (SWO_STREAM != 0) - if (TraceTransport == 2U) { - if (count >= (USB_BLOCK_SIZE - (index_o & (USB_BLOCK_SIZE - 1U)))) { - osThreadFlagsSet(SWO_ThreadId, 1U); - } - } -#endif - } - if (event & ARM_USART_EVENT_RX_OVERFLOW) { - SetTraceError(DAP_SWO_BUFFER_OVERRUN); - } - if (event & (ARM_USART_EVENT_RX_BREAK | - ARM_USART_EVENT_RX_FRAMING_ERROR | - ARM_USART_EVENT_RX_PARITY_ERROR)) { - SetTraceError(DAP_SWO_STREAM_ERROR); - } -} - -// Enable or disable SWO Mode (UART) -// enable: enable flag -// return: 1 - Success, 0 - Error -__WEAK uint32_t SWO_Mode_UART (uint32_t enable) { - int32_t status; - - USART_Ready = 0U; - - if (enable != 0U) { - status = pUSART->Initialize(USART_Callback); - if (status != ARM_DRIVER_OK) { - return (0U); - } - status = pUSART->PowerControl(ARM_POWER_FULL); - if (status != ARM_DRIVER_OK) { - pUSART->Uninitialize(); - return (0U); - } - } else { - pUSART->Control(ARM_USART_CONTROL_RX, 0U); - pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); - pUSART->PowerControl(ARM_POWER_OFF); - pUSART->Uninitialize(); - } - return (1U); -} - -// Configure SWO Baudrate (UART) -// baudrate: requested baudrate -// return: actual baudrate or 0 when not configured -__WEAK uint32_t SWO_Baudrate_UART (uint32_t baudrate) { - int32_t status; - uint32_t index; - uint32_t num; - - if (baudrate > SWO_UART_MAX_BAUDRATE) { - baudrate = SWO_UART_MAX_BAUDRATE; - } - - if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { - pUSART->Control(ARM_USART_CONTROL_RX, 0U); - if (pUSART->GetStatus().rx_busy) { - TraceIndexI += pUSART->GetRxCount(); - pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); - } - } - - status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1, - baudrate); - - if (status == ARM_DRIVER_OK) { - USART_Ready = 1U; - } else { - USART_Ready = 0U; - return (0U); - } - - if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { - if ((TraceStatus & DAP_SWO_CAPTURE_PAUSED) == 0U) { - index = TraceIndexI & (SWO_BUFFER_SIZE - 1U); - num = TRACE_BLOCK_SIZE - (index & (TRACE_BLOCK_SIZE - 1U)); - TraceBlockSize = num; - pUSART->Receive(&TraceBuf[index], num); - } - pUSART->Control(ARM_USART_CONTROL_RX, 1U); - } - - return (baudrate); -} - -// Control SWO Capture (UART) -// active: active flag -// return: 1 - Success, 0 - Error -__WEAK uint32_t SWO_Control_UART (uint32_t active) { - int32_t status; - - if (active) { - if (!USART_Ready) { - return (0U); - } - TraceBlockSize = 1U; - status = pUSART->Receive(&TraceBuf[0], 1U); - if (status != ARM_DRIVER_OK) { - return (0U); - } - status = pUSART->Control(ARM_USART_CONTROL_RX, 1U); - if (status != ARM_DRIVER_OK) { - return (0U); - } - } else { - pUSART->Control(ARM_USART_CONTROL_RX, 0U); - if (pUSART->GetStatus().rx_busy) { - TraceIndexI += pUSART->GetRxCount(); - pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); - } - } - return (1U); -} - -// Start SWO Capture (UART) -// buf: pointer to buffer for capturing -// num: number of bytes to capture -__WEAK void SWO_Capture_UART (uint8_t *buf, uint32_t num) { - TraceBlockSize = num; - pUSART->Receive(buf, num); -} - -// Get SWO Pending Trace Count (UART) -// return: number of pending trace data bytes -__WEAK uint32_t SWO_GetCount_UART (void) { - uint32_t count; - - if (pUSART->GetStatus().rx_busy) { - count = pUSART->GetRxCount(); - } else { - count = 0U; - } - return (count); -} - -#endif /* (SWO_UART != 0) */ - - -#if (SWO_MANCHESTER != 0) - -// Enable or disable SWO Mode (Manchester) -// enable: enable flag -// return: 1 - Success, 0 - Error -__WEAK uint32_t SWO_Mode_Manchester (uint32_t enable) { - return (0U); -} - -// Configure SWO Baudrate (Manchester) -// baudrate: requested baudrate -// return: actual baudrate or 0 when not configured -__WEAK uint32_t SWO_Baudrate_Manchester (uint32_t baudrate) { - return (0U); -} - -// Control SWO Capture (Manchester) -// active: active flag -// return: 1 - Success, 0 - Error -__WEAK uint32_t SWO_Control_Manchester (uint32_t active) { - return (0U); -} - -// Start SWO Capture (Manchester) -// buf: pointer to buffer for capturing -// num: number of bytes to capture -__WEAK void SWO_Capture_Manchester (uint8_t *buf, uint32_t num) { -} - -// Get SWO Pending Trace Count (Manchester) -// return: number of pending trace data bytes -__WEAK uint32_t SWO_GetCount_Manchester (void) { -} - -#endif /* (SWO_MANCHESTER != 0) */ - - -// Clear Trace Errors and Data -static void ClearTrace (void) { - -#if (SWO_STREAM != 0) - if (TraceTransport == 2U) { - if (TransferBusy != 0U) { - SWO_AbortTransfer(); - TransferBusy = 0U; - } - } -#endif - - TraceError[0] = 0U; - TraceError[1] = 0U; - TraceError_n = 0U; - TraceIndexI = 0U; - TraceIndexO = 0U; - -#if (TIMESTAMP_CLOCK != 0U) - TraceTimestamp.index = 0U; - TraceTimestamp.tick = 0U; -#endif -} - -// Resume Trace Capture -static void ResumeTrace (void) { - uint32_t index_i; - uint32_t index_o; - - if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) { - index_i = TraceIndexI; - index_o = TraceIndexO; - if ((index_i - index_o) < SWO_BUFFER_SIZE) { - index_i &= SWO_BUFFER_SIZE - 1U; - switch (TraceMode) { -#if (SWO_UART != 0) - case DAP_SWO_UART: - TraceStatus = DAP_SWO_CAPTURE_ACTIVE; - SWO_Capture_UART(&TraceBuf[index_i], 1U); - break; -#endif -#if (SWO_MANCHESTER != 0) - case DAP_SWO_MANCHESTER: - TraceStatus = DAP_SWO_CAPTURE_ACTIVE; - SWO_Capture_Manchester(&TraceBuf[index_i], 1U); - break; -#endif - default: - break; - } - } - } -} - -// Get Trace Count -// return: number of available data bytes in trace buffer -static uint32_t GetTraceCount (void) { - uint32_t count; - - if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) { - do { - TraceUpdate = 0U; - count = TraceIndexI - TraceIndexO; - switch (TraceMode) { -#if (SWO_UART != 0) - case DAP_SWO_UART: - count += SWO_GetCount_UART(); - break; -#endif -#if (SWO_MANCHESTER != 0) - case DAP_SWO_MANCHESTER: - count += SWO_GetCount_Manchester(); - break; -#endif - default: - break; - } - } while (TraceUpdate != 0U); - } else { - count = TraceIndexI - TraceIndexO; - } - - return (count); -} - -// Get Trace Status (clear Error flags) -// return: Trace Status (Active flag and Error flags) -static uint8_t GetTraceStatus (void) { - uint8_t status; - uint32_t n; - - n = TraceError_n; - TraceError_n ^= 1U; - status = TraceStatus | TraceError[n]; - TraceError[n] = 0U; - - return (status); -} - -// Set Trace Error flag(s) -// flag: error flag(s) to set -static void SetTraceError (uint8_t flag) { - TraceError[TraceError_n] |= flag; -} - - -// Process SWO Transport command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) { - uint8_t transport; - uint32_t result; - - if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) == 0U) { - transport = *request; - switch (transport) { - case 0U: - case 1U: -#if (SWO_STREAM != 0) - case 2U: -#endif - TraceTransport = transport; - result = 1U; - break; - default: - result = 0U; - break; - } - } else { - result = 0U; - } - - if (result != 0U) { - *response = DAP_OK; - } else { - *response = DAP_ERROR; - } - - return ((1U << 16) | 1U); -} - - -// Process SWO Mode command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) { - uint8_t mode; - uint32_t result; - - mode = *request; - - switch (TraceMode) { -#if (SWO_UART != 0) - case DAP_SWO_UART: - SWO_Mode_UART(0U); - break; -#endif -#if (SWO_MANCHESTER != 0) - case DAP_SWO_MANCHESTER: - SWO_Mode_Manchester(0U); - break; -#endif - default: - break; - } - - switch (mode) { - case DAP_SWO_OFF: - result = 1U; - break; -#if (SWO_UART != 0) - case DAP_SWO_UART: - result = SWO_Mode_UART(1U); - break; -#endif -#if (SWO_MANCHESTER != 0) - case DAP_SWO_MANCHESTER: - result = SWO_Mode_Manchester(1U); - break; -#endif - default: - result = 0U; - break; - } - if (result != 0U) { - TraceMode = mode; - } else { - TraceMode = DAP_SWO_OFF; - } - - TraceStatus = 0U; - - if (result != 0U) { - *response = DAP_OK; - } else { - *response = DAP_ERROR; - } - - return ((1U << 16) | 1U); -} - - -// Process SWO Baudrate command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) { - uint32_t baudrate; - - baudrate = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8) | - (uint32_t)(*(request+2) << 16) | - (uint32_t)(*(request+3) << 24); - - switch (TraceMode) { -#if (SWO_UART != 0) - case DAP_SWO_UART: - baudrate = SWO_Baudrate_UART(baudrate); - break; -#endif -#if (SWO_MANCHESTER != 0) - case DAP_SWO_MANCHESTER: - baudrate = SWO_Baudrate_Manchester(baudrate); - break; -#endif - default: - baudrate = 0U; - break; - } - - if (baudrate == 0U) { - TraceStatus = 0U; - } - - *response++ = (uint8_t)(baudrate >> 0); - *response++ = (uint8_t)(baudrate >> 8); - *response++ = (uint8_t)(baudrate >> 16); - *response = (uint8_t)(baudrate >> 24); - - return ((4U << 16) | 4U); -} - - -// Process SWO Control command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t SWO_Control (const uint8_t *request, uint8_t *response) { - uint8_t active; - uint32_t result; - - active = *request & DAP_SWO_CAPTURE_ACTIVE; - - if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) { - if (active) { - ClearTrace(); - } - switch (TraceMode) { -#if (SWO_UART != 0) - case DAP_SWO_UART: - result = SWO_Control_UART(active); - break; -#endif -#if (SWO_MANCHESTER != 0) - case DAP_SWO_MANCHESTER: - result = SWO_Control_Manchester(active); - break; -#endif - default: - result = 0U; - break; - } - if (result != 0U) { - TraceStatus = active; -#if (SWO_STREAM != 0) - if (TraceTransport == 2U) { - osThreadFlagsSet(SWO_ThreadId, 1U); - } -#endif - } - } else { - result = 1U; - } - - if (result != 0U) { - *response = DAP_OK; - } else { - *response = DAP_ERROR; - } - - return ((1U << 16) | 1U); -} - - -// Process SWO Status command and prepare response -// response: pointer to response data -// return: number of bytes in response -uint32_t SWO_Status (uint8_t *response) { - uint8_t status; - uint32_t count; - - status = GetTraceStatus(); - count = GetTraceCount(); - - *response++ = status; - *response++ = (uint8_t)(count >> 0); - *response++ = (uint8_t)(count >> 8); - *response++ = (uint8_t)(count >> 16); - *response = (uint8_t)(count >> 24); - - return (5U); -} - - -// Process SWO Extended Status command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) { - uint8_t cmd; - uint8_t status; - uint32_t count; -#if (TIMESTAMP_CLOCK != 0U) - uint32_t index; - uint32_t tick; -#endif - uint32_t num; - - num = 0U; - cmd = *request; - - if (cmd & 0x01U) { - status = GetTraceStatus(); - *response++ = status; - num += 1U; - } - - if (cmd & 0x02U) { - count = GetTraceCount(); - *response++ = (uint8_t)(count >> 0); - *response++ = (uint8_t)(count >> 8); - *response++ = (uint8_t)(count >> 16); - *response++ = (uint8_t)(count >> 24); - num += 4U; - } - -#if (TIMESTAMP_CLOCK != 0U) - if (cmd & 0x04U) { - do { - TraceUpdate = 0U; - index = TraceTimestamp.index; - tick = TraceTimestamp.tick; - } while (TraceUpdate != 0U); - *response++ = (uint8_t)(index >> 0); - *response++ = (uint8_t)(index >> 8); - *response++ = (uint8_t)(index >> 16); - *response++ = (uint8_t)(index >> 24); - *response++ = (uint8_t)(tick >> 0); - *response++ = (uint8_t)(tick >> 8); - *response++ = (uint8_t)(tick >> 16); - *response++ = (uint8_t)(tick >> 24); - num += 4U; - } -#endif - - return ((1U << 16) | num); -} - - -// Process SWO Data command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t SWO_Data (const uint8_t *request, uint8_t *response) { - uint8_t status; - uint32_t count; - uint32_t index; - uint32_t n, i; - - status = GetTraceStatus(); - count = GetTraceCount(); - - if (TraceTransport == 1U) { - n = (uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8); - if (n > (DAP_PACKET_SIZE - 4U)) { - n = DAP_PACKET_SIZE - 4U; - } - if (count > n) { - count = n; - } - } else { - count = 0U; - } - - *response++ = status; - *response++ = (uint8_t)(count >> 0); - *response++ = (uint8_t)(count >> 8); - - if (TraceTransport == 1U) { - index = TraceIndexO; - for (i = index, n = count; n; n--) { - i &= SWO_BUFFER_SIZE - 1U; - *response++ = TraceBuf[i++]; - } - TraceIndexO = index + count; - ResumeTrace(); - } - - return ((2U << 16) | (3U + count)); -} - - -#if (SWO_STREAM != 0) - -// SWO Data Transfer complete callback -void SWO_TransferComplete (void) { - TraceIndexO += TransferSize; - TransferBusy = 0U; - ResumeTrace(); - osThreadFlagsSet(SWO_ThreadId, 1U); -} - -// SWO Thread -__NO_RETURN void SWO_Thread (void *argument) { - uint32_t timeout; - uint32_t flags; - uint32_t count; - uint32_t index; - uint32_t i, n; - (void) argument; - - timeout = osWaitForever; - - for (;;) { - flags = osThreadFlagsWait(1U, osFlagsWaitAny, timeout); - if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { - timeout = SWO_STREAM_TIMEOUT; - } else { - timeout = osWaitForever; - flags = osFlagsErrorTimeout; - } - if (TransferBusy == 0U) { - count = GetTraceCount(); - if (count != 0U) { - index = TraceIndexO & (SWO_BUFFER_SIZE - 1U); - n = SWO_BUFFER_SIZE - index; - if (count > n) { - count = n; - } - if (flags != osFlagsErrorTimeout) { - i = index & (USB_BLOCK_SIZE - 1U); - if (i == 0U) { - count &= ~(USB_BLOCK_SIZE - 1U); - } else { - n = USB_BLOCK_SIZE - i; - if (count >= n) { - count = n; - } else { - count = 0U; - } - } - } - if (count != 0U) { - TransferSize = count; - TransferBusy = 1U; - SWO_QueueTransfer(&TraceBuf[index], count); - } - } - } - } -} - -#endif /* (SWO_STREAM != 0) */ - - -#endif /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/SW_DP.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Source/SW_DP.c deleted file mode 100644 index 803cf42..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/SW_DP.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 1. December 2017 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Source - * Title: SW_DP.c CMSIS-DAP SW DP I/O - * - *---------------------------------------------------------------------------*/ - -#include "DAP_config.h" -#include "DAP.h" - - -// SW Macros - -#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET -#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR - -#define SW_CLOCK_CYCLE() \ - PIN_SWCLK_CLR(); \ - PIN_DELAY(); \ - PIN_SWCLK_SET(); \ - PIN_DELAY() - -#define SW_WRITE_BIT(bit) \ - PIN_SWDIO_OUT(bit); \ - PIN_SWCLK_CLR(); \ - PIN_DELAY(); \ - PIN_SWCLK_SET(); \ - PIN_DELAY() - -#define SW_READ_BIT(bit) \ - PIN_SWCLK_CLR(); \ - PIN_DELAY(); \ - bit = PIN_SWDIO_IN(); \ - PIN_SWCLK_SET(); \ - PIN_DELAY() - -#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) - - -// Generate SWJ Sequence -// count: sequence bit count -// data: pointer to sequence bit data -// return: none -#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) -void SWJ_Sequence (uint32_t count, const uint8_t *data) { - uint32_t val; - uint32_t n; - - val = 0U; - n = 0U; - while (count--) { - if (n == 0U) { - val = *data++; - n = 8U; - } - if (val & 1U) { - PIN_SWDIO_TMS_SET(); - } else { - PIN_SWDIO_TMS_CLR(); - } - SW_CLOCK_CYCLE(); - val >>= 1; - n--; - } -} -#endif - - -// Generate SWD Sequence -// info: sequence information -// swdo: pointer to SWDIO generated data -// swdi: pointer to SWDIO captured data -// return: none -#if (DAP_SWD != 0) -void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) { - uint32_t val; - uint32_t bit; - uint32_t n, k; - - n = info & SWD_SEQUENCE_CLK; - if (n == 0U) { - n = 64U; - } - - if (info & SWD_SEQUENCE_DIN) { - while (n) { - val = 0U; - for (k = 8U; k && n; k--, n--) { - SW_READ_BIT(bit); - val >>= 1; - val |= bit << 7; - } - val >>= k; - *swdi++ = (uint8_t)val; - } - } else { - while (n) { - val = *swdo++; - for (k = 8U; k && n; k--, n--) { - SW_WRITE_BIT(val); - val >>= 1; - } - } - } -} -#endif - - -#if (DAP_SWD != 0) - - -// SWD Transfer I/O -// request: A[3:2] RnW APnDP -// data: DATA[31:0] -// return: ACK[2:0] -#define SWD_TransferFunction(speed) /**/ \ -static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \ - uint32_t ack; \ - uint32_t bit; \ - uint32_t val; \ - uint32_t parity; \ - \ - uint32_t n; \ - \ - /* Packet Request */ \ - parity = 0U; \ - SW_WRITE_BIT(1U); /* Start Bit */ \ - bit = request >> 0; \ - SW_WRITE_BIT(bit); /* APnDP Bit */ \ - parity += bit; \ - bit = request >> 1; \ - SW_WRITE_BIT(bit); /* RnW Bit */ \ - parity += bit; \ - bit = request >> 2; \ - SW_WRITE_BIT(bit); /* A2 Bit */ \ - parity += bit; \ - bit = request >> 3; \ - SW_WRITE_BIT(bit); /* A3 Bit */ \ - parity += bit; \ - SW_WRITE_BIT(parity); /* Parity Bit */ \ - SW_WRITE_BIT(0U); /* Stop Bit */ \ - SW_WRITE_BIT(1U); /* Park Bit */ \ - \ - /* Turnaround */ \ - PIN_SWDIO_OUT_DISABLE(); \ - for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ - SW_CLOCK_CYCLE(); \ - } \ - \ - /* Acknowledge response */ \ - SW_READ_BIT(bit); \ - ack = bit << 0; \ - SW_READ_BIT(bit); \ - ack |= bit << 1; \ - SW_READ_BIT(bit); \ - ack |= bit << 2; \ - \ - if (ack == DAP_TRANSFER_OK) { /* OK response */ \ - /* Data transfer */ \ - if (request & DAP_TRANSFER_RnW) { \ - /* Read data */ \ - val = 0U; \ - parity = 0U; \ - for (n = 32U; n; n--) { \ - SW_READ_BIT(bit); /* Read RDATA[0:31] */ \ - parity += bit; \ - val >>= 1; \ - val |= bit << 31; \ - } \ - SW_READ_BIT(bit); /* Read Parity */ \ - if ((parity ^ bit) & 1U) { \ - ack = DAP_TRANSFER_ERROR; \ - } \ - if (data) { *data = val; } \ - /* Turnaround */ \ - for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ - SW_CLOCK_CYCLE(); \ - } \ - PIN_SWDIO_OUT_ENABLE(); \ - } else { \ - /* Turnaround */ \ - for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ - SW_CLOCK_CYCLE(); \ - } \ - PIN_SWDIO_OUT_ENABLE(); \ - /* Write data */ \ - val = *data; \ - parity = 0U; \ - for (n = 32U; n; n--) { \ - SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \ - parity += val; \ - val >>= 1; \ - } \ - SW_WRITE_BIT(parity); /* Write Parity Bit */ \ - } \ - /* Capture Timestamp */ \ - if (request & DAP_TRANSFER_TIMESTAMP) { \ - DAP_Data.timestamp = TIMESTAMP_GET(); \ - } \ - /* Idle cycles */ \ - n = DAP_Data.transfer.idle_cycles; \ - if (n) { \ - PIN_SWDIO_OUT(0U); \ - for (; n; n--) { \ - SW_CLOCK_CYCLE(); \ - } \ - } \ - PIN_SWDIO_OUT(1U); \ - return ((uint8_t)ack); \ - } \ - \ - if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \ - /* WAIT or FAULT response */ \ - if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \ - for (n = 32U+1U; n; n--) { \ - SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \ - } \ - } \ - /* Turnaround */ \ - for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ - SW_CLOCK_CYCLE(); \ - } \ - PIN_SWDIO_OUT_ENABLE(); \ - if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \ - PIN_SWDIO_OUT(0U); \ - for (n = 32U+1U; n; n--) { \ - SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \ - } \ - } \ - PIN_SWDIO_OUT(1U); \ - return ((uint8_t)ack); \ - } \ - \ - /* Protocol error */ \ - for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \ - SW_CLOCK_CYCLE(); /* Back off data phase */ \ - } \ - PIN_SWDIO_OUT_ENABLE(); \ - PIN_SWDIO_OUT(1U); \ - return ((uint8_t)ack); \ -} - - -#undef PIN_DELAY -#define PIN_DELAY() PIN_DELAY_FAST() -SWD_TransferFunction(Fast) - -#undef PIN_DELAY -#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) -SWD_TransferFunction(Slow) - - -// SWD Transfer I/O -// request: A[3:2] RnW APnDP -// data: DATA[31:0] -// return: ACK[2:0] -uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { - if (DAP_Data.fast_clock) { - return SWD_TransferFast(request, data); - } else { - return SWD_TransferSlow(request, data); - } -} - - -#endif /* (DAP_SWD != 0) */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/UART.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Source/UART.c deleted file mode 100644 index 8e9eae5..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Source/UART.c +++ /dev/null @@ -1,652 +0,0 @@ -/* - * Copyright (c) 2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 1. March 2021 - * $Revision: V1.0.0 - * - * Project: CMSIS-DAP Source - * Title: UART.c CMSIS-DAP UART - * - *---------------------------------------------------------------------------*/ - -#include "DAP_config.h" -#include "DAP.h" - -#if (DAP_UART != 0) - -#ifdef DAP_FW_V1 -#error "UART Communication Port not supported in DAP V1!" -#endif - -#include "Driver_USART.h" - -#include "cmsis_os2.h" -#include - -#define UART_RX_BLOCK_SIZE 32U /* Uart Rx Block Size (must be 2^n) */ - -// USART Driver -#define _USART_Driver_(n) Driver_USART##n -#define USART_Driver_(n) _USART_Driver_(n) -extern ARM_DRIVER_USART USART_Driver_(DAP_UART_DRIVER); -#define pUSART (&USART_Driver_(DAP_UART_DRIVER)) - -// UART Configuration -#if (DAP_UART_USB_COM_PORT != 0) -static uint8_t UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; -#else -static uint8_t UartTransport = DAP_UART_TRANSPORT_NONE; -#endif - -// UART Flags -static uint8_t UartConfigured = 0U; -static uint8_t UartReceiveEnabled = 0U; -static uint8_t UartTransmitEnabled = 0U; -static uint8_t UartTransmitActive = 0U; - -// UART TX Buffer -static uint8_t UartTxBuf[DAP_UART_TX_BUFFER_SIZE]; -static volatile uint32_t UartTxIndexI = 0U; -static volatile uint32_t UartTxIndexO = 0U; - -// UART RX Buffer -static uint8_t UartRxBuf[DAP_UART_RX_BUFFER_SIZE]; -static volatile uint32_t UartRxIndexI = 0U; -static volatile uint32_t UartRxIndexO = 0U; - -// Uart Errors -static volatile uint8_t UartErrorRxDataLost = 0U; -static volatile uint8_t UartErrorFraming = 0U; -static volatile uint8_t UartErrorParity = 0U; - -// UART Transmit -static uint32_t UartTxNum = 0U; - -// Function prototypes -static uint8_t UART_Init (void); -static void UART_Uninit (void); -static uint8_t UART_Get_Status (void); -static uint8_t UART_Receive_Enable (void); -static uint8_t UART_Transmit_Enable (void); -static void UART_Receive_Disable (void); -static void UART_Transmit_Disable (void); -static void UART_Receive_Flush (void); -static void UART_Transmit_Flush (void); -static void UART_Receive (void); -static void UART_Transmit (void); - - -// USART Driver Callback function -// event: event mask -static void USART_Callback (uint32_t event) { - if (event & ARM_USART_EVENT_SEND_COMPLETE) { - UartTxIndexO += UartTxNum; - UartTransmitActive = 0U; - UART_Transmit(); - } - if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { - UartRxIndexI += UART_RX_BLOCK_SIZE; - UART_Receive(); - } - if (event & ARM_USART_EVENT_RX_OVERFLOW) { - UartErrorRxDataLost = 1U; - } - if (event & ARM_USART_EVENT_RX_FRAMING_ERROR) { - UartErrorFraming = 1U; - } - if (event & ARM_USART_EVENT_RX_PARITY_ERROR) { - UartErrorParity = 1U; - } -} - -// Init UART -// return: DAP_OK or DAP_ERROR -static uint8_t UART_Init (void) { - int32_t status; - uint8_t ret = DAP_ERROR; - - UartConfigured = 0U; - UartReceiveEnabled = 0U; - UartTransmitEnabled = 0U; - UartTransmitActive = 0U; - UartErrorRxDataLost = 0U; - UartErrorFraming = 0U; - UartErrorParity = 0U; - UartTxIndexI = 0U; - UartTxIndexO = 0U; - UartRxIndexI = 0U; - UartRxIndexO = 0U; - UartTxNum = 0U; - - status = pUSART->Initialize(USART_Callback); - if (status == ARM_DRIVER_OK) { - status = pUSART->PowerControl(ARM_POWER_FULL); - } - if (status == ARM_DRIVER_OK) { - ret = DAP_OK; - } - - return (ret); -} - -// Un-Init UART -static void UART_Uninit (void) { - UartConfigured = 0U; - - pUSART->PowerControl(ARM_POWER_OFF); - pUSART->Uninitialize(); -} - -// Get UART Status -// return: status -static uint8_t UART_Get_Status (void) { - uint8_t status = 0U; - - if (UartReceiveEnabled != 0U) { - status |= DAP_UART_STATUS_RX_ENABLED; - } - if (UartErrorRxDataLost != 0U) { - UartErrorRxDataLost = 0U; - status |= DAP_UART_STATUS_RX_DATA_LOST; - } - if (UartErrorFraming != 0U) { - UartErrorFraming = 0U; - status |= DAP_UART_STATUS_FRAMING_ERROR; - } - if (UartErrorParity != 0U) { - UartErrorParity = 0U; - status |= DAP_UART_STATUS_PARITY_ERROR; - } - if (UartTransmitEnabled != 0U) { - status |= DAP_UART_STATUS_TX_ENABLED; - } - - return (status); -} - -// Enable UART Receive -// return: DAP_OK or DAP_ERROR -static uint8_t UART_Receive_Enable (void) { - int32_t status; - uint8_t ret = DAP_ERROR; - - if (UartReceiveEnabled == 0U) { - // Flush Buffers - UartRxIndexI = 0U; - UartRxIndexO = 0U; - - UART_Receive(); - status = pUSART->Control(ARM_USART_CONTROL_RX, 1U); - if (status == ARM_DRIVER_OK) { - UartReceiveEnabled = 1U; - ret = DAP_OK; - } - } else { - ret = DAP_OK; - } - - return (ret); -} - -// Enable UART Transmit -// return: DAP_OK or DAP_ERROR -static uint8_t UART_Transmit_Enable (void) { - int32_t status; - uint8_t ret = DAP_ERROR; - - if (UartTransmitEnabled == 0U) { - // Flush Buffers - UartTransmitActive = 0U; - UartTxIndexI = 0U; - UartTxIndexO = 0U; - UartTxNum = 0U; - - status = pUSART->Control(ARM_USART_CONTROL_TX, 1U); - if (status == ARM_DRIVER_OK) { - UartTransmitEnabled = 1U; - ret = DAP_OK; - } - } else { - ret = DAP_OK; - } - - return (ret); -} - -// Disable UART Receive -static void UART_Receive_Disable (void) { - if (UartReceiveEnabled != 0U) { - pUSART->Control(ARM_USART_CONTROL_RX, 0U); - pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); - UartReceiveEnabled = 0U; - } -} - -// Disable UART Transmit -static void UART_Transmit_Disable (void) { - if (UartTransmitEnabled != 0U) { - pUSART->Control(ARM_USART_ABORT_SEND, 0U); - pUSART->Control(ARM_USART_CONTROL_TX, 0U); - UartTransmitActive = 0U; - UartTransmitEnabled = 0U; - } -} - -// Flush UART Receive buffer -static void UART_Receive_Flush (void) { - pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); - UartRxIndexI = 0U; - UartRxIndexO = 0U; - if (UartReceiveEnabled != 0U) { - UART_Receive(); - } -} - -// Flush UART Transmit buffer -static void UART_Transmit_Flush (void) { - pUSART->Control(ARM_USART_ABORT_SEND, 0U); - UartTransmitActive = 0U; - UartTxIndexI = 0U; - UartTxIndexO = 0U; - UartTxNum = 0U; -} - -// Receive data from target via UART -static void UART_Receive (void) { - uint32_t index; - - index = UartRxIndexI & (DAP_UART_RX_BUFFER_SIZE - 1U); - pUSART->Receive(&UartRxBuf[index], UART_RX_BLOCK_SIZE); -} - -// Transmit available data to target via UART -static void UART_Transmit (void) { - uint32_t count; - uint32_t index; - - count = UartTxIndexI - UartTxIndexO; - index = UartTxIndexO & (DAP_UART_TX_BUFFER_SIZE - 1U); - - if (count != 0U) { - if ((index + count) <= DAP_UART_TX_BUFFER_SIZE) { - UartTxNum = count; - } else { - UartTxNum = DAP_UART_TX_BUFFER_SIZE - index; - } - UartTransmitActive = 1U; - pUSART->Send(&UartTxBuf[index], UartTxNum); - } -} - -// Process UART Transport command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t UART_Transport (const uint8_t *request, uint8_t *response) { - uint8_t transport; - uint8_t ret = DAP_ERROR; - - transport = *request; - switch (transport) { - case DAP_UART_TRANSPORT_NONE: - switch (UartTransport) { - case DAP_UART_TRANSPORT_NONE: - ret = DAP_OK; - break; - case DAP_UART_TRANSPORT_USB_COM_PORT: -#if (DAP_UART_USB_COM_PORT != 0) - USB_COM_PORT_Activate(0U); - UartTransport = DAP_UART_TRANSPORT_NONE; - ret = DAP_OK; -#endif - break; - case DAP_UART_TRANSPORT_DAP_COMMAND: - UART_Receive_Disable(); - UART_Transmit_Disable(); - UART_Uninit(); - UartTransport = DAP_UART_TRANSPORT_NONE; - ret= DAP_OK; - break; - } - break; - case DAP_UART_TRANSPORT_USB_COM_PORT: - switch (UartTransport) { - case DAP_UART_TRANSPORT_NONE: -#if (DAP_UART_USB_COM_PORT != 0) - if (USB_COM_PORT_Activate(1U) == 0U) { - UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; - ret = DAP_OK; - } -#endif - break; - case DAP_UART_TRANSPORT_USB_COM_PORT: - ret = DAP_OK; - break; - case DAP_UART_TRANSPORT_DAP_COMMAND: - UART_Receive_Disable(); - UART_Transmit_Disable(); - UART_Uninit(); - UartTransport = DAP_UART_TRANSPORT_NONE; -#if (DAP_UART_USB_COM_PORT != 0) - if (USB_COM_PORT_Activate(1U) == 0U) { - UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; - ret = DAP_OK; - } -#endif - break; - } - break; - case DAP_UART_TRANSPORT_DAP_COMMAND: - switch (UartTransport) { - case DAP_UART_TRANSPORT_NONE: - ret = UART_Init(); - if (ret == DAP_OK) { - UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; - } - break; - case DAP_UART_TRANSPORT_USB_COM_PORT: -#if (DAP_UART_USB_COM_PORT != 0) - USB_COM_PORT_Activate(0U); - UartTransport = DAP_UART_TRANSPORT_NONE; -#endif - ret = UART_Init(); - if (ret == DAP_OK) { - UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; - } - break; - case DAP_UART_TRANSPORT_DAP_COMMAND: - ret = DAP_OK; - break; - } - break; - default: - break; - } - - *response = ret; - - return ((1U << 16) | 1U); -} - -// Process UART Configure command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t UART_Configure (const uint8_t *request, uint8_t *response) { - uint8_t control, status; - uint32_t baudrate; - int32_t result; - - if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { - status = DAP_UART_CFG_ERROR_DATA_BITS | - DAP_UART_CFG_ERROR_PARITY | - DAP_UART_CFG_ERROR_STOP_BITS; - baudrate = 0U; // baudrate error - } else { - - status = 0U; - control = *request; - baudrate = (uint32_t)(*(request+1) << 0) | - (uint32_t)(*(request+2) << 8) | - (uint32_t)(*(request+3) << 16) | - (uint32_t)(*(request+4) << 24); - - result = pUSART->Control(control | - ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_FLOW_CONTROL_NONE, - baudrate); - if (result == ARM_DRIVER_OK) { - UartConfigured = 1U; - } else { - UartConfigured = 0U; - switch (result) { - case ARM_USART_ERROR_BAUDRATE: - status = 0U; - baudrate = 0U; - break; - case ARM_USART_ERROR_DATA_BITS: - status = DAP_UART_CFG_ERROR_DATA_BITS; - break; - case ARM_USART_ERROR_PARITY: - status = DAP_UART_CFG_ERROR_PARITY; - break; - case ARM_USART_ERROR_STOP_BITS: - status = DAP_UART_CFG_ERROR_STOP_BITS; - break; - default: - status = DAP_UART_CFG_ERROR_DATA_BITS | - DAP_UART_CFG_ERROR_PARITY | - DAP_UART_CFG_ERROR_STOP_BITS; - baudrate = 0U; - break; - } - } - } - - *response++ = status; - *response++ = (uint8_t)(baudrate >> 0); - *response++ = (uint8_t)(baudrate >> 8); - *response++ = (uint8_t)(baudrate >> 16); - *response = (uint8_t)(baudrate >> 24); - - return ((5U << 16) | 5U); -} - -// Process UART Control command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t UART_Control (const uint8_t *request, uint8_t *response) { - uint8_t control; - uint8_t result; - uint8_t ret = DAP_OK; - - if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { - ret = DAP_ERROR; - } else { - - control = *request; - - if ((control & DAP_UART_CONTROL_RX_DISABLE) != 0U) { - // Receive disable - UART_Receive_Disable(); - } else if ((control & DAP_UART_CONTROL_RX_ENABLE) != 0U) { - // Receive enable - if (UartConfigured != 0U) { - result = UART_Receive_Enable(); - if (result != DAP_OK) { - ret = DAP_ERROR; - } - } else { - ret = DAP_ERROR; - } - } - if ((control & DAP_UART_CONTROL_RX_BUF_FLUSH) != 0U) { - UART_Receive_Flush(); - } - - if ((control & DAP_UART_CONTROL_TX_DISABLE) != 0U) { - // Transmit disable - UART_Transmit_Disable(); - } else if ((control & DAP_UART_CONTROL_TX_ENABLE) != 0U) { - // Transmit enable - if (UartConfigured != 0U) { - result = UART_Transmit_Enable(); - if (result != DAP_OK) { - ret = DAP_ERROR; - } - } else { - ret = DAP_ERROR; - } - } - if ((control & DAP_UART_CONTROL_TX_BUF_FLUSH) != 0U) { - UART_Transmit_Flush(); - } - } - - *response = ret; - - return ((1U << 16) | 1U); -} - -// Process UART Status command and prepare response -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t UART_Status (uint8_t *response) { - uint32_t rx_cnt, tx_cnt; - uint32_t cnt; - uint8_t status; - - if ((UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) || - (UartConfigured == 0U)) { - rx_cnt = 0U; - tx_cnt = 0U; - status = 0U; - } else { - - rx_cnt = UartRxIndexI - UartRxIndexO; - rx_cnt += pUSART->GetRxCount(); - if (rx_cnt > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { - // Overflow - UartErrorRxDataLost = 1U; - rx_cnt = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); - UartRxIndexO = UartRxIndexI - rx_cnt; - } - - tx_cnt = UartTxIndexI - UartTxIndexO; - cnt = pUSART->GetTxCount(); - if (UartTransmitActive != 0U) { - tx_cnt -= cnt; - } - - status = UART_Get_Status(); - } - - *response++ = status; - *response++ = (uint8_t)(rx_cnt >> 0); - *response++ = (uint8_t)(rx_cnt >> 8); - *response++ = (uint8_t)(rx_cnt >> 16); - *response++ = (uint8_t)(rx_cnt >> 24); - *response++ = (uint8_t)(tx_cnt >> 0); - *response++ = (uint8_t)(tx_cnt >> 8); - *response++ = (uint8_t)(tx_cnt >> 16); - *response = (uint8_t)(tx_cnt >> 24); - - return ((0U << 16) | 9U); -} - -// Process UART Transfer command and prepare response -// request: pointer to request data -// response: pointer to response data -// return: number of bytes in response (lower 16 bits) -// number of bytes in request (upper 16 bits) -uint32_t UART_Transfer (const uint8_t *request, uint8_t *response) { - uint32_t rx_cnt, tx_cnt; - uint32_t rx_num, tx_num; - uint8_t *rx_data; - const - uint8_t *tx_data; - uint32_t num; - uint32_t index; - uint8_t status; - - if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { - status = 0U; - rx_cnt = 0U; - tx_cnt = 0U; - } else { - - // RX Data - rx_cnt = ((uint32_t)(*(request+0) << 0) | - (uint32_t)(*(request+1) << 8)); - - if (rx_cnt > (DAP_PACKET_SIZE - 6U)) { - rx_cnt = (DAP_PACKET_SIZE - 6U); - } - rx_num = UartRxIndexI - UartRxIndexO; - rx_num += pUSART->GetRxCount(); - if (rx_num > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { - // Overflow - UartErrorRxDataLost = 1U; - rx_num = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); - UartRxIndexO = UartRxIndexI - rx_num; - } - if (rx_cnt > rx_num) { - rx_cnt = rx_num; - } - - rx_data = (response+5); - index = UartRxIndexO & (DAP_UART_RX_BUFFER_SIZE - 1U); - if ((index + rx_cnt) <= DAP_UART_RX_BUFFER_SIZE) { - memcpy( rx_data, &UartRxBuf[index], rx_cnt); - } else { - num = DAP_UART_RX_BUFFER_SIZE - index; - memcpy( rx_data, &UartRxBuf[index], num); - memcpy(&rx_data[num], &UartRxBuf[0], rx_cnt - num); - } - UartRxIndexO += rx_cnt; - - // TX Data - tx_cnt = ((uint32_t)(*(request+2) << 0) | - (uint32_t)(*(request+3) << 8)); - tx_data = (request+4); - - if (tx_cnt > (DAP_PACKET_SIZE - 5U)) { - tx_cnt = (DAP_PACKET_SIZE - 5U); - } - tx_num = UartTxIndexI - UartTxIndexO; - num = pUSART->GetTxCount(); - if (UartTransmitActive != 0U) { - tx_num -= num; - } - if (tx_cnt > (DAP_UART_TX_BUFFER_SIZE - tx_num)) { - tx_cnt = (DAP_UART_TX_BUFFER_SIZE - tx_num); - } - - index = UartTxIndexI & (DAP_UART_TX_BUFFER_SIZE - 1U); - if ((index + tx_cnt) <= DAP_UART_TX_BUFFER_SIZE) { - memcpy(&UartTxBuf[index], tx_data, tx_cnt); - } else { - num = DAP_UART_TX_BUFFER_SIZE - index; - memcpy(&UartTxBuf[index], tx_data, num); - memcpy(&UartTxBuf[0], &tx_data[num], tx_cnt - num); - } - UartTxIndexI += tx_cnt; - - if (UartTransmitActive == 0U) { - UART_Transmit(); - } - - status = UART_Get_Status(); - } - - *response++ = status; - *response++ = (uint8_t)(tx_cnt >> 0); - *response++ = (uint8_t)(tx_cnt >> 8); - *response++ = (uint8_t)(rx_cnt >> 0); - *response = (uint8_t)(rx_cnt >> 8); - - return (((4U + tx_cnt) << 16) | (5U + rx_cnt)); -} - -#endif /* DAP_UART */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/CMSIS_DAP_v2.inf b/external/CMSIS_5/CMSIS/DAP/Firmware/Template/CMSIS_DAP_v2.inf deleted file mode 100644 index 287f04a..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/CMSIS_DAP_v2.inf +++ /dev/null @@ -1,54 +0,0 @@ -[Version] -Signature = "$Windows NT$" -Class = USBDevice -ClassGUID = {88BAE032-5A81-49f0-BC3D-A4FF138216D6} -Provider = %ManufacturerName% -DriverVer = 04/13/2016, 1.0.0.0 -CatalogFile.nt = CMSIS_DAP_v2_x86.cat -CatalogFile.ntx86 = CMSIS_DAP_v2_x86.cat -CatalogFile.ntamd64 = CMSIS_DAP_v2_amd64.cat - -; ========== Manufacturer/Models sections =========== - -[Manufacturer] -%ManufacturerName% = Devices, NTx86, NTamd64 - -[Devices.NTx86] -%DeviceName% = USB_Install, USB\VID_c251&PID_f000 - -[Devices.NTamd64] -%DeviceName% = USB_Install, USB\VID_c251&PID_f000 - -; ========== Class definition =========== - -[ClassInstall32] -AddReg = ClassInstall_AddReg - -[ClassInstall_AddReg] -HKR,,,,%ClassName% -HKR,,NoInstallClass,,1 -HKR,,IconPath,0x10000,"%%SystemRoot%%\System32\setupapi.dll,-20" -HKR,,LowerLogoVersion,,5.2 - -; =================== Installation =================== - -[USB_Install] -Include = winusb.inf -Needs = WINUSB.NT - -[USB_Install.Services] -Include = winusb.inf -Needs = WINUSB.NT.Services - -[USB_Install.HW] -AddReg = Dev_AddReg - -[Dev_AddReg] -HKR,,DeviceInterfaceGUIDs,0x10000,"{CDB3B5AD-293B-4663-AA36-1AAE46463776}" - -; =================== Strings =================== - -[Strings] -ClassName = "Universal Serial Bus devices" -ManufacturerName = "KEIL - Tools By ARM" -DeviceName = "CMSIS-DAP v2" diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_CDC_ACM_UART_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_CDC_ACM_UART_0.c deleted file mode 100644 index 7f12203..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_CDC_ACM_UART_0.c +++ /dev/null @@ -1,381 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device:CDC - * Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_User_CDC_ACM_UART_0.c - * Purpose: USB Device Communication Device Class (CDC) - * Abstract Control Model (ACM) USB <-> UART Bridge User module - * Rev.: V1.0.8 - *----------------------------------------------------------------------------*/ -/** - * \addtogroup usbd_cdcFunctions - * - * USBD_User_CDC_ACM_UART_0.c implements the application specific - * functionality of the CDC ACM class and is used to demonstrate a USB <-> UART - * bridge. All data received on USB is transmitted on UART and all data - * received on UART is transmitted on USB. - * - * Details of operation: - * UART -> USB: - * Initial reception on UART is started after the USB Host sets line coding - * with SetLineCoding command. Having received a full UART buffer, any - * new reception is restarted on the same buffer. Any data received on - * the UART is sent over USB using the CDC0_ACM_UART_to_USB_Thread thread. - * USB -> UART: - * While the UART transmit is not busy, data transmission on the UART is - * started in the USBD_CDC0_ACM_DataReceived callback as soon as data is - * received on the USB. Further data received on USB is transmitted on - * UART in the UART callback routine until there is no more data available. - * In this case, the next UART transmit is restarted from the - * USBD_CDC0_ACM_DataReceived callback as soon as new data is received - * on the USB. - * - * The following constants in this module affect the module functionality: - * - * - UART_PORT: specifies UART Port - * default value: 0 (=UART0) - * - UART_BUFFER_SIZE: specifies UART data Buffer Size - * default value: 512 - * - * Notes: - * If the USB is slower than the UART, data can get lost. This may happen - * when USB is pausing during data reception because of the USB Host being - * too loaded with other tasks and not polling the Bulk IN Endpoint often - * enough (up to 2 seconds of gap in polling Bulk IN Endpoint may occur). - * This problem can be solved by using a large enough UART buffer to - * compensate up to a few seconds of received UART data or by using UART - * flow control. - * If the device that receives the UART data (usually a PC) is too loaded - * with other tasks it can also loose UART data. This problem can only be - * solved by using UART flow control. - * - * This file has to be adapted in case of UART flow control usage. - */ - - -//! [code_USBD_User_CDC_ACM] -#include -#include - -#include "rl_usb.h" - -#include "Driver_USART.h" - -#include "DAP_config.h" -#include "DAP.h" - -// UART Configuration ---------------------------------------------------------- - -#define UART_BUFFER_SIZE (512) // UART Buffer Size - -//------------------------------------------------------------------------------ - -#define _UART_Driver_(n) Driver_USART##n -#define UART_Driver_(n) _UART_Driver_(n) -extern ARM_DRIVER_USART UART_Driver_(DAP_UART_DRIVER); -#define ptrUART (&UART_Driver_(DAP_UART_DRIVER)) - -// Local Variables -static uint8_t uart_rx_buf[UART_BUFFER_SIZE]; -static uint8_t uart_tx_buf[UART_BUFFER_SIZE]; - -static volatile int32_t uart_rx_cnt = 0; -static volatile int32_t usb_tx_cnt = 0; - -static void *cdc_acm_bridge_tid = 0U; -static CDC_LINE_CODING cdc_acm_line_coding = { 0U, 0U, 0U, 0U }; - -static uint8_t cdc_acm_active = 1U; -static osMutexId_t cdc_acm_mutex_id = NULL; - -// Acquire mutex -__STATIC_INLINE void CDC_ACM_Lock (void) { - if (cdc_acm_mutex_id == NULL) { - cdc_acm_mutex_id = osMutexNew(NULL); - } - osMutexAcquire(cdc_acm_mutex_id, osWaitForever); -} - -// Release mutex -__STATIC_INLINE void CDC_ACM_Unlock (void) { - osMutexRelease(cdc_acm_mutex_id); -} - -// Change communication settings. -// \param[in] line_coding pointer to CDC_LINE_CODING structure. -// \return true set line coding request processed. -// \return false set line coding request not supported or not processed. -static bool CDC_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) { - uint32_t data_bits = 0U, parity = 0U, stop_bits = 0U; - int32_t status; - - (void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U); - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); - (void)ptrUART->Control (ARM_USART_CONTROL_TX, 0U); - (void)ptrUART->Control (ARM_USART_CONTROL_RX, 0U); - - switch (line_coding->bCharFormat) { - case 0: // 1 Stop bit - stop_bits = ARM_USART_STOP_BITS_1; - break; - case 1: // 1.5 Stop bits - stop_bits = ARM_USART_STOP_BITS_1_5; - break; - case 2: // 2 Stop bits - stop_bits = ARM_USART_STOP_BITS_2; - break; - default: - return false; - } - - switch (line_coding->bParityType) { - case 0: // None - parity = ARM_USART_PARITY_NONE; - break; - case 1: // Odd - parity = ARM_USART_PARITY_ODD; - break; - case 2: // Even - parity = ARM_USART_PARITY_EVEN; - break; - default: - return false; - } - - switch (line_coding->bDataBits) { - case 5: - data_bits = ARM_USART_DATA_BITS_5; - break; - case 6: - data_bits = ARM_USART_DATA_BITS_6; - break; - case 7: - data_bits = ARM_USART_DATA_BITS_7; - break; - case 8: - data_bits = ARM_USART_DATA_BITS_8; - break; - default: - return false; - } - - status = ptrUART->Control(ARM_USART_MODE_ASYNCHRONOUS | - data_bits | - parity | - stop_bits , - line_coding->dwDTERate ); - - if (status != ARM_DRIVER_OK) { - return false; - } - - // Store requested settings to local variable - memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding)); - - uart_rx_cnt = 0; - usb_tx_cnt = 0; - - (void)ptrUART->Control (ARM_USART_CONTROL_TX, 1U); - (void)ptrUART->Control (ARM_USART_CONTROL_RX, 1U); - - (void)ptrUART->Receive (uart_rx_buf, UART_BUFFER_SIZE); - - return true; -} - -// Activate or Deactivate USBD COM PORT -// \param[in] cmd 0=deactivate, 1=activate -// \return 0=Ok, 0xFF=Error -uint8_t USB_COM_PORT_Activate (uint32_t cmd) { - switch (cmd) { - case 0U: - cdc_acm_active = 0U; - USBD_CDC0_ACM_Uninitialize(); - break; - case 1U: - USBD_CDC0_ACM_Initialize(); - CDC_ACM_Lock(); - CDC_ACM_SetLineCoding(&cdc_acm_line_coding); - cdc_acm_active = 1U; - CDC_ACM_Unlock(); - break; - } - - return 0U; -} - -// Called when UART has transmitted or received requested number of bytes. -// \param[in] event UART event -// - ARM_USART_EVENT_SEND_COMPLETE: all requested data was sent -// - ARM_USART_EVENT_RECEIVE_COMPLETE: all requested data was received -static void UART_Callback (uint32_t event) { - int32_t cnt; - - if (cdc_acm_active == 0U) { - return; - } - - if (event & ARM_USART_EVENT_SEND_COMPLETE) { - // USB -> UART - cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE); - if (cnt > 0) { - (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt)); - } - } - - if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { - // UART data received, restart new reception - uart_rx_cnt += UART_BUFFER_SIZE; - (void)ptrUART->Receive(uart_rx_buf, UART_BUFFER_SIZE); - } -} - -// Thread: Sends data received on UART to USB -// \param[in] arg not used. -__NO_RETURN static void CDC0_ACM_UART_to_USB_Thread (void *arg) { - int32_t cnt, cnt_to_wrap; - - (void)(arg); - - for (;;) { - // UART - > USB - if (ptrUART->GetStatus().rx_busy != 0U) { - cnt = uart_rx_cnt; - cnt += (int32_t)ptrUART->GetRxCount(); - cnt -= usb_tx_cnt; - if (cnt >= (UART_BUFFER_SIZE - 32)) { - // Dump old data in UART receive buffer if USB is not consuming fast enough - cnt = (UART_BUFFER_SIZE - 32); - usb_tx_cnt = uart_rx_cnt - (UART_BUFFER_SIZE - 32); - } - if (cnt > 0) { - cnt_to_wrap = (int32_t)(UART_BUFFER_SIZE - ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))); - if (cnt > cnt_to_wrap) { - cnt = cnt_to_wrap; - } - cnt = USBD_CDC_ACM_WriteData(0U, (uart_rx_buf + ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))), cnt); - if (cnt > 0) { - usb_tx_cnt += cnt; - } - } - } - (void)osDelay(10U); - } -} - -static osRtxThread_t cdc0_acm_uart_to_usb_thread_cb_mem __SECTION(.bss.os.thread.cb); -static uint64_t cdc0_acm_uart_to_usb_thread_stack_mem[512U / 8U] __SECTION(.bss.os.thread.cdc.stack); -static const osThreadAttr_t cdc0_acm_uart_to_usb_thread_attr = { - "CDC0_ACM_UART_to_USB_Thread", - 0U, - &cdc0_acm_uart_to_usb_thread_cb_mem, - sizeof(osRtxThread_t), - &cdc0_acm_uart_to_usb_thread_stack_mem[0], - sizeof(cdc0_acm_uart_to_usb_thread_stack_mem), - osPriorityNormal, - 0U, - 0U -}; - - -// CDC ACM Callbacks ----------------------------------------------------------- - -// Called when new data was received from the USB Host. -// \param[in] len number of bytes available to read. -void USBD_CDC0_ACM_DataReceived (uint32_t len) { - int32_t cnt; - - (void)(len); - - if (cdc_acm_active == 0U) { - return; - } - - if (ptrUART->GetStatus().tx_busy == 0U) { - // Start USB -> UART - cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE); - if (cnt > 0) { - (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt)); - } - } -} - -// Called during USBD_Initialize to initialize the USB CDC class instance (ACM). -void USBD_CDC0_ACM_Initialize (void) { - (void)ptrUART->Initialize (UART_Callback); - (void)ptrUART->PowerControl (ARM_POWER_FULL); - - cdc_acm_bridge_tid = osThreadNew (CDC0_ACM_UART_to_USB_Thread, NULL, &cdc0_acm_uart_to_usb_thread_attr); -} - - -// Called during USBD_Uninitialize to de-initialize the USB CDC class instance (ACM). -void USBD_CDC0_ACM_Uninitialize (void) { - if (osThreadTerminate (cdc_acm_bridge_tid) == osOK) { - cdc_acm_bridge_tid = NULL; - } - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); - (void)ptrUART->PowerControl (ARM_POWER_OFF); - (void)ptrUART->Uninitialize (); -} - - -// Called upon USB Bus Reset Event. -void USBD_CDC0_ACM_Reset (void) { - if (cdc_acm_active == 0U ) { - return; - } - (void)ptrUART->Control (ARM_USART_ABORT_SEND, 0U); - (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U); -} - - -// Called upon USB Host request to change communication settings. -// \param[in] line_coding pointer to CDC_LINE_CODING structure. -// \return true set line coding request processed. -// \return false set line coding request not supported or not processed. -bool USBD_CDC0_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) { - bool ret = false; - - CDC_ACM_Lock(); - if (cdc_acm_active == 0U) { - // Store requested settings to local variable - memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding)); - ret = true; - } else { - ret = CDC_ACM_SetLineCoding(line_coding); - } - CDC_ACM_Unlock(); - - return ret; -} - - -// Called upon USB Host request to retrieve communication settings. -// \param[out] line_coding pointer to CDC_LINE_CODING structure. -// \return true get line coding request processed. -// \return false get line coding request not supported or not processed. -bool USBD_CDC0_ACM_GetLineCoding (CDC_LINE_CODING *line_coding) { - - // Load settings from ones stored on USBD_CDC0_ACM_SetLineCoding callback - *line_coding = cdc_acm_line_coding; - - return true; -} - - -// Called upon USB Host request to set control line states. -// \param [in] state control line settings bitmap. -// - bit 0: DTR state -// - bit 1: RTS state -// \return true set control line state request processed. -// \return false set control line state request not supported or not processed. -bool USBD_CDC0_ACM_SetControlLineState (uint16_t state) { - // Add code for set control line state - - (void)(state); - - return true; -} - -//! [code_USBD_User_CDC_ACM] diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_CustomClass_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_CustomClass_0.c deleted file mode 100644 index 186c7b9..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_CustomClass_0.c +++ /dev/null @@ -1,358 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2016 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_User_CustomClass_0.c - * Purpose: USB Device Custom Class User module - * Rev.: V6.7.3 - *----------------------------------------------------------------------------*/ -/* - * USBD_User_CustomClass_0.c is a code template for the Custom Class 0 - * class request handling. It allows user to handle all Custom Class class - * requests. - * - * Uncomment "Example code" lines to see example that receives data on - * Endpoint 1 OUT and echoes it back on Endpoint 1 IN. - * To try the example you also have to enable Bulk Endpoint 1 IN/OUT in Custom - * Class configuration in USBD_Config_CustomClass_0.h file. - */ - -/** - * \addtogroup usbd_custom_classFunctions - * - */ - - -//! [code_USBD_User_CustomClass] - -#include -#include -#include -#include "cmsis_os2.h" -#define osObjectsExternal -#include "osObjects.h" -#include "rl_usb.h" -#include "Driver_USBD.h" -#include "DAP_config.h" -#include "DAP.h" - -static volatile uint16_t USB_RequestIndexI; // Request Index In -static volatile uint16_t USB_RequestIndexO; // Request Index Out -static volatile uint16_t USB_RequestCountI; // Request Count In -static volatile uint16_t USB_RequestCountO; // Request Count Out -static volatile uint8_t USB_RequestIdle; // Request Idle Flag - -static volatile uint16_t USB_ResponseIndexI; // Response Index In -static volatile uint16_t USB_ResponseIndexO; // Response Index Out -static volatile uint16_t USB_ResponseCountI; // Response Count In -static volatile uint16_t USB_ResponseCountO; // Response Count Out -static volatile uint8_t USB_ResponseIdle; // Response Idle Flag - -static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Request Buffer -static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO"))); // Response Buffer -static uint16_t USB_RespSize[DAP_PACKET_COUNT]; // Response Size - -// \brief Callback function called during USBD_Initialize to initialize the USB Custom class instance -void USBD_CustomClass0_Initialize (void) { - // Handle Custom Class Initialization - - // Initialize variables - USB_RequestIndexI = 0U; - USB_RequestIndexO = 0U; - USB_RequestCountI = 0U; - USB_RequestCountO = 0U; - USB_RequestIdle = 1U; - USB_ResponseIndexI = 0U; - USB_ResponseIndexO = 0U; - USB_ResponseCountI = 0U; - USB_ResponseCountO = 0U; - USB_ResponseIdle = 1U; -} - -// \brief Callback function called during USBD_Uninitialize to de-initialize the USB Custom class instance -void USBD_CustomClass0_Uninitialize (void) { - // Handle Custom Class De-initialization -} - -// \brief Callback function called upon USB Bus Reset signaling -void USBD_CustomClass0_Reset (void) { - // Handle USB Bus Reset Event -} - -// \brief Callback function called when Endpoint Start was requested (by activating interface or configuration) -// \param[in] ep_addr endpoint address. -void USBD_CustomClass0_EndpointStart (uint8_t ep_addr) { - // Start communication on Endpoint - if (ep_addr == USB_ENDPOINT_OUT(1U)) { - USB_RequestIdle = 0U; - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[0], DAP_PACKET_SIZE); - } -} - -// \brief Callback function called when Endpoint Stop was requested (by de-activating interface or activating configuration 0) -// \param[in] ep_addr endpoint address. -void USBD_CustomClass0_EndpointStop (uint8_t ep_addr) { - // Handle Endpoint communication stopped - (void)ep_addr; -} - -// \brief Callback function called when Custom Class 0 received SETUP PACKET on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] setup_packet pointer to received setup packet. -// \param[out] buf pointer to data buffer used for data stage requested by setup packet. -// \param[out] len pointer to number of data bytes in data stage requested by setup packet. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet if no data stage) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -usbdRequestStatus USBD_CustomClass0_Endpoint0_SetupPacketReceived (const USB_SETUP_PACKET *setup_packet, uint8_t **buf, uint32_t *len) { - (void)setup_packet; - (void)buf; - (void)len; - - switch (setup_packet->bmRequestType.Recipient) { - case USB_REQUEST_TO_DEVICE: - break; - case USB_REQUEST_TO_INTERFACE: - break; - case USB_REQUEST_TO_ENDPOINT: - break; - default: - break; - } - - return usbdRequestNotProcessed; -} - -// \brief Callback function called when SETUP PACKET was processed by USB library -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback nor by Custom Class callback) -// \param[in] setup_packet pointer to processed setup packet. -void USBD_CustomClass0_Endpoint0_SetupPacketProcessed (const USB_SETUP_PACKET *setup_packet) { - (void)setup_packet; - - switch (setup_packet->bmRequestType.Recipient) { - case USB_REQUEST_TO_DEVICE: - break; - case USB_REQUEST_TO_INTERFACE: - break; - case USB_REQUEST_TO_ENDPOINT: - break; - default: - break; - } -} - -// \brief Callback function called when Custom Class 0 received OUT DATA on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] len number of received data bytes. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (send Zero-Length Packet) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -// \return usbdRequestNAK: request was processed but the device is busy (return NAK) -usbdRequestStatus USBD_CustomClass0_Endpoint0_OutDataReceived (uint32_t len) { - (void)len; - return usbdRequestNotProcessed; -} - -// \brief Callback function called when Custom Class 0 sent IN DATA on Control Endpoint 0 -// (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed -// previously by Device callback) -// \param[in] len number of sent data bytes. -// \return usbdRequestStatus enumerator value indicating the function execution status -// \return usbdRequestNotProcessed:request was not processed; processing will be done by USB library -// \return usbdRequestOK: request was processed successfully (return ACK) -// \return usbdRequestStall: request was processed but is not supported (stall Endpoint 0) -// \return usbdRequestNAK: request was processed but the device is busy (return NAK) -usbdRequestStatus USBD_CustomClass0_Endpoint0_InDataSent (uint32_t len) { - (void)len; - return usbdRequestNotProcessed; -} - -// \brief Callback function called when DATA was sent or received on Endpoint n -// \param[in] event event on Endpoint: -// - ARM_USBD_EVENT_OUT = data OUT received -// - ARM_USBD_EVENT_IN = data IN sent -void USBD_CustomClass0_Endpoint1_Event (uint32_t event) { - // Handle Endpoint 1 events - uint32_t n; - - if (event & ARM_USBD_EVENT_OUT) { - n = USBD_EndpointReadGetResult(0U, USB_ENDPOINT_OUT(1U)); - if (n != 0U) { - if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) { - DAP_TransferAbort = 1U; - } else { - USB_RequestIndexI++; - if (USB_RequestIndexI == DAP_PACKET_COUNT) { - USB_RequestIndexI = 0U; - } - USB_RequestCountI++; - osThreadFlagsSet(DAP_ThreadId, 0x01); - } - } - // Start reception of next request packet - if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); - } else { - USB_RequestIdle = 1U; - } - } - if (event & ARM_USBD_EVENT_IN) { - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]); - USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - } else { - USB_ResponseIdle = 1U; - } - } -} -void USBD_CustomClass0_Endpoint2_Event (uint32_t event) { - // Handle Endpoint 2 events - if (event & ARM_USBD_EVENT_IN) { - SWO_TransferComplete(); - } -} -void USBD_CustomClass0_Endpoint3_Event (uint32_t event) { - // Handle Endpoint 3 events - (void)event; -} -void USBD_CustomClass0_Endpoint4_Event (uint32_t event) { - // Handle Endpoint 4 events - (void)event; -} -void USBD_CustomClass0_Endpoint5_Event (uint32_t event) { - // Handle Endpoint 5 events - (void)event; -} -void USBD_CustomClass0_Endpoint6_Event (uint32_t event) { - // Handle Endpoint 6 events - (void)event; -} -void USBD_CustomClass0_Endpoint7_Event (uint32_t event) { - // Handle Endpoint 7 events - (void)event; -} -void USBD_CustomClass0_Endpoint8_Event (uint32_t event) { - // Handle Endpoint 8 events - (void)event; -} -void USBD_CustomClass0_Endpoint9_Event (uint32_t event) { - // Handle Endpoint 9 events - (void)event; -} -void USBD_CustomClass0_Endpoint10_Event (uint32_t event) { - // Handle Endpoint 10 events - (void)event; -} -void USBD_CustomClass0_Endpoint11_Event (uint32_t event) { - // Handle Endpoint 11 events - (void)event; -} -void USBD_CustomClass0_Endpoint12_Event (uint32_t event) { - // Handle Endpoint 12 events - (void)event; -} -void USBD_CustomClass0_Endpoint13_Event (uint32_t event) { - // Handle Endpoint 13 events - (void)event; -} -void USBD_CustomClass0_Endpoint14_Event (uint32_t event) { - // Handle Endpoint 14 events - (void)event; -} -void USBD_CustomClass0_Endpoint15_Event (uint32_t event) { - // Handle Endpoint 15 events - (void)event; -} - -// DAP Thread. -__NO_RETURN void DAP_Thread (void *argument) { - uint32_t flags; - uint32_t n; - (void) argument; - - for (;;) { - osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - - // Process pending requests - while (USB_RequestCountI != USB_RequestCountO) { - - // Handle Queue Commands - n = USB_RequestIndexO; - while (USB_Request[n][0] == ID_DAP_QueueCommands) { - USB_Request[n][0] = ID_DAP_ExecuteCommands; - n++; - if (n == DAP_PACKET_COUNT) { - n = 0U; - } - if (n == USB_RequestIndexI) { - flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - if (flags & 0x80U) { - break; - } - } - } - - // Execute DAP Command (process request and prepare response) - USB_RespSize[USB_ResponseIndexI] = - (uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]); - - // Update Request Index and Count - USB_RequestIndexO++; - if (USB_RequestIndexO == DAP_PACKET_COUNT) { - USB_RequestIndexO = 0U; - } - USB_RequestCountO++; - - if (USB_RequestIdle) { - if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { - USB_RequestIdle = 0U; - USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); - } - } - - // Update Response Index and Count - USB_ResponseIndexI++; - if (USB_ResponseIndexI == DAP_PACKET_COUNT) { - USB_ResponseIndexI = 0U; - } - USB_ResponseCountI++; - - if (USB_ResponseIdle) { - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - n = USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - USB_ResponseIdle = 0U; - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[n], USB_RespSize[n]); - } - } - } - } -} - -// SWO Data Queue Transfer -// buf: pointer to buffer with data -// num: number of bytes to transfer -void SWO_QueueTransfer (uint8_t *buf, uint32_t num) { - USBD_EndpointWrite(0U, USB_ENDPOINT_IN(2U), buf, num); -} - -// SWO Data Abort Transfer -void SWO_AbortTransfer (void) { - USBD_EndpointAbort(0U, USB_ENDPOINT_IN(2U)); -} - -//! [code_USBD_User_CustomClass] diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_HID_0.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_HID_0.c deleted file mode 100644 index 206537b..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_HID_0.c +++ /dev/null @@ -1,246 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::USB:Device - * Copyright (c) 2004-2017 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: USBD_User_HID_0.c - * Purpose: USB Device Human Interface Device class (HID) User module - * Rev.: V6.2.3 - *----------------------------------------------------------------------------*/ -/** - * \addtogroup usbd_hidFunctions - * - * USBD_User_HID_0.c implements the application specific functionality of the - * HID class and is used to receive and send data reports to the USB Host. - * - * The implementation must match the configuration file USBD_Config_HID_0.h. - * The following values in USBD_Config_HID_0.h affect the user code: - * - * - 'Endpoint polling Interval' specifies the frequency of requests - * initiated by USB Host for \ref USBD_HIDn_GetReport. - * - * - 'Number of Output Reports' configures the values for \em rid of - * \ref USBD_HIDn_SetReport. - * - * - 'Number of Input Reports' configures the values for \em rid of - * \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger. - * - * - 'Maximum Input Report Size' specifies the maximum value for: - * - return of \ref USBD_HIDn_GetReport - * - len of \ref USBD_HID_GetReportTrigger. - * - * - 'Maximum Output Report Size' specifies the maximum value for \em len - * in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT - * - * - 'Maximum Feature Report Size' specifies the maximum value for \em len - * in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE - * - */ - - -//! [code_USBD_User_HID] - -#include -#include -#include "cmsis_os2.h" -#define osObjectsExternal -#include "osObjects.h" -#include "rl_usb.h" -#include "RTE\USB\USBD_Config_HID_0.h" -#include "DAP_config.h" -#include "DAP.h" - - -#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE) -#error "USB HID0 Output Report Size must match DAP Packet Size" -#endif -#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE) -#error "USB HID Input Report Size must match DAP Packet Size" -#endif - -static volatile uint16_t USB_RequestIndexI; // Request Index In -static volatile uint16_t USB_RequestIndexO; // Request Index Out -static volatile uint16_t USB_RequestCountI; // Request Count In -static volatile uint16_t USB_RequestCountO; // Request Count Out - -static volatile uint16_t USB_ResponseIndexI; // Response Index In -static volatile uint16_t USB_ResponseIndexO; // Response Index Out -static volatile uint16_t USB_ResponseCountI; // Response Count In -static volatile uint16_t USB_ResponseCountO; // Response Count Out -static volatile uint8_t USB_ResponseIdle; // Response Idle Flag - -static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer -static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer - - -// Called during USBD_Initialize to initialize the USB HID class instance. -void USBD_HID0_Initialize (void) { - // Initialize variables - USB_RequestIndexI = 0U; - USB_RequestIndexO = 0U; - USB_RequestCountI = 0U; - USB_RequestCountO = 0U; - USB_ResponseIndexI = 0U; - USB_ResponseIndexO = 0U; - USB_ResponseCountI = 0U; - USB_ResponseCountO = 0U; - USB_ResponseIdle = 1U; -} - - -// Called during USBD_Uninitialize to de-initialize the USB HID class instance. -void USBD_HID0_Uninitialize (void) { -} - - -// \brief Prepare HID Report data to send. -// \param[in] rtype report type: -// - HID_REPORT_INPUT = input report requested -// - HID_REPORT_FEATURE = feature report requested -// \param[in] req request type: -// - USBD_HID_REQ_EP_CTRL = control endpoint request -// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request -// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request -// \param[in] rid report ID (0 if only one report exists). -// \param[out] buf buffer containing report data to send. -// \return number of report data bytes prepared to send or invalid report requested. -// - value >= 0: number of report data bytes prepared to send -// - value = -1: invalid report requested -int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) { - (void)rid; - - switch (rtype) { - case HID_REPORT_INPUT: - switch (req) { - case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint - case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint - break; - case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained. - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE); - USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - return ((int32_t)DAP_PACKET_SIZE); - } else { - USB_ResponseIdle = 1U; - } - break; - } - break; - case HID_REPORT_FEATURE: - break; - } - return (0); -} - - -// \brief Process received HID Report data. -// \param[in] rtype report type: -// - HID_REPORT_OUTPUT = output report received -// - HID_REPORT_FEATURE = feature report received -// \param[in] req request type: -// - USBD_HID_REQ_EP_CTRL = report received on control endpoint -// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint -// \param[in] rid report ID (0 if only one report exists). -// \param[in] buf buffer that receives report data. -// \param[in] len length of received report data. -// \return true received report data processed. -// \return false received report data not processed or request not supported. -bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) { - (void)req; - (void)rid; - - switch (rtype) { - case HID_REPORT_OUTPUT: - if (len == 0) { - break; - } - if (buf[0] == ID_DAP_TransferAbort) { - DAP_TransferAbort = 1U; - break; - } - if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) { - osThreadFlagsSet(DAP_ThreadId, 0x80U); - break; // Discard packet when buffer is full - } - // Store received data into request buffer - memcpy(USB_Request[USB_RequestIndexI], buf, (uint32_t)len); - USB_RequestIndexI++; - if (USB_RequestIndexI == DAP_PACKET_COUNT) { - USB_RequestIndexI = 0U; - } - USB_RequestCountI++; - osThreadFlagsSet(DAP_ThreadId, 0x01U); - break; - case HID_REPORT_FEATURE: - break; - } - return true; -} - - -// DAP Thread. -__NO_RETURN void DAP_Thread (void *argument) { - uint32_t flags; - uint32_t n; - (void) argument; - - for (;;) { - osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - - // Process pending requests - while (USB_RequestCountI != USB_RequestCountO) { - - // Handle Queue Commands - n = USB_RequestIndexO; - while (USB_Request[n][0] == ID_DAP_QueueCommands) { - USB_Request[n][0] = ID_DAP_ExecuteCommands; - n++; - if (n == DAP_PACKET_COUNT) { - n = 0U; - } - if (n == USB_RequestIndexI) { - flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever); - if (flags & 0x80U) { - break; - } - } - } - - // Execute DAP Command (process request and prepare response) - DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]); - - // Update Request Index and Count - USB_RequestIndexO++; - if (USB_RequestIndexO == DAP_PACKET_COUNT) { - USB_RequestIndexO = 0U; - } - USB_RequestCountO++; - - // Update Response Index and Count - USB_ResponseIndexI++; - if (USB_ResponseIndexI == DAP_PACKET_COUNT) { - USB_ResponseIndexI = 0U; - } - USB_ResponseCountI++; - - if (USB_ResponseIdle) { - if (USB_ResponseCountI != USB_ResponseCountO) { - // Load data from response buffer to be sent back - n = USB_ResponseIndexO++; - if (USB_ResponseIndexO == DAP_PACKET_COUNT) { - USB_ResponseIndexO = 0U; - } - USB_ResponseCountO++; - USB_ResponseIdle = 0U; - USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE); - } - } - } - } -} - -//! [code_USBD_User_HID] diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/main.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/main.c deleted file mode 100644 index 8c354a8..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/main.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2013-2021 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 21. May 2021 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Template MDK5 - * Title: main.c CMSIS-DAP Main module - * - *---------------------------------------------------------------------------*/ - -#include "cmsis_os2.h" -#include "osObjects.h" -#include "rl_usb.h" -#include "DAP_config.h" -#include "DAP.h" - -// Application Main program -__NO_RETURN void app_main (void *argument) { - (void)argument; - - DAP_Setup(); // DAP Setup - - USBD_Initialize(0U); // USB Device Initialization - USBD_Connect(0U); // USB Device Connect - - while (!USBD_Configured(0U)); // Wait for USB Device to configure - - LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED - LED_RUNNING_OUT(1U); // Turn on Target Running LED - Delayms(500U); // Wait for 500ms - LED_RUNNING_OUT(0U); // Turn off Target Running LED - LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED - - // Create DAP Thread - DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr); - - // Create SWO Thread - SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr); - - osDelay(osWaitForever); - for (;;) {} -} - -int main (void) { - - SystemCoreClockUpdate(); - osKernelInitialize(); // Initialize CMSIS-RTOS - osThreadNew(app_main, NULL, NULL); // Create application main thread - if (osKernelGetState() == osKernelReady) { - osKernelStart(); // Start thread execution - } - - for (;;) {} -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/osObjects.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/osObjects.h deleted file mode 100644 index 4662c22..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Template/MDK5/osObjects.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 11. June 2021 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Template MDK5 - * Title: osObjects.h CMSIS-DAP RTOS2 Objects - * - *---------------------------------------------------------------------------*/ - -#ifndef __osObjects_h__ -#define __osObjects_h__ - -#include "cmsis_os2.h" - -#ifdef osObjectsExternal -extern osThreadId_t DAP_ThreadId; -extern osThreadId_t SWO_ThreadId; -#else -static const osThreadAttr_t DAP_ThreadAttr = { - .priority = osPriorityNormal -}; -static const osThreadAttr_t SWO_ThreadAttr = { - .priority = osPriorityAboveNormal -}; -extern osThreadId_t DAP_ThreadId; - osThreadId_t DAP_ThreadId; -extern osThreadId_t SWO_ThreadId; - osThreadId_t SWO_ThreadId; -#endif - -extern void DAP_Thread (void *argument); -extern void SWO_Thread (void *argument); - -extern void app_main (void *argument); - -#endif /* __osObjects_h__ */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/README.md b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/README.md deleted file mode 100644 index 8467e3a..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/README.md +++ /dev/null @@ -1,37 +0,0 @@ -CMSIS-DAP debug unit validation -------------------------------- - -The following debug functionality is tested: - -- Execution breakpoint with hit count -- Breakpoint on read -- Breakpoint on write -- Memory read -- Memory write -- Register read -- Register write -- Single stepping -- Run/stop debugging - -The test is self-contained and can be executed on the hardware target. - -To configure the test for a specific hardware target: - -1. Open the µVision project and select device mounted on hardware target - (automatically selects flash algorithm for download). -2. Select CMSIS-DAP as the debugger (if not already selected). -3. Build the project. - -To run the test on the hardware target: - -1. Connect the CMSIS-DAP debug unit via JTAG/SWD to the hardware target. -2. Connect the CMSIS-DAP debug unit under test to a PC via USB. -3. Open the µVision project and start a debug session. -4. Test results are printed into a `test.log` file. - -To run the test on the target in batch mode, open a Command window and execute: -``` -C:\> .\test.bat -``` - -Test results are printed into a `test_results.txt` file. diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/startup_ARMCM3.s b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/startup_ARMCM3.s deleted file mode 100644 index 16e56b0..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/startup_ARMCM3.s +++ /dev/null @@ -1,262 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM3.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM3 Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 0: Watchdog Timer - DCD RTC_IRQHandler ; 1: Real Time Clock - DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 - DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 - DCD MCIA_IRQHandler ; 4: MCIa - DCD MCIB_IRQHandler ; 5: MCIb - DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA - DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA - DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA - DCD UART4_IRQHandler ; 9: UART4 - not connected - DCD AACI_IRQHandler ; 10: AACI / AC97 - DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt - DCD ENET_IRQHandler ; 12: Ethernet - DCD USBDC_IRQHandler ; 13: USB Device - DCD USBHC_IRQHandler ; 14: USB Host Controller - DCD CHLCD_IRQHandler ; 15: Character LCD - DCD FLEXRAY_IRQHandler ; 16: Flexray - DCD CAN_IRQHandler ; 17: CAN - DCD LIN_IRQHandler ; 18: LIN - DCD I2C_IRQHandler ; 19: I2C ADC/DAC - DCD 0 ; 20: Reserved - DCD 0 ; 21: Reserved - DCD 0 ; 22: Reserved - DCD 0 ; 23: Reserved - DCD 0 ; 24: Reserved - DCD 0 ; 25: Reserved - DCD 0 ; 26: Reserved - DCD 0 ; 27: Reserved - DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD - DCD 0 ; 29: Reserved - CPU FPGA - DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA - DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT TIM0_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT MCIA_IRQHandler [WEAK] - EXPORT MCIB_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT AACI_IRQHandler [WEAK] - EXPORT CLCD_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT USBDC_IRQHandler [WEAK] - EXPORT USBHC_IRQHandler [WEAK] - EXPORT CHLCD_IRQHandler [WEAK] - EXPORT FLEXRAY_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT LIN_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT CPU_CLCD_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - -WDT_IRQHandler -RTC_IRQHandler -TIM0_IRQHandler -TIM2_IRQHandler -MCIA_IRQHandler -MCIB_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -AACI_IRQHandler -CLCD_IRQHandler -ENET_IRQHandler -USBDC_IRQHandler -USBHC_IRQHandler -CHLCD_IRQHandler -FLEXRAY_IRQHandler -CAN_IRQHandler -LIN_IRQHandler -I2C_IRQHandler -CPU_CLCD_IRQHandler -SPI_IRQHandler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/system_ARMCM3.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/system_ARMCM3.c deleted file mode 100644 index 658d154..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/system_ARMCM3.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM3.c - * @brief CMSIS Device System Source File for - * ARMCM3 Device Series - * @version V5.00 - * @date 07. September 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __Vectors; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &__Vectors; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/_CMSIS_DAP/RTE_Components.h b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/_CMSIS_DAP/RTE_Components.h deleted file mode 100644 index 1963e3e..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/RTE/_CMSIS_DAP/RTE_Components.h +++ /dev/null @@ -1,21 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'Validation' - * Target: 'CMSIS_DAP' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "ARMCM3.h" - - - -#endif /* RTE_COMPONENTS_H */ diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.CMSIS_DAP.cprj b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.CMSIS_DAP.cprj deleted file mode 100644 index 7d9dada..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.CMSIS_DAP.cprj +++ /dev/null @@ -1,45 +0,0 @@ - - - - - - - Validation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvguix b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvguix deleted file mode 100644 index b437522..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvguix +++ /dev/null @@ -1,1878 +0,0 @@ - - - - -6.1 - -
### uVision Project, (C) Keil Software
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- - - - 0 - 2560 - 1440 - - - - - - 1 - 0 - - 100 - 0 - - .\README.md - 2 - 1 - 8 - 1 - - 0 - - - - - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvoptx b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvoptx deleted file mode 100644 index 84ce206..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvoptx +++ /dev/null @@ -1,248 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - CMSIS_DAP - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 7 - - 0 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - .\test.ini - - - - - .\test.ini - BIN\CMSIS_AGDI.dll - - - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - -T0 - - - 0 - CMSIS_AGDI - -X"" -O206 -S8 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN0 - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - - - - - 0 - - - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - Source Code - 1 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - .\test.c - test.c - 0 - 0 - - - - - Documentation - 1 - 0 - 0 - 0 - - 2 - 2 - 5 - 0 - 0 - 0 - .\README.md - README.md - 0 - 0 - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - - ::Device - 1 - 0 - 0 - 1 - - - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvprojx b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvprojx deleted file mode 100644 index 42c772c..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/Validation.uvprojx +++ /dev/null @@ -1,449 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - CMSIS_DAP - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - ARMCM3 - ARM - ARM.CMSIS.5.7.0 - http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - 0 - $$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h - - - - - - - - - - $$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - Validation - 1 - 0 - 0 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 0 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x20000000 - - - - - - - - - - - - - Source Code - - - test.c - 1 - .\test.c - - - - - Documentation - - - README.md - 5 - .\README.md - - - - - ::CMSIS - - - ::Device - - - - - - - - - - - - - - - - - - - - - - - - RTE\Device\ARMCM3\startup_ARMCM3.s - - - - - - - - RTE\Device\ARMCM3\system_ARMCM3.c - - - - - - - - - - diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.bat b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.bat deleted file mode 100644 index 5ecb345..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.bat +++ /dev/null @@ -1,50 +0,0 @@ -@ECHO off - -REM Usage: test.bat [PATH TO UV4.exe] - -IF "%1"=="" ( - SET UV4_EXE=C:\Keil_v5\UV4\UV4.exe -) ELSE ( - SET UV4_EXE=%1 -) -ECHO Using %UV4_EXE% - -ECHO. -ECHO Building application... -IF EXIST .\Objects\Validation.axf del .\Objects\Validation.axf - -%UV4_EXE% -b Validation.uvprojx - -IF EXIST .\Objects\Validation.axf ( - ECHO Build succeded -) ELSE ( - ECHO Build failed - GOTO :done -) - -ECHO. -ECHO Loading application to hardware target... -%UV4_EXE% -f Validation.uvprojx -t"CMSIS_DAP" - -IF ERRORLEVEL 1 ( - ECHO Flash download failed - GOTO :done -) - -ECHO. -ECHO Debugging hardware target... -IF EXIST .\test_results.txt del .\test_results.txt - -%UV4_EXE% -d Validation.uvprojx -t"CMSIS_DAP" - -IF EXIST .\test_results.txt ( - TYPE .\test_results.txt -) ELSE ( - ECHO Test ended abnormally - file test_results.txt was not produced - GOTO :done -) - -ECHO. -ECHO All tests completed - -:done diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.c b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.c deleted file mode 100644 index 7d976a1..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------- - * - * $Date: 1. December 2017 - * $Revision: V2.0.0 - * - * Project: CMSIS-DAP Validation - * Title: test.c CMSIS-DAP debug unit test module - * - *---------------------------------------------------------------------------*/ - -// Debug Variables -volatile int test_state = 0; -volatile int test_success = 0; -volatile int bpTestCounter = 0; -volatile char mem_rw_success = 0; - int test_array1[256] = {0}; - int test_array2[256] = {0}; - -// Breakpoint Test function -static void BP_Test (void) { - int i; - - for (i = 0; i < 10; i++) { - // increment counter so we know on which iteration breakpoint is hit - bpTestCounter++; - test_state++; - } -} - -// Test function -static void Test(void) { - int i; - - test_state++; // 'test_state' = 11 - i = test_success; // 'test_success' read access - - test_state++; // 'test_state' = 12 - test_success = i; // 'test_success' write access - - test_state++; // 'test_state' = 13 - - // test_array1 should have already been written by debugger - // copy test_array1 into test_array2 for future comparison - mem_rw_success = 1; // assume all values were written correctly - for (i = 0; i < 256; i++) { - if (test_array1[i] != (0x1000+i)) { - mem_rw_success = 0; - } - test_array2[i] = test_array1[i]; - } - - test_state++; // 'test_state' = 14 - test_state++; // 'test_state' = 15 - test_state++; // 'test_state' = 16 - // execute 'test_state -= 16' from debugger - test_state++; // 'test_state' = 1 - - if (test_state == 1) { - test_success = 1; - } else { - test_success = 0; - } -} - -// 'main' function -int main (void) { - - BP_Test(); - Test(); - - for (;;) {}; -} diff --git a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.ini b/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.ini deleted file mode 100644 index 9872059..0000000 --- a/external/CMSIS_5/CMSIS/DAP/Firmware/Validation/MDK5/test.ini +++ /dev/null @@ -1,430 +0,0 @@ -/******************************************************************************/ -/* test.ini: Initialization file to test the debug functionality */ -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2012-2017 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user license from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - -// ensure logging into file is turned off -LOG OFF - -// overall test success flag -define int testSuccess; -testSuccess = 0; - -// flags to show which particular tests succeeded -define char bpExecSuccess; -bpExecSuccess = 0; -define char bpReadSuccess; -bpReadSuccess = 0; -define char bpWriteSuccess; -bpWriteSuccess = 0; -define char memReadSuccess; -memReadSuccess = 0; -define char memWriteSuccess; -memWriteSuccess = 0; -define char regReadSuccess; -regReadSuccess = 0; -define char regWriteSuccess; -regWriteSuccess = 0; - - -// function to read and write registers -FUNC void RegReadWrite(void) { - unsigned long VR0, VR1, VR2, VR3, VR4, VR5, VR6, VR7, VR8, VR9; - unsigned long VR10, VR11, VR12, VR13, VR14, VR15, VxPSR; - unsigned long VR_0, VR_1, VR_2, VR_3, VR_4, VR_5, VR_6, VR_7, VR_8, VR_9; - unsigned long VR_10, VR_11, VR_12, VR_13, VR_14, VR_15, V_xPSR; - unsigned long bogus; - - bogus = 0x0badF00D; - - printf("Register read started\n"); - - // initialize temporary variables with bogus value - VR0 = bogus; - VR1 = bogus; - VR2 = bogus; - VR3 = bogus; - VR4 = bogus; - VR5 = bogus; - VR6 = bogus; - VR7 = bogus; - VR8 = bogus; - VR9 = bogus; - VR10 = bogus; - VR11 = bogus; - VR12 = bogus; - VR13 = bogus; - VR14 = bogus; - VR15 = bogus; - VxPSR = bogus; - - // read and save current register values - VR0 = R0; - VR1 = R1; - VR2 = R2; - VR3 = R3; - VR4 = R4; - VR5 = R5; - VR6 = R6; - VR7 = R7; - VR8 = R8; - VR9 = R9; - VR10 = R10; - VR11 = R11; - VR12 = R12; - VR13 = R13; - VR14 = R14; - VR15 = R15; - VxPSR = xPSR; - - // print read register values - printf("R0 = 0x%x\n", VR0); - printf("R1 = 0x%x\n", VR1); - printf("R2 = 0x%x\n", VR2); - printf("R3 = 0x%x\n", VR3); - printf("R4 = 0x%x\n", VR4); - printf("R5 = 0x%x\n", VR5); - printf("R6 = 0x%x\n", VR6); - printf("R7 = 0x%x\n", VR7); - printf("R8 = 0x%x\n", VR8); - printf("R9 = 0x%x\n", VR9); - printf("R10 = 0x%x\n", VR10); - printf("R11 = 0x%x\n", VR11); - printf("R12 = 0x%x\n", VR12); - printf("R13 = 0x%x\n", VR13); - printf("R14 = 0x%x\n", VR14); - printf("R15 = 0x%x\n", VR15); - printf("xPSR = 0x%x\n", VxPSR); - - // check if all values differ from bogus value - regReadSuccess = - (VR0 != bogus) && - (VR1 != bogus) && - (VR2 != bogus) && - (VR3 != bogus) && - (VR4 != bogus) && - (VR5 != bogus) && - (VR6 != bogus) && - (VR7 != bogus) && - (VR8 != bogus) && - (VR9 != bogus) && - (VR10 != bogus) && - (VR11 != bogus) && - (VR12 != bogus) && - (VR13 != bogus) && - (VR14 != bogus) && - (VR15 != bogus) && - (VxPSR != bogus); - - if (regReadSuccess != 0) { - printf("Register read passed\n"); - } else { - printf("Register read failed\n"); - // there is no reason to test write if read fails - return; - } - - printf("Register write started\n"); - - // fill all registers with bogus value - R0 = bogus; - R1 = bogus; - R2 = bogus; - R3 = bogus; - R4 = bogus; - R5 = bogus; - R6 = bogus; - R7 = bogus; - R8 = bogus; - R9 = bogus; - R10 = bogus; - R11 = bogus; - R12 = bogus; - // register R13-R15 and xPSR on hardware do not accept 0x0badf00d, use 0x0 instead - R13 = 0x0; - R14 = 0x0; - R15 = 0x0; - xPSR = 0x0; - - // read back into another array - VR_0 = R0; - VR_1 = R1; - VR_2 = R2; - VR_3 = R3; - VR_4 = R4; - VR_5 = R5; - VR_6 = R6; - VR_7 = R7; - VR_8 = R8; - VR_9 = R9; - VR_10 = R10; - VR_11 = R11; - VR_12 = R12; - VR_13 = R13; - VR_14 = R14; - VR_15 = R15; - V_xPSR = xPSR; - - // print the values again - printf("R0 = 0x%x\n", VR_0); - printf("R1 = 0x%x\n", VR_1); - printf("R2 = 0x%x\n", VR_2); - printf("R3 = 0x%x\n", VR_3); - printf("R4 = 0x%x\n", VR_4); - printf("R5 = 0x%x\n", VR_5); - printf("R6 = 0x%x\n", VR_6); - printf("R7 = 0x%x\n", VR_7); - printf("R8 = 0x%x\n", VR_8); - printf("R9 = 0x%x\n", VR_9); - printf("R10 = 0x%x\n", VR_10); - printf("R11 = 0x%x\n", VR_11); - printf("R12 = 0x%x\n", VR_12); - printf("R13 = 0x%x\n", VR_13); - printf("R14 = 0x%x\n", VR_14); - printf("R15 = 0x%x\n", VR_15); - printf("xPSR = 0x%x\n", V_xPSR); - - // check if new values are bogus - regWriteSuccess = - (VR_0 == bogus) && - (VR_1 == bogus) && - (VR_2 == bogus) && - (VR_3 == bogus) && - (VR_4 == bogus) && - (VR_5 == bogus) && - (VR_6 == bogus) && - (VR_7 == bogus) && - (VR_8 == bogus) && - (VR_9 == bogus) && - (VR_10 == bogus) && - (VR_11 == bogus) && - (VR_12 == bogus) && - (VR_13 == 0x0) && - (VR_14 == 0x0) && - (VR_15 == 0x0) && - (V_xPSR == 0x0); - - if (regWriteSuccess != 0) { - printf("Register write passed\n"); - } else { - printf("Register write failed\n"); - } - - // write saved values back into registers - // values are required to be written correctly for the rest of the test - R0 = VR0; - R1 = VR1; - R2 = VR2; - R3 = VR3; - R4 = VR4; - R5 = VR5; - R6 = VR6; - R7 = VR7; - R8 = VR8; - R9 = VR9; - R10 = VR10; - R11 = VR11; - R12 = VR12; - R13 = VR13; - R14 = VR14; - R15 = VR15; - xPSR = VxPSR; -} - - -// function to write predefined numbers into test_array1 -FUNC void MemWrite(unsigned long address) { - unsigned int i; - unsigned int val; - - printf("Memory write started\n"); - val = 0x1000; - for (i = 0; i < 256; i++) { - _WWORD(address, val); - val++; - address += 4; - } - printf("Memory write completed\n"); -} - -// function to read from test_array2 and check if write and read was successful -FUNC void MemRead(unsigned long address) { - unsigned int i; - unsigned int val, v; - - printf("Memory read started\n"); - val = 0x1000; - memReadSuccess = 1; // assume it is true - for (i = 0; i < 256; i++) { - v = _RWORD(address); - if (v != val) { - memReadSuccess = 0; - } - val++; - address += 4; - } - if (memReadSuccess != 0) { - printf("Memory read passed\n"); - } else { - printf("Memory read failed\n"); - } -} - - -// check execution breakpoint -FUNC void CheckBpExec(unsigned long address) { - // PC should be at address and value of bpTestCounter variable should be 9 - - if ((R15 == address) && (`bpTestCounter == 9)) { - bpExecSuccess = 1; - } - printf("Execution breakpoint (%d): %d\n", `bpTestCounter, bpExecSuccess); -} - -// check breakpoint on read -FUNC void CheckBpRead(int test_state) { - // PC should be at address - - if (`test_state == test_state) { - bpReadSuccess = 1; - } - printf("Breakpoint on read: %d\n",bpReadSuccess); -} - - -// check breakpoint on write -FUNC void CheckBpWrite(int test_state) { - // PC should be at address - - if (`test_state == test_state) { - bpWriteSuccess = 1; - } - printf("Breakpoint on write: %d\n", bpWriteSuccess); -} - - -// evaluate test -FUNC void EvalSuccess(void) { - char success; - - success = testSuccess && - bpExecSuccess && bpReadSuccess && bpWriteSuccess && - regReadSuccess && regWriteSuccess && - memReadSuccess && memWriteSuccess; - - exec("LOG >.\\test_results.txt"); - - // print test results to log file - if (success) { - printf("Test passed!\n"); - } else { - printf("Test failed!\n"); - } - - printf("\nIndividual test results:\n"); - - printf("Execution breakpoint: "); - if (bpExecSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - printf("Breakpoint on read: "); - if (bpReadSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - printf("Breakpoint on write: "); - if (bpWriteSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - printf("Register read: "); - if (regReadSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - printf("Register write: "); - if (regWriteSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - printf("Memory read: "); - if (memReadSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - printf("Memory write: "); - if (memWriteSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - printf("Control flow: "); - if (testSuccess) { - printf("passed\n"); - } else { - printf("failed\n"); - } - - exec("LOG OFF"); -} - - -LOG >.\\test.log // start logging - -RegReadWrite(); // check register read/write - -BK * // remove all existing breakpoints -BS \test.c\43, 9 // set execution breakpoint (hit count=9) -G // run to break point -CheckBpExec(\test.c\43); // check execution breakpoint - -BK * // remove all existing breakpoints -BS READ test_success // set a read access breakpoint -G // run to break point -CheckBpRead(11); // check breakpoint on read - -BK * // remove all existing breakpoints -BS WRITE test_success // set a write access breakpoint -G // run to break point -CheckBpWrite(12); // check breakpoint on write - -BK * // remove all existing breakpoints -G,\test.c\61 // run until line 61 -MemWrite(&test_array1[0]); // test memory write - -G,\test.c\69 // run until line 69 -memWriteSuccess = `mem_rw_success; // application memory test result -MemRead(&test_array2[0]); // test memory read - -T 3 // step 3 times - -`test_state -= 16; // modify 'test_state' application variable - -G,\test.c\88 // run until line 88 - -testSuccess = `test_success; // read 'test_success' application variable - -LOG OFF // stop logging - -EvalSuccess(); // evaluate test results - -EXIT // exit debug mode diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_CAN.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_CAN.c deleted file mode 100644 index 5007fea..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_CAN.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2015-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_CAN.h" - -#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) // CAN driver version - -// Driver Version -static const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION }; - -// Driver Capabilities -static const ARM_CAN_CAPABILITIES can_driver_capabilities = { - 32U, // Number of CAN Objects available - 0U, // Does not support reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control. - 0U, // Does not support CAN with Flexible Data-rate mode (CAN_FD) - 0U, // Does not support restricted operation mode - 0U, // Does not support bus monitoring mode - 0U, // Does not support internal loopback mode - 0U, // Does not support external loopback mode - 0U // Reserved (must be zero) -}; - -// Object Capabilities -static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities = { - 1U, // Object supports transmission - 1U, // Object supports reception - 0U, // Object does not support RTR reception and automatic Data transmission - 0U, // Object does not support RTR transmission and automatic Data reception - 0U, // Object does not allow assignment of multiple filters to it - 0U, // Object does not support exact identifier filtering - 0U, // Object does not support range identifier filtering - 0U, // Object does not support mask identifier filtering - 0U, // Object can not buffer messages - 0U // Reserved (must be zero) -}; - -static uint8_t can_driver_powered = 0U; -static uint8_t can_driver_initialized = 0U; -static ARM_CAN_SignalUnitEvent_t CAN_SignalUnitEvent = NULL; -static ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent = NULL; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_CAN_GetVersion (void) { - // Return driver version - return can_driver_version; -} - -static ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void) { - // Return driver capabilities - return can_driver_capabilities; -} - -static int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, - ARM_CAN_SignalObjectEvent_t cb_object_event) { - - if (can_driver_initialized != 0U) { return ARM_DRIVER_OK; } - - CAN_SignalUnitEvent = cb_unit_event; - CAN_SignalObjectEvent = cb_object_event; - - // Add code for pin, memory, RTX objects initialization - // .. - - can_driver_initialized = 1U; - - return ARM_DRIVER_OK; -} - -static int32_t ARM_CAN_Uninitialize (void) { - - // Add code for pin, memory, RTX objects de-initialization - // .. - - can_driver_initialized = 0U; - - return ARM_DRIVER_OK; -} - -static int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state) { - switch (state) { - case ARM_POWER_OFF: - can_driver_powered = 0U; - // Add code to disable interrupts and put peripheral into reset mode, - // and if possible disable clock - // .. - - break; - - case ARM_POWER_FULL: - if (can_driver_initialized == 0U) { return ARM_DRIVER_ERROR; } - if (can_driver_powered != 0U) { return ARM_DRIVER_OK; } - - // Add code to enable clocks, reset variables enable interrupts - // and put peripheral into operational - // .. - - can_driver_powered = 1U; - break; - - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static uint32_t ARM_CAN_GetClock (void) { - - // Add code to return peripheral clock frequency - // .. -} - -static int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) { - - if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } - - // Add code to setup peripheral parameters to generate specified bitrate - // with specified bit segments - // .. - - return ARM_DRIVER_OK; -} - -static int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode) { - - if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } - - switch (mode) { - case ARM_CAN_MODE_INITIALIZATION: - // Add code to put peripheral into initialization mode - // .. - break; - case ARM_CAN_MODE_NORMAL: - // Add code to put peripheral into normal operation mode - // .. - break; - case ARM_CAN_MODE_RESTRICTED: - // Add code to put peripheral into restricted operation mode - // .. - break; - case ARM_CAN_MODE_MONITOR: - // Add code to put peripheral into bus monitoring mode - // .. - break; - case ARM_CAN_MODE_LOOPBACK_INTERNAL: - // Add code to put peripheral into internal loopback mode - // .. - break; - case ARM_CAN_MODE_LOOPBACK_EXTERNAL: - // Add code to put peripheral into external loopback mode - // .. - break; - } - - return ARM_DRIVER_OK; -} - -static ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx) { - // Return object capabilities - return can_object_capabilities; -} - -static int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) { - - if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } - - switch (operation) { - case ARM_CAN_FILTER_ID_EXACT_ADD: - // Add code to setup peripheral to receive messages with specified exact ID - break; - case ARM_CAN_FILTER_ID_MASKABLE_ADD: - // Add code to setup peripheral to receive messages with specified maskable ID - break; - case ARM_CAN_FILTER_ID_RANGE_ADD: - // Add code to setup peripheral to receive messages within specified range of IDs - break; - case ARM_CAN_FILTER_ID_EXACT_REMOVE: - // Add code to remove specified exact ID from being received by peripheral - break; - case ARM_CAN_FILTER_ID_MASKABLE_REMOVE: - // Add code to remove specified maskable ID from being received by peripheral - break; - case ARM_CAN_FILTER_ID_RANGE_REMOVE: - // Add code to remove specified range of IDs from being received by peripheral - break; - } - - return ARM_DRIVER_OK; -} - -static int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) { - - if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } - - switch (obj_cfg) { - case ARM_CAN_OBJ_INACTIVE: - // Deactivate object - // .. - break; - case ARM_CAN_OBJ_RX_RTR_TX_DATA: - // Setup object to automatically return data when RTR with it's ID is received - // .. - break; - case ARM_CAN_OBJ_TX_RTR_RX_DATA: - // Setup object to send RTR and receive data response - // .. - break; - case ARM_CAN_OBJ_TX: - // Setup object to be used for sending messages - // .. - break; - case ARM_CAN_OBJ_RX: - // Setup object to be used for receiving messages - // .. - break; - } - - return ARM_DRIVER_OK; -} - -static int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) { - - if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } - - // Add code to send requested message - // .. - - return ((int32_t)size); -} - -static int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) { - - if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } - - // Add code to read previously received message - // (reception was started when object was configured for reception) - // .. - - return ((int32_t)size); -} - -static int32_t ARM_CAN_Control (uint32_t control, uint32_t arg) { - - if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } - - switch (control & ARM_CAN_CONTROL_Msk) { - case ARM_CAN_ABORT_MESSAGE_SEND: - // Add code to abort message pending to be sent - // .. - break; - case ARM_CAN_SET_FD_MODE: - // Add code to enable Flexible Data-rate mode - // .. - break; - case ARM_CAN_SET_TRANSCEIVER_DELAY: - // Add code to set transceiver delay - // .. - break; - default: - // Handle unknown control code - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static ARM_CAN_STATUS ARM_CAN_GetStatus (void) { - - // Add code to return device bus and error status - // .. -} - - -// IRQ handlers -// Add interrupt routines to handle transmission, reception, error and status interrupts -// .. - -// CAN driver functions structure - -extern \ -ARM_DRIVER_CAN Driver_CAN0; -ARM_DRIVER_CAN Driver_CAN0 = { - ARM_CAN_GetVersion, - ARM_CAN_GetCapabilities, - ARM_CAN_Initialize, - ARM_CAN_Uninitialize, - ARM_CAN_PowerControl, - ARM_CAN_GetClock, - ARM_CAN_SetBitrate, - ARM_CAN_SetMode, - ARM_CAN_ObjectGetCapabilities, - ARM_CAN_ObjectSetFilter, - ARM_CAN_ObjectConfigure, - ARM_CAN_MessageSend, - ARM_CAN_MessageRead, - ARM_CAN_Control, - ARM_CAN_GetStatus -}; - diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c deleted file mode 100644 index 2817b8c..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_ETH_MAC.h" - -#define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_ETH_MAC_API_VERSION, - ARM_ETH_MAC_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = { - 0, /* 1 = IPv4 header checksum verified on receive */ - 0, /* 1 = IPv6 checksum verification supported on receive */ - 0, /* 1 = UDP payload checksum verified on receive */ - 0, /* 1 = TCP payload checksum verified on receive */ - 0, /* 1 = ICMP payload checksum verified on receive */ - 0, /* 1 = IPv4 header checksum generated on transmit */ - 0, /* 1 = IPv6 checksum generation supported on transmit */ - 0, /* 1 = UDP payload checksum generated on transmit */ - 0, /* 1 = TCP payload checksum generated on transmit */ - 0, /* 1 = ICMP payload checksum generated on transmit */ - 0, /* Ethernet Media Interface type */ - 0, /* 1 = driver provides initial valid MAC address */ - 0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated */ - 0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated */ - 0, /* 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated */ - 0, /* 1 = Precision Timer supported */ - 0 /* Reserved (must be zero) */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void) -{ - return DriverCapabilities; -} - -static int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event) -{ -} - -static int32_t ARM_ETH_MAC_Uninitialize(void) -{ -} - -static int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr) -{ -} - -static int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr) -{ -} - -static int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr) -{ -} - -static int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags) -{ -} - -static int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len) -{ -} - -static uint32_t ARM_ETH_MAC_GetRxFrameSize(void) -{ -} - -static int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time) -{ -} - -static int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time) -{ -} - -static int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg) -{ - switch (control) - { - case ARM_ETH_MAC_CONFIGURE: - - switch (arg & ARM_ETH_MAC_SPEED_Msk) - { - case ARM_ETH_MAC_SPEED_10M: - break; - case ARM_ETH_SPEED_100M: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (arg & ARM_ETH_MAC_DUPLEX_Msk) - { - case ARM_ETH_MAC_DUPLEX_FULL: - break; - } - - if (arg & ARM_ETH_MAC_LOOPBACK) - { - } - - if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) || - (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST)) - { - } - - if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST) - { - } - - if (arg & ARM_ETH_MAC_ADDRESS_ALL) - { - } - - break; - - case ARM_ETH_MAC_CONTROL_TX: - break; - - case ARM_ETH_MAC_CONTROL_RX: - break; - - case ARM_ETH_MAC_FLUSH: - if (arg & ARM_ETH_MAC_FLUSH_RX) - { - } - if (arg & ARM_ETH_MAC_FLUSH_TX) - { - } - break; - - case ARM_ETH_MAC_SLEEP: - break; - - case ARM_ETH_MAC_VLAN_FILTER: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -static int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time) -{ -} - -static int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) -{ -} - -static int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data) -{ -} - -static void ARM_ETH_MAC_SignalEvent(uint32_t event) -{ -} - -// End ETH MAC Interface - -extern \ -ARM_DRIVER_ETH_MAC Driver_ETH_MAC0; -ARM_DRIVER_ETH_MAC Driver_ETH_MAC0 = -{ - ARM_ETH_MAC_GetVersion, - ARM_ETH_MAC_GetCapabilities, - ARM_ETH_MAC_Initialize, - ARM_ETH_MAC_Uninitialize, - ARM_ETH_MAC_PowerControl, - ARM_ETH_MAC_GetMacAddress, - ARM_ETH_MAC_SetMacAddress, - ARM_ETH_MAC_SetAddressFilter, - ARM_ETH_MAC_SendFrame, - ARM_ETH_MAC_ReadFrame, - ARM_ETH_MAC_GetRxFrameSize, - ARM_ETH_MAC_GetRxFrameTime, - ARM_ETH_MAC_GetTxFrameTime, - ARM_ETH_MAC_ControlTimer, - ARM_ETH_MAC_Control, - ARM_ETH_MAC_PHY_Read, - ARM_ETH_MAC_PHY_Write -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c deleted file mode 100644 index e496a28..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_ETH_PHY.h" - -#define ARM_ETH_PHY_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_ETH_PHY_API_VERSION, - ARM_ETH_PHY_DRV_VERSION -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void) -{ - return DriverVersion; -} - -static int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write) -{ -} - -static int32_t ARM_ETH_PHY_Uninitialize(void) -{ -} - -static int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_ETH_PHY_SetInterface(uint32_t interface) -{ - switch (interface) - { - case ARM_ETH_INTERFACE_MII: - break; - case ARM_ETH_INTERFACE_RMII: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -static int32_t ARM_ETH_PHY_SetMode(uint32_t mode) -{ - switch (mode & ARM_ETH_PHY_SPEED_Msk) - { - case ARM_ETH_PHY_SPEED_10M: - break; - case ARM_ETH_PHY_SPEED_100M: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (mode & ARM_ETH_PHY_DUPLEX_Msk) - { - case ARM_ETH_PHY_DUPLEX_HALF: - break; - case ARM_ETH_PHY_DUPLEX_FULL: - break; - } - - if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE) - { - } - - if (mode & ARM_ETH_PHY_LOOPBACK) - { - } - - if (mode & ARM_ETH_PHY_ISOLATE) - { - } -} - -static ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void) -{ -} - -static ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void) -{ -} - -extern \ -ARM_DRIVER_ETH_PHY Driver_ETH_PHY0; -ARM_DRIVER_ETH_PHY Driver_ETH_PHY0 = -{ - ARM_ETH_PHY_GetVersion, - ARM_ETH_PHY_Initialize, - ARM_ETH_PHY_Uninitialize, - ARM_ETH_PHY_PowerControl, - ARM_ETH_PHY_SetInterface, - ARM_ETH_PHY_SetMode, - ARM_ETH_PHY_GetLinkState, - ARM_ETH_PHY_GetLinkInfo, -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Flash.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Flash.c deleted file mode 100644 index cdccd2a..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Flash.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_Flash.h" - -#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Sector Information */ -#ifdef FLASH_SECTORS -static ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = { - FLASH_SECTORS -}; -#else -#define FLASH_SECTOR_INFO NULL -#endif - -/* Flash Information */ -static ARM_FLASH_INFO FlashInfo = { - 0, /* FLASH_SECTOR_INFO */ - 0, /* FLASH_SECTOR_COUNT */ - 0, /* FLASH_SECTOR_SIZE */ - 0, /* FLASH_PAGE_SIZE */ - 0, /* FLASH_PROGRAM_UNIT */ - 0, /* FLASH_ERASED_VALUE */ - { 0, 0, 0 } /* Reserved (must be zero) */ -}; - -/* Flash Status */ -static ARM_FLASH_STATUS FlashStatus; - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_FLASH_API_VERSION, - ARM_FLASH_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_FLASH_CAPABILITIES DriverCapabilities = { - 0, /* event_ready */ - 0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */ - 0, /* erase_chip */ - 0 /* reserved (must be zero) */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) -{ - return DriverCapabilities; -} - -static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) -{ -} - -static int32_t ARM_Flash_Uninitialize(void) -{ -} - -static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt) -{ -} - -static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt) -{ -} - -static int32_t ARM_Flash_EraseSector(uint32_t addr) -{ -} - -static int32_t ARM_Flash_EraseChip(void) -{ -} - -static ARM_FLASH_STATUS ARM_Flash_GetStatus(void) -{ - return FlashStatus; -} - -static ARM_FLASH_INFO * ARM_Flash_GetInfo(void) -{ - return &FlashInfo; -} - -static void ARM_Flash_SignalEvent(uint32_t event) -{ -} - -// End Flash Interface - -extern \ -ARM_DRIVER_FLASH Driver_Flash0; -ARM_DRIVER_FLASH Driver_Flash0 = { - ARM_Flash_GetVersion, - ARM_Flash_GetCapabilities, - ARM_Flash_Initialize, - ARM_Flash_Uninitialize, - ARM_Flash_PowerControl, - ARM_Flash_ReadData, - ARM_Flash_ProgramData, - ARM_Flash_EraseSector, - ARM_Flash_EraseChip, - ARM_Flash_GetStatus, - ARM_Flash_GetInfo -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_I2C.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_I2C.c deleted file mode 100644 index f9a4740..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_I2C.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_I2C.h" - -#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_I2C_API_VERSION, - ARM_I2C_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_I2C_CAPABILITIES DriverCapabilities = { - 0 /* supports 10-bit addressing */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_I2C_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void) -{ - return DriverCapabilities; -} - -static int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event) -{ -} - -static int32_t ARM_I2C_Uninitialize(void) -{ -} - -static int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ -} - -static int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ -} - -static int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num) -{ -} - -static int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num) -{ -} - -static int32_t ARM_I2C_GetDataCount(void) -{ -} - -static int32_t ARM_I2C_Control(uint32_t control, uint32_t arg) -{ - switch (control) - { - case ARM_I2C_OWN_ADDRESS: - break; - - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - break; - case ARM_I2C_BUS_SPEED_FAST: - break; - case ARM_I2C_BUS_SPEED_FAST_PLUS: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - break; - - case ARM_I2C_BUS_CLEAR: - break; - - case ARM_I2C_ABORT_TRANSFER: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -static ARM_I2C_STATUS ARM_I2C_GetStatus(void) -{ -} - -static void ARM_I2C_SignalEvent(uint32_t event) -{ - // function body -} - -// End I2C Interface - -extern \ -ARM_DRIVER_I2C Driver_I2C0; -ARM_DRIVER_I2C Driver_I2C0 = { - ARM_I2C_GetVersion, - ARM_I2C_GetCapabilities, - ARM_I2C_Initialize, - ARM_I2C_Uninitialize, - ARM_I2C_PowerControl, - ARM_I2C_MasterTransmit, - ARM_I2C_MasterReceive, - ARM_I2C_SlaveTransmit, - ARM_I2C_SlaveReceive, - ARM_I2C_GetDataCount, - ARM_I2C_Control, - ARM_I2C_GetStatus -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_MCI.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_MCI.c deleted file mode 100644 index dd73c04..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_MCI.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_MCI.h" - -#define ARM_MCI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_MCI_API_VERSION, - ARM_MCI_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_MCI_CAPABILITIES DriverCapabilities = { - 0, /* cd_state */ - 0, /* cd_event */ - 0, /* wp_state */ - 0, /* vdd */ - 0, /* vdd_1v8 */ - 0, /* vccq */ - 0, /* vccq_1v8 */ - 0, /* vccq_1v2 */ - 0, /* data_width_4 */ - 0, /* data_width_8 */ - 0, /* data_width_4_ddr */ - 0, /* data_width_8_ddr */ - 0, /* high_speed */ - 0, /* uhs_signaling */ - 0, /* uhs_tuning */ - 0, /* uhs_sdr50 */ - 0, /* uhs_sdr104 */ - 0, /* uhs_ddr50 */ - 0, /* uhs_driver_type_a */ - 0, /* uhs_driver_type_c */ - 0, /* uhs_driver_type_d */ - 0, /* sdio_interrupt */ - 0, /* read_wait */ - 0, /* suspend_resume */ - 0, /* mmc_interrupt */ - 0, /* mmc_boot */ - 0, /* rst_n */ - 0, /* ccs */ - 0, /* ccs_timeout */ - 0 /* Reserved */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_MCI_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void) -{ - return DriverCapabilities; -} - -static int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event) -{ -} - -static int32_t ARM_MCI_Uninitialize(void) -{ -} - -static int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_MCI_CardPower(uint32_t voltage) -{ - switch (voltage & ARM_MCI_POWER_VDD_Msk) - { - case ARM_MCI_POWER_VDD_OFF: - return ARM_DRIVER_OK; - - case ARM_MCI_POWER_VDD_3V3: - return ARM_DRIVER_OK; - - default: - break; - } - return ARM_DRIVER_ERROR; -} - -static int32_t ARM_MCI_ReadCD(void) -{ -} - -static int32_t ARM_MCI_ReadWP(void) -{ -} - -static int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response) -{ -} - -static int32_t ARM_MCI_SetupTransfer(uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode) -{ -} - -static int32_t ARM_MCI_AbortTransfer(void) -{ -} - -static int32_t ARM_MCI_Control(uint32_t control, uint32_t arg) -{ - switch (control) - { - case ARM_MCI_BUS_SPEED: - break; - - case ARM_MCI_BUS_SPEED_MODE: - break; - - case ARM_MCI_BUS_CMD_MODE: - /* Implement external pull-up control to support MMC cards in open-drain mode */ - /* Default mode is push-pull and is configured in Driver_MCI0.Initialize() */ - if (arg == ARM_MCI_BUS_CMD_PUSH_PULL) - { - /* Configure external circuit to work in push-pull mode */ - } - else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN) - { - /* Configure external circuit to work in open-drain mode */ - } - else - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - break; - - case ARM_MCI_BUS_DATA_WIDTH: - switch (arg) - { - case ARM_MCI_BUS_DATA_WIDTH_1: - break; - case ARM_MCI_BUS_DATA_WIDTH_4: - break; - case ARM_MCI_BUS_DATA_WIDTH_8: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - break; - - case ARM_MCI_CONTROL_RESET: - break; - - case ARM_MCI_CONTROL_CLOCK_IDLE: - break; - - case ARM_MCI_DATA_TIMEOUT: - break; - - case ARM_MCI_MONITOR_SDIO_INTERRUPT: - break; - - case ARM_MCI_CONTROL_READ_WAIT: - break; - - case ARM_MCI_DRIVER_STRENGTH: - default: return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -static ARM_MCI_STATUS ARM_MCI_GetStatus(void) -{ -} - -static void ARM_MCI_SignalEvent(uint32_t event) -{ - // function body -} - -// End MCI Interface - -extern \ -ARM_DRIVER_MCI Driver_MCI0; -ARM_DRIVER_MCI Driver_MCI0 = { - ARM_MCI_GetVersion, - ARM_MCI_GetCapabilities, - ARM_MCI_Initialize, - ARM_MCI_Uninitialize, - ARM_MCI_PowerControl, - ARM_MCI_CardPower, - ARM_MCI_ReadCD, - ARM_MCI_ReadWP, - ARM_MCI_SendCommand, - ARM_MCI_SetupTransfer, - ARM_MCI_AbortTransfer, - ARM_MCI_Control, - ARM_MCI_GetStatus -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_NAND.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_NAND.c deleted file mode 100644 index dbb6725..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_NAND.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_NAND.h" - -#define ARM_NAND_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_NAND_API_VERSION, - ARM_NAND_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_NAND_CAPABILITIES DriverCapabilities = { - 0, /* Signal Device Ready event (R/Bn rising edge) */ - 0, /* Supports re-entrant operation (SendCommand/Address, Read/WriteData) */ - 0, /* Supports Sequence operation (ExecuteSequence, AbortSequence) */ - 0, /* Supports VCC Power Supply Control */ - 0, /* Supports 1.8 VCC Power Supply */ - 0, /* Supports VCCQ I/O Power Supply Control */ - 0, /* Supports 1.8 VCCQ I/O Power Supply */ - 0, /* Supports VPP High Voltage Power Supply Control */ - 0, /* Supports WPn (Write Protect) Control */ - 0, /* Number of CEn (Chip Enable) lines: ce_lines + 1 */ - 0, /* Supports manual CEn (Chip Enable) Control */ - 0, /* Supports R/Bn (Ready/Busy) Monitoring */ - 0, /* Supports 16-bit data */ - 0, /* Supports NV-DDR Data Interface (ONFI) */ - 0, /* Supports NV-DDR2 Data Interface (ONFI) */ - 0, /* Fastest (highest) SDR Timing Mode supported (ONFI) */ - 0, /* Fastest (highest) NV_DDR Timing Mode supported (ONFI) */ - 0, /* Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) */ - 0, /* Supports Driver Strength 2.0x = 18 Ohms */ - 0, /* Supports Driver Strength 1.4x = 25 Ohms */ - 0, /* Supports Driver Strength 0.7x = 50 Ohms */ -#if (ARM_NAND_API_VERSION > 0x201U) - 0 /* Reserved (must be zero) */ -#endif -}; - -/* Exported functions */ - -static ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) { - return DriverVersion; -} - -static ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) { - return DriverCapabilities; -} - -static int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_Uninitialize (void) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) { - - switch ((int32_t)state) { - case ARM_POWER_OFF: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_POWER_FULL: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_NAND_DevicePower (uint32_t voltage) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd, - uint32_t addr_col, uint32_t addr_row, - void *data, uint32_t data_cnt, - uint8_t *status, uint32_t *count) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_AbortSequence (uint32_t dev_num) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) { - - switch (control) { - case ARM_NAND_BUS_MODE: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_NAND_BUS_DATA_WIDTH: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_NAND_DEVICE_READY_EVENT: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_ERROR; -} - -static ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) { - ARM_NAND_STATUS stat; - - stat.busy = 0U; - stat.ecc_error = 0U; - - return stat; -} - -static int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -/* NAND Driver Control Block */ -extern \ -ARM_DRIVER_NAND Driver_NAND0; -ARM_DRIVER_NAND Driver_NAND0 = { - ARM_NAND_GetVersion, - ARM_NAND_GetCapabilities, - ARM_NAND_Initialize, - ARM_NAND_Uninitialize, - ARM_NAND_PowerControl, - ARM_NAND_DevicePower, - ARM_NAND_WriteProtect, - ARM_NAND_ChipEnable, - ARM_NAND_GetDeviceBusy, - ARM_NAND_SendCommand, - ARM_NAND_SendAddress, - ARM_NAND_ReadData, - ARM_NAND_WriteData, - ARM_NAND_ExecuteSequence, - ARM_NAND_AbortSequence, - ARM_NAND_Control, - ARM_NAND_GetStatus, - ARM_NAND_InquireECC -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SAI.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SAI.c deleted file mode 100644 index eb445e4..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SAI.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_SAI.h" - -#define ARM_SAI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_SAI_API_VERSION, - ARM_SAI_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_SAI_CAPABILITIES DriverCapabilities = { - 1, /* supports asynchronous Transmit/Receive */ - 0, /* supports synchronous Transmit/Receive */ - 0, /* supports user defined Protocol */ - 1, /* supports I2S Protocol */ - 0, /* supports MSB/LSB justified Protocol */ - 0, /* supports PCM short/long frame Protocol */ - 0, /* supports AC'97 Protocol */ - 0, /* supports Mono mode */ - 0, /* supports Companding */ - 0, /* supports MCLK (Master Clock) pin */ - 0, /* supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR */ - 0 /* reserved (must be zero) */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_SAI_GetVersion (void) -{ - return DriverVersion; -} - -static ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void) -{ - return DriverCapabilities; -} - -static int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event) -{ -} - -static int32_t ARM_SAI_Uninitialize (void) -{ -} - -static int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_SAI_Send (const void *data, uint32_t num) -{ -} - -static int32_t ARM_SAI_Receive (void *data, uint32_t num) -{ -} - -static uint32_t ARM_SAI_GetTxCount (void) -{ -} - -static uint32_t ARM_SAI_GetRxCount (void) -{ -} - -static int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2) -{ -} - -static ARM_SAI_STATUS ARM_SAI_GetStatus (void) -{ -} - -static void ARM_SAI_SignalEvent(uint32_t event) -{ - // function body -} - -// End SAI Interface - -extern \ -ARM_DRIVER_SAI Driver_SAI0; -ARM_DRIVER_SAI Driver_SAI0 = { - ARM_SAI_GetVersion, - ARM_SAI_GetCapabilities, - ARM_SAI_Initialize, - ARM_SAI_Uninitialize, - ARM_SAI_PowerControl, - ARM_SAI_Send, - ARM_SAI_Receive, - ARM_SAI_GetTxCount, - ARM_SAI_GetRxCount, - ARM_SAI_Control, - ARM_SAI_GetStatus -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SPI.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SPI.c deleted file mode 100644 index 1112940..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SPI.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_SPI.h" - -#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_SPI_API_VERSION, - ARM_SPI_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_SPI_CAPABILITIES DriverCapabilities = { - 0, /* Reserved (must be zero) */ - 0, /* TI Synchronous Serial Interface */ - 0, /* Microwire Interface */ - 0, /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ - 0 /* Reserved (must be zero) */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_SPI_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities(void) -{ - return DriverCapabilities; -} - -static int32_t ARM_SPI_Initialize(ARM_SPI_SignalEvent_t cb_event) -{ -} - -static int32_t ARM_SPI_Uninitialize(void) -{ -} - -static int32_t ARM_SPI_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_SPI_Send(const void *data, uint32_t num) -{ -} - -static int32_t ARM_SPI_Receive(void *data, uint32_t num) -{ -} - -static int32_t ARM_SPI_Transfer(const void *data_out, void *data_in, uint32_t num) -{ -} - -static uint32_t ARM_SPI_GetDataCount(void) -{ -} - -static int32_t ARM_SPI_Control(uint32_t control, uint32_t arg) -{ - switch (control & ARM_SPI_CONTROL_Msk) - { - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_MODE_INACTIVE: // SPI Inactive - return ARM_DRIVER_OK; - - case ARM_SPI_MODE_MASTER: // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps - break; - - case ARM_SPI_MODE_SLAVE: // SPI Slave (Output on MISO, Input on MOSI) - break; - - case ARM_SPI_SET_BUS_SPEED: // Set Bus Speed in bps; arg = value - break; - - case ARM_SPI_GET_BUS_SPEED: // Get Bus Speed in bps - break; - - case ARM_SPI_SET_DEFAULT_TX_VALUE: // Set default Transmit value; arg = value - break; - - case ARM_SPI_CONTROL_SS: // Control Slave Select; arg = 0:inactive, 1:active - break; - - case ARM_SPI_ABORT_TRANSFER: // Abort current data transfer - break; - } -} - -static ARM_SPI_STATUS ARM_SPI_GetStatus(void) -{ -} - -static void ARM_SPI_SignalEvent(uint32_t event) -{ - // function body -} - -// End SPI Interface - -extern \ -ARM_DRIVER_SPI Driver_SPI0; -ARM_DRIVER_SPI Driver_SPI0 = { - ARM_SPI_GetVersion, - ARM_SPI_GetCapabilities, - ARM_SPI_Initialize, - ARM_SPI_Uninitialize, - ARM_SPI_PowerControl, - ARM_SPI_Send, - ARM_SPI_Receive, - ARM_SPI_Transfer, - ARM_SPI_GetDataCount, - ARM_SPI_Control, - ARM_SPI_GetStatus -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Storage.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Storage.c deleted file mode 100644 index e71ed2d..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Storage.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "Driver_Storage.h" - -#define ARM_STORAGE_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_STORAGE_API_VERSION, - ARM_STORAGE_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_STORAGE_CAPABILITIES DriverCapabilities = { - 0, /* Asynchronous Mode */ - 0, /* Supports EraseAll operation */ - 0 /* Reserved */ -}; - - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_Storage_GetVersion (void) { - return DriverVersion; -} - -static ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void) { - return DriverCapabilities; -} - -static int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback) { -} - -static int32_t ARM_Storage_Uninitialize (void) { -} - -static int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size) { -} - -static int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size) { -} - -static int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size) { -} - -static int32_t ARM_Storage_EraseAll (void) { -} - -static ARM_STORAGE_STATUS ARM_Storage_GetStatus (void) { -} - -static int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info) { -} - -static uint32_t ARM_Storage_ResolveAddress(uint64_t addr) { -} - -static int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block) { -} - -static int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block) { -} - -// End Storage Interface - -extern \ -ARM_DRIVER_STORAGE Driver_Storage0; -ARM_DRIVER_STORAGE Driver_Storage0 = { - ARM_Storage_GetVersion, - ARM_Storage_GetCapabilities, - ARM_Storage_Initialize, - ARM_Storage_Uninitialize, - ARM_Storage_PowerControl, - ARM_Storage_ReadData, - ARM_Storage_ProgramData, - ARM_Storage_Erase, - ARM_Storage_EraseAll, - ARM_Storage_GetStatus, - ARM_Storage_GetInfo, - ARM_Storage_ResolveAddress, - ARM_Storage_GetNextBlock, - ARM_Storage_GetBlock -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USART.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USART.c deleted file mode 100644 index 8977ad0..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USART.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_USART.h" - -#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_USART_API_VERSION, - ARM_USART_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USART_CAPABILITIES DriverCapabilities = { - 1, /* supports UART (Asynchronous) mode */ - 0, /* supports Synchronous Master mode */ - 0, /* supports Synchronous Slave mode */ - 0, /* supports UART Single-wire mode */ - 0, /* supports UART IrDA mode */ - 0, /* supports UART Smart Card mode */ - 0, /* Smart Card Clock generator available */ - 0, /* RTS Flow Control available */ - 0, /* CTS Flow Control available */ - 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ - 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ - 0, /* RTS Line: 0=not available, 1=available */ - 0, /* CTS Line: 0=not available, 1=available */ - 0, /* DTR Line: 0=not available, 1=available */ - 0, /* DSR Line: 0=not available, 1=available */ - 0, /* DCD Line: 0=not available, 1=available */ - 0, /* RI Line: 0=not available, 1=available */ - 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ - 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ - 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ - 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ - 0 /* Reserved (must be zero) */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) -{ - return DriverCapabilities; -} - -static int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event) -{ -} - -static int32_t ARM_USART_Uninitialize(void) -{ -} - -static int32_t ARM_USART_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_USART_Send(const void *data, uint32_t num) -{ -} - -static int32_t ARM_USART_Receive(void *data, uint32_t num) -{ -} - -static int32_t ARM_USART_Transfer(const void *data_out, void *data_in, uint32_t num) -{ -} - -static uint32_t ARM_USART_GetTxCount(void) -{ -} - -static uint32_t ARM_USART_GetRxCount(void) -{ -} - -static int32_t ARM_USART_Control(uint32_t control, uint32_t arg) -{ -} - -static ARM_USART_STATUS ARM_USART_GetStatus(void) -{ -} - -static int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control) -{ -} - -static ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void) -{ -} - -static void ARM_USART_SignalEvent(uint32_t event) -{ - // function body -} - -// End USART Interface - -extern \ -ARM_DRIVER_USART Driver_USART0; -ARM_DRIVER_USART Driver_USART0 = { - ARM_USART_GetVersion, - ARM_USART_GetCapabilities, - ARM_USART_Initialize, - ARM_USART_Uninitialize, - ARM_USART_PowerControl, - ARM_USART_Send, - ARM_USART_Receive, - ARM_USART_Transfer, - ARM_USART_GetTxCount, - ARM_USART_GetRxCount, - ARM_USART_Control, - ARM_USART_GetStatus, - ARM_USART_SetModemControl, - ARM_USART_GetModemStatus -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBD.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBD.c deleted file mode 100644 index 06554d1..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBD.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_USBD.h" - -#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION usbd_driver_version = { - ARM_USBD_API_VERSION, - ARM_USBD_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = { - 0, /* vbus_detection */ - 0, /* event_vbus_on */ - 0, /* event_vbus_off */ - 0 /* reserved */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_USBD_GetVersion(void) -{ - return usbd_driver_version; -} - -static ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities(void) -{ - return usbd_driver_capabilities; -} - -static int32_t ARM_USBD_Initialize(ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) -{ -} - -static int32_t ARM_USBD_Uninitialize(void) -{ -} - -static int32_t ARM_USBD_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_USBD_DeviceConnect(void) -{ -} - -static int32_t ARM_USBD_DeviceDisconnect(void) -{ -} - -static ARM_USBD_STATE ARM_USBD_DeviceGetState(void) -{ -} - -static int32_t ARM_USBD_DeviceRemoteWakeup(void) -{ -} - -static int32_t ARM_USBD_DeviceSetAddress(uint8_t dev_addr) -{ -} - -static int32_t ARM_USBD_ReadSetupPacket(uint8_t *setup) -{ -} - -static int32_t ARM_USBD_EndpointConfigure(uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size) -{ -} - -static int32_t ARM_USBD_EndpointUnconfigure(uint8_t ep_addr) -{ -} - -static int32_t ARM_USBD_EndpointStall(uint8_t ep_addr, bool stall) -{ -} - -static int32_t ARM_USBD_EndpointTransfer(uint8_t ep_addr, uint8_t *data, uint32_t num) -{ -} - -static uint32_t ARM_USBD_EndpointTransferGetResult(uint8_t ep_addr) -{ -} - -static int32_t ARM_USBD_EndpointTransferAbort(uint8_t ep_addr) -{ -} - -static uint16_t ARM_USBD_GetFrameNumber(void) -{ -} - -static void ARM_USBD_SignalDeviceEvent(uint32_t event) -{ - // function body -} - -static void ARM_USBD_SignalEndpointEvent(uint8_t ep_addr, uint32_t ep_event) -{ - // function body -} - -// End USBD Interface - -extern \ -ARM_DRIVER_USBD Driver_USBD0; -ARM_DRIVER_USBD Driver_USBD0 = -{ - ARM_USBD_GetVersion, - ARM_USBD_GetCapabilities, - ARM_USBD_Initialize, - ARM_USBD_Uninitialize, - ARM_USBD_PowerControl, - ARM_USBD_DeviceConnect, - ARM_USBD_DeviceDisconnect, - ARM_USBD_DeviceGetState, - ARM_USBD_DeviceRemoteWakeup, - ARM_USBD_DeviceSetAddress, - ARM_USBD_ReadSetupPacket, - ARM_USBD_EndpointConfigure, - ARM_USBD_EndpointUnconfigure, - ARM_USBD_EndpointStall, - ARM_USBD_EndpointTransfer, - ARM_USBD_EndpointTransferGetResult, - ARM_USBD_EndpointTransferAbort, - ARM_USBD_GetFrameNumber -}; diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBH.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBH.c deleted file mode 100644 index 3d06689..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBH.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_USBH.h" - -/* USB Host Driver */ - -#define ARM_USBH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION usbh_driver_version = { - ARM_USBH_API_VERSION, - ARM_USBH_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USBH_CAPABILITIES usbd_driver_capabilities = { - 0x0001, /* Root HUB available Ports Mask */ - 0, /* Automatic SPLIT packet handling */ - 0, /* Signal Connect event */ - 0, /* Signal Disconnect event */ - 0, /* Signal Overcurrent event */ - 0 /* Reserved (must be zero) */ -}; - -// -// Functions -// - -static ARM_DRIVER_VERSION ARM_USBH_GetVersion(void) -{ - return usbh_driver_version; -} - -static ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities(void) -{ - return usbd_driver_capabilities; -} - -static int32_t ARM_USBH_Initialize(ARM_USBH_SignalPortEvent_t cb_port_event, - ARM_USBH_SignalPipeEvent_t cb_pipe_event) -{ -} - -static int32_t ARM_USBH_Uninitialize(void) -{ -} - -static int32_t ARM_USBH_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - } - return ARM_DRIVER_OK; -} - -static int32_t ARM_USBH_PortVbusOnOff(uint8_t port, bool vbus) -{ -} - -static int32_t ARM_USBH_PortReset(uint8_t port) -{ -} - -static int32_t ARM_USBH_PortSuspend(uint8_t port) -{ -} - -static int32_t ARM_USBH_PortResume(uint8_t port) -{ -} - -static ARM_USBH_PORT_STATE ARM_USBH_PortGetState(uint8_t port) -{ -} - -static ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate(uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size, - uint8_t ep_interval) -{ -} - -static int32_t ARM_USBH_PipeModify(ARM_USBH_PIPE_HANDLE pipe_hndl, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint16_t ep_max_packet_size) -{ -} - -static int32_t ARM_USBH_PipeDelete(ARM_USBH_PIPE_HANDLE pipe_hndl) -{ -} - -static int32_t ARM_USBH_PipeReset(ARM_USBH_PIPE_HANDLE pipe_hndl) -{ -} - -static int32_t ARM_USBH_PipeTransfer(ARM_USBH_PIPE_HANDLE pipe_hndl, - uint32_t packet, - uint8_t *data, - uint32_t num) -{ -} - -static uint32_t ARM_USBH_PipeTransferGetResult(ARM_USBH_PIPE_HANDLE pipe_hndl) -{ -} - -static int32_t ARM_USBH_PipeTransferAbort(ARM_USBH_PIPE_HANDLE pipe_hndl) -{ -} - -static uint16_t ARM_USBH_GetFrameNumber(void) -{ -} - -static void ARM_USBH_SignalPortEvent(uint8_t port, uint32_t event) -{ - // function body -} - -static void ARM_USBH_SignalPipeEvent(ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event) -{ - // function body -} - -// End USBH Interface - -extern \ -ARM_DRIVER_USBH Driver_USBH0; -ARM_DRIVER_USBH Driver_USBH0 = { - ARM_USBH_GetVersion, - ARM_USBH_GetCapabilities, - ARM_USBH_Initialize, - ARM_USBH_Uninitialize, - ARM_USBH_PowerControl, - ARM_USBH_PortVbusOnOff, - ARM_USBH_PortReset, - ARM_USBH_PortSuspend, - ARM_USBH_PortResume, - ARM_USBH_PortGetState, - ARM_USBH_PipeCreate, - ARM_USBH_PipeModify, - ARM_USBH_PipeDelete, - ARM_USBH_PipeReset, - ARM_USBH_PipeTransfer, - ARM_USBH_PipeTransferGetResult, - ARM_USBH_PipeTransferAbort, - ARM_USBH_GetFrameNumber -}; - diff --git a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_WiFi.c b/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_WiFi.c deleted file mode 100644 index 03797ca..0000000 --- a/external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_WiFi.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2013-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_WiFi.h" - -#define ARM_WIFI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) // Driver version - -// Driver Version -static const ARM_DRIVER_VERSION driver_version = { - ARM_WIFI_API_VERSION, - ARM_WIFI_DRV_VERSION -}; - -// Driver Capabilities -static const ARM_WIFI_CAPABILITIES driver_capabilities = { - 0U, // Station supported - 0U, // Access Point supported - 0U, // Concurrent Station and Access Point not supported - 0U, // WiFi Protected Setup (WPS) for Station supported - 0U, // WiFi Protected Setup (WPS) for Access Point not supported - 0U, // Access Point: event generated on Station connect - 0U, // Access Point: event not generated on Station disconnect - 0U, // Event not generated on Ethernet frame reception in bypass mode - 0U, // Bypass or pass-through mode (Ethernet interface) not supported - 0U, // IP (UDP/TCP) (Socket interface) supported - 0U, // IPv6 (Socket interface) not supported - 0U, // Ping (ICMP) supported - 0U // Reserved (must be zero) -}; -static ARM_DRIVER_VERSION ARM_WiFi_GetVersion (void) { - return driver_version; -} - -static ARM_WIFI_CAPABILITIES ARM_WiFi_GetCapabilities (void) { - return driver_capabilities; -} - -static int32_t ARM_WiFi_Initialize (ARM_WIFI_SignalEvent_t cb_event) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_Uninitialize (void) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_PowerControl (ARM_POWER_STATE state) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_GetModuleInfo (char *module_info, uint32_t max_len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} -static int32_t ARM_WiFi_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_Deactivate (uint32_t interface) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static uint32_t ARM_WiFi_IsConnected (void) { - return 0U; -} - -static int32_t ARM_WiFi_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_BypassControl (uint32_t interface, uint32_t mode) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len){ - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len){ - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static uint32_t ARM_WiFi_EthGetRxFrameSize (uint32_t interface){ - return 0U; -} - -static int32_t ARM_WiFi_SocketCreate (int32_t af, int32_t type, int32_t protocol) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketListen (int32_t socket, int32_t backlog) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketRecv (int32_t socket, void *buf, uint32_t len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketSend (int32_t socket, const void *buf, uint32_t len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketClose (int32_t socket) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static int32_t ARM_WiFi_Ping (const uint8_t *ip, uint32_t ip_len) { - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -/* WiFi Driver Control Block */ -extern \ -ARM_DRIVER_WIFI Driver_WiFi0; -ARM_DRIVER_WIFI Driver_WiFi0 = { - ARM_WiFi_GetVersion, - ARM_WiFi_GetCapabilities, - ARM_WiFi_Initialize, - ARM_WiFi_Uninitialize, - ARM_WiFi_PowerControl, - ARM_WiFi_GetModuleInfo, - ARM_WiFi_SetOption, - ARM_WiFi_GetOption, - ARM_WiFi_Scan, - ARM_WiFi_Activate, - ARM_WiFi_Deactivate, - ARM_WiFi_IsConnected, - ARM_WiFi_GetNetInfo, - ARM_WiFi_BypassControl, - ARM_WiFi_EthSendFrame, - ARM_WiFi_EthReadFrame, - ARM_WiFi_EthGetRxFrameSize, - ARM_WiFi_SocketCreate, - ARM_WiFi_SocketBind, - ARM_WiFi_SocketListen, - ARM_WiFi_SocketAccept, - ARM_WiFi_SocketConnect, - ARM_WiFi_SocketRecv, - ARM_WiFi_SocketRecvFrom, - ARM_WiFi_SocketSend, - ARM_WiFi_SocketSendTo, - ARM_WiFi_SocketGetSockName, - ARM_WiFi_SocketGetPeerName, - ARM_WiFi_SocketGetOpt, - ARM_WiFi_SocketSetOpt, - ARM_WiFi_SocketClose, - ARM_WiFi_SocketGetHostByName, - ARM_WiFi_Ping -}; diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_CAN.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_CAN.h deleted file mode 100644 index ea51851..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_CAN.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Copyright (c) 2015-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V1.3 - * - * Project: CAN (Controller Area Network) Driver definitions - */ - -/* History: - * Version 1.3 - * Removed volatile from ARM_CAN_STATUS - * Version 1.2 - * Added ARM_CAN_UNIT_STATE_BUS_OFF unit state and - * ARM_CAN_EVENT_UNIT_INACTIVE unit event - * Version 1.1 - * ARM_CAN_STATUS made volatile - * Version 1.0 - * Initial release - */ - -#ifndef DRIVER_CAN_H_ -#define DRIVER_CAN_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,3) /* API version */ - - -#define _ARM_Driver_CAN_(n) Driver_CAN##n -#define ARM_Driver_CAN_(n) _ARM_Driver_CAN_(n) - - -/****** CAN Bitrate selection codes *****/ -typedef enum _ARM_CAN_BITRATE_SELECT { - ARM_CAN_BITRATE_NOMINAL, ///< Select nominal (flexible data-rate arbitration) bitrate - ARM_CAN_BITRATE_FD_DATA ///< Select flexible data-rate data bitrate -} ARM_CAN_BITRATE_SELECT; - -/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/ -#define ARM_CAN_BIT_PROP_SEG_Pos 0UL ///< bits 7..0 -#define ARM_CAN_BIT_PROP_SEG_Msk (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos) -#define ARM_CAN_BIT_PROP_SEG(x) (((x) << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk) - -/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/ -#define ARM_CAN_BIT_PHASE_SEG1_Pos 8UL ///< bits 15..8 -#define ARM_CAN_BIT_PHASE_SEG1_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos) -#define ARM_CAN_BIT_PHASE_SEG1(x) (((x) << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk) - -/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/ -#define ARM_CAN_BIT_PHASE_SEG2_Pos 16UL ///< bits 23..16 -#define ARM_CAN_BIT_PHASE_SEG2_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos) -#define ARM_CAN_BIT_PHASE_SEG2(x) (((x) << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk) - -/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/ -#define ARM_CAN_BIT_SJW_Pos 24UL ///< bits 28..24 -#define ARM_CAN_BIT_SJW_Msk (0x1FUL << ARM_CAN_BIT_SJW_Pos) -#define ARM_CAN_BIT_SJW(x) (((x) << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk) - -/****** CAN Mode codes *****/ -typedef enum _ARM_CAN_MODE { - ARM_CAN_MODE_INITIALIZATION, ///< Initialization mode - ARM_CAN_MODE_NORMAL, ///< Normal operation mode - ARM_CAN_MODE_RESTRICTED, ///< Restricted operation mode - ARM_CAN_MODE_MONITOR, ///< Bus monitoring mode - ARM_CAN_MODE_LOOPBACK_INTERNAL, ///< Loopback internal mode - ARM_CAN_MODE_LOOPBACK_EXTERNAL ///< Loopback external mode -} ARM_CAN_MODE; - -/****** CAN Filter Operation codes *****/ -typedef enum _ARM_CAN_FILTER_OPERATION { - ARM_CAN_FILTER_ID_EXACT_ADD, ///< Add exact id filter - ARM_CAN_FILTER_ID_EXACT_REMOVE, ///< Remove exact id filter - ARM_CAN_FILTER_ID_RANGE_ADD, ///< Add range id filter - ARM_CAN_FILTER_ID_RANGE_REMOVE, ///< Remove range id filter - ARM_CAN_FILTER_ID_MASKABLE_ADD, ///< Add maskable id filter - ARM_CAN_FILTER_ID_MASKABLE_REMOVE ///< Remove maskable id filter -} ARM_CAN_FILTER_OPERATION; - -/****** CAN Object Configuration codes *****/ -typedef enum _ARM_CAN_OBJ_CONFIG { - ARM_CAN_OBJ_INACTIVE, ///< CAN object inactive - ARM_CAN_OBJ_TX, ///< CAN transmit object - ARM_CAN_OBJ_RX, ///< CAN receive object - ARM_CAN_OBJ_RX_RTR_TX_DATA, ///< CAN object that on RTR reception automatically transmits Data Frame - ARM_CAN_OBJ_TX_RTR_RX_DATA ///< CAN object that transmits RTR and automatically receives Data Frame -} ARM_CAN_OBJ_CONFIG; - -/** -\brief CAN Object Capabilities -*/ -typedef struct _ARM_CAN_OBJ_CAPABILITIES { - uint32_t tx : 1; ///< Object supports transmission - uint32_t rx : 1; ///< Object supports reception - uint32_t rx_rtr_tx_data : 1; ///< Object supports RTR reception and automatic Data Frame transmission - uint32_t tx_rtr_rx_data : 1; ///< Object supports RTR transmission and automatic Data Frame reception - uint32_t multiple_filters : 1; ///< Object allows assignment of multiple filters to it - uint32_t exact_filtering : 1; ///< Object supports exact identifier filtering - uint32_t range_filtering : 1; ///< Object supports range identifier filtering - uint32_t mask_filtering : 1; ///< Object supports mask identifier filtering - uint32_t message_depth : 8; ///< Number of messages buffers (FIFO) for that object - uint32_t reserved : 16; ///< Reserved (must be zero) -} ARM_CAN_OBJ_CAPABILITIES; - -/****** CAN Control Function Operation codes *****/ -#define ARM_CAN_CONTROL_Pos 0UL -#define ARM_CAN_CONTROL_Msk (0xFFUL << ARM_CAN_CONTROL_Pos) -#define ARM_CAN_SET_FD_MODE (1UL << ARM_CAN_CONTROL_Pos) ///< Set FD operation mode; arg: 0 = disable, 1 = enable -#define ARM_CAN_ABORT_MESSAGE_SEND (2UL << ARM_CAN_CONTROL_Pos) ///< Abort sending of CAN message; arg = object -#define ARM_CAN_CONTROL_RETRANSMISSION (3UL << ARM_CAN_CONTROL_Pos) ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state) -#define ARM_CAN_SET_TRANSCEIVER_DELAY (4UL << ARM_CAN_CONTROL_Pos) ///< Set transceiver delay; arg = delay in time quanta - -/****** CAN ID Frame Format codes *****/ -#define ARM_CAN_ID_IDE_Pos 31UL -#define ARM_CAN_ID_IDE_Msk (1UL << ARM_CAN_ID_IDE_Pos) - -/****** CAN Identifier encoding *****/ -#define ARM_CAN_STANDARD_ID(id) (id & 0x000007FFUL) ///< CAN identifier in standard format (11-bits) -#define ARM_CAN_EXTENDED_ID(id) ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits) - -/** -\brief CAN Message Information -*/ -typedef struct _ARM_CAN_MSG_INFO { - uint32_t id; ///< CAN identifier with frame format specifier (bit 31) - uint32_t rtr : 1; ///< Remote transmission request frame - uint32_t edl : 1; ///< Flexible data-rate format extended data length - uint32_t brs : 1; ///< Flexible data-rate format with bitrate switch - uint32_t esi : 1; ///< Flexible data-rate format error state indicator - uint32_t dlc : 4; ///< Data length code - uint32_t reserved : 24; -} ARM_CAN_MSG_INFO; - -/****** CAN specific error code *****/ -#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Bitrate selection not supported -#define ARM_CAN_INVALID_BITRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Requested bitrate not supported -#define ARM_CAN_INVALID_BIT_PROP_SEG (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Propagation segment value not supported -#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Phase segment 1 value not supported -#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Phase segment 2 value not supported -#define ARM_CAN_INVALID_BIT_SJW (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< SJW value not supported -#define ARM_CAN_NO_MESSAGE_AVAILABLE (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Message is not available - -/****** CAN Status codes *****/ -#define ARM_CAN_UNIT_STATE_INACTIVE (0U) ///< Unit state: Not active on bus (initialization) -#define ARM_CAN_UNIT_STATE_ACTIVE (1U) ///< Unit state: Active on bus (can generate active error frame) -#define ARM_CAN_UNIT_STATE_PASSIVE (2U) ///< Unit state: Error passive (can not generate active error frame) -#define ARM_CAN_UNIT_STATE_BUS_OFF (3U) ///< Unit state: Bus-off (can recover to active state) -#define ARM_CAN_LEC_NO_ERROR (0U) ///< Last error code: No error -#define ARM_CAN_LEC_BIT_ERROR (1U) ///< Last error code: Bit error -#define ARM_CAN_LEC_STUFF_ERROR (2U) ///< Last error code: Bit stuffing error -#define ARM_CAN_LEC_CRC_ERROR (3U) ///< Last error code: CRC error -#define ARM_CAN_LEC_FORM_ERROR (4U) ///< Last error code: Illegal fixed-form bit -#define ARM_CAN_LEC_ACK_ERROR (5U) ///< Last error code: Acknowledgment error - -/** -\brief CAN Status -*/ -typedef struct _ARM_CAN_STATUS { - uint32_t unit_state : 4; ///< Unit bus state - uint32_t last_error_code : 4; ///< Last error code - uint32_t tx_error_count : 8; ///< Transmitter error count - uint32_t rx_error_count : 8; ///< Receiver error count - uint32_t reserved : 8; -} ARM_CAN_STATUS; - - -/****** CAN Unit Event *****/ -#define ARM_CAN_EVENT_UNIT_INACTIVE (0U) ///< Unit entered Inactive state -#define ARM_CAN_EVENT_UNIT_ACTIVE (1U) ///< Unit entered Error Active state -#define ARM_CAN_EVENT_UNIT_WARNING (2U) ///< Unit entered Error Warning state (one or both error counters >= 96) -#define ARM_CAN_EVENT_UNIT_PASSIVE (3U) ///< Unit entered Error Passive state -#define ARM_CAN_EVENT_UNIT_BUS_OFF (4U) ///< Unit entered Bus-off state - -/****** CAN Send/Receive Event *****/ -#define ARM_CAN_EVENT_SEND_COMPLETE (1UL << 0) ///< Send complete -#define ARM_CAN_EVENT_RECEIVE (1UL << 1) ///< Message received -#define ARM_CAN_EVENT_RECEIVE_OVERRUN (1UL << 2) ///< Received message overrun - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_CAN_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_CAN_CAPABILITIES - - \fn int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, - ARM_CAN_SignalObjectEvent_t cb_object_event) - \brief Initialize CAN interface and register signal (callback) functions. - \param[in] cb_unit_event Pointer to \ref ARM_CAN_SignalUnitEvent callback function - \param[in] cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function - \return \ref execution_status - - \fn int32_t ARM_CAN_Uninitialize (void) - \brief De-initialize CAN interface. - \return \ref execution_status - - \fn int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state) - \brief Control CAN interface power. - \param[in] state Power state - - \ref ARM_POWER_OFF : power off: no operation possible - - \ref ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events - - \ref ARM_POWER_FULL : power on: full operation at maximum performance - \return \ref execution_status - - \fn uint32_t ARM_CAN_GetClock (void) - \brief Retrieve CAN base clock frequency. - \return base clock frequency - - \fn int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) - \brief Set bitrate for CAN interface. - \param[in] select Bitrate selection - - \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate - - \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate - \param[in] bitrate Bitrate - \param[in] bit_segments Bit segments settings - - \ref ARM_CAN_BIT_PROP_SEG(x) : number of time quanta for propagation time segment - - \ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1 - - \ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2 - - \ref ARM_CAN_BIT_SJW(x) : number of time quanta for (re-)synchronization jump width - \return \ref execution_status - - \fn int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode) - \brief Set operating mode for CAN interface. - \param[in] mode Operating mode - - \ref ARM_CAN_MODE_INITIALIZATION : initialization mode - - \ref ARM_CAN_MODE_NORMAL : normal operation mode - - \ref ARM_CAN_MODE_RESTRICTED : restricted operation mode - - \ref ARM_CAN_MODE_MONITOR : bus monitoring mode - - \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode - - \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode - \return \ref execution_status - - \fn ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx) - \brief Retrieve capabilities of an object. - \param[in] obj_idx Object index - \return \ref ARM_CAN_OBJ_CAPABILITIES - - \fn int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) - \brief Add or remove filter for message reception. - \param[in] obj_idx Object index of object that filter should be or is assigned to - \param[in] operation Operation on filter - - \ref ARM_CAN_FILTER_ID_EXACT_ADD : add exact id filter - - \ref ARM_CAN_FILTER_ID_EXACT_REMOVE : remove exact id filter - - \ref ARM_CAN_FILTER_ID_RANGE_ADD : add range id filter - - \ref ARM_CAN_FILTER_ID_RANGE_REMOVE : remove range id filter - - \ref ARM_CAN_FILTER_ID_MASKABLE_ADD : add maskable id filter - - \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter - \param[in] id ID or start of ID range (depending on filter type) - \param[in] arg Mask or end of ID range (depending on filter type) - \return \ref execution_status - - \fn int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) - \brief Configure object. - \param[in] obj_idx Object index - \param[in] obj_cfg Object configuration state - - \ref ARM_CAN_OBJ_INACTIVE : deactivate object - - \ref ARM_CAN_OBJ_RX : configure object for reception - - \ref ARM_CAN_OBJ_TX : configure object for transmission - - \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame - - \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame - \return \ref execution_status - - \fn int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) - \brief Send message on CAN bus. - \param[in] obj_idx Object index - \param[in] msg_info Pointer to CAN message information - \param[in] data Pointer to data buffer - \param[in] size Number of data bytes to send - \return value >= 0 number of data bytes accepted to send - \return value < 0 \ref execution_status - - \fn int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) - \brief Read message received on CAN bus. - \param[in] obj_idx Object index - \param[out] msg_info Pointer to read CAN message information - \param[out] data Pointer to data buffer for read data - \param[in] size Maximum number of data bytes to read - \return value >= 0 number of data bytes read - \return value < 0 \ref execution_status - - \fn int32_t ARM_CAN_Control (uint32_t control, uint32_t arg) - \brief Control CAN interface. - \param[in] control Operation - - \ref ARM_CAN_SET_FD_MODE : set FD operation mode - - \ref ARM_CAN_ABORT_MESSAGE_SEND : abort sending of CAN message - - \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission - - \ref ARM_CAN_SET_TRANSCEIVER_DELAY : set transceiver delay - \param[in] arg Argument of operation - \return \ref execution_status - - \fn ARM_CAN_STATUS ARM_CAN_GetStatus (void) - \brief Get CAN status. - \return CAN status \ref ARM_CAN_STATUS - - \fn void ARM_CAN_SignalUnitEvent (uint32_t event) - \brief Signal CAN unit event. - \param[in] event \ref CAN_unit_events - \return none - - \fn void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event) - \brief Signal CAN object event. - \param[in] obj_idx Object index - \param[in] event \ref CAN_events - \return none -*/ - -typedef void (*ARM_CAN_SignalUnitEvent_t) (uint32_t event); ///< Pointer to \ref ARM_CAN_SignalUnitEvent : Signal CAN Unit Event. -typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event. - - -/** -\brief CAN Device Driver Capabilities. -*/ -typedef struct _ARM_CAN_CAPABILITIES { - uint32_t num_objects : 8; ///< Number of \ref can_objects available - uint32_t reentrant_operation : 1; ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control - uint32_t fd_mode : 1; ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control) - uint32_t restricted_mode : 1; ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode) - uint32_t monitor_mode : 1; ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode) - uint32_t internal_loopback : 1; ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode) - uint32_t external_loopback : 1; ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode) - uint32_t reserved : 18; ///< Reserved (must be zero) -} ARM_CAN_CAPABILITIES; - - -/** -\brief Access structure of the CAN Driver. -*/ -typedef struct _ARM_DRIVER_CAN { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_CAN_GetVersion : Get driver version. - ARM_CAN_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_CAN_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_CAN_SignalUnitEvent_t cb_unit_event, - ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_CAN_Uninitialize : De-initialize CAN interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_CAN_PowerControl : Control CAN interface power. - uint32_t (*GetClock) (void); ///< Pointer to \ref ARM_CAN_GetClock : Retrieve CAN base clock frequency. - int32_t (*SetBitrate) (ARM_CAN_BITRATE_SELECT select, - uint32_t bitrate, - uint32_t bit_segments); ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface. - int32_t (*SetMode) (ARM_CAN_MODE mode); ///< Pointer to \ref ARM_CAN_SetMode : Set operating mode for CAN interface. - ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object. - int32_t (*ObjectSetFilter) (uint32_t obj_idx, - ARM_CAN_FILTER_OPERATION operation, - uint32_t id, - uint32_t arg); ///< Pointer to \ref ARM_CAN_ObjectSetFilter : Add or remove filter for message reception. - int32_t (*ObjectConfigure) (uint32_t obj_idx, - ARM_CAN_OBJ_CONFIG obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure : Configure object. - int32_t (*MessageSend) (uint32_t obj_idx, - ARM_CAN_MSG_INFO *msg_info, - const uint8_t *data, - uint8_t size); ///< Pointer to \ref ARM_CAN_MessageSend : Send message on CAN bus. - int32_t (*MessageRead) (uint32_t obj_idx, - ARM_CAN_MSG_INFO *msg_info, - uint8_t *data, - uint8_t size); ///< Pointer to \ref ARM_CAN_MessageRead : Read message received on CAN bus. - int32_t (*Control) (uint32_t control, - uint32_t arg); ///< Pointer to \ref ARM_CAN_Control : Control CAN interface. - ARM_CAN_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_CAN_GetStatus : Get CAN status. -} const ARM_DRIVER_CAN; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_CAN_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_Common.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_Common.h deleted file mode 100644 index 59d5b75..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_Common.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 2. Feb 2017 - * $Revision: V2.0 - * - * Project: Common Driver definitions - */ - -/* History: - * Version 2.0 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Added General return codes definitions - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_COMMON_H_ -#define DRIVER_COMMON_H_ - -#include -#include -#include - -#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) - -/** -\brief Driver Version -*/ -typedef struct _ARM_DRIVER_VERSION { - uint16_t api; ///< API version - uint16_t drv; ///< Driver version -} ARM_DRIVER_VERSION; - -/* General return codes */ -#define ARM_DRIVER_OK 0 ///< Operation succeeded -#define ARM_DRIVER_ERROR -1 ///< Unspecified error -#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy -#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred -#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported -#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error -#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors - -/** -\brief General power states -*/ -typedef enum _ARM_POWER_STATE { - ARM_POWER_OFF, ///< Power off: no operation possible - ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events - ARM_POWER_FULL ///< Power on: full operation at maximum performance -} ARM_POWER_STATE; - -#endif /* DRIVER_COMMON_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH.h deleted file mode 100644 index d7bfaf4..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 24. January 2020 - * $Revision: V2.2 - * - * Project: Ethernet PHY and MAC Driver common definitions - */ - -/* History: - * Version 2.2 - * Removed volatile from ARM_ETH_LINK_INFO - * Version 2.1 - * ARM_ETH_LINK_INFO made volatile - * Version 2.0 - * Removed ARM_ETH_STATUS enumerator - * Removed ARM_ETH_MODE enumerator - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_ETH_H_ -#define DRIVER_ETH_H_ - -#include "Driver_Common.h" - -/** -\brief Ethernet Media Interface type -*/ -#define ARM_ETH_INTERFACE_MII (0U) ///< Media Independent Interface (MII) -#define ARM_ETH_INTERFACE_RMII (1U) ///< Reduced Media Independent Interface (RMII) -#define ARM_ETH_INTERFACE_SMII (2U) ///< Serial Media Independent Interface (SMII) - -/** -\brief Ethernet link speed -*/ -#define ARM_ETH_SPEED_10M (0U) ///< 10 Mbps link speed -#define ARM_ETH_SPEED_100M (1U) ///< 100 Mbps link speed -#define ARM_ETH_SPEED_1G (2U) ///< 1 Gpbs link speed - -/** -\brief Ethernet duplex mode -*/ -#define ARM_ETH_DUPLEX_HALF (0U) ///< Half duplex link -#define ARM_ETH_DUPLEX_FULL (1U) ///< Full duplex link - -/** -\brief Ethernet link state -*/ -typedef enum _ARM_ETH_LINK_STATE { - ARM_ETH_LINK_DOWN, ///< Link is down - ARM_ETH_LINK_UP ///< Link is up -} ARM_ETH_LINK_STATE; - -/** -\brief Ethernet link information -*/ -typedef struct _ARM_ETH_LINK_INFO { - uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit - uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full - uint32_t reserved : 29; -} ARM_ETH_LINK_INFO; - -/** -\brief Ethernet MAC Address -*/ -typedef struct _ARM_ETH_MAC_ADDR { - uint8_t b[6]; ///< MAC Address (6 bytes), MSB first -} ARM_ETH_MAC_ADDR; - -#endif /* DRIVER_ETH_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_MAC.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_MAC.h deleted file mode 100644 index 1dcc94c..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_MAC.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 24. January 2020 - * $Revision: V2.2 - * - * Project: Ethernet MAC (Media Access Control) Driver definitions - */ - -/* History: - * Version 2.2 - * Removed volatile from ARM_ETH_LINK_INFO - * Version 2.1 - * Added ARM_ETH_MAC_SLEEP Control - * Version 2.0 - * Changed MAC Address handling: - * moved from ARM_ETH_MAC_Initialize - * to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress - * Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter - * Extended ARM_ETH_MAC_SendFrame function with flags - * Added ARM_ETH_MAC_Control function: - * more control options (Broadcast, Multicast, Checksum offload, VLAN, ...) - * replaces ARM_ETH_MAC_SetMode - * replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx - * Added optional event on transmitted frame - * Added support for PTP (Precision Time Protocol) through new functions: - * ARM_ETH_MAC_ControlTimer - * ARM_ETH_MAC_GetRxFrameTime - * ARM_ETH_MAC_GetTxFrameTime - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Name space prefix ARM_ added - * Version 1.01 - * Renamed capabilities items for checksum offload - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_ETH_MAC_H_ -#define DRIVER_ETH_MAC_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_ETH.h" - -#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */ - - -#define _ARM_Driver_ETH_MAC_(n) Driver_ETH_MAC##n -#define ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n) - - -/****** Ethernet MAC Control Codes *****/ - -#define ARM_ETH_MAC_CONFIGURE (0x01UL) ///< Configure MAC; arg = configuration -#define ARM_ETH_MAC_CONTROL_TX (0x02UL) ///< Transmitter; arg: 0=disabled (default), 1=enabled -#define ARM_ETH_MAC_CONTROL_RX (0x03UL) ///< Receiver; arg: 0=disabled (default), 1=enabled -#define ARM_ETH_MAC_FLUSH (0x04UL) ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_... -#define ARM_ETH_MAC_SLEEP (0x05UL) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit -#define ARM_ETH_MAC_VLAN_FILTER (0x06UL) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default) - -/*----- Ethernet MAC Configuration -----*/ -#define ARM_ETH_MAC_SPEED_Pos 0 -#define ARM_ETH_MAC_SPEED_Msk (3UL << ARM_ETH_MAC_SPEED_Pos) -#define ARM_ETH_MAC_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed -#define ARM_ETH_MAC_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed -#define ARM_ETH_MAC_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed -#define ARM_ETH_MAC_DUPLEX_Pos 2 -#define ARM_ETH_MAC_DUPLEX_Msk (1UL << ARM_ETH_MAC_DUPLEX_Pos) -#define ARM_ETH_MAC_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link -#define ARM_ETH_MAC_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link -#define ARM_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode -#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload -#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload -#define ARM_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address -#define ARM_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address -#define ARM_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode) - -/*----- Ethernet MAC Flush Flags -----*/ -#define ARM_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer -#define ARM_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer - -/*----- Ethernet MAC VLAN Filter Flag -----*/ -#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit) - - -/****** Ethernet MAC Frame Transmit Flags *****/ -#define ARM_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment -#define ARM_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted -#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp - - -/****** Ethernet MAC Timer Control Codes *****/ -#define ARM_ETH_MAC_TIMER_GET_TIME (0x01UL) ///< Get current time -#define ARM_ETH_MAC_TIMER_SET_TIME (0x02UL) ///< Set new time -#define ARM_ETH_MAC_TIMER_INC_TIME (0x03UL) ///< Increment current time -#define ARM_ETH_MAC_TIMER_DEC_TIME (0x04UL) ///< Decrement current time -#define ARM_ETH_MAC_TIMER_SET_ALARM (0x05UL) ///< Set alarm time -#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK (0x06UL) ///< Adjust clock frequency; time->ns: correction factor * 2^31 - - -/** -\brief Ethernet MAC Time -*/ -typedef struct _ARM_ETH_MAC_TIME { - uint32_t ns; ///< Nano seconds - uint32_t sec; ///< Seconds -} ARM_ETH_MAC_TIME; - - -/****** Ethernet MAC Event *****/ -#define ARM_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received -#define ARM_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted -#define ARM_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet) -#define ARM_ETH_MAC_EVENT_TIMER_ALARM (1UL << 3) ///< Timer Alarm - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_ETH_MAC_CAPABILITIES -*/ -/** - \fn int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event) - \brief Initialize Ethernet MAC Device. - \param[in] cb_event Pointer to \ref ARM_ETH_MAC_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_Uninitialize (void) - \brief De-initialize Ethernet MAC Device. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state) - \brief Control Ethernet MAC Device Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) - \brief Get Ethernet MAC Address. - \param[in] ptr_addr Pointer to address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) - \brief Set Ethernet MAC Address. - \param[in] ptr_addr Pointer to address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, - uint32_t num_addr) - \brief Configure Address Filter. - \param[in] ptr_addr Pointer to addresses - \param[in] num_addr Number of addresses to configure - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) - \brief Send Ethernet frame. - \param[in] frame Pointer to frame buffer with data to send - \param[in] len Frame buffer length in bytes - \param[in] flags Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...) - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len) - \brief Read data of received Ethernet frame. - \param[in] frame Pointer to frame buffer for data to read into - \param[in] len Frame buffer length in bytes - \return number of data bytes read or execution status - - value >= 0: number of data bytes read - - value < 0: error occurred, value is execution status as defined with \ref execution_status -*/ -/** - \fn uint32_t ARM_ETH_MAC_GetRxFrameSize (void) - \brief Get size of received Ethernet frame. - \return number of bytes in received frame -*/ -/** - \fn int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time) - \brief Get time of received Ethernet frame. - \param[in] time Pointer to time structure for data to read into - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time) - \brief Get time of transmitted Ethernet frame. - \param[in] time Pointer to time structure for data to read into - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg) - \brief Control Ethernet Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) - \brief Control Precision Timer. - \param[in] control Operation - \param[in] time Pointer to time structure - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) - \brief Read Ethernet PHY Register through Management Interface. - \param[in] phy_addr 5-bit device address - \param[in] reg_addr 5-bit register address - \param[out] data Pointer where the result is written to - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) - \brief Write Ethernet PHY Register through Management Interface. - \param[in] phy_addr 5-bit device address - \param[in] reg_addr 5-bit register address - \param[in] data 16-bit data to write - \return \ref execution_status -*/ - -/** - \fn void ARM_ETH_MAC_SignalEvent (uint32_t event) - \brief Callback function that signals a Ethernet Event. - \param[in] event event notification mask - \return none -*/ - -typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event. - - -/** -\brief Ethernet MAC Capabilities -*/ -typedef struct _ARM_ETH_MAC_CAPABILITIES { - uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive - uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive - uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive - uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive - uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive - uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit - uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit - uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit - uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit - uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit - uint32_t media_interface : 2; ///< Ethernet Media Interface type - uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address - uint32_t event_rx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated - uint32_t event_tx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated - uint32_t event_wakeup : 1; ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated - uint32_t precision_timer : 1; ///< 1 = Precision Timer supported - uint32_t reserved : 15; ///< Reserved (must be zero) -} ARM_ETH_MAC_CAPABILITIES; - - -/** -\brief Access structure of the Ethernet MAC Driver -*/ -typedef struct _ARM_DRIVER_ETH_MAC { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version. - ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_ETH_MAC_SignalEvent_t cb_event); ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power. - int32_t (*GetMacAddress) ( ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address. - int32_t (*SetMacAddress) (const ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address. - int32_t (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter. - int32_t (*SendFrame) (const uint8_t *frame, uint32_t len, uint32_t flags); ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame. - int32_t (*ReadFrame) ( uint8_t *frame, uint32_t len); ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame. - uint32_t (*GetRxFrameSize) (void); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame. - int32_t (*GetRxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame. - int32_t (*GetTxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame. - int32_t (*ControlTimer) (uint32_t control, ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface. - int32_t (*PHY_Read) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface. - int32_t (*PHY_Write) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface. -} const ARM_DRIVER_ETH_MAC; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_ETH_MAC_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_PHY.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_PHY.h deleted file mode 100644 index cb7c0f5..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_PHY.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 24. January 2020 - * $Revision: V2.2 - * - * Project: Ethernet PHY (Physical Transceiver) Driver definitions - */ - -/* History: - * Version 2.2 - * Removed volatile from ARM_ETH_LINK_INFO - * Version 2.1 - * ARM_ETH_LINK_INFO made volatile - * Version 2.0 - * changed parameter "mode" in function ARM_ETH_PHY_SetMode - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_ETH_PHY_H_ -#define DRIVER_ETH_PHY_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_ETH.h" - -#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */ - - -#define _ARM_Driver_ETH_PHY_(n) Driver_ETH_PHY##n -#define ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n) - - -/****** Ethernet PHY Mode *****/ -#define ARM_ETH_PHY_SPEED_Pos 0 -#define ARM_ETH_PHY_SPEED_Msk (3UL << ARM_ETH_PHY_SPEED_Pos) -#define ARM_ETH_PHY_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed -#define ARM_ETH_PHY_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed -#define ARM_ETH_PHY_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed -#define ARM_ETH_PHY_DUPLEX_Pos 2 -#define ARM_ETH_PHY_DUPLEX_Msk (1UL << ARM_ETH_PHY_DUPLEX_Pos) -#define ARM_ETH_PHY_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link -#define ARM_ETH_PHY_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link -#define ARM_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode -#define ARM_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode -#define ARM_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read, - ARM_ETH_PHY_Write_t fn_write) - \brief Initialize Ethernet PHY Device. - \param[in] fn_read Pointer to \ref ARM_ETH_MAC_PHY_Read - \param[in] fn_write Pointer to \ref ARM_ETH_MAC_PHY_Write - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_Uninitialize (void) - \brief De-initialize Ethernet PHY Device. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state) - \brief Control Ethernet PHY Device Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_SetInterface (uint32_t interface) - \brief Set Ethernet Media Interface. - \param[in] interface Media Interface type - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_SetMode (uint32_t mode) - \brief Set Ethernet PHY Device Operation mode. - \param[in] mode Operation Mode - \return \ref execution_status -*/ -/** - \fn ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void) - \brief Get Ethernet PHY Device Link state. - \return current link status \ref ARM_ETH_LINK_STATE -*/ -/** - \fn ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void) - \brief Get Ethernet PHY Device Link information. - \return current link parameters \ref ARM_ETH_LINK_INFO -*/ - - -typedef int32_t (*ARM_ETH_PHY_Read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register. -typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register. - - -/** -\brief Access structure of the Ethernet PHY Driver -*/ -typedef struct _ARM_DRIVER_ETH_PHY { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version. - int32_t (*Initialize) (ARM_ETH_PHY_Read_t fn_read, - ARM_ETH_PHY_Write_t fn_write); ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power. - int32_t (*SetInterface) (uint32_t interface); ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface. - int32_t (*SetMode) (uint32_t mode); ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode. - ARM_ETH_LINK_STATE (*GetLinkState) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state. - ARM_ETH_LINK_INFO (*GetLinkInfo) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information. -} const ARM_DRIVER_ETH_PHY; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_ETH_PHY_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_Flash.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_Flash.h deleted file mode 100644 index 91c8114..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_Flash.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 24. January 2020 - * $Revision: V2.3 - * - * Project: Flash Driver definitions - */ - -/* History: - * Version 2.3 - * Removed volatile from ARM_FLASH_STATUS - * Version 2.2 - * Padding bytes added to ARM_FLASH_INFO - * Version 2.1 - * ARM_FLASH_STATUS made volatile - * Version 2.0 - * Renamed driver NOR -> Flash (more generic) - * Non-blocking operation - * Added Events, Status and Capabilities - * Linked Flash information (GetInfo) - * Version 1.11 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_FLASH_H_ -#define DRIVER_FLASH_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ - - -#define _ARM_Driver_Flash_(n) Driver_Flash##n -#define ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n) - - -#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 } - -/** -\brief Flash Sector information -*/ -typedef struct _ARM_FLASH_SECTOR { - uint32_t start; ///< Sector Start address - uint32_t end; ///< Sector End address (start+size-1) -} const ARM_FLASH_SECTOR; - -/** -\brief Flash information -*/ -typedef struct _ARM_FLASH_INFO { - ARM_FLASH_SECTOR *sector_info; ///< Sector layout information (NULL=Uniform sectors) - uint32_t sector_count; ///< Number of sectors - uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used) - uint32_t page_size; ///< Optimal programming page size in bytes - uint32_t program_unit; ///< Smallest programmable unit in bytes - uint8_t erased_value; ///< Contents of erased memory (usually 0xFF) - uint8_t reserved[3]; ///< Reserved (must be zero) -} const ARM_FLASH_INFO; - - -/** -\brief Flash Status -*/ -typedef struct _ARM_FLASH_STATUS { - uint32_t busy : 1; ///< Flash busy flag - uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation) - uint32_t reserved : 30; -} ARM_FLASH_STATUS; - - -/****** Flash Event *****/ -#define ARM_FLASH_EVENT_READY (1UL << 0) ///< Flash Ready -#define ARM_FLASH_EVENT_ERROR (1UL << 1) ///< Read/Program/Erase Error - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_Flash_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_FLASH_CAPABILITIES -*/ -/** - \fn int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event) - \brief Initialize the Flash Interface. - \param[in] cb_event Pointer to \ref ARM_Flash_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_Uninitialize (void) - \brief De-initialize the Flash Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state) - \brief Control the Flash interface power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt) - \brief Read data from Flash. - \param[in] addr Data address. - \param[out] data Pointer to a buffer storing the data read from Flash. - \param[in] cnt Number of data items to read. - \return number of data items read or \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt) - \brief Program data to Flash. - \param[in] addr Data address. - \param[in] data Pointer to a buffer containing the data to be programmed to Flash. - \param[in] cnt Number of data items to program. - \return number of data items programmed or \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_EraseSector (uint32_t addr) - \brief Erase Flash Sector. - \param[in] addr Sector address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_EraseChip (void) - \brief Erase complete Flash. - Optional function for faster full chip erase. - \return \ref execution_status -*/ -/** - \fn ARM_FLASH_STATUS ARM_Flash_GetStatus (void) - \brief Get Flash status. - \return Flash status \ref ARM_FLASH_STATUS -*/ -/** - \fn ARM_FLASH_INFO * ARM_Flash_GetInfo (void) - \brief Get Flash information. - \return Pointer to Flash information \ref ARM_FLASH_INFO -*/ - -/** - \fn void ARM_Flash_SignalEvent (uint32_t event) - \brief Signal Flash event. - \param[in] event Event notification mask - \return none -*/ - -typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event. - - -/** -\brief Flash Driver Capabilities. -*/ -typedef struct _ARM_FLASH_CAPABILITIES { - uint32_t event_ready : 1; ///< Signal Flash Ready event - uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit - uint32_t erase_chip : 1; ///< Supports EraseChip operation - uint32_t reserved : 28; ///< Reserved (must be zero) -} ARM_FLASH_CAPABILITIES; - - -/** -\brief Access structure of the Flash Driver -*/ -typedef struct _ARM_DRIVER_FLASH { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version. - ARM_FLASH_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_Flash_SignalEvent_t cb_event); ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power. - int32_t (*ReadData) (uint32_t addr, void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash. - int32_t (*ProgramData) (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash. - int32_t (*EraseSector) (uint32_t addr); ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector. - int32_t (*EraseChip) (void); ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash. - ARM_FLASH_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status. - ARM_FLASH_INFO * (*GetInfo) (void); ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information. -} const ARM_DRIVER_FLASH; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_FLASH_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_I2C.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_I2C.h deleted file mode 100644 index 8ed095a..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_I2C.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V2.4 - * - * Project: I2C (Inter-Integrated Circuit) Driver definitions - */ - -/* History: - * Version 2.4 - * Removed volatile from ARM_I2C_STATUS - * Version 2.3 - * ARM_I2C_STATUS made volatile - * Version 2.2 - * Removed function ARM_I2C_MasterTransfer in order to simplify drivers - * and added back parameter "xfer_pending" to functions - * ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive - * Version 2.1 - * Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending" - * from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive - * Added function ARM_I2C_GetDataCount - * Removed flag "address_nack" from ARM_I2C_STATUS - * Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE - * with event ARM_I2C_EVENT_TRANSFER_DONE - * Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE - * Removed parameter "arg" from function ARM_I2C_SignalEvent - * Version 2.0 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * Added: - * Slave Mode - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_I2C_H_ -#define DRIVER_I2C_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ - - -#define _ARM_Driver_I2C_(n) Driver_I2C##n -#define ARM_Driver_I2C_(n) _ARM_Driver_I2C_(n) - - -/****** I2C Control Codes *****/ - -#define ARM_I2C_OWN_ADDRESS (0x01UL) ///< Set Own Slave Address; arg = address -#define ARM_I2C_BUS_SPEED (0x02UL) ///< Set Bus Speed; arg = speed -#define ARM_I2C_BUS_CLEAR (0x03UL) ///< Execute Bus clear: send nine clock pulses -#define ARM_I2C_ABORT_TRANSFER (0x04UL) ///< Abort Master/Slave Transmit/Receive - -/*----- I2C Bus Speed -----*/ -#define ARM_I2C_BUS_SPEED_STANDARD (0x01UL) ///< Standard Speed (100kHz) -#define ARM_I2C_BUS_SPEED_FAST (0x02UL) ///< Fast Speed (400kHz) -#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03UL) ///< Fast+ Speed ( 1MHz) -#define ARM_I2C_BUS_SPEED_HIGH (0x04UL) ///< High Speed (3.4MHz) - - -/****** I2C Address Flags *****/ - -#define ARM_I2C_ADDRESS_10BIT (0x0400UL) ///< 10-bit address flag -#define ARM_I2C_ADDRESS_GC (0x8000UL) ///< General Call flag - - -/** -\brief I2C Status -*/ -typedef struct _ARM_I2C_STATUS { - uint32_t busy : 1; ///< Busy flag - uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master - uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver - uint32_t general_call : 1; ///< General Call indication (cleared on start of next Slave operation) - uint32_t arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation) - uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation) - uint32_t reserved : 26; -} ARM_I2C_STATUS; - - -/****** I2C Event *****/ -#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished -#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer -#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Addressed as Slave Transmitter but transmit operation is not set. -#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Addressed as Slave Receiver but receive operation is not set. -#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave -#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< Slave addressed with general call address -#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration -#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position) -#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_I2C_CAPABILITIES - - \fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event) - \brief Initialize I2C Interface. - \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_I2C_Uninitialize (void) - \brief De-initialize I2C Interface. - \return \ref execution_status - - \fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state) - \brief Control I2C Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) - \brief Start transmitting data as I2C Master. - \param[in] addr Slave address (7-bit or 10-bit) - \param[in] data Pointer to buffer with data to transmit to I2C Slave - \param[in] num Number of data bytes to transmit - \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated - \return \ref execution_status - - \fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) - \brief Start receiving data as I2C Master. - \param[in] addr Slave address (7-bit or 10-bit) - \param[out] data Pointer to buffer for data to receive from I2C Slave - \param[in] num Number of data bytes to receive - \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated - \return \ref execution_status - - \fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num) - \brief Start transmitting data as I2C Slave. - \param[in] data Pointer to buffer with data to transmit to I2C Master - \param[in] num Number of data bytes to transmit - \return \ref execution_status - - \fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num) - \brief Start receiving data as I2C Slave. - \param[out] data Pointer to buffer for data to receive from I2C Master - \param[in] num Number of data bytes to receive - \return \ref execution_status - - \fn int32_t ARM_I2C_GetDataCount (void) - \brief Get transferred data count. - \return number of data bytes transferred; -1 when Slave is not addressed by Master - - \fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg) - \brief Control I2C Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return \ref execution_status - - \fn ARM_I2C_STATUS ARM_I2C_GetStatus (void) - \brief Get I2C status. - \return I2C status \ref ARM_I2C_STATUS - - \fn void ARM_I2C_SignalEvent (uint32_t event) - \brief Signal I2C Events. - \param[in] event \ref I2C_events notification mask -*/ - -typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event. - - -/** -\brief I2C Driver Capabilities. -*/ -typedef struct _ARM_I2C_CAPABILITIES { - uint32_t address_10_bit : 1; ///< supports 10-bit addressing - uint32_t reserved : 31; ///< Reserved (must be zero) -} ARM_I2C_CAPABILITIES; - - -/** -\brief Access structure of the I2C Driver. -*/ -typedef struct _ARM_DRIVER_I2C { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version. - ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power. - int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master. - int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master. - int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave. - int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave. - int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface. - ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status. -} const ARM_DRIVER_I2C; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_I2C_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_MCI.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_MCI.h deleted file mode 100644 index eef69f6..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_MCI.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V2.4 - * - * Project: MCI (Memory Card Interface) Driver definitions - */ - -/* History: - * Version 2.4 - * Removed volatile from ARM_MCI_STATUS - * Version 2.3 - * ARM_MCI_STATUS made volatile - * Version 2.2 - * Added timeout and error flags to ARM_MCI_STATUS - * Added support for controlling optional RST_n pin (eMMC) - * Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK) - * Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT - * Version 2.1 - * Decoupled SPI mode from MCI driver - * Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP - * Version 2.0 - * Added support for: - * SD UHS-I (Ultra High Speed) - * SD I/O Interrupt - * Read Wait (SD I/O) - * Suspend/Resume (SD I/O) - * MMC Interrupt - * MMC Boot - * Stream Data transfer (MMC) - * VCCQ Power Supply Control (eMMC) - * Command Completion Signal (CCS) for CE-ATA - * Added ARM_MCI_Control function - * Added ARM_MCI_GetStatus function - * Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions - * (replaced by ARM_MCI_Control) - * Changed ARM_MCI_CardPower function (voltage parameter) - * Changed ARM_MCI_SendCommnad function (flags parameter) - * Changed ARM_MCI_SetupTransfer function (mode parameter) - * Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_MCI_H_ -#define DRIVER_MCI_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ - - -#define _ARM_Driver_MCI_(n) Driver_MCI##n -#define ARM_Driver_MCI_(n) _ARM_Driver_MCI_(n) - - -/****** MCI Send Command Flags *****/ -#define ARM_MCI_RESPONSE_Pos 0 -#define ARM_MCI_RESPONSE_Msk (3UL << ARM_MCI_RESPONSE_Pos) -#define ARM_MCI_RESPONSE_NONE (0UL << ARM_MCI_RESPONSE_Pos) ///< No response expected (default) -#define ARM_MCI_RESPONSE_SHORT (1UL << ARM_MCI_RESPONSE_Pos) ///< Short response (48-bit) -#define ARM_MCI_RESPONSE_SHORT_BUSY (2UL << ARM_MCI_RESPONSE_Pos) ///< Short response with busy signal (48-bit) -#define ARM_MCI_RESPONSE_LONG (3UL << ARM_MCI_RESPONSE_Pos) ///< Long response (136-bit) - -#define ARM_MCI_RESPONSE_INDEX (1UL << 2) ///< Check command index in response -#define ARM_MCI_RESPONSE_CRC (1UL << 3) ///< Check CRC in response - -#define ARM_MCI_WAIT_BUSY (1UL << 4) ///< Wait until busy before sending the command - -#define ARM_MCI_TRANSFER_DATA (1UL << 5) ///< Activate Data transfer - -#define ARM_MCI_CARD_INITIALIZE (1UL << 6) ///< Execute Memory Card initialization sequence - -#define ARM_MCI_INTERRUPT_COMMAND (1UL << 7) ///< Send Interrupt command (CMD40 - MMC only) -#define ARM_MCI_INTERRUPT_RESPONSE (1UL << 8) ///< Send Interrupt response (CMD40 - MMC only) - -#define ARM_MCI_BOOT_OPERATION (1UL << 9) ///< Execute Boot operation (MMC only) -#define ARM_MCI_BOOT_ALTERNATIVE (1UL << 10) ///< Execute Alternative Boot operation (MMC only) -#define ARM_MCI_BOOT_ACK (1UL << 11) ///< Expect Boot Acknowledge (MMC only) - -#define ARM_MCI_CCSD (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device -#define ARM_MCI_CCS (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device - - -/****** MCI Setup Transfer Mode *****/ -#define ARM_MCI_TRANSFER_READ (0UL << 0) ///< Data Read Transfer (from MCI) -#define ARM_MCI_TRANSFER_WRITE (1UL << 0) ///< Data Write Transfer (to MCI) -#define ARM_MCI_TRANSFER_BLOCK (0UL << 1) ///< Block Data transfer (default) -#define ARM_MCI_TRANSFER_STREAM (1UL << 1) ///< Stream Data transfer (MMC only) - - -/****** MCI Control Codes *****/ -#define ARM_MCI_BUS_SPEED (0x01UL) ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s -#define ARM_MCI_BUS_SPEED_MODE (0x02UL) ///< Set Bus Speed Mode as specified with arg -#define ARM_MCI_BUS_CMD_MODE (0x03UL) ///< Set CMD Line Mode as specified with arg -#define ARM_MCI_BUS_DATA_WIDTH (0x04UL) ///< Set Bus Data Width as specified with arg -#define ARM_MCI_DRIVER_STRENGTH (0x05UL) ///< Set SD UHS-I Driver Strength as specified with arg -#define ARM_MCI_CONTROL_RESET (0x06UL) ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active -#define ARM_MCI_CONTROL_CLOCK_IDLE (0x07UL) ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled -#define ARM_MCI_UHS_TUNING_OPERATION (0x08UL) ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute -#define ARM_MCI_UHS_TUNING_RESULT (0x09UL) ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error -#define ARM_MCI_DATA_TIMEOUT (0x0AUL) ///< Set Data timeout; arg = timeout in bus cycles -#define ARM_MCI_CSS_TIMEOUT (0x0BUL) ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles -#define ARM_MCI_MONITOR_SDIO_INTERRUPT (0x0CUL) ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled -#define ARM_MCI_CONTROL_READ_WAIT (0x0DUL) ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled -#define ARM_MCI_SUSPEND_TRANSFER (0x0EUL) ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer -#define ARM_MCI_RESUME_TRANSFER (0x0FUL) ///< Resume Data transfer (SD I/O) - -/*----- MCI Bus Speed Mode -----*/ -#define ARM_MCI_BUS_DEFAULT_SPEED (0x00UL) ///< SD/MMC: Default Speed mode up to 25/26MHz -#define ARM_MCI_BUS_HIGH_SPEED (0x01UL) ///< SD/MMC: High Speed mode up to 50/52MHz -#define ARM_MCI_BUS_UHS_SDR12 (0x02UL) ///< SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_SDR25 (0x03UL) ///< SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_SDR50 (0x04UL) ///< SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_SDR104 (0x05UL) ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_DDR50 (0x06UL) ///< SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling - -/*----- MCI CMD Line Mode -----*/ -#define ARM_MCI_BUS_CMD_PUSH_PULL (0x00UL) ///< Push-Pull CMD line (default) -#define ARM_MCI_BUS_CMD_OPEN_DRAIN (0x01UL) ///< Open Drain CMD line (MMC only) - -/*----- MCI Bus Data Width -----*/ -#define ARM_MCI_BUS_DATA_WIDTH_1 (0x00UL) ///< Bus data width: 1 bit (default) -#define ARM_MCI_BUS_DATA_WIDTH_4 (0x01UL) ///< Bus data width: 4 bits -#define ARM_MCI_BUS_DATA_WIDTH_8 (0x02UL) ///< Bus data width: 8 bits -#define ARM_MCI_BUS_DATA_WIDTH_4_DDR (0x03UL) ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only -#define ARM_MCI_BUS_DATA_WIDTH_8_DDR (0x04UL) ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only - -/*----- MCI Driver Strength -----*/ -#define ARM_MCI_DRIVER_TYPE_A (0x01UL) ///< SD UHS-I Driver Type A -#define ARM_MCI_DRIVER_TYPE_B (0x00UL) ///< SD UHS-I Driver Type B (default) -#define ARM_MCI_DRIVER_TYPE_C (0x02UL) ///< SD UHS-I Driver Type C -#define ARM_MCI_DRIVER_TYPE_D (0x03UL) ///< SD UHS-I Driver Type D - - -/****** MCI Card Power *****/ -#define ARM_MCI_POWER_VDD_Pos 0 -#define ARM_MCI_POWER_VDD_Msk (0x0FUL << ARM_MCI_POWER_VDD_Pos) -#define ARM_MCI_POWER_VDD_OFF (0x01UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) turned off -#define ARM_MCI_POWER_VDD_3V3 (0x02UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 3.3V -#define ARM_MCI_POWER_VDD_1V8 (0x03UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 1.8V -#define ARM_MCI_POWER_VCCQ_Pos 4 -#define ARM_MCI_POWER_VCCQ_Msk (0x0FUL << ARM_MCI_POWER_VCCQ_Pos) -#define ARM_MCI_POWER_VCCQ_OFF (0x01UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ turned off -#define ARM_MCI_POWER_VCCQ_3V3 (0x02UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 3.3V -#define ARM_MCI_POWER_VCCQ_1V8 (0x03UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.8V -#define ARM_MCI_POWER_VCCQ_1V2 (0x04UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.2V - - -/** -\brief MCI Status -*/ -typedef struct _ARM_MCI_STATUS { - uint32_t command_active : 1; ///< Command active flag - uint32_t command_timeout : 1; ///< Command timeout flag (cleared on start of next command) - uint32_t command_error : 1; ///< Command error flag (cleared on start of next command) - uint32_t transfer_active : 1; ///< Transfer active flag - uint32_t transfer_timeout : 1; ///< Transfer timeout flag (cleared on start of next command) - uint32_t transfer_error : 1; ///< Transfer error flag (cleared on start of next command) - uint32_t sdio_interrupt : 1; ///< SD I/O Interrupt flag (cleared on start of monitoring) - uint32_t ccs : 1; ///< CCS flag (cleared on start of next command) - uint32_t reserved : 24; -} ARM_MCI_STATUS; - - -/****** MCI Card Event *****/ -#define ARM_MCI_EVENT_CARD_INSERTED (1UL << 0) ///< Memory Card inserted -#define ARM_MCI_EVENT_CARD_REMOVED (1UL << 1) ///< Memory Card removed -#define ARM_MCI_EVENT_COMMAND_COMPLETE (1UL << 2) ///< Command completed -#define ARM_MCI_EVENT_COMMAND_TIMEOUT (1UL << 3) ///< Command timeout -#define ARM_MCI_EVENT_COMMAND_ERROR (1UL << 4) ///< Command response error (CRC error or invalid response) -#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5) ///< Data transfer completed -#define ARM_MCI_EVENT_TRANSFER_TIMEOUT (1UL << 6) ///< Data transfer timeout -#define ARM_MCI_EVENT_TRANSFER_ERROR (1UL << 7) ///< Data transfer CRC failed -#define ARM_MCI_EVENT_SDIO_INTERRUPT (1UL << 8) ///< SD I/O Interrupt -#define ARM_MCI_EVENT_CCS (1UL << 9) ///< Command Completion Signal (CCS) -#define ARM_MCI_EVENT_CCS_TIMEOUT (1UL << 10) ///< Command Completion Signal (CCS) Timeout - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_MCI_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_MCI_CAPABILITIES -*/ -/** - \fn int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event) - \brief Initialize the Memory Card Interface - \param[in] cb_event Pointer to \ref ARM_MCI_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_Uninitialize (void) - \brief De-initialize Memory Card Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state) - \brief Control Memory Card Interface Power. - \param[in] state Power state \ref ARM_POWER_STATE - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_CardPower (uint32_t voltage) - \brief Set Memory Card Power supply voltage. - \param[in] voltage Memory Card Power supply voltage - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_ReadCD (void) - \brief Read Card Detect (CD) state. - \return 1:card detected, 0:card not detected, or error -*/ -/** - \fn int32_t ARM_MCI_ReadWP (void) - \brief Read Write Protect (WP) state. - \return 1:write protected, 0:not write protected, or error -*/ -/** - \fn int32_t ARM_MCI_SendCommand (uint32_t cmd, - uint32_t arg, - uint32_t flags, - uint32_t *response) - \brief Send Command to card and get the response. - \param[in] cmd Memory Card command - \param[in] arg Command argument - \param[in] flags Command flags - \param[out] response Pointer to buffer for response - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_SetupTransfer (uint8_t *data, - uint32_t block_count, - uint32_t block_size, - uint32_t mode) - \brief Setup read or write transfer operation. - \param[in,out] data Pointer to data block(s) to be written or read - \param[in] block_count Number of blocks - \param[in] block_size Size of a block in bytes - \param[in] mode Transfer mode - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_AbortTransfer (void) - \brief Abort current read/write data transfer. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_Control (uint32_t control, uint32_t arg) - \brief Control MCI Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return \ref execution_status -*/ -/** - \fn ARM_MCI_STATUS ARM_MCI_GetStatus (void) - \brief Get MCI status. - \return MCI status \ref ARM_MCI_STATUS -*/ - -/** - \fn void ARM_MCI_SignalEvent (uint32_t event) - \brief Callback function that signals a MCI Card Event. - \param[in] event \ref mci_event_gr - \return none -*/ - -typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event. - - -/** -\brief MCI Driver Capabilities. -*/ -typedef struct _ARM_MCI_CAPABILITIES { - uint32_t cd_state : 1; ///< Card Detect State available - uint32_t cd_event : 1; ///< Signal Card Detect change event - uint32_t wp_state : 1; ///< Write Protect State available - uint32_t vdd : 1; ///< Supports VDD Card Power Supply Control - uint32_t vdd_1v8 : 1; ///< Supports 1.8 VDD Card Power Supply - uint32_t vccq : 1; ///< Supports VCCQ Card Power Supply Control (eMMC) - uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ Card Power Supply (eMMC) - uint32_t vccq_1v2 : 1; ///< Supports 1.2 VCCQ Card Power Supply (eMMC) - uint32_t data_width_4 : 1; ///< Supports 4-bit data - uint32_t data_width_8 : 1; ///< Supports 8-bit data - uint32_t data_width_4_ddr : 1; ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only - uint32_t data_width_8_ddr : 1; ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only - uint32_t high_speed : 1; ///< Supports SD/MMC High Speed Mode - uint32_t uhs_signaling : 1; ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling - uint32_t uhs_tuning : 1; ///< Supports SD UHS-I tuning - uint32_t uhs_sdr50 : 1; ///< Supports SD UHS-I SDR50 (Single Data Rate) up to 50MB/s - uint32_t uhs_sdr104 : 1; ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s - uint32_t uhs_ddr50 : 1; ///< Supports SD UHS-I DDR50 (Dual Data Rate) up to 50MB/s - uint32_t uhs_driver_type_a : 1; ///< Supports SD UHS-I Driver Type A - uint32_t uhs_driver_type_c : 1; ///< Supports SD UHS-I Driver Type C - uint32_t uhs_driver_type_d : 1; ///< Supports SD UHS-I Driver Type D - uint32_t sdio_interrupt : 1; ///< Supports SD I/O Interrupt - uint32_t read_wait : 1; ///< Supports Read Wait (SD I/O) - uint32_t suspend_resume : 1; ///< Supports Suspend/Resume (SD I/O) - uint32_t mmc_interrupt : 1; ///< Supports MMC Interrupt - uint32_t mmc_boot : 1; ///< Supports MMC Boot - uint32_t rst_n : 1; ///< Supports RST_n Pin Control (eMMC) - uint32_t ccs : 1; ///< Supports Command Completion Signal (CCS) for CE-ATA - uint32_t ccs_timeout : 1; ///< Supports Command Completion Signal (CCS) timeout for CE-ATA - uint32_t reserved : 3; ///< Reserved (must be zero) -} ARM_MCI_CAPABILITIES; - - -/** -\brief Access structure of the MCI Driver. -*/ -typedef struct _ARM_DRIVER_MCI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version. - ARM_MCI_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power. - int32_t (*CardPower) (uint32_t voltage); ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage. - int32_t (*ReadCD) (void); ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state. - int32_t (*ReadWP) (void); ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state. - int32_t (*SendCommand) (uint32_t cmd, - uint32_t arg, - uint32_t flags, - uint32_t *response); ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response. - int32_t (*SetupTransfer) (uint8_t *data, - uint32_t block_count, - uint32_t block_size, - uint32_t mode); ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation. - int32_t (*AbortTransfer) (void); ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface. - ARM_MCI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status. -} const ARM_DRIVER_MCI; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_MCI_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_NAND.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_NAND.h deleted file mode 100644 index 9f5c2c3..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_NAND.h +++ /dev/null @@ -1,426 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V2.4 - * - * Project: NAND Flash Driver definitions - */ - -/* History: - * Version 2.4 - * Removed volatile from ARM_NAND_STATUS - * Version 2.3 - * Extended ARM_NAND_ECC_INFO structure - * Version 2.2 - * ARM_NAND_STATUS made volatile - * Version 2.1 - * Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions - * Version 2.0 - * New simplified driver: - * complexity moved to upper layer (command agnostic) - * Added support for: - * NV-DDR & NV-DDR2 Interface (ONFI specification) - * VCC, VCCQ and VPP Power Supply Control - * WP (Write Protect) Control - * Version 1.11 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_NAND_H_ -#define DRIVER_NAND_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ - - -#define _ARM_Driver_NAND_(n) Driver_NAND##n -#define ARM_Driver_NAND_(n) _ARM_Driver_NAND_(n) - - -/****** NAND Device Power *****/ -#define ARM_NAND_POWER_VCC_Pos 0 -#define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos) -#define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos) ///< VCC Power off -#define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 3.3V -#define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 1.8V -#define ARM_NAND_POWER_VCCQ_Pos 3 -#define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos) -#define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off -#define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V -#define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V -#define ARM_NAND_POWER_VPP_OFF (1UL << 6) ///< VPP off -#define ARM_NAND_POWER_VPP_ON (1UL << 7) ///< VPP on - - -/****** NAND Control Codes *****/ -#define ARM_NAND_BUS_MODE (0x01UL) ///< Set Bus Mode as specified with arg -#define ARM_NAND_BUS_DATA_WIDTH (0x02UL) ///< Set Bus Data Width as specified with arg -#define ARM_NAND_DRIVER_STRENGTH (0x03UL) ///< Set Driver Strength as specified with arg -#define ARM_NAND_DEVICE_READY_EVENT (0x04UL) ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled -#define ARM_NAND_DRIVER_READY_EVENT (0x05UL) ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled - -/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/ -#define ARM_NAND_BUS_INTERFACE_Pos 4 -#define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos) -#define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: SDR (Single Data Rate) - Traditional interface (default) -#define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR (Double Data Rate) -#define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR2 (Double Data Rate) -#define ARM_NAND_BUS_TIMING_MODE_Pos 0 -#define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos) -#define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 0 (default) -#define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 1 -#define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 2 -#define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 3 -#define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 4 (SDR EDO capable) -#define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 5 (SDR EDO capable) -#define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 6 (NV-DDR2 only) -#define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 7 (NV-DDR2 only) -#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8 -#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) -#define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default) -#define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1 -#define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2 -#define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4 -#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12 -#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) -#define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default) -#define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1 -#define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2 -#define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4 -#define ARM_NAND_BUS_DDR2_VEN (1UL << 16) ///< DDR2 Enable external VREFQ as reference -#define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) ///< DDR2 Enable complementary DQS (DQS_c) signal -#define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) ///< DDR2 Enable complementary RE_n (RE_c) signal - -/*----- NAND Data Bus Width -----*/ -#define ARM_NAND_BUS_DATA_WIDTH_8 (0x00UL) ///< Bus Data Width: 8 bit (default) -#define ARM_NAND_BUS_DATA_WIDTH_16 (0x01UL) ///< Bus Data Width: 16 bit - -/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/ -#define ARM_NAND_DRIVER_STRENGTH_18 (0x00UL) ///< Driver Strength 2.0x = 18 Ohms -#define ARM_NAND_DRIVER_STRENGTH_25 (0x01UL) ///< Driver Strength 1.4x = 25 Ohms -#define ARM_NAND_DRIVER_STRENGTH_35 (0x02UL) ///< Driver Strength 1.0x = 35 Ohms (default) -#define ARM_NAND_DRIVER_STRENGTH_50 (0x03UL) ///< Driver Strength 0.7x = 50 Ohms - - -/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/ -#define ARM_NAND_ECC_INDEX_Pos 0 -#define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos) -#define ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk) ///< Select ECC -#define ARM_NAND_ECC0 (1UL << 8) ///< Use ECC0 of selected ECC -#define ARM_NAND_ECC1 (1UL << 9) ///< Use ECC1 of selected ECC - -/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/ -#define ARM_NAND_DRIVER_DONE_EVENT (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE - -/****** NAND Sequence Execution Code *****/ -#define ARM_NAND_CODE_SEND_CMD1 (1UL << 17) ///< Send Command 1 -#define ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18) ///< Send Column Address 1 -#define ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19) ///< Send Column Address 2 -#define ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20) ///< Send Row Address 1 -#define ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21) ///< Send Row Address 2 -#define ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22) ///< Send Row Address 3 -#define ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23) ///< Auto-increment Row Address -#define ARM_NAND_CODE_WRITE_DATA (1UL << 24) ///< Write Data -#define ARM_NAND_CODE_SEND_CMD2 (1UL << 25) ///< Send Command 2 -#define ARM_NAND_CODE_WAIT_BUSY (1UL << 26) ///< Wait while R/Bn busy -#define ARM_NAND_CODE_READ_DATA (1UL << 27) ///< Read Data -#define ARM_NAND_CODE_SEND_CMD3 (1UL << 28) ///< Send Command 3 -#define ARM_NAND_CODE_READ_STATUS (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0) - -/*----- NAND Sequence Execution Code: Command -----*/ -#define ARM_NAND_CODE_CMD1_Pos 0 -#define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos) -#define ARM_NAND_CODE_CMD2_Pos 8 -#define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos) -#define ARM_NAND_CODE_CMD3_Pos 16 -#define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos) - -/*----- NAND Sequence Execution Code: Column Address -----*/ -#define ARM_NAND_CODE_ADDR_COL1_Pos 0 -#define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos) -#define ARM_NAND_CODE_ADDR_COL2_Pos 8 -#define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos) - -/*----- NAND Sequence Execution Code: Row Address -----*/ -#define ARM_NAND_CODE_ADDR_ROW1_Pos 0 -#define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos) -#define ARM_NAND_CODE_ADDR_ROW2_Pos 8 -#define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos) -#define ARM_NAND_CODE_ADDR_ROW3_Pos 16 -#define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos) - - -/****** NAND specific error codes *****/ -#define ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< ECC generation/correction failed - - -/** -\brief NAND ECC (Error Correction Code) Information -*/ -typedef struct _ARM_NAND_ECC_INFO { - uint32_t type : 2; ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare - uint32_t page_layout : 1; ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1| - uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count - uint32_t page_size : 4; ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description) - uint32_t reserved : 14; ///< Reserved (must be zero) - uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size) - uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated - uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up) - uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare) - /* Extended description */ - uint16_t virtual_page_size [2]; ///< Virtual Page size in bytes (Main/Spare) - uint16_t codeword_offset [2]; ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare) - uint16_t codeword_gap [2]; ///< Codeword gap in bytes till next protected data - uint16_t ecc_gap [2]; ///< ECC gap in bytes till next generated ECC -} ARM_NAND_ECC_INFO; - - -/** -\brief NAND Status -*/ -typedef struct _ARM_NAND_STATUS { - uint32_t busy : 1; ///< Driver busy flag - uint32_t ecc_error : 1; ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence) - uint32_t reserved : 30; -} ARM_NAND_STATUS; - - -/****** NAND Event *****/ -#define ARM_NAND_EVENT_DEVICE_READY (1UL << 0) ///< Device Ready: R/Bn rising edge -#define ARM_NAND_EVENT_DRIVER_READY (1UL << 1) ///< Driver Ready -#define ARM_NAND_EVENT_DRIVER_DONE (1UL << 2) ///< Driver operation done -#define ARM_NAND_EVENT_ECC_ERROR (1UL << 3) ///< ECC could not correct data - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_NAND_CAPABILITIES -*/ -/** - \fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) - \brief Initialize the NAND Interface. - \param[in] cb_event Pointer to \ref ARM_NAND_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_Uninitialize (void) - \brief De-initialize the NAND Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) - \brief Control the NAND interface power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_DevicePower (uint32_t voltage) - \brief Set device power supply voltage. - \param[in] voltage NAND Device supply voltage - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) - \brief Control WPn (Write Protect). - \param[in] dev_num Device number - \param[in] enable - - \b false Write Protect off - - \b true Write Protect on - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) - \brief Control CEn (Chip Enable). - \param[in] dev_num Device number - \param[in] enable - - \b false Chip Enable off - - \b true Chip Enable on - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) - \brief Get Device Busy pin state. - \param[in] dev_num Device number - \return 1=busy, 0=not busy, or error -*/ -/** - \fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) - \brief Send command to NAND device. - \param[in] dev_num Device number - \param[in] cmd Command - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) - \brief Send address to NAND device. - \param[in] dev_num Device number - \param[in] addr Address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) - \brief Read data from NAND device. - \param[in] dev_num Device number - \param[out] data Pointer to buffer for data to read from NAND device - \param[in] cnt Number of data items to read - \param[in] mode Operation mode - \return number of data items read or \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) - \brief Write data to NAND device. - \param[in] dev_num Device number - \param[out] data Pointer to buffer with data to write to NAND device - \param[in] cnt Number of data items to write - \param[in] mode Operation mode - \return number of data items written or \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd, - uint32_t addr_col, uint32_t addr_row, - void *data, uint32_t data_cnt, - uint8_t *status, uint32_t *count) - \brief Execute sequence of operations. - \param[in] dev_num Device number - \param[in] code Sequence code - \param[in] cmd Command(s) - \param[in] addr_col Column address - \param[in] addr_row Row address - \param[in,out] data Pointer to data to be written or read - \param[in] data_cnt Number of data items in one iteration - \param[out] status Pointer to status read - \param[in,out] count Number of iterations - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num) - \brief Abort sequence execution. - \param[in] dev_num Device number - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) - \brief Control NAND Interface. - \param[in] dev_num Device number - \param[in] control Operation - \param[in] arg Argument of operation - \return \ref execution_status -*/ -/** - \fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) - \brief Get NAND status. - \param[in] dev_num Device number - \return NAND status \ref ARM_NAND_STATUS -*/ -/** - \fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) - \brief Inquire about available ECC. - \param[in] index Inquire ECC index - \param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved - \return \ref execution_status -*/ - -/** - \fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event) - \brief Signal NAND event. - \param[in] dev_num Device number - \param[in] event Event notification mask - \return none -*/ - -typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event); ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event. - - -/** -\brief NAND Driver Capabilities. -*/ -typedef struct _ARM_NAND_CAPABILITIES { - uint32_t event_device_ready : 1; ///< Signal Device Ready event (R/Bn rising edge) - uint32_t reentrant_operation : 1; ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData) - uint32_t sequence_operation : 1; ///< Supports Sequence operation (ExecuteSequence, AbortSequence) - uint32_t vcc : 1; ///< Supports VCC Power Supply Control - uint32_t vcc_1v8 : 1; ///< Supports 1.8 VCC Power Supply - uint32_t vccq : 1; ///< Supports VCCQ I/O Power Supply Control - uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ I/O Power Supply - uint32_t vpp : 1; ///< Supports VPP High Voltage Power Supply Control - uint32_t wp : 1; ///< Supports WPn (Write Protect) Control - uint32_t ce_lines : 4; ///< Number of CEn (Chip Enable) lines: ce_lines + 1 - uint32_t ce_manual : 1; ///< Supports manual CEn (Chip Enable) Control - uint32_t rb_monitor : 1; ///< Supports R/Bn (Ready/Busy) Monitoring - uint32_t data_width_16 : 1; ///< Supports 16-bit data - uint32_t ddr : 1; ///< Supports NV-DDR Data Interface (ONFI) - uint32_t ddr2 : 1; ///< Supports NV-DDR2 Data Interface (ONFI) - uint32_t sdr_timing_mode : 3; ///< Fastest (highest) SDR Timing Mode supported (ONFI) - uint32_t ddr_timing_mode : 3; ///< Fastest (highest) NV_DDR Timing Mode supported (ONFI) - uint32_t ddr2_timing_mode : 3; ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) - uint32_t driver_strength_18 : 1; ///< Supports Driver Strength 2.0x = 18 Ohms - uint32_t driver_strength_25 : 1; ///< Supports Driver Strength 1.4x = 25 Ohms - uint32_t driver_strength_50 : 1; ///< Supports Driver Strength 0.7x = 50 Ohms - uint32_t reserved : 2; ///< Reserved (must be zero) -} ARM_NAND_CAPABILITIES; - - -/** -\brief Access structure of the NAND Driver. -*/ -typedef struct _ARM_DRIVER_NAND { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version. - ARM_NAND_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_NAND_SignalEvent_t cb_event); ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power. - int32_t (*DevicePower) (uint32_t voltage); ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage. - int32_t (*WriteProtect) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect). - int32_t (*ChipEnable) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable). - int32_t (*GetDeviceBusy) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state. - int32_t (*SendCommand) (uint32_t dev_num, uint8_t cmd); ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device. - int32_t (*SendAddress) (uint32_t dev_num, uint8_t addr); ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device. - int32_t (*ReadData) (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device. - int32_t (*WriteData) (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device. - int32_t (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd, - uint32_t addr_col, uint32_t addr_row, - void *data, uint32_t data_cnt, - uint8_t *status, uint32_t *count); ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations. - int32_t (*AbortSequence) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. - int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface. - ARM_NAND_STATUS (*GetStatus) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status. - int32_t (*InquireECC) ( int32_t index, ARM_NAND_ECC_INFO *info); ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. -} const ARM_DRIVER_NAND; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_NAND_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_SAI.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_SAI.h deleted file mode 100644 index 6aff8c2..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_SAI.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V1.2 - * - * Project: SAI (Serial Audio Interface) Driver definitions - */ - -/* History: - * Version 1.2 - * Removed volatile from ARM_SAI_STATUS - * Version 1.1 - * ARM_SAI_STATUS made volatile - * Version 1.0 - * Initial release - */ - -#ifndef DRIVER_SAI_H_ -#define DRIVER_SAI_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2) /* API version */ - - -#define _ARM_Driver_SAI_(n) Driver_SAI##n -#define ARM_Driver_SAI_(n) _ARM_Driver_SAI_(n) - - -/****** SAI Control Codes *****/ - -#define ARM_SAI_CONTROL_Msk (0xFFUL) -#define ARM_SAI_CONFIGURE_TX (0x01UL) ///< Configure Transmitter; arg1 and arg2 provide additional configuration -#define ARM_SAI_CONFIGURE_RX (0x02UL) ///< Configure Receiver; arg1 and arg2 provide additional configuration -#define ARM_SAI_CONTROL_TX (0x03UL) ///< Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute -#define ARM_SAI_CONTROL_RX (0x04UL) ///< Control Receiver; arg1.0: 0=disable (default), 1=enable -#define ARM_SAI_MASK_SLOTS_TX (0x05UL) ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default -#define ARM_SAI_MASK_SLOTS_RX (0x06UL) ///< Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default -#define ARM_SAI_ABORT_SEND (0x07UL) ///< Abort \ref ARM_SAI_Send -#define ARM_SAI_ABORT_RECEIVE (0x08UL) ///< Abort \ref ARM_SAI_Receive - -/*----- SAI Control Codes: Configuration Parameters: Mode -----*/ -#define ARM_SAI_MODE_Pos 8 -#define ARM_SAI_MODE_Msk (1UL << ARM_SAI_MODE_Pos) -#define ARM_SAI_MODE_MASTER (1UL << ARM_SAI_MODE_Pos) ///< Master Mode -#define ARM_SAI_MODE_SLAVE (0UL << ARM_SAI_MODE_Pos) ///< Slave Mode (default) - -/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/ -#define ARM_SAI_SYNCHRONIZATION_Pos 9 -#define ARM_SAI_SYNCHRONIZATION_Msk (1UL << ARM_SAI_SYNCHRONIZATION_Pos) -#define ARM_SAI_ASYNCHRONOUS (0UL << ARM_SAI_SYNCHRONIZATION_Pos) ///< Asynchronous (default) -#define ARM_SAI_SYNCHRONOUS (1UL << ARM_SAI_SYNCHRONIZATION_Pos) ///< Synchronous - -/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/ -#define ARM_SAI_PROTOCOL_Pos 10 -#define ARM_SAI_PROTOCOL_Msk (7UL << ARM_SAI_PROTOCOL_Pos) -#define ARM_SAI_PROTOCOL_USER (0UL << ARM_SAI_PROTOCOL_Pos) ///< User defined (default) -#define ARM_SAI_PROTOCOL_I2S (1UL << ARM_SAI_PROTOCOL_Pos) ///< I2S -#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED (2UL << ARM_SAI_PROTOCOL_Pos) ///< MSB (left) justified -#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED (3UL << ARM_SAI_PROTOCOL_Pos) ///< LSB (right) justified -#define ARM_SAI_PROTOCOL_PCM_SHORT (4UL << ARM_SAI_PROTOCOL_Pos) ///< PCM with short frame -#define ARM_SAI_PROTOCOL_PCM_LONG (5UL << ARM_SAI_PROTOCOL_Pos) ///< PCM with long frame -#define ARM_SAI_PROTOCOL_AC97 (6UL << ARM_SAI_PROTOCOL_Pos) ///< AC'97 - -/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/ -#define ARM_SAI_DATA_SIZE_Pos 13 -#define ARM_SAI_DATA_SIZE_Msk (0x1FUL << ARM_SAI_DATA_SIZE_Pos) -#define ARM_SAI_DATA_SIZE(n) ((((n)-1UL)&0x1FUL) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32) - -/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/ -#define ARM_SAI_BIT_ORDER_Pos 18 -#define ARM_SAI_BIT_ORDER_Msk (1UL << ARM_SAI_BIT_ORDER_Pos) -#define ARM_SAI_MSB_FIRST (0UL << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with MSB first (default) -#define ARM_SAI_LSB_FIRST (1UL << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with LSB first; User Protocol only (ignored otherwise) - -/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/ -#define ARM_SAI_MONO_MODE (1UL << 19) ///< Mono Mode (only for I2S, MSB/LSB justified) - -/*----- SAI Control Codes:Configuration Parameters: Companding -----*/ -#define ARM_SAI_COMPANDING_Pos 20 -#define ARM_SAI_COMPANDING_Msk (3UL << ARM_SAI_COMPANDING_Pos) -#define ARM_SAI_COMPANDING_NONE (0UL << ARM_SAI_COMPANDING_Pos) ///< No companding (default) -#define ARM_SAI_COMPANDING_A_LAW (2UL << ARM_SAI_COMPANDING_Pos) ///< A-Law companding -#define ARM_SAI_COMPANDING_U_LAW (3UL << ARM_SAI_COMPANDING_Pos) ///< u-Law companding - -/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/ -#define ARM_SAI_CLOCK_POLARITY_Pos 23 -#define ARM_SAI_CLOCK_POLARITY_Msk (1UL << ARM_SAI_CLOCK_POLARITY_Pos) -#define ARM_SAI_CLOCK_POLARITY_0 (0UL << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on falling edge, Capture on rising edge (default) -#define ARM_SAI_CLOCK_POLARITY_1 (1UL << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on rising edge, Capture on falling edge - -/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/ -#define ARM_SAI_MCLK_PIN_Pos 24 -#define ARM_SAI_MCLK_PIN_Msk (3UL << ARM_SAI_MCLK_PIN_Pos) -#define ARM_SAI_MCLK_PIN_INACTIVE (0UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK not used (default) -#define ARM_SAI_MCLK_PIN_OUTPUT (1UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is output (Master only) -#define ARM_SAI_MCLK_PIN_INPUT (2UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is input (Master only) - - -/****** SAI Configuration (arg1) *****/ - -/*----- SAI Configuration (arg1): Frame Length -----*/ -#define ARM_SAI_FRAME_LENGTH_Pos 0 -#define ARM_SAI_FRAME_LENGTH_Msk (0x3FFUL << ARM_SAI_FRAME_LENGTH_Pos) -#define ARM_SAI_FRAME_LENGTH(n) ((((n)-1UL)&0x3FFUL) << ARM_SAI_FRAME_LENGTH_Pos) ///< Frame length in bits (8..1024); default depends on protocol and data - -/*----- SAI Configuration (arg1): Frame Sync Width -----*/ -#define ARM_SAI_FRAME_SYNC_WIDTH_Pos 10 -#define ARM_SAI_FRAME_SYNC_WIDTH_Msk (0xFFUL << ARM_SAI_FRAME_SYNC_WIDTH_Pos) -#define ARM_SAI_FRAME_SYNC_WIDTH(n) ((((n)-1UL)&0xFFUL) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/ -#define ARM_SAI_FRAME_SYNC_POLARITY_Pos 18 -#define ARM_SAI_FRAME_SYNC_POLARITY_Msk (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) -#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active high (default); User Protocol only (ignored otherwise) -#define ARM_SAI_FRAME_SYNC_POLARITY_LOW (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active low; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Frame Sync Early -----*/ -#define ARM_SAI_FRAME_SYNC_EARLY (1UL << 19) ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Slot Count -----*/ -#define ARM_SAI_SLOT_COUNT_Pos 20 -#define ARM_SAI_SLOT_COUNT_Msk (0x1FUL << ARM_SAI_SLOT_COUNT_Pos) -#define ARM_SAI_SLOT_COUNT(n) ((((n)-1UL)&0x1FUL) << ARM_SAI_SLOT_COUNT_Pos) ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Slot Size -----*/ -#define ARM_SAI_SLOT_SIZE_Pos 25 -#define ARM_SAI_SLOT_SIZE_Msk (3UL << ARM_SAI_SLOT_SIZE_Pos) -#define ARM_SAI_SLOT_SIZE_DEFAULT (0UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size is equal to data size (default) -#define ARM_SAI_SLOT_SIZE_16 (1UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 16 bits; User Protocol only (ignored otherwise) -#define ARM_SAI_SLOT_SIZE_32 (3UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 32 bits; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Slot Offset -----*/ -#define ARM_SAI_SLOT_OFFSET_Pos 27 -#define ARM_SAI_SLOT_OFFSET_Msk (0x1FUL << ARM_SAI_SLOT_OFFSET_Pos) -#define ARM_SAI_SLOT_OFFSET(n) (((n)&0x1FUL) << ARM_SAI_SLOT_OFFSET_Pos) ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise) - -/****** SAI Configuration (arg2) *****/ - -/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/ -#define ARM_SAI_AUDIO_FREQ_Msk (0x0FFFFFUL) ///< Audio frequency mask - -/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/ -#define ARM_SAI_MCLK_PRESCALER_Pos 20 -#define ARM_SAI_MCLK_PRESCALER_Msk (0xFFFUL << ARM_SAI_MCLK_PRESCALER_Pos) -#define ARM_SAI_MCLK_PRESCALER(n) ((((n)-1UL)&0xFFFUL) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1) - - -/****** SAI specific error codes *****/ -#define ARM_SAI_ERROR_SYNCHRONIZATION (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Synchronization not supported -#define ARM_SAI_ERROR_PROTOCOL (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Protocol not supported -#define ARM_SAI_ERROR_DATA_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified Data size not supported -#define ARM_SAI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported -#define ARM_SAI_ERROR_MONO_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Mono mode not supported -#define ARM_SAI_ERROR_COMPANDING (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Companding not supported -#define ARM_SAI_ERROR_CLOCK_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock polarity not supported -#define ARM_SAI_ERROR_AUDIO_FREQ (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Audio frequency not supported -#define ARM_SAI_ERROR_MCLK_PIN (ARM_DRIVER_ERROR_SPECIFIC - 9) ///< Specified MCLK Pin setting not supported -#define ARM_SAI_ERROR_MCLK_PRESCALER (ARM_DRIVER_ERROR_SPECIFIC - 10) ///< Specified MCLK Prescaler not supported -#define ARM_SAI_ERROR_FRAME_LENGTH (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported -#define ARM_SAI_ERROR_FRAME_LENGHT (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported @deprecated use \ref ARM_SAI_ERROR_FRAME_LENGTH instead -#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH (ARM_DRIVER_ERROR_SPECIFIC - 12) ///< Specified Frame Sync width not supported -#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 13) ///< Specified Frame Sync polarity not supported -#define ARM_SAI_ERROR_FRAME_SYNC_EARLY (ARM_DRIVER_ERROR_SPECIFIC - 14) ///< Specified Frame Sync early not supported -#define ARM_SAI_ERROR_SLOT_COUNT (ARM_DRIVER_ERROR_SPECIFIC - 15) ///< Specified Slot count not supported -#define ARM_SAI_ERROR_SLOT_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 16) ///< Specified Slot size not supported -#define ARM_SAI_ERROR_SLOT_OFFESET (ARM_DRIVER_ERROR_SPECIFIC - 17) ///< Specified Slot offset not supported - - -/** -\brief SAI Status -*/ -typedef struct _ARM_SAI_STATUS { - uint32_t tx_busy : 1; ///< Transmitter busy flag - uint32_t rx_busy : 1; ///< Receiver busy flag - uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) - uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) - uint32_t frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation) - uint32_t reserved : 27; -} ARM_SAI_STATUS; - - -/****** SAI Event *****/ -#define ARM_SAI_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed -#define ARM_SAI_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed -#define ARM_SAI_EVENT_TX_UNDERFLOW (1UL << 2) ///< Transmit data not available -#define ARM_SAI_EVENT_RX_OVERFLOW (1UL << 3) ///< Receive data overflow -#define ARM_SAI_EVENT_FRAME_ERROR (1UL << 4) ///< Sync Frame error in Slave mode (optional) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_SAI_CAPABILITIES - - \fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event) - \brief Initialize SAI Interface. - \param[in] cb_event Pointer to \ref ARM_SAI_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_SAI_Uninitialize (void) - \brief De-initialize SAI Interface. - \return \ref execution_status - - \fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state) - \brief Control SAI Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_SAI_Send (const void *data, uint32_t num) - \brief Start sending data to SAI transmitter. - \param[in] data Pointer to buffer with data to send to SAI transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_SAI_Receive (void *data, uint32_t num) - \brief Start receiving data from SAI receiver. - \param[out] data Pointer to buffer for data to receive from SAI receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn uint32_t ARM_SAI_GetTxCount (void) - \brief Get transmitted data count. - \return number of data items transmitted - - \fn uint32_t ARM_SAI_GetRxCount (void) - \brief Get received data count. - \return number of data items received - - \fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2) - \brief Control SAI Interface. - \param[in] control Operation - \param[in] arg1 Argument 1 of operation (optional) - \param[in] arg2 Argument 2 of operation (optional) - \return common \ref execution_status and driver specific \ref sai_execution_status - - \fn ARM_SAI_STATUS ARM_SAI_GetStatus (void) - \brief Get SAI status. - \return SAI status \ref ARM_SAI_STATUS - - \fn void ARM_SAI_SignalEvent (uint32_t event) - \brief Signal SAI Events. - \param[in] event \ref SAI_events notification mask - \return none -*/ - -typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event. - - -/** -\brief SAI Driver Capabilities. -*/ -typedef struct _ARM_SAI_CAPABILITIES { - uint32_t asynchronous : 1; ///< supports asynchronous Transmit/Receive - uint32_t synchronous : 1; ///< supports synchronous Transmit/Receive - uint32_t protocol_user : 1; ///< supports user defined Protocol - uint32_t protocol_i2s : 1; ///< supports I2S Protocol - uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol - uint32_t protocol_pcm : 1; ///< supports PCM short/long frame Protocol - uint32_t protocol_ac97 : 1; ///< supports AC'97 Protocol - uint32_t mono_mode : 1; ///< supports Mono mode - uint32_t companding : 1; ///< supports Companding - uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin - uint32_t event_frame_error : 1; ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR - uint32_t reserved : 21; ///< Reserved (must be zero) -} ARM_SAI_CAPABILITIES; - - -/** -\brief Access structure of the SAI Driver. -*/ -typedef struct _ARM_DRIVER_SAI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version. - ARM_SAI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_SAI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface. - uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count. - uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count. - int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface. - ARM_SAI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status. -} const ARM_DRIVER_SAI; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_SAI_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_SPI.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_SPI.h deleted file mode 100644 index 1c8517e..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_SPI.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V2.3 - * - * Project: SPI (Serial Peripheral Interface) Driver definitions - */ - -/* History: - * Version 2.3 - * Removed Simplex Mode (deprecated) - * Removed volatile from ARM_SPI_STATUS - * Version 2.2 - * ARM_SPI_STATUS made volatile - * Version 2.1 - * Renamed status flag "tx_rx_busy" to "busy" - * Version 2.0 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * Added: - * Slave Mode - * Half-duplex Modes - * Configurable number of data bits - * Support for TI Mode and Microwire - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added "send_done_event" to Capabilities - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_SPI_H_ -#define DRIVER_SPI_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ - - -#define _ARM_Driver_SPI_(n) Driver_SPI##n -#define ARM_Driver_SPI_(n) _ARM_Driver_SPI_(n) - - -/****** SPI Control Codes *****/ - -#define ARM_SPI_CONTROL_Pos 0 -#define ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos) - -/*----- SPI Control Codes: Mode -----*/ -#define ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) ///< SPI Inactive -#define ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps -#define ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output on MISO, Input on MOSI) -#define ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps @deprecated Simplex Mode has been removed -#define ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output/Input on MISO) @deprecated Simplex Mode has been removed - -/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/ -#define ARM_SPI_FRAME_FORMAT_Pos 8 -#define ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos) -#define ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 0 (default) -#define ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 1 -#define ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 0 -#define ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 1 -#define ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Texas Instruments Frame Format -#define ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) ///< National Semiconductor Microwire Frame Format - -/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/ -#define ARM_SPI_DATA_BITS_Pos 12 -#define ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos) -#define ARM_SPI_DATA_BITS(n) (((n) & 0x3FUL) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits - -/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/ -#define ARM_SPI_BIT_ORDER_Pos 18 -#define ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos) -#define ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from MSB to LSB (default) -#define ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from LSB to MSB - -/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/ -#define ARM_SPI_SS_MASTER_MODE_Pos 19 -#define ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos) -#define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default) -#define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled -#define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output -#define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input -#define ARM_SPI_SS_SLAVE_MODE_Pos 21 -#define ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) -#define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Hardware monitored (default) -#define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Software controlled - - -/*----- SPI Control Codes: Miscellaneous Controls -----*/ -#define ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) ///< Set Bus Speed in bps; arg = value -#define ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) ///< Get Bus Speed in bps -#define ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) ///< Set default Transmit value; arg = value -#define ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) ///< Control Slave Select; arg: 0=inactive, 1=active -#define ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) ///< Abort current data transfer - - -/****** SPI Slave Select Signal definitions *****/ -#define ARM_SPI_SS_INACTIVE 0UL ///< SPI Slave Select Signal Inactive -#define ARM_SPI_SS_ACTIVE 1UL ///< SPI Slave Select Signal Active - - -/****** SPI specific error codes *****/ -#define ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported -#define ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported -#define ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported -#define ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported -#define ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported - - -/** -\brief SPI Status -*/ -typedef struct _ARM_SPI_STATUS { - uint32_t busy : 1; ///< Transmitter/Receiver busy flag - uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) - uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation) - uint32_t reserved : 29; -} ARM_SPI_STATUS; - - -/****** SPI Event *****/ -#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed -#define ARM_SPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow -#define ARM_SPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_SPI_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_SPI_CAPABILITIES - - \fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event) - \brief Initialize SPI Interface. - \param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_SPI_Uninitialize (void) - \brief De-initialize SPI Interface. - \return \ref execution_status - - \fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state) - \brief Control SPI Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_SPI_Send (const void *data, uint32_t num) - \brief Start sending data to SPI transmitter. - \param[in] data Pointer to buffer with data to send to SPI transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_SPI_Receive (void *data, uint32_t num) - \brief Start receiving data from SPI receiver. - \param[out] data Pointer to buffer for data to receive from SPI receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn int32_t ARM_SPI_Transfer (const void *data_out, - void *data_in, - uint32_t num) - \brief Start sending/receiving data to/from SPI transmitter/receiver. - \param[in] data_out Pointer to buffer with data to send to SPI transmitter - \param[out] data_in Pointer to buffer for data to receive from SPI receiver - \param[in] num Number of data items to transfer - \return \ref execution_status - - \fn uint32_t ARM_SPI_GetDataCount (void) - \brief Get transferred data count. - \return number of data items transferred - - \fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg) - \brief Control SPI Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return common \ref execution_status and driver specific \ref spi_execution_status - - \fn ARM_SPI_STATUS ARM_SPI_GetStatus (void) - \brief Get SPI status. - \return SPI status \ref ARM_SPI_STATUS - - \fn void ARM_SPI_SignalEvent (uint32_t event) - \brief Signal SPI Events. - \param[in] event \ref SPI_events notification mask - \return none -*/ - -typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event. - - -/** -\brief SPI Driver Capabilities. -*/ -typedef struct _ARM_SPI_CAPABILITIES { - uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave) @deprecated Reserved (must be zero) - uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface - uint32_t microwire : 1; ///< supports Microwire Interface - uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT - uint32_t reserved : 28; ///< Reserved (must be zero) -} ARM_SPI_CAPABILITIES; - - -/** -\brief Access structure of the SPI Driver. -*/ -typedef struct _ARM_DRIVER_SPI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version. - ARM_SPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_SPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface. - int32_t (*Transfer) (const void *data_out, - void *data_in, - uint32_t num); ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI. - uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface. - ARM_SPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status. -} const ARM_DRIVER_SPI; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_SPI_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_Storage.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_Storage.h deleted file mode 100644 index 21356a2..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_Storage.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 24. January 2020 - * $Revision: V1.2 - * - * Project: Storage Driver definitions - */ - -/* History: - * Version 1.2 - * Removed volatile from ARM_STORAGE_STATUS - * Version 1.1 - * ARM_STORAGE_STATUS made volatile - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_STORAGE_H_ -#define DRIVER_STORAGE_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "Driver_Common.h" - -#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2) /* API version */ - - -#define _ARM_Driver_Storage_(n) Driver_Storage##n -#define ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n) - -#define ARM_STORAGE_INVALID_OFFSET (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's - /// address space). A storage block may never start at this address. - -#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL) ///< Invalid address within the processor's memory address space. - /// Refer to memory-mapped storage, i.e. \ref ARM_DRIVER_STORAGE::ResolveAddress(). - -/****** Storage specific error codes *****/ -#define ARM_STORAGE_ERROR_NOT_ERASABLE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable. -#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable. -#define ARM_STORAGE_ERROR_PROTECTED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected. - -/** - * \brief Attributes of the storage range within a storage block. - */ -typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES { - uint32_t erasable : 1; ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'. - /// @note if 'erasable' is 0 (i.e. the 'erase' operation isn't available) then - /// 'erase_unit' (see below) is immaterial and should be 0. - uint32_t programmable : 1; ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'. - /// Writes are typically achieved through the ProgramData operation (following an erase); - /// if storage isn't erasable (see 'erasable' above) but is memory-mapped - /// (i.e. 'memory_mapped'), it can be written directly using memory-store operations. - uint32_t executable : 1; ///< This storage block can hold program data; the processor can fetch and execute code - /// sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO). - uint32_t protectable : 1; ///< The entire block can be protected from program and erase operations. Once protection - /// is enabled for a block, its 'erasable' and 'programmable' bits are turned off. - uint32_t reserved : 28; - uint32_t erase_unit; ///< Minimum erase size in bytes. - /// The offset of the start of the erase-range should also be aligned with this value. - /// Applicable if the 'erasable' attribute is set for the block. - /// @note if 'erasable' (see above) is 0 (i.e. the 'erase' operation isn't available) then - /// 'erase_unit' is immaterial and should be 0. - uint32_t protection_unit; ///< Minimum protectable size in bytes. Applicable if the 'protectable' - /// attribute is set for the block. This should be a divisor of the block's size. A - /// block can be considered to be made up of consecutive, individually-protectable fragments. -} ARM_STORAGE_BLOCK_ATTRIBUTES; - -/** - * \brief A storage block is a range of memory with uniform attributes. - */ -typedef struct _ARM_STORAGE_BLOCK { - uint64_t addr; ///< This is the start address of the storage block. It is - /// expressed as an offset from the start of the storage map - /// maintained by the owning storage controller. - uint64_t size; ///< This is the size of the storage block, in units of bytes. - /// Together with addr, it describes a range [addr, addr+size). - ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block. -} ARM_STORAGE_BLOCK; - -/** - * The check for a valid ARM_STORAGE_BLOCK. - */ -#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0)) - -/** - * \brief Values for encoding storage memory-types with respect to programmability. - * - * Please ensure that the maximum of the following memory types doesn't exceed 16; we - * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability. - */ -#define ARM_STORAGE_PROGRAMMABILITY_RAM (0U) -#define ARM_STORAGE_PROGRAMMABILITY_ROM (1U) ///< Read-only memory. -#define ARM_STORAGE_PROGRAMMABILITY_WORM (2U) ///< write-once-read-only-memory (WORM). -#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE (3U) ///< re-programmable based on erase. Supports multiple writes. - -/** - * Values for encoding data-retention levels for storage blocks. - * - * Please ensure that the maximum of the following retention types doesn't exceed 16; we - * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level. - */ -#define ARM_RETENTION_WHILE_DEVICE_ACTIVE (0U) ///< Data is retained only during device activity. -#define ARM_RETENTION_ACROSS_SLEEP (1U) ///< Data is retained across processor sleep. -#define ARM_RETENTION_ACROSS_DEEP_SLEEP (2U) ///< Data is retained across processor deep-sleep. -#define ARM_RETENTION_BATTERY_BACKED (3U) ///< Data is battery-backed. Device can be powered off. -#define ARM_RETENTION_NVM (4U) ///< Data is retained in non-volatile memory. - -/** - * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM. - */ -typedef struct _ARM_STORAGE_SECURITY_FEATURES { - uint32_t acls : 1; ///< Protection against internal software attacks using ACLs. - uint32_t rollback_protection : 1; ///< Roll-back protection. Set to true if the creator of the storage - /// can ensure that an external attacker can't force an - /// older firmware to run or to revert back to a previous state. - uint32_t tamper_proof : 1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors). - uint32_t internal_flash : 1; ///< Internal flash. - uint32_t reserved1 : 12; - - /** - * Encode support for hardening against various classes of attacks. - */ - uint32_t software_attacks : 1; ///< device software (malware running on the device). - uint32_t board_level_attacks : 1; ///< board level attacks (debug probes, copy protection fuses.) - uint32_t chip_level_attacks : 1; ///< chip level attacks (tamper-protection). - uint32_t side_channel_attacks : 1; ///< side channel attacks. - uint32_t reserved2 : 12; -} ARM_STORAGE_SECURITY_FEATURES; - -#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */ - -/** - * Device level metadata regarding the Storage implementation. - */ -typedef struct _ARM_STORAGE_INFO { - uint64_t total_storage; ///< Total available storage, in bytes. - uint32_t program_unit; ///< Minimum programming size in bytes. - /// The offset of the start of the program-range should also be aligned with this value. - /// Applicable only if the 'programmable' attribute is set for a block. - /// @note setting program_unit to 0 has the effect of disabling the size and alignment - /// restrictions (setting it to 1 also has the same effect). - uint32_t optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers - /// have internal buffers into which to receive data. Writing in chunks of - /// 'optimal_program_unit' would achieve maximum programming speed. - /// Applicable only if the 'programmable' attribute is set for the underlying block(s). - uint32_t program_cycles; ///< A measure of endurance for reprogramming. - /// Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance. - uint32_t erased_value : 1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF). - uint32_t memory_mapped : 1; ///< This storage device has a mapping onto the processor's memory address space. - /// @note For a memory-mapped block which isn't erasable but is programmable (i.e. if - /// 'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to - /// the memory-mapped storage without going through the ProgramData operation. - uint32_t programmability : 4; ///< A value to indicate storage programmability. - uint32_t retention_level : 4; - uint32_t reserved : 22; - ARM_STORAGE_SECURITY_FEATURES security; ///< \ref ARM_STORAGE_SECURITY_FEATURES -} ARM_STORAGE_INFO; - -/** -\brief Operating status of the storage controller. -*/ -typedef struct _ARM_STORAGE_STATUS { - uint32_t busy : 1; ///< Controller busy flag - uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation) - uint32_t reserved : 30; -} ARM_STORAGE_STATUS; - -/** - * \brief Storage Driver API Capabilities. - */ -typedef struct _ARM_STORAGE_CAPABILITIES { - uint32_t asynchronous_ops : 1; ///< Used to indicate if APIs like initialize, - /// read, erase, program, etc. can operate in asynchronous mode. - /// Setting this bit to 1 means that the driver is capable - /// of launching asynchronous operations; command completion is - /// signaled by the invocation of a completion callback. If - /// set to 1, drivers may still complete asynchronous - /// operations synchronously as necessary (in which case they - /// return a positive error code to indicate synchronous completion). - uint32_t erase_all : 1; ///< Supports EraseAll operation. - uint32_t reserved : 30; ///< Reserved (must be zero) -} ARM_STORAGE_CAPABILITIES; - -/** - * Command opcodes for Storage. - */ -typedef enum _ARM_STORAGE_OPERATION { - ARM_STORAGE_OPERATION_GET_VERSION, - ARM_STORAGE_OPERATION_GET_CAPABILITIES, - ARM_STORAGE_OPERATION_INITIALIZE, - ARM_STORAGE_OPERATION_UNINITIALIZE, - ARM_STORAGE_OPERATION_POWER_CONTROL, - ARM_STORAGE_OPERATION_READ_DATA, - ARM_STORAGE_OPERATION_PROGRAM_DATA, - ARM_STORAGE_OPERATION_ERASE, - ARM_STORAGE_OPERATION_ERASE_ALL, - ARM_STORAGE_OPERATION_GET_STATUS, - ARM_STORAGE_OPERATION_GET_INFO, - ARM_STORAGE_OPERATION_RESOLVE_ADDRESS, - ARM_STORAGE_OPERATION_GET_NEXT_BLOCK, - ARM_STORAGE_OPERATION_GET_BLOCK -} ARM_STORAGE_OPERATION; - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_Storage_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_STORAGE_CAPABILITIES -*/ -/** - \fn int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback) - \brief Initialize the Storage interface. - \param [in] callback Pointer to \ref ARM_Storage_Callback_t. - Caller-defined callback to be invoked upon command completion - for asynchronous APIs (including the completion of - initialization). Use a NULL pointer when no callback - signals are required. - \return If asynchronous activity is launched, invocation - ARM_DRIVER_OK, and the caller can expect to receive a callback in the - future with a status value of ARM_DRIVER_OK or an error-code. In the - case of synchronous execution, control returns after completion with a - value of 1. Return values less than ARM_DRIVER_OK (0) signify errors. -*/ -/** - \fn int32_t ARM_Storage_Uninitialize (void) - \brief De-initialize the Storage Interface. - \return If asynchronous activity is launched, an invocation returns - ARM_DRIVER_OK, and the caller can expect to receive a callback in the - future with a status value of ARM_DRIVER_OK or an error-code. In the - case of synchronous execution, control returns after completion with a - value of 1. Return values less than ARM_DRIVER_OK (0) signify errors. -*/ -/** - \fn int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state) - \brief Control the Storage interface power. - \param[in] state Power state - \return If asynchronous activity is launched, an invocation returns - ARM_DRIVER_OK, and the caller can expect to receive a callback in the - future with a status value of ARM_DRIVER_OK or an error-code. In the - case of synchronous execution, control returns after completion with a - value of 1. Return values less than ARM_DRIVER_OK (0) signify errors. -*/ -/** - \fn int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size) - \brief Read data from Storage. - \param[in] addr Data address. - \param[out] data Pointer to a buffer storing the data read from Storage. - \param[in] size Number of bytes to read. The data buffer - should be at least as large as this size. - \return If asynchronous activity is launched, an invocation returns - ARM_DRIVER_OK, and the caller can expect to receive a callback in the - future with the number of successfully transferred bytes passed in as - the 'status' parameter. In the case of synchronous execution, control - returns after completion with a positive transfer-count. Return values - less than ARM_DRIVER_OK (0) signify errors. -*/ -/** - \fn int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size) - \brief Program data to Storage. - \param [in] addr This is the start address of the range to be written into. It - needs to be aligned to the device's \em program_unit - specified in \ref ARM_STORAGE_INFO. - \param [in] data The source of the write operation. The buffer is owned by the - caller and should remain accessible for the lifetime of this - command. - \param [in] size The number of bytes requested to be written. The buffer - should be at least as large as this size. \note 'size' should - be a multiple of the device's 'program_unit' (see \ref - ARM_STORAGE_INFO). - \return If asynchronous activity is launched, an invocation returns - ARM_DRIVER_OK, and the caller can expect to receive a callback in the - future with the number of successfully transferred bytes passed in as - the 'status' parameter. In the case of synchronous execution, control - returns after completion with a positive transfer-count. Return values - less than ARM_DRIVER_OK (0) signify errors. -*/ -/** - \fn int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size) - \brief Erase Storage range. - \param [in] addr This is the start-address of the range to be erased. It must - start at an 'erase_unit' boundary of the underlying block. - \param [in] size Size (in bytes) of the range to be erased. 'addr + size' - must be aligned with the 'erase_unit' of the underlying - block. - \return If the range to be erased doesn't align with the erase_units of the - respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is - returned. If any part of the range is protected, - ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the range - is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All - such sanity-check failures result in the error code being - returned synchronously and the storage bytes within the range - remain unaffected. Otherwise the function executes in the - following ways: If asynchronous activity is launched, an - invocation returns ARM_DRIVER_OK, and the caller can expect to - receive a callback in the future with the number of successfully - erased bytes passed in as the 'status' parameter. In the case of - synchronous execution, control returns after completion with a - positive erase-count. Return values less than ARM_DRIVER_OK (0) - signify errors. -*/ -/** - \fn int32_t ARM_Storage_EraseAll (void) - \brief Erase complete Storage. - \return If any part of the storage range is protected, - ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the - storage range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is - returned. All such sanity-check failures result in the error code - being returned synchronously and the storage bytes within the - range remain unaffected. Otherwise the function executes in the - following ways: If asynchronous activity is launched, an - invocation returns ARM_DRIVER_OK, and the caller can expect to - receive a callback in the future with ARM_DRIVER_OK passed in as - the 'status' parameter. In the case of synchronous execution, - control returns after completion with a value of 1. Return values - less than ARM_DRIVER_OK (0) signify errors. -*/ -/** - \fn ARM_STORAGE_STATUS ARM_Storage_GetStatus (void) - \brief Get Storage status. - \return Storage status \ref ARM_STORAGE_STATUS -*/ -/** - \fn int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info) - \brief Get Storage information. - \param[out] info A caller-supplied buffer capable of being filled in with an \ref ARM_STORAGE_INFO. - \return ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level - metadata about the storage controller is filled into the supplied - buffer, else an appropriate error value. -*/ -/** - \fn uint32_t ARM_Storage_ResolveAddress(uint64_t addr) - \brief Resolve an address relative to the storage controller into a memory address. - \param[in] addr The address for which we want a resolution to the processor's physical address space. It is an offset from the - start of the storage map maintained by the owning storage - controller. - \return The resolved address in the processor's address space, else ARM_STORAGE_INVALID_ADDRESS. -*/ -/** - \fn int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block); - \brief Advance to the successor of the current block (iterator). - \param[in] prev_block An existing block (iterator) within the same storage - controller. The memory buffer holding this block is owned - by the caller. This pointer may be NULL; if so, the - invocation fills in the first block into the out parameter: - 'next_block'. - \param[out] next_block A caller-owned buffer large enough to be filled in with - the following ARM_STORAGE_BLOCK. It is legal to provide the - same buffer using 'next_block' as was passed in with 'prev_block'. It - is also legal to pass a NULL into this parameter if the - caller isn't interested in populating a buffer with the next - block, i.e. if the caller only wishes to establish the - presence of a next block. - \return ARM_DRIVER_OK if a valid next block is found (or first block, if - prev_block is passed as NULL); upon successful operation, the contents - of the next (or first) block are filled into the buffer pointed to by - the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is - guaranteed to be true. Upon reaching the end of the sequence of blocks - (iterators), or in case the driver is unable to fetch information about - the next (or first) block, an error (negative) value is returned and an - invalid StorageBlock is populated into the supplied buffer. If - prev_block is NULL, the first block is returned. -*/ -/** - \fn int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block); - \brief Find the storage block (iterator) encompassing a given storage address. - \param[in] addr Storage address in bytes. - \param[out] block A caller-owned buffer large enough to be filled in with the - ARM_STORAGE_BLOCK encapsulating the given address. This value - can also be passed in as NULL if the caller isn't interested - in populating a buffer with the block, if the caller only - wishes to establish the presence of a containing storage - block. - \return ARM_DRIVER_OK if a containing storage-block is found. In this case, - if block is non-NULL, the buffer pointed to by it is populated with - the contents of the storage block, i.e. if block is valid and a block is - found, ARM_STORAGE_VALID_BLOCK(block) would return true following this - call. If there is no storage block containing the given offset, or in - case the driver is unable to resolve an address to a storage-block, an - error (negative) value is returned and an invalid StorageBlock is - populated into the supplied buffer. -*/ - -/** - * Provides the typedef for the callback function \ref ARM_Storage_Callback_t. - */ -typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation); - -/** - * The set of operations constituting the Storage driver. - */ -typedef struct _ARM_DRIVER_STORAGE { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_Storage_GetVersion : Get driver version. - ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_Storage_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_Storage_Callback_t callback); ///< Pointer to \ref ARM_Storage_Initialize : Initialize the Storage Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_Storage_Uninitialize : De-initialize the Storage Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_Storage_PowerControl : Control the Storage interface power. - int32_t (*ReadData) (uint64_t addr, void *data, uint32_t size); ///< Pointer to \ref ARM_Storage_ReadData : Read data from Storage. - int32_t (*ProgramData) (uint64_t addr, const void *data, uint32_t size); ///< Pointer to \ref ARM_Storage_ProgramData : Program data to Storage. - int32_t (*Erase) (uint64_t addr, uint32_t size); ///< Pointer to \ref ARM_Storage_Erase : Erase Storage range. - int32_t (*EraseAll) (void); ///< Pointer to \ref ARM_Storage_EraseAll : Erase complete Storage. - ARM_STORAGE_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_Storage_GetStatus : Get Storage status. - int32_t (*GetInfo) (ARM_STORAGE_INFO *info); ///< Pointer to \ref ARM_Storage_GetInfo : Get Storage information. - uint32_t (*ResolveAddress) (uint64_t addr); ///< Pointer to \ref ARM_Storage_ResolveAddress : Resolve a storage address. - int32_t (*GetNextBlock) (const ARM_STORAGE_BLOCK* prev, ARM_STORAGE_BLOCK *next); ///< Pointer to \ref ARM_Storage_GetNextBlock : fetch successor for current block. - int32_t (*GetBlock) (uint64_t addr, ARM_STORAGE_BLOCK *block); ///< Pointer to \ref ARM_Storage_GetBlock : -} const ARM_DRIVER_STORAGE; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_STORAGE_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USART.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_USART.h deleted file mode 100644 index 7947b33..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USART.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V2.4 - * - * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) - * Driver definitions - */ - -/* History: - * Version 2.4 - * Removed volatile from ARM_USART_STATUS and ARM_USART_MODEM_STATUS - * Version 2.3 - * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile - * Version 2.2 - * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions - * Version 2.1 - * Removed optional argument parameter from Signal Event - * Version 2.0 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * renamed driver UART -> USART (Asynchronous & Synchronous) - * Added modes: - * Synchronous - * Single-wire - * IrDA - * Smart Card - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added events: - * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT - * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD - * Added functions: SetTxThreshold, SetRxThreshold - * Added "rx_timeout_event" to capabilities - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_USART_H_ -#define DRIVER_USART_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ - - -#define _ARM_Driver_USART_(n) Driver_USART##n -#define ARM_Driver_USART_(n) _ARM_Driver_USART_(n) - - -/****** USART Control Codes *****/ - -#define ARM_USART_CONTROL_Pos 0 -#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) - -/*----- USART Control Codes: Mode -----*/ -#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) -#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate -#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate -#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate - -/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ -#define ARM_USART_DATA_BITS_Pos 8 -#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) -#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits -#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit -#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits -#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) -#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits - -/*----- USART Control Codes: Mode Parameters: Parity -----*/ -#define ARM_USART_PARITY_Pos 12 -#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) -#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) -#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity -#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity - -/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ -#define ARM_USART_STOP_BITS_Pos 14 -#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) -#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) -#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits -#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits -#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits - -/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ -#define ARM_USART_FLOW_CONTROL_Pos 16 -#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) -#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) -#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control -#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control -#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control - -/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ -#define ARM_USART_CPOL_Pos 18 -#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) -#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) -#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 - -/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ -#define ARM_USART_CPHA_Pos 19 -#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) -#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) -#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 - - -/*----- USART Control Codes: Miscellaneous Controls -----*/ -#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value -#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period -#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods -#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated -#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled -#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send -#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive -#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer - - - -/****** USART specific error codes *****/ -#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported -#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported -#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported -#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported -#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported -#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported -#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported -#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported - - -/** -\brief USART Status -*/ -typedef struct _ARM_USART_STATUS { - uint32_t tx_busy : 1; ///< Transmitter busy flag - uint32_t rx_busy : 1; ///< Receiver busy flag - uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) - uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) - uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) - uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) - uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) - uint32_t reserved : 25; -} ARM_USART_STATUS; - -/** -\brief USART Modem Control -*/ -typedef enum _ARM_USART_MODEM_CONTROL { - ARM_USART_RTS_CLEAR, ///< Deactivate RTS - ARM_USART_RTS_SET, ///< Activate RTS - ARM_USART_DTR_CLEAR, ///< Deactivate DTR - ARM_USART_DTR_SET ///< Activate DTR -} ARM_USART_MODEM_CONTROL; - -/** -\brief USART Modem Status -*/ -typedef struct _ARM_USART_MODEM_STATUS { - uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive - uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive - uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive - uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive - uint32_t reserved : 28; -} ARM_USART_MODEM_STATUS; - - -/****** USART Event *****/ -#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data -#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed -#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed -#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) -#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) -#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow -#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) -#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive -#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive -#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive -#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) -#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) -#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) -#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) - \brief Get driver capabilities - \return \ref ARM_USART_CAPABILITIES - - \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) - \brief Initialize USART Interface. - \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_USART_Uninitialize (void) - \brief De-initialize USART Interface. - \return \ref execution_status - - \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) - \brief Control USART Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_USART_Send (const void *data, uint32_t num) - \brief Start sending data to USART transmitter. - \param[in] data Pointer to buffer with data to send to USART transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_USART_Receive (void *data, uint32_t num) - \brief Start receiving data from USART receiver. - \param[out] data Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn int32_t ARM_USART_Transfer (const void *data_out, - void *data_in, - uint32_t num) - \brief Start sending/receiving data to/from USART transmitter/receiver. - \param[in] data_out Pointer to buffer with data to send to USART transmitter - \param[out] data_in Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to transfer - \return \ref execution_status - - \fn uint32_t ARM_USART_GetTxCount (void) - \brief Get transmitted data count. - \return number of data items transmitted - - \fn uint32_t ARM_USART_GetRxCount (void) - \brief Get received data count. - \return number of data items received - - \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) - \brief Control USART Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return common \ref execution_status and driver specific \ref usart_execution_status - - \fn ARM_USART_STATUS ARM_USART_GetStatus (void) - \brief Get USART status. - \return USART status \ref ARM_USART_STATUS - - \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) - \brief Set USART Modem Control line state. - \param[in] control \ref ARM_USART_MODEM_CONTROL - \return \ref execution_status - - \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) - \brief Get USART Modem Status lines state. - \return modem status \ref ARM_USART_MODEM_STATUS - - \fn void ARM_USART_SignalEvent (uint32_t event) - \brief Signal USART Events. - \param[in] event \ref USART_events notification mask - \return none -*/ - -typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. - - -/** -\brief USART Device Driver Capabilities. -*/ -typedef struct _ARM_USART_CAPABILITIES { - uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode - uint32_t synchronous_master : 1; ///< supports Synchronous Master mode - uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode - uint32_t single_wire : 1; ///< supports UART Single-wire mode - uint32_t irda : 1; ///< supports UART IrDA mode - uint32_t smart_card : 1; ///< supports UART Smart Card mode - uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available - uint32_t flow_control_rts : 1; ///< RTS Flow Control available - uint32_t flow_control_cts : 1; ///< CTS Flow Control available - uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE - uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT - uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available - uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available - uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available - uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available - uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available - uint32_t ri : 1; ///< RI Line: 0=not available, 1=available - uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS - uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR - uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD - uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI - uint32_t reserved : 11; ///< Reserved (must be zero) -} ARM_USART_CAPABILITIES; - - -/** -\brief Access structure of the USART Driver. -*/ -typedef struct _ARM_DRIVER_USART { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. - ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. - int32_t (*Transfer) (const void *data_out, - void *data_in, - uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. - uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. - uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. - ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. - int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. - ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. -} const ARM_DRIVER_USART; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_USART_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USB.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_USB.h deleted file mode 100644 index 472050e..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USB.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 24. January 2020 - * $Revision: V2.0 - * - * Project: USB Driver common definitions - */ - -/* History: - * Version 2.0 - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added PID Types - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_USB_H_ -#define DRIVER_USB_H_ - -#include "Driver_Common.h" - -/* USB Role */ -#define ARM_USB_ROLE_NONE (0U) -#define ARM_USB_ROLE_HOST (1U) -#define ARM_USB_ROLE_DEVICE (2U) - -/* USB Pins */ -#define ARM_USB_PIN_DP (1U << 0) ///< USB D+ pin -#define ARM_USB_PIN_DM (1U << 1) ///< USB D- pin -#define ARM_USB_PIN_VBUS (1U << 2) ///< USB VBUS pin -#define ARM_USB_PIN_OC (1U << 3) ///< USB OverCurrent pin -#define ARM_USB_PIN_ID (1U << 4) ///< USB ID pin - -/* USB Speed */ -#define ARM_USB_SPEED_LOW (0U) ///< Low-speed USB -#define ARM_USB_SPEED_FULL (1U) ///< Full-speed USB -#define ARM_USB_SPEED_HIGH (2U) ///< High-speed USB - -/* USB PID Types */ -#define ARM_USB_PID_OUT (1U) -#define ARM_USB_PID_IN (9U) -#define ARM_USB_PID_SOF (5U) -#define ARM_USB_PID_SETUP (13U) -#define ARM_USB_PID_DATA0 (3U) -#define ARM_USB_PID_DATA1 (11U) -#define ARM_USB_PID_DATA2 (7U) -#define ARM_USB_PID_MDATA (15U) -#define ARM_USB_PID_ACK (2U) -#define ARM_USB_PID_NAK (10U) -#define ARM_USB_PID_STALL (14U) -#define ARM_USB_PID_NYET (6U) -#define ARM_USB_PID_PRE (12U) -#define ARM_USB_PID_ERR (12U) -#define ARM_USB_PID_SPLIT (8U) -#define ARM_USB_PID_PING (4U) -#define ARM_USB_PID_RESERVED (0U) - -/* USB Endpoint Address (bEndpointAddress) */ -#define ARM_USB_ENDPOINT_NUMBER_MASK (0x0FU) -#define ARM_USB_ENDPOINT_DIRECTION_MASK (0x80U) - -/* USB Endpoint Type */ -#define ARM_USB_ENDPOINT_CONTROL (0U) ///< Control Endpoint -#define ARM_USB_ENDPOINT_ISOCHRONOUS (1U) ///< Isochronous Endpoint -#define ARM_USB_ENDPOINT_BULK (2U) ///< Bulk Endpoint -#define ARM_USB_ENDPOINT_INTERRUPT (3U) ///< Interrupt Endpoint - -/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */ -#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK (0x07FFU) -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK (0x1800U) -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1 (0x0000U) -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2 (0x0800U) -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3 (0x1000U) - -#endif /* DRIVER_USB_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USBD.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_USBD.h deleted file mode 100644 index b4152bd..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USBD.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V2.3 - * - * Project: USB Device Driver definitions - */ - -/* History: - * Version 2.3 - * Removed volatile from ARM_USBD_STATE - * Version 2.2 - * ARM_USBD_STATE made volatile - * Version 2.1 - * Added ARM_USBD_ReadSetupPacket function - * Version 2.0 - * Removed ARM_USBD_DeviceConfigure function - * Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function - * Removed ARM_USBD_EndpointReadStart function - * Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer - * Added ARM_USBD_EndpointTransferGetResult function - * Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_USBD_H_ -#define DRIVER_USBD_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_USB.h" - -#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ - - -#define _ARM_Driver_USBD_(n) Driver_USBD##n -#define ARM_Driver_USBD_(n) _ARM_Driver_USBD_(n) - - -/** -\brief USB Device State -*/ -typedef struct _ARM_USBD_STATE { - uint32_t vbus : 1; ///< USB Device VBUS flag - uint32_t speed : 2; ///< USB Device speed setting (ARM_USB_SPEED_xxx) - uint32_t active : 1; ///< USB Device active flag - uint32_t reserved : 28; -} ARM_USBD_STATE; - - -/****** USB Device Event *****/ -#define ARM_USBD_EVENT_VBUS_ON (1UL << 0) ///< USB Device VBUS On -#define ARM_USBD_EVENT_VBUS_OFF (1UL << 1) ///< USB Device VBUS Off -#define ARM_USBD_EVENT_RESET (1UL << 2) ///< USB Reset occurred -#define ARM_USBD_EVENT_HIGH_SPEED (1UL << 3) ///< USB switch to High Speed occurred -#define ARM_USBD_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred -#define ARM_USBD_EVENT_RESUME (1UL << 5) ///< USB Resume occurred - -/****** USB Endpoint Event *****/ -#define ARM_USBD_EVENT_SETUP (1UL << 0) ///< SETUP Packet -#define ARM_USBD_EVENT_OUT (1UL << 1) ///< OUT Packet(s) -#define ARM_USBD_EVENT_IN (1UL << 2) ///< IN Packet(s) - - -#ifndef __DOXYGEN_MW__ // exclude from middleware documentation - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USBD_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_USBD_CAPABILITIES -*/ -/** - \fn int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) - \brief Initialize USB Device Interface. - \param[in] cb_device_event Pointer to \ref ARM_USBD_SignalDeviceEvent - \param[in] cb_endpoint_event Pointer to \ref ARM_USBD_SignalEndpointEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_Uninitialize (void) - \brief De-initialize USB Device Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state) - \brief Control USB Device Interface Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_DeviceConnect (void) - \brief Connect USB Device. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_DeviceDisconnect (void) - \brief Disconnect USB Device. - \return \ref execution_status -*/ -/** - \fn ARM_USBD_STATE ARM_USBD_DeviceGetState (void) - \brief Get current USB Device State. - \return Device State \ref ARM_USBD_STATE -*/ -/** - \fn int32_t ARM_USBD_DeviceRemoteWakeup (void) - \brief Trigger USB Remote Wakeup. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr) - \brief Set USB Device Address. - \param[in] dev_addr Device Address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup) - \brief Read setup packet received over Control Endpoint. - \param[out] setup Pointer to buffer for setup packet - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointConfigure (uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size) - \brief Configure USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx) - \param[in] ep_max_packet_size Endpoint Maximum Packet Size - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr) - \brief Unconfigure USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall) - \brief Set/Clear Stall for USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] stall Operation - - \b false Clear - - \b true Set - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) - \brief Read data from or Write data to USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[out] data Pointer to buffer for data to read or with data to write - \param[in] num Number of data bytes to transfer - \return \ref execution_status -*/ -/** - \fn uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr) - \brief Get result of USB Endpoint transfer. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return number of successfully transferred data bytes -*/ -/** - \fn int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr) - \brief Abort current USB Endpoint transfer. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return \ref execution_status -*/ -/** - \fn uint16_t ARM_USBD_GetFrameNumber (void) - \brief Get current USB Frame Number. - \return Frame Number -*/ - -/** - \fn void ARM_USBD_SignalDeviceEvent (uint32_t event) - \brief Signal USB Device Event. - \param[in] event \ref USBD_dev_events - \return none -*/ -/** - \fn void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event) - \brief Signal USB Endpoint Event. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] event \ref USBD_ep_events - \return none -*/ - -typedef void (*ARM_USBD_SignalDeviceEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event. -typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event); ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event. - - -/** -\brief USB Device Driver Capabilities. -*/ -typedef struct _ARM_USBD_CAPABILITIES { - uint32_t vbus_detection : 1; ///< VBUS detection - uint32_t event_vbus_on : 1; ///< Signal VBUS On event - uint32_t event_vbus_off : 1; ///< Signal VBUS Off event - uint32_t reserved : 29; ///< Reserved (must be zero) -} ARM_USBD_CAPABILITIES; - - -/** -\brief Access structure of the USB Device Driver. -*/ -typedef struct _ARM_DRIVER_USBD { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version. - ARM_USBD_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event); ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power. - int32_t (*DeviceConnect) (void); ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device. - int32_t (*DeviceDisconnect) (void); ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device. - ARM_USBD_STATE (*DeviceGetState) (void); ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State. - int32_t (*DeviceRemoteWakeup) (void); ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup. - int32_t (*DeviceSetAddress) (uint8_t dev_addr); ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address. - int32_t (*ReadSetupPacket) (uint8_t *setup); ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint. - int32_t (*EndpointConfigure) (uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint. - int32_t (*EndpointUnconfigure) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint. - int32_t (*EndpointStall) (uint8_t ep_addr, bool stall); ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint. - int32_t (*EndpointTransfer) (uint8_t ep_addr, uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint. - uint32_t (*EndpointTransferGetResult) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer. - int32_t (*EndpointTransferAbort) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer. - uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number. -} const ARM_DRIVER_USBD; - -#endif /* __DOXYGEN_MW__ */ - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_USBD_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USBH.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_USBH.h deleted file mode 100644 index b92ee85..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_USBH.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 31. March 2020 - * $Revision: V2.3 - * - * Project: USB Host Driver definitions -*/ - -/* History: - * Version 2.3 - * Removed volatile from ARM_USBH_PORT_STATE - * Version 2.2 - * ARM_USBH_PORT_STATE made volatile - * Version 2.1 - * Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE - * Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe... - * Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent - * Version 2.0 - * Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff - * Changed function ARM_USBH_EndpointCreate parameters - * Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify - * Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset - * Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer - * Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort - * Added function ARM_USBH_EndpointTransferGetResult - * Added function ARM_USBH_GetFrameNumber - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.20 - * Added API for OHCI/EHCI Host Controller Interface (HCI) - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_USBH_H_ -#define DRIVER_USBH_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_USB.h" - -#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ - - -#define _ARM_Driver_USBH_(n) Driver_USBH##n -#define ARM_Driver_USBH_(n) _ARM_Driver_USBH_(n) - - -/** -\brief USB Host Port State -*/ -typedef struct _ARM_USBH_PORT_STATE { - uint32_t connected : 1; ///< USB Host Port connected flag - uint32_t overcurrent : 1; ///< USB Host Port overcurrent flag - uint32_t speed : 2; ///< USB Host Port speed setting (ARM_USB_SPEED_xxx) - uint32_t reserved : 28; -} ARM_USBH_PORT_STATE; - -/** -\brief USB Host Pipe Handle -*/ -typedef uint32_t ARM_USBH_PIPE_HANDLE; -#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE /* Legacy name */ - - -/****** USB Host Packet Information *****/ -#define ARM_USBH_PACKET_TOKEN_Pos 0 -#define ARM_USBH_PACKET_TOKEN_Msk (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos) -#define ARM_USBH_PACKET_SETUP (0x01UL << ARM_USBH_PACKET_TOKEN_Pos) ///< SETUP Packet -#define ARM_USBH_PACKET_OUT (0x02UL << ARM_USBH_PACKET_TOKEN_Pos) ///< OUT Packet -#define ARM_USBH_PACKET_IN (0x03UL << ARM_USBH_PACKET_TOKEN_Pos) ///< IN Packet -#define ARM_USBH_PACKET_PING (0x04UL << ARM_USBH_PACKET_TOKEN_Pos) ///< PING Packet - -#define ARM_USBH_PACKET_DATA_Pos 4 -#define ARM_USBH_PACKET_DATA_Msk (0x0FUL << ARM_USBH_PACKET_DATA_Pos) -#define ARM_USBH_PACKET_DATA0 (0x01UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA0 PID -#define ARM_USBH_PACKET_DATA1 (0x02UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA1 PID - -#define ARM_USBH_PACKET_SPLIT_Pos 8 -#define ARM_USBH_PACKET_SPLIT_Msk (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos) -#define ARM_USBH_PACKET_SSPLIT (0x08UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet -#define ARM_USBH_PACKET_SSPLIT_S (0x09UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data Start -#define ARM_USBH_PACKET_SSPLIT_E (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data End -#define ARM_USBH_PACKET_SSPLIT_S_E (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data All -#define ARM_USBH_PACKET_CSPLIT (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos) ///< CSPLIT Packet - -#define ARM_USBH_PACKET_PRE (1UL << 12) ///< PRE Token - - -/****** USB Host Port Event *****/ -#define ARM_USBH_EVENT_CONNECT (1UL << 0) ///< USB Device Connected to Port -#define ARM_USBH_EVENT_DISCONNECT (1UL << 1) ///< USB Device Disconnected from Port -#define ARM_USBH_EVENT_OVERCURRENT (1UL << 2) ///< USB Device caused Overcurrent -#define ARM_USBH_EVENT_RESET (1UL << 3) ///< USB Reset completed -#define ARM_USBH_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred -#define ARM_USBH_EVENT_RESUME (1UL << 5) ///< USB Resume occurred -#define ARM_USBH_EVENT_REMOTE_WAKEUP (1UL << 6) ///< USB Device activated Remote Wakeup - -/****** USB Host Pipe Event *****/ -#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Transfer completed -#define ARM_USBH_EVENT_HANDSHAKE_NAK (1UL << 1) ///< NAK Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_NYET (1UL << 2) ///< NYET Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_MDATA (1UL << 3) ///< MDATA Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_STALL (1UL << 4) ///< STALL Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_ERR (1UL << 5) ///< ERR Handshake received -#define ARM_USBH_EVENT_BUS_ERROR (1UL << 6) ///< Bus Error detected - - -#ifndef __DOXYGEN_MW__ // exclude from middleware documentation - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USBH_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_USBH_CAPABILITIES -*/ -/** - \fn int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event, - ARM_USBH_SignalPipeEvent_t cb_pipe_event) - \brief Initialize USB Host Interface. - \param[in] cb_port_event Pointer to \ref ARM_USBH_SignalPortEvent - \param[in] cb_pipe_event Pointer to \ref ARM_USBH_SignalPipeEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_Uninitialize (void) - \brief De-initialize USB Host Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state) - \brief Control USB Host Interface Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus) - \brief Root HUB Port VBUS on/off. - \param[in] port Root HUB Port Number - \param[in] vbus - - \b false VBUS off - - \b true VBUS on - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortReset (uint8_t port) - \brief Do Root HUB Port Reset. - \param[in] port Root HUB Port Number - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortSuspend (uint8_t port) - \brief Suspend Root HUB Port (stop generating SOFs). - \param[in] port Root HUB Port Number - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortResume (uint8_t port) - \brief Resume Root HUB Port (start generating SOFs). - \param[in] port Root HUB Port Number - \return \ref execution_status -*/ -/** - \fn ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port) - \brief Get current Root HUB Port State. - \param[in] port Root HUB Port Number - \return Port State \ref ARM_USBH_PORT_STATE -*/ -/** - \fn ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size, - uint8_t ep_interval) - \brief Create Pipe in System. - \param[in] dev_addr Device Address - \param[in] dev_speed Device Speed - \param[in] hub_addr Hub Address - \param[in] hub_port Hub Port - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx) - \param[in] ep_max_packet_size Endpoint Maximum Packet Size - \param[in] ep_interval Endpoint Polling Interval - \return Pipe Handle \ref ARM_USBH_PIPE_HANDLE -*/ -/** - \fn int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint16_t ep_max_packet_size) - \brief Modify Pipe in System. - \param[in] pipe_hndl Pipe Handle - \param[in] dev_addr Device Address - \param[in] dev_speed Device Speed - \param[in] hub_addr Hub Address - \param[in] hub_port Hub Port - \param[in] ep_max_packet_size Endpoint Maximum Packet Size - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Delete Pipe from System. - \param[in] pipe_hndl Pipe Handle - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Reset Pipe. - \param[in] pipe_hndl Pipe Handle - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint32_t packet, - uint8_t *data, - uint32_t num) - \brief Transfer packets through USB Pipe. - \param[in] pipe_hndl Pipe Handle - \param[in] packet Packet information - \param[in] data Pointer to buffer with data to send or for data to receive - \param[in] num Number of data bytes to transfer - \return \ref execution_status -*/ -/** - \fn uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Get result of USB Pipe transfer. - \param[in] pipe_hndl Pipe Handle - \return number of successfully transferred data bytes -*/ -/** - \fn int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Abort current USB Pipe transfer. - \param[in] pipe_hndl Pipe Handle - \return \ref execution_status -*/ -/** - \fn uint16_t ARM_USBH_GetFrameNumber (void) - \brief Get current USB Frame Number. - \return Frame Number -*/ - -/** - \fn void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event) - \brief Signal Root HUB Port Event. - \param[in] port Root HUB Port Number - \param[in] event \ref USBH_port_events - \return none -*/ -/** - \fn void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event) - \brief Signal Pipe Event. - \param[in] pipe_hndl Pipe Handle - \param[in] event \ref USBH_pipe_events - \return none -*/ - -typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event. -typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event. -#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t /* Legacy name */ - - -/** -\brief USB Host Driver Capabilities. -*/ -typedef struct _ARM_USBH_CAPABILITIES { - uint32_t port_mask : 15; ///< Root HUB available Ports Mask - uint32_t auto_split : 1; ///< Automatic SPLIT packet handling - uint32_t event_connect : 1; ///< Signal Connect event - uint32_t event_disconnect : 1; ///< Signal Disconnect event - uint32_t event_overcurrent : 1; ///< Signal Overcurrent event - uint32_t reserved : 13; ///< Reserved (must be zero) -} ARM_USBH_CAPABILITIES; - - -/** -\brief Access structure of USB Host Driver. -*/ -typedef struct _ARM_DRIVER_USBH { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version. - ARM_USBH_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USBH_SignalPortEvent_t cb_port_event, - ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. - int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. - int32_t (*PortReset) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset. - int32_t (*PortSuspend) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs). - int32_t (*PortResume) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). - ARM_USBH_PORT_STATE (*PortGetState) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. - ARM_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size, - uint8_t ep_interval); ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. - int32_t (*PipeModify) (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. - int32_t (*PipeDelete) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. - int32_t (*PipeReset) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. - int32_t (*PipeTransfer) (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint32_t packet, - uint8_t *data, - uint32_t num); ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. - uint32_t (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. - int32_t (*PipeTransferAbort) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. - uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. -} const ARM_DRIVER_USBH; - - -// HCI (OHCI/EHCI) - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void) - \brief Get USB Host HCI (OHCI/EHCI) driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_USBH_HCI_CAPABILITIES -*/ -/** - \fn int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt) - \brief Initialize USB Host HCI (OHCI/EHCI) Interface. - \param[in] cb_interrupt Pointer to Interrupt Handler Routine - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_HCI_Uninitialize (void) - \brief De-initialize USB Host HCI (OHCI/EHCI) Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state) - \brief Control USB Host HCI (OHCI/EHCI) Interface Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus) - \brief USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off. - \param[in] port Root HUB Port Number - \param[in] vbus - - \b false VBUS off - - \b true VBUS on - \return \ref execution_status -*/ - -/** - \fn void ARM_USBH_HCI_Interrupt (void) - \brief USB Host HCI Interrupt Handler. - \return none -*/ - -typedef void (*ARM_USBH_HCI_Interrupt_t) (void); ///< Pointer to Interrupt Handler Routine. - - -/** -\brief USB Host HCI (OHCI/EHCI) Driver Capabilities. -*/ -typedef struct _ARM_USBH_HCI_CAPABILITIES { - uint32_t port_mask : 15; ///< Root HUB available Ports Mask - uint32_t reserved : 17; ///< Reserved (must be zero) -} ARM_USBH_HCI_CAPABILITIES; - - -/** - \brief Access structure of USB Host HCI (OHCI/EHCI) Driver. -*/ -typedef struct _ARM_DRIVER_USBH_HCI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version. - ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power. - int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off. -} const ARM_DRIVER_USBH_HCI; - -#endif /* __DOXYGEN_MW__ */ - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_USBH_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/Include/Driver_WiFi.h b/external/CMSIS_5/CMSIS/Driver/Include/Driver_WiFi.h deleted file mode 100644 index eb8979f..0000000 --- a/external/CMSIS_5/CMSIS/Driver/Include/Driver_WiFi.h +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright (c) 2019-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 30. March 2022 - * $Revision: V1.1 - * - * Project: WiFi (Wireless Fidelity Interface) Driver definitions - */ - -/* History: - * Version 1.1 - * Extended Socket Receive/RecvFrom/Send/SendTo (support for polling) - * Version 1.0 - * Initial release - */ - -#ifndef DRIVER_WIFI_H_ -#define DRIVER_WIFI_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_WIFI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1) /* API version */ - - -#define _ARM_Driver_WiFi_(n) Driver_WiFi##n -#define ARM_Driver_WiFi_(n) _ARM_Driver_WiFi_(n) - - -/****** WiFi SetOption/GetOption Function Option Codes *****/ -#define ARM_WIFI_BSSID 1U ///< Station/AP Set/Get BSSID of AP to connect or of AP; data = &bssid, len = 6, uint8_t[6] -#define ARM_WIFI_TX_POWER 2U ///< Station/AP Set/Get transmit power; data = &power, len = 4, uint32_t: 0 .. 20 [dBm] -#define ARM_WIFI_LP_TIMER 3U ///< Station Set/Get low-power deep-sleep time; data = &time, len = 4, uint32_t [seconds]: 0 = disable (default) -#define ARM_WIFI_DTIM 4U ///< Station/AP Set/Get DTIM interval; data = &dtim, len = 4, uint32_t [beacons] -#define ARM_WIFI_BEACON 5U ///< AP Set/Get beacon interval; data = &interval, len = 4, uint32_t [ms] -#define ARM_WIFI_MAC 6U ///< Station/AP Set/Get MAC; data = &mac, len = 6, uint8_t[6] -#define ARM_WIFI_IP 7U ///< Station/AP Set/Get IPv4 static/assigned address; data = &ip, len = 4, uint8_t[4] -#define ARM_WIFI_IP_SUBNET_MASK 8U ///< Station/AP Set/Get IPv4 subnet mask; data = &mask, len = 4, uint8_t[4] -#define ARM_WIFI_IP_GATEWAY 9U ///< Station/AP Set/Get IPv4 gateway address; data = &ip, len = 4, uint8_t[4] -#define ARM_WIFI_IP_DNS1 10U ///< Station/AP Set/Get IPv4 primary DNS address; data = &ip, len = 4, uint8_t[4] -#define ARM_WIFI_IP_DNS2 11U ///< Station/AP Set/Get IPv4 secondary DNS address; data = &ip, len = 4, uint8_t[4] -#define ARM_WIFI_IP_DHCP 12U ///< Station/AP Set/Get IPv4 DHCP client/server enable/disable; data = &dhcp, len = 4, uint32_t: 0 = disable, non-zero = enable (default) -#define ARM_WIFI_IP_DHCP_POOL_BEGIN 13U ///< AP Set/Get IPv4 DHCP pool begin address; data = &ip, len = 4, uint8_t[4] -#define ARM_WIFI_IP_DHCP_POOL_END 14U ///< AP Set/Get IPv4 DHCP pool end address; data = &ip, len = 4, uint8_t[4] -#define ARM_WIFI_IP_DHCP_LEASE_TIME 15U ///< AP Set/Get IPv4 DHCP lease time; data = &time, len = 4, uint32_t [seconds] -#define ARM_WIFI_IP6_GLOBAL 16U ///< Station/AP Set/Get IPv6 global address; data = &ip6, len = 16, uint8_t[16] -#define ARM_WIFI_IP6_LINK_LOCAL 17U ///< Station/AP Set/Get IPv6 link local address; data = &ip6, len = 16, uint8_t[16] -#define ARM_WIFI_IP6_SUBNET_PREFIX_LEN 18U ///< Station/AP Set/Get IPv6 subnet prefix length; data = &len, len = 4, uint32_t: 1 .. 127 -#define ARM_WIFI_IP6_GATEWAY 19U ///< Station/AP Set/Get IPv6 gateway address; data = &ip6, len = 16, uint8_t[16] -#define ARM_WIFI_IP6_DNS1 20U ///< Station/AP Set/Get IPv6 primary DNS address; data = &ip6, len = 16, uint8_t[16] -#define ARM_WIFI_IP6_DNS2 21U ///< Station/AP Set/Get IPv6 secondary DNS address; data = &ip6, len = 16, uint8_t[16] -#define ARM_WIFI_IP6_DHCP_MODE 22U ///< Station/AP Set/Get IPv6 DHCPv6 client mode; data = &mode, len = 4, uint32_t: ARM_WIFI_IP6_DHCP_xxx (default Off) - -/****** WiFi Security Type *****/ -#define ARM_WIFI_SECURITY_OPEN 0U ///< Open -#define ARM_WIFI_SECURITY_WEP 1U ///< Wired Equivalent Privacy (WEP) with Pre-Sheared Key (PSK) -#define ARM_WIFI_SECURITY_WPA 2U ///< WiFi Protected Access (WPA) with PSK -#define ARM_WIFI_SECURITY_WPA2 3U ///< WiFi Protected Access II (WPA2) with PSK -#define ARM_WIFI_SECURITY_UNKNOWN 255U ///< Unknown - -/****** WiFi Protected Setup (WPS) Method *****/ -#define ARM_WIFI_WPS_METHOD_NONE 0U ///< Not used -#define ARM_WIFI_WPS_METHOD_PBC 1U ///< Push Button Configuration -#define ARM_WIFI_WPS_METHOD_PIN 2U ///< PIN - -/****** WiFi IPv6 Dynamic Host Configuration Protocol (DHCP) Mode *****/ -#define ARM_WIFI_IP6_DHCP_OFF 0U ///< Static Host Configuration (default) -#define ARM_WIFI_IP6_DHCP_STATELESS 1U ///< Dynamic Host Configuration stateless DHCPv6 -#define ARM_WIFI_IP6_DHCP_STATEFULL 2U ///< Dynamic Host Configuration statefull DHCPv6 - -/****** WiFi Event *****/ -#define ARM_WIFI_EVENT_AP_CONNECT (1UL << 0) ///< Access Point: Station has connected; arg = &mac, mac (uint8_t[6]) -#define ARM_WIFI_EVENT_AP_DISCONNECT (1UL << 1) ///< Access Point: Station has disconnected; arg = &mac, mac (uint8_t[6]) -#define ARM_WIFI_EVENT_ETH_RX_FRAME (1UL << 4) ///< Ethernet Frame Received (in bypass mode only); arg = interface (0 = Station, 1 = Access Point) - - -/** -\brief WiFi Configuration -*/ -typedef struct ARM_WIFI_CONFIG_s { - const char *ssid; ///< Pointer to Service Set Identifier (SSID) null-terminated string - const char *pass; ///< Pointer to Password null-terminated string - uint8_t security; ///< Security type (ARM_WIFI_SECURITY_xxx) - uint8_t ch; ///< WiFi Channel (0 = auto, otherwise = exact channel) - uint8_t reserved; ///< Reserved - uint8_t wps_method; ///< WiFi Protected Setup (WPS) method (ARM_WIFI_WPS_METHOD_xxx) - const char *wps_pin; ///< Pointer to WiFi Protected Setup (WPS) PIN null-terminated string -} ARM_WIFI_CONFIG_t; - -/** -\brief WiFi Scan Information -*/ -typedef struct ARM_WIFI_SCAN_INFO_s { - char ssid[32+1]; ///< Service Set Identifier (SSID) null-terminated string - uint8_t bssid[6]; ///< Basic Service Set Identifier (BSSID) - uint8_t security; ///< Security type (ARM_WIFI_SECURITY_xxx) - uint8_t ch; ///< WiFi Channel - uint8_t rssi; ///< Received Signal Strength Indicator -} ARM_WIFI_SCAN_INFO_t; - -/** -\brief WiFi Network Information -*/ -typedef struct ARM_WIFI_NET_INFO_s { - char ssid[32+1]; ///< Service Set Identifier (SSID) null-terminated string - char pass[64+1]; ///< Password null-terminated string - uint8_t security; ///< Security type (ARM_WIFI_SECURITY_xxx) - uint8_t ch; ///< WiFi Channel - uint8_t rssi; ///< Received Signal Strength Indicator -} ARM_WIFI_NET_INFO_t; - -/****** Socket Address Family definitions *****/ -#define ARM_SOCKET_AF_INET 1 ///< IPv4 -#define ARM_SOCKET_AF_INET6 2 ///< IPv6 - -/****** Socket Type definitions *****/ -#define ARM_SOCKET_SOCK_STREAM 1 ///< Stream socket -#define ARM_SOCKET_SOCK_DGRAM 2 ///< Datagram socket - -/****** Socket Protocol definitions *****/ -#define ARM_SOCKET_IPPROTO_TCP 1 ///< TCP -#define ARM_SOCKET_IPPROTO_UDP 2 ///< UDP - -/****** Socket Option definitions *****/ -#define ARM_SOCKET_IO_FIONBIO 1 ///< Non-blocking I/O (Set only, default = 0); opt_val = &nbio, opt_len = sizeof(nbio), nbio (integer): 0=blocking, non-blocking otherwise -#define ARM_SOCKET_SO_RCVTIMEO 2 ///< Receive timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout) -#define ARM_SOCKET_SO_SNDTIMEO 3 ///< Send timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout) -#define ARM_SOCKET_SO_KEEPALIVE 4 ///< Keep-alive messages (default = 0); opt_val = &keepalive, opt_len = sizeof(keepalive), keepalive (integer): 0=disabled, enabled otherwise -#define ARM_SOCKET_SO_TYPE 5 ///< Socket Type (Get only); opt_val = &socket_type, opt_len = sizeof(socket_type), socket_type (integer): ARM_SOCKET_SOCK_xxx - -/****** Socket Function return codes *****/ -#define ARM_SOCKET_ERROR (-1) ///< Unspecified error -#define ARM_SOCKET_ESOCK (-2) ///< Invalid socket -#define ARM_SOCKET_EINVAL (-3) ///< Invalid argument -#define ARM_SOCKET_ENOTSUP (-4) ///< Operation not supported -#define ARM_SOCKET_ENOMEM (-5) ///< Not enough memory -#define ARM_SOCKET_EAGAIN (-6) ///< Operation would block or timed out -#define ARM_SOCKET_EINPROGRESS (-7) ///< Operation in progress -#define ARM_SOCKET_ETIMEDOUT (-8) ///< Operation timed out -#define ARM_SOCKET_EISCONN (-9) ///< Socket is connected -#define ARM_SOCKET_ENOTCONN (-10) ///< Socket is not connected -#define ARM_SOCKET_ECONNREFUSED (-11) ///< Connection rejected by the peer -#define ARM_SOCKET_ECONNRESET (-12) ///< Connection reset by the peer -#define ARM_SOCKET_ECONNABORTED (-13) ///< Connection aborted locally -#define ARM_SOCKET_EALREADY (-14) ///< Connection already in progress -#define ARM_SOCKET_EADDRINUSE (-15) ///< Address in use -#define ARM_SOCKET_EHOSTNOTFOUND (-16) ///< Host not found - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_WIFI_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_WIFI_CAPABILITIES ARM_WIFI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_WIFI_CAPABILITIES -*/ -/** - \fn int32_t ARM_WIFI_Initialize (ARM_WIFI_SignalEvent_t cb_event) - \brief Initialize WiFi Module. - \param[in] cb_event Pointer to \ref ARM_WIFI_SignalEvent_t - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed -*/ -/** - \fn int32_t ARM_WIFI_Uninitialize (void) - \brief De-initialize WiFi Module. - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed -*/ -/** - \fn int32_t ARM_WIFI_PowerControl (ARM_POWER_STATE state) - \brief Control WiFi Module Power. - \param[in] state Power state - - \ref ARM_POWER_OFF : Power off: no operation possible - - \ref ARM_POWER_LOW : Low-power mode: sleep or deep-sleep depending on \ref ARM_WIFI_LP_TIMER option set - - \ref ARM_POWER_FULL : Power on: full operation at maximum performance - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid state) -*/ -/** - \fn int32_t ARM_WIFI_GetModuleInfo (char *module_info, uint32_t max_len) - \brief Get Module information. - \param[out] module_info Pointer to character buffer were info string will be returned - \param[in] max_len Maximum length of string to return (including null terminator) - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (NULL module_info pointer or max_len equals to 0) -*/ -/** - \fn int32_t ARM_WIFI_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len) - \brief Set WiFi Module Options. - \param[in] interface Interface (0 = Station, 1 = Access Point) - \param[in] option Option to set - \param[in] data Pointer to data relevant to selected option - \param[in] len Length of data (in bytes) - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface, NULL data pointer or len less than option specifies) -*/ -/** - \fn int32_t ARM_WIFI_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len) - \brief Get WiFi Module Options. - \param[in] interface Interface (0 = Station, 1 = Access Point) - \param[in] option Option to get - \param[out] data Pointer to memory where data for selected option will be returned - \param[in,out] len Pointer to length of data (input/output) - - input: maximum length of data that can be returned (in bytes) - - output: length of returned data (in bytes) - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface, NULL data or len pointer, or *len less than option specifies) -*/ -/** - \fn int32_t ARM_WIFI_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num) - \brief Scan for available networks in range. - \param[out] scan_info Pointer to array of ARM_WIFI_SCAN_INFO_t structures where available Scan Information will be returned - \param[in] max_num Maximum number of Network Information structures to return - \return number of ARM_WIFI_SCAN_INFO_t structures returned or error code - - value >= 0 : Number of ARM_WIFI_SCAN_INFO_t structures returned - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (NULL scan_info pointer or max_num equal to 0) -*/ -/** - \fn int32_t ARM_WIFI_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config) - \brief Activate interface (Connect to a wireless network or activate an access point). - \param[in] interface Interface (0 = Station, 1 = Access Point) - \param[in] config Pointer to ARM_WIFI_CONFIG_t structure where Configuration parameters are located - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_TIMEOUT : Timeout occurred - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported (security type, channel autodetect or WPS not supported) - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface, NULL config pointer or invalid configuration) -*/ -/** - \fn int32_t ARM_WIFI_Deactivate (uint32_t interface) - \brief Deactivate interface (Disconnect from a wireless network or deactivate an access point). - \param[in] interface Interface (0 = Station, 1 = Access Point) - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface) -*/ -/** - \fn uint32_t ARM_WIFI_IsConnected (void) - \brief Get station connection status. - \return station connection status - - value != 0: Station connected - - value = 0: Station not connected -*/ -/** - \fn int32_t ARM_WIFI_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info) - \brief Get station Network Information. - \param[out] net_info Pointer to ARM_WIFI_NET_INFO_t structure where station Network Information will be returned - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed (station not connected) - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface or NULL net_info pointer) -*/ -/** - \fn int32_t ARM_WIFI_BypassControl (uint32_t interface, uint32_t mode) - \brief Enable or disable bypass (pass-through) mode. Transmit and receive Ethernet frames (IP layer bypassed and WiFi/Ethernet translation). - \param[in] interface Interface (0 = Station, 1 = Access Point) - \param[in] mode - - value = 1: all packets bypass internal IP stack - - value = 0: all packets processed by internal IP stack - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface or mode) -*/ -/** - \fn int32_t ARM_WIFI_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len) - \brief Send Ethernet frame (in bypass mode only). - \param[in] interface Interface (0 = Station, 1 = Access Point) - \param[in] frame Pointer to frame buffer with data to send - \param[in] len Frame buffer length in bytes - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_BUSY : Driver is busy - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface or NULL frame pointer) -*/ -/** - \fn int32_t ARM_WIFI_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len) - \brief Read data of received Ethernet frame (in bypass mode only). - \param[in] interface Interface (0 = Station, 1 = Access Point) - \param[in] frame Pointer to frame buffer for data to read into - \param[in] len Frame buffer length in bytes - \return number of data bytes read or error code - - value >= 0 : Number of data bytes read - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (invalid interface or NULL frame pointer) -*/ -/** - \fn uint32_t ARM_WIFI_EthGetRxFrameSize (uint32_t interface) - \brief Get size of received Ethernet frame (in bypass mode only). - \param[in] interface Interface (0 = Station, 1 = Access Point) - \return number of bytes in received frame -*/ -/** - \fn int32_t ARM_WIFI_SocketCreate (int32_t af, int32_t type, int32_t protocol) - \brief Create a communication socket. - \param[in] af Address family - \param[in] type Socket type - \param[in] protocol Socket protocol - \return status information - - Socket identification number (>=0) - - \ref ARM_SOCKET_EINVAL : Invalid argument - - \ref ARM_SOCKET_ENOTSUP : Operation not supported - - \ref ARM_SOCKET_ENOMEM : Not enough memory - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) - \brief Assign a local address to a socket. - \param[in] socket Socket identification number - \param[in] ip Pointer to local IP address - \param[in] ip_len Length of 'ip' address in bytes - \param[in] port Local port number - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (address or socket already bound) - - \ref ARM_SOCKET_EADDRINUSE : Address already in use - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketListen (int32_t socket, int32_t backlog) - \brief Listen for socket connections. - \param[in] socket Socket identification number - \param[in] backlog Number of connection requests that can be queued - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (socket not bound) - - \ref ARM_SOCKET_ENOTSUP : Operation not supported - - \ref ARM_SOCKET_EISCONN : Socket is already connected - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) - \brief Accept a new connection on a socket. - \param[in] socket Socket identification number - \param[out] ip Pointer to buffer where address of connecting socket shall be returned (NULL for none) - \param[in,out] ip_len Pointer to length of 'ip' (or NULL if 'ip' is NULL) - - length of supplied 'ip' on input - - length of stored 'ip' on output - \param[out] port Pointer to buffer where port of connecting socket shall be returned (NULL for none) - \return status information - - socket identification number of accepted socket (>=0) - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (socket not in listen mode) - - \ref ARM_SOCKET_ENOTSUP : Operation not supported (socket type does not support accepting connections) - - \ref ARM_SOCKET_ECONNRESET : Connection reset by the peer - - \ref ARM_SOCKET_ECONNABORTED : Connection aborted locally - - \ref ARM_SOCKET_EAGAIN : Operation would block or timed out (may be called again) - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) - \brief Connect a socket to a remote host. - \param[in] socket Socket identification number - \param[in] ip Pointer to remote IP address - \param[in] ip_len Length of 'ip' address in bytes - \param[in] port Remote port number - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument - - \ref ARM_SOCKET_EALREADY : Connection already in progress - - \ref ARM_SOCKET_EINPROGRESS : Operation in progress - - \ref ARM_SOCKET_EISCONN : Socket is connected - - \ref ARM_SOCKET_ECONNREFUSED : Connection rejected by the peer - - \ref ARM_SOCKET_ECONNABORTED : Connection aborted locally - - \ref ARM_SOCKET_EADDRINUSE : Address already in use - - \ref ARM_SOCKET_ETIMEDOUT : Operation timed out - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketRecv (int32_t socket, void *buf, uint32_t len) - \brief Receive data or check if data is available on a connected socket. - \param[in] socket Socket identification number - \param[out] buf Pointer to buffer where data should be stored - \param[in] len Length of buffer (in bytes), set len = 0 to check if data is available - \return status information - - number of bytes received (>=0), if len != 0 - - 0 : Data is available (len = 0) - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (pointer to buffer or length) - - \ref ARM_SOCKET_ENOTCONN : Socket is not connected - - \ref ARM_SOCKET_ECONNRESET : Connection reset by the peer - - \ref ARM_SOCKET_ECONNABORTED : Connection aborted locally - - \ref ARM_SOCKET_EAGAIN : Operation would block or timed out (may be called again) - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port) - \brief Receive data or check if data is available on a socket. - \param[in] socket Socket identification number - \param[out] buf Pointer to buffer where data should be stored - \param[in] len Length of buffer (in bytes), set len = 0 to check if data is available - \param[out] ip Pointer to buffer where remote source address shall be returned (NULL for none) - \param[in,out] ip_len Pointer to length of 'ip' (or NULL if 'ip' is NULL) - - length of supplied 'ip' on input - - length of stored 'ip' on output - \param[out] port Pointer to buffer where remote source port shall be returned (NULL for none) - \return status information - - number of bytes received (>=0), if len != 0 - - 0 : Data is available (len = 0) - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (pointer to buffer or length) - - \ref ARM_SOCKET_ENOTCONN : Socket is not connected - - \ref ARM_SOCKET_ECONNRESET : Connection reset by the peer - - \ref ARM_SOCKET_ECONNABORTED : Connection aborted locally - - \ref ARM_SOCKET_EAGAIN : Operation would block or timed out (may be called again) - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketSend (int32_t socket, const void *buf, uint32_t len) - \brief Send data or check if data can be sent on a connected socket. - \param[in] socket Socket identification number - \param[in] buf Pointer to buffer containing data to send - \param[in] len Length of data (in bytes), set len = 0 to check if data can be sent - \return status information - - number of bytes sent (>=0), if len != 0 - - 0 : Data can be sent (len = 0) - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (pointer to buffer or length) - - \ref ARM_SOCKET_ENOTCONN : Socket is not connected - - \ref ARM_SOCKET_ECONNRESET : Connection reset by the peer - - \ref ARM_SOCKET_ECONNABORTED : Connection aborted locally - - \ref ARM_SOCKET_EAGAIN : Operation would block or timed out (may be called again) - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port) - \brief Send data or check if data can be sent on a socket. - \param[in] socket Socket identification number - \param[in] buf Pointer to buffer containing data to send - \param[in] len Length of data (in bytes), set len = 0 to check if data can be sent - \param[in] ip Pointer to remote destination IP address - \param[in] ip_len Length of 'ip' address in bytes - \param[in] port Remote destination port number - \return status information - - number of bytes sent (>=0), if len != 0 - - 0 : Data can be sent (len = 0) - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (pointer to buffer or length) - - \ref ARM_SOCKET_ENOTCONN : Socket is not connected - - \ref ARM_SOCKET_ECONNRESET : Connection reset by the peer - - \ref ARM_SOCKET_ECONNABORTED : Connection aborted locally - - \ref ARM_SOCKET_EAGAIN : Operation would block or timed out (may be called again) - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) - \brief Retrieve local IP address and port of a socket. - \param[in] socket Socket identification number - \param[out] ip Pointer to buffer where local address shall be returned (NULL for none) - \param[in,out] ip_len Pointer to length of 'ip' (or NULL if 'ip' is NULL) - - length of supplied 'ip' on input - - length of stored 'ip' on output - \param[out] port Pointer to buffer where local port shall be returned (NULL for none) - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (pointer to buffer or length) - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) - \brief Retrieve remote IP address and port of a socket. - \param[in] socket Socket identification number - \param[out] ip Pointer to buffer where remote address shall be returned (NULL for none) - \param[in,out] ip_len Pointer to length of 'ip' (or NULL if 'ip' is NULL) - - length of supplied 'ip' on input - - length of stored 'ip' on output - \param[out] port Pointer to buffer where remote port shall be returned (NULL for none) - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument (pointer to buffer or length) - - \ref ARM_SOCKET_ENOTCONN : Socket is not connected - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len) - \brief Get socket option. - \param[in] socket Socket identification number - \param[in] opt_id Option identifier - \param[out] opt_val Pointer to the buffer that will receive the option value - \param[in,out] opt_len Pointer to length of the option value - - length of buffer on input - - length of data on output - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument - - \ref ARM_SOCKET_ENOTSUP : Operation not supported - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len) - \brief Set socket option. - \param[in] socket Socket identification number - \param[in] opt_id Option identifier - \param[in] opt_val Pointer to the option value - \param[in] opt_len Length of the option value in bytes - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EINVAL : Invalid argument - - \ref ARM_SOCKET_ENOTSUP : Operation not supported - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketClose (int32_t socket) - \brief Close and release a socket. - \param[in] socket Socket identification number - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_ESOCK : Invalid socket - - \ref ARM_SOCKET_EAGAIN : Operation would block (may be called again) - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len) - \brief Retrieve host IP address from host name. - \param[in] name Host name - \param[in] af Address family - \param[out] ip Pointer to buffer where resolved IP address shall be returned - \param[in,out] ip_len Pointer to length of 'ip' - - length of supplied 'ip' on input - - length of stored 'ip' on output - \return status information - - 0 : Operation successful - - \ref ARM_SOCKET_EINVAL : Invalid argument - - \ref ARM_SOCKET_ENOTSUP : Operation not supported - - \ref ARM_SOCKET_ETIMEDOUT : Operation timed out - - \ref ARM_SOCKET_EHOSTNOTFOUND : Host not found - - \ref ARM_SOCKET_ERROR : Unspecified error -*/ -/** - \fn int32_t ARM_WIFI_Ping (const uint8_t *ip, uint32_t ip_len) - \brief Probe remote host with Ping command. - \param[in] ip Pointer to remote host IP address - \param[in] ip_len Length of 'ip' address in bytes - \return execution status - - \ref ARM_DRIVER_OK : Operation successful - - \ref ARM_DRIVER_ERROR : Operation failed - - \ref ARM_DRIVER_ERROR_TIMEOUT : Timeout occurred - - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported - - \ref ARM_DRIVER_ERROR_PARAMETER : Parameter error (NULL ip pointer or ip_len different than 4 or 16) -*/ -/** - \fn void ARM_WIFI_SignalEvent (uint32_t event, void *arg) - \brief Signal WiFi Events. - \param[in] event \ref wifi_event notification mask - \param[in] arg Pointer to argument of signaled event - \return none -*/ - -typedef void (*ARM_WIFI_SignalEvent_t) (uint32_t event, void *arg); ///< Pointer to \ref ARM_WIFI_SignalEvent : Signal WiFi Event. - - -/** -\brief WiFi Driver Capabilities. -*/ -typedef struct _ARM_WIFI_CAPABILITIES { - uint32_t station : 1; ///< Station - uint32_t ap : 1; ///< Access Point - uint32_t station_ap : 1; ///< Concurrent Station and Access Point - uint32_t wps_station : 1; ///< WiFi Protected Setup (WPS) for Station - uint32_t wps_ap : 1; ///< WiFi Protected Setup (WPS) for Access Point - uint32_t event_ap_connect : 1; ///< Access Point: event generated on Station connect - uint32_t event_ap_disconnect : 1; ///< Access Point: event generated on Station disconnect - uint32_t event_eth_rx_frame : 1; ///< Event generated on Ethernet frame reception in bypass mode - uint32_t bypass_mode : 1; ///< Bypass or pass-through mode (Ethernet interface) - uint32_t ip : 1; ///< IP (UDP/TCP) (Socket interface) - uint32_t ip6 : 1; ///< IPv6 (Socket interface) - uint32_t ping : 1; ///< Ping (ICMP) - uint32_t reserved : 20; ///< Reserved (must be zero) -} ARM_WIFI_CAPABILITIES; - -/** -\brief Access structure of the WiFi Driver. -*/ -typedef struct _ARM_DRIVER_WIFI { - ARM_DRIVER_VERSION (*GetVersion) (void); - ARM_WIFI_CAPABILITIES (*GetCapabilities) (void); - int32_t (*Initialize) (ARM_WIFI_SignalEvent_t cb_event); - int32_t (*Uninitialize) (void); - int32_t (*PowerControl) (ARM_POWER_STATE state); - int32_t (*GetModuleInfo) (char *module_info, uint32_t max_len); - int32_t (*SetOption) (uint32_t interface, uint32_t option, const void *data, uint32_t len); - int32_t (*GetOption) (uint32_t interface, uint32_t option, void *data, uint32_t *len); - int32_t (*Scan) (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num); - int32_t (*Activate) (uint32_t interface, const ARM_WIFI_CONFIG_t *config); - int32_t (*Deactivate) (uint32_t interface); - uint32_t (*IsConnected) (void); - int32_t (*GetNetInfo) (ARM_WIFI_NET_INFO_t *net_info); - int32_t (*BypassControl) (uint32_t interface, uint32_t mode); - int32_t (*EthSendFrame) (uint32_t interface, const uint8_t *frame, uint32_t len); - int32_t (*EthReadFrame) (uint32_t interface, uint8_t *frame, uint32_t len); - uint32_t (*EthGetRxFrameSize) (uint32_t interface); - int32_t (*SocketCreate) (int32_t af, int32_t type, int32_t protocol); - int32_t (*SocketBind) (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port); - int32_t (*SocketListen) (int32_t socket, int32_t backlog); - int32_t (*SocketAccept) (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port); - int32_t (*SocketConnect) (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port); - int32_t (*SocketRecv) (int32_t socket, void *buf, uint32_t len); - int32_t (*SocketRecvFrom) (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port); - int32_t (*SocketSend) (int32_t socket, const void *buf, uint32_t len); - int32_t (*SocketSendTo) (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port); - int32_t (*SocketGetSockName) (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port); - int32_t (*SocketGetPeerName) (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port); - int32_t (*SocketGetOpt) (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len); - int32_t (*SocketSetOpt) (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len); - int32_t (*SocketClose) (int32_t socket); - int32_t (*SocketGetHostByName) (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len); - int32_t (*Ping) (const uint8_t *ip, uint32_t ip_len); -} const ARM_DRIVER_WIFI; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_WIFI_H_ */ diff --git a/external/CMSIS_5/CMSIS/Driver/VIO/Include/cmsis_vio.h b/external/CMSIS_5/CMSIS/Driver/VIO/Include/cmsis_vio.h deleted file mode 100644 index 8339cc1..0000000 --- a/external/CMSIS_5/CMSIS/Driver/VIO/Include/cmsis_vio.h +++ /dev/null @@ -1,175 +0,0 @@ -/****************************************************************************** - * @file cmsis_vio.h - * @brief CMSIS Virtual I/O header file - * @version V0.1.0 - * @date 23. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_VIO_H -#define __CMSIS_VIO_H - -#include - -/******************************************************************************* - * Generic I/O mapping recommended for CMSIS-VIO - * Note: not every I/O must be physically available - */ - -// vioSetSignal: mask values -#define vioLED0 (1U << 0) ///< \ref vioSetSignal \a mask parameter: LED 0 (for 3-color: red) -#define vioLED1 (1U << 1) ///< \ref vioSetSignal \a mask parameter: LED 1 (for 3-color: green) -#define vioLED2 (1U << 2) ///< \ref vioSetSignal \a mask parameter: LED 2 (for 3-color: blue) -#define vioLED3 (1U << 3) ///< \ref vioSetSignal \a mask parameter: LED 3 -#define vioLED4 (1U << 4) ///< \ref vioSetSignal \a mask parameter: LED 4 -#define vioLED5 (1U << 5) ///< \ref vioSetSignal \a mask parameter: LED 5 -#define vioLED6 (1U << 6) ///< \ref vioSetSignal \a mask parameter: LED 6 -#define vioLED7 (1U << 7) ///< \ref vioSetSignal \a mask parameter: LED 7 - -// vioSetSignal: signal values -#define vioLEDon (0xFFU) ///< \ref vioSetSignal \a signal parameter: pattern to turn any LED on -#define vioLEDoff (0x00U) ///< \ref vioSetSignal \a signal parameter: pattern to turn any LED off - -// vioGetSignal: mask values and return values -#define vioBUTTON0 (1U << 0) ///< \ref vioGetSignal \a mask parameter: Push button 0 -#define vioBUTTON1 (1U << 1) ///< \ref vioGetSignal \a mask parameter: Push button 1 -#define vioBUTTON2 (1U << 2) ///< \ref vioGetSignal \a mask parameter: Push button 2 -#define vioBUTTON3 (1U << 3) ///< \ref vioGetSignal \a mask parameter: Push button 3 -#define vioJOYup (1U << 4) ///< \ref vioGetSignal \a mask parameter: Joystick button: up -#define vioJOYdown (1U << 5) ///< \ref vioGetSignal \a mask parameter: Joystick button: down -#define vioJOYleft (1U << 6) ///< \ref vioGetSignal \a mask parameter: Joystick button: left -#define vioJOYright (1U << 7) ///< \ref vioGetSignal \a mask parameter: Joystick button: right -#define vioJOYselect (1U << 8) ///< \ref vioGetSignal \a mask parameter: Joystick button: select -#define vioJOYall (vioJOYup | \ - vioJOYdown | \ - vioJOYleft | \ - vioJOYright | \ - vioJOYselect) ///< \ref vioGetSignal \a mask Joystick button: all - -// vioSetValue / vioGetValue: id values -#define vioAIN0 (0U) ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 0 -#define vioAIN1 (1U) ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 1 -#define vioAIN2 (2U) ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 2 -#define vioAIN3 (3U) ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog input value 3 -#define vioAOUT0 (3U) ///< \ref vioSetValue / \ref vioGetValue \a id parameter: Analog output value 0 - -// vioSetXYZ / vioGetXZY: id values -#define vioMotionGyro (0U) ///< \ref vioSetXYZ / \ref vioGetXYZ \a id parameter: for Gyroscope -#define vioMotionAccelero (1U) ///< \ref vioSetXYZ / \ref vioGetXYZ \a id parameter: for Accelerometer -#define vioMotionMagneto (2U) ///< \ref vioSetXYZ / \ref vioGetXYZ \a id parameter: for Magnetometer - -// vioPrint: levels -#define vioLevelNone (0U) ///< \ref vioPrint \a level parameter: None -#define vioLevelHeading (1U) ///< \ref vioPrint \a level parameter: Heading -#define vioLevelMessage (2U) ///< \ref vioPrint \a level parameter: Message -#define vioLevelError (3U) ///< \ref vioPrint \a level parameter: Error - -/// 3-D vector value -typedef struct { - int32_t X; ///< X coordinate - int32_t Y; ///< Y coordinate - int32_t Z; ///< Z coordinate -} vioValueXYZ_t; - -/// IPv4 Internet Address -typedef struct { - uint8_t addr[4]; ///< IPv4 address value used in \ref vioSetIPv4 / \ref vioGetIPv4 -} vioAddrIPv4_t; - -/// IPv6 Internet Address -typedef struct { - uint8_t addr[16]; ///< IPv6 address value used in \ref vioSetIPv6 / \ref vioGetIPv6 -} vioAddrIPv6_t; - -#ifdef __cplusplus -extern "C" -{ -#endif - -/// Initialize test input, output. -/// \return none. -void vioInit (void); - -/// Print formated string to test terminal. -/// \param[in] level level (vioLevel...). -/// \param[in] format formated string to print. -/// \param[in] ... optional arguments (depending on format string). -/// \return number of characters written or -1 in case of error. -int32_t vioPrint (uint32_t level, const char *format, ...); - -/// Set signal output. -/// \param[in] mask bit mask of signals to set. -/// \param[in] signal signal value to set. -/// \return none. -void vioSetSignal (uint32_t mask, uint32_t signal); - -/// Get signal input. -/// \param[in] mask bit mask of signals to read. -/// \return signal value. -uint32_t vioGetSignal (uint32_t mask); - -/// Set value output. -/// \param[in] id output identifier. -/// \param[in] value value to set. -/// \return none. -void vioSetValue (uint32_t id, int32_t value); - -/// Get value input. -/// \param[in] id input identifier. -/// \return value retrieved from input. -int32_t vioGetValue (uint32_t id); - -/// Set XYZ value output. -/// \param[in] id output identifier. -/// \param[in] valueXYZ XYZ data to set. -/// \return none. -void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ); - -/// Get XYZ value input. -/// \param[in] id input identifier. -/// \return XYZ data retrieved from XYZ peripheral. -vioValueXYZ_t vioGetXYZ (uint32_t id); - -/// Set IPv4 address output. -/// \param[in] id output identifier. -/// \param[in] addrIPv4 pointer to IPv4 address. -/// \return none. -void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4); - -/// Get IPv4 address input. -/// \param[in] id input identifier. -/// \return IPv4 address retrieved from peripheral. -vioAddrIPv4_t vioGetIPv4 (uint32_t id); - -/// Set IPv6 address output. -/// \param[in] id output identifier. -/// \param[in] addrIPv6 pointer to IPv6 address. -/// \return none. -void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6); - -/// Get IPv6 address from peripheral. -/// \param[in] id input identifier. -/// \return IPv6 address retrieved from peripheral. -vioAddrIPv6_t vioGetIPv6 (uint32_t id); - -#ifdef __cplusplus -} -#endif - -#endif /* __CMSIS_VIO_H */ diff --git a/external/CMSIS_5/CMSIS/Driver/VIO/Source/vio.c b/external/CMSIS_5/CMSIS/Driver/VIO/Source/vio.c deleted file mode 100644 index 108efdc..0000000 --- a/external/CMSIS_5/CMSIS/Driver/VIO/Source/vio.c +++ /dev/null @@ -1,337 +0,0 @@ -/****************************************************************************** - * @file vio.c - * @brief Virtual I/O implementation template - * @version V1.0.0 - * @date 23. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include "cmsis_vio.h" - -#include "RTE_Components.h" // Component selection -#include CMSIS_device_header - -#if !defined CMSIS_VOUT || !defined CMSIS_VIN -// Add user includes here: - -#endif - -// VIO input, output definitions -#define VIO_PRINT_MAX_SIZE 64U // maximum size of print memory -#define VIO_PRINTMEM_NUM 4U // number of print memories -#define VIO_VALUE_NUM 3U // number of values -#define VIO_VALUEXYZ_NUM 3U // number of XYZ values -#define VIO_IPV4_ADDRESS_NUM 2U // number of IPv4 addresses -#define VIO_IPV6_ADDRESS_NUM 2U // number of IPv6 addresses - -// VIO input, output variables -__USED uint32_t vioSignalIn; // Memory for incoming signal -__USED uint32_t vioSignalOut; // Memory for outgoing signal -__USED char vioPrintMem[VIO_PRINTMEM_NUM][VIO_PRINT_MAX_SIZE]; // Memory for the last value for each level -__USED int32_t vioValue [VIO_VALUE_NUM]; // Memory for value used in vioGetValue/vioSetValue -__USED vioValueXYZ_t vioValueXYZ[VIO_VALUEXYZ_NUM]; // Memory for XYZ value for 3-D vector -__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM]; // Memory for IPv4 address value used in vioSetIPv4/vioGetIPv4 -__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM]; // Memory for IPv6 address value used in vioSetIPv6/vioGetIPv6 - -#if !defined CMSIS_VOUT -// Add global user types, variables, functions here: - -#endif - -#if !defined CMSIS_VIN -// Add global user types, variables, functions here: - -#endif - -// Initialize test input, output. -void vioInit (void) { -#if !defined CMSIS_VOUT -// Add user variables here: - -#endif -#if !defined CMSIS_VIN -// Add user variables here: - -#endif - - vioSignalIn = 0U; - vioSignalOut = 0U; - - memset (vioPrintMem, 0, sizeof(vioPrintMem)); - memset (vioValue, 0, sizeof(vioValue)); - memset (vioValueXYZ, 0, sizeof(vioValueXYZ)); - memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4)); - memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6)); - -#if !defined CMSIS_VOUT -// Add user code here: - -#endif - -#if !defined CMSIS_VIN -// Add user code here: - -#endif -} - -// Print formated string to test terminal. -int32_t vioPrint (uint32_t level, const char *format, ...) { - va_list args; - int32_t ret; -#if !defined CMSIS_VOUT -// Add user variables here: - -#endif - - if (level > vioLevelError) { - return (-1); - } - - if (level > VIO_PRINTMEM_NUM) { - return (-1); - } - - va_start(args, format); - - ret = vsnprintf((char *)vioPrintMem[level], sizeof(vioPrintMem[level]), format, args); - - va_end(args); - -#if !defined CMSIS_VOUT -// Add user code here: - -#endif - - return (ret); -} - -// Set signal output. -void vioSetSignal (uint32_t mask, uint32_t signal) { -#if !defined CMSIS_VOUT -// Add user variables here: - -#endif - - vioSignalOut &= ~mask; - vioSignalOut |= mask & signal; - -#if !defined CMSIS_VOUT -// Add user code here: - -#endif -} - -// Get signal input. -uint32_t vioGetSignal (uint32_t mask) { - uint32_t signal; -#if !defined CMSIS_VIN -// Add user variables here: - -#endif - -#if !defined CMSIS_VIN -// Add user code here: - -// vioSignalIn = ...; -#endif - - signal = vioSignalIn; - - return (signal & mask); -} - -// Set value output. -void vioSetValue (uint32_t id, int32_t value) { - uint32_t index = id; -#if !defined CMSIS_VOUT -// Add user variables here: - -#endif - - if (index >= VIO_VALUE_NUM) { - return; /* return in case of out-of-range index */ - } - - vioValue[index] = value; - -#if !defined CMSIS_VOUT -// Add user code here: - -#endif -} - -// Get value input. -int32_t vioGetValue (uint32_t id) { - uint32_t index = id; - int32_t value = 0; -#if !defined CMSIS_VIN -// Add user variables here: - -#endif - - if (index >= VIO_VALUE_NUM) { - return value; /* return default in case of out-of-range index */ - } - -#if !defined CMSIS_VIN -// Add user code here: - -// vioValue[index] = ...; -#endif - - value = vioValue[index]; - - return value; -} - -// Set XYZ value output. -void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) { - uint32_t index = id; -#if !defined CMSIS_VOUT -// Add user variables here: - -#endif - - if (index >= VIO_VALUEXYZ_NUM) { - return; /* return in case of out-of-range index */ - } - - vioValueXYZ[index] = valueXYZ; - -#if !defined CMSIS_VOUT -// Add user code here: - -#endif -} - -// Get XYZ value input. -vioValueXYZ_t vioGetXYZ (uint32_t id) { - uint32_t index = id; - vioValueXYZ_t valueXYZ = {0, 0, 0}; -#if !defined CMSIS_VIN -// Add user variables here: - -#endif - - if (index >= VIO_VALUEXYZ_NUM) { - return valueXYZ; /* return default in case of out-of-range index */ - } - -#if !defined CMSIS_VIN -// Add user code here: - -// vioValueXYZ[index] = ...; -#endif - - valueXYZ = vioValueXYZ[index]; - - return valueXYZ; -} - -// Set IPv4 address output. -void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) { - uint32_t index = id; -#if !defined CMSIS_VOUT -// Add user variables here: - -#endif - - if (index >= VIO_IPV4_ADDRESS_NUM) { - return; /* return in case of out-of-range index */ - } - - vioAddrIPv4[index] = addrIPv4; - -#if !defined CMSIS_VOUT -// Add user code here: - -#endif -} - -// Get IPv4 address input. -vioAddrIPv4_t vioGetIPv4 (uint32_t id) { - uint32_t index = id; - vioAddrIPv4_t addrIPv4 = {0U, 0U, 0U, 0U}; -#if !defined CMSIS_VIN -// Add user variables here: - -#endif - - if (index >= VIO_IPV4_ADDRESS_NUM) { - return addrIPv4; /* return default in case of out-of-range index */ - } - -#if !defined CMSIS_VIN -// Add user code here: - -// vioAddrIPv4[index] = ...; -#endif - - addrIPv4 = vioAddrIPv4[index]; - - return addrIPv4; -} - -// Set IPv6 address output. -void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) { - uint32_t index = id; -#if !defined CMSIS_VOUT -// Add user variables here: - -#endif - - if (index >= VIO_IPV6_ADDRESS_NUM) { - return; /* return in case of out-of-range index */ - } - - vioAddrIPv6[index] = addrIPv6; - -#if !defined CMSIS_VOUT -// Add user code here: - -#endif -} - -// Get IPv6 address input. -vioAddrIPv6_t vioGetIPv6 (uint32_t id) { - uint32_t index = id; - vioAddrIPv6_t addrIPv6 = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, - 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; -#if !defined CMSIS_VIN -// Add user variables here: - -#endif - - if (index >= VIO_IPV6_ADDRESS_NUM) { - return addrIPv6; /* return default in case of out-of-range index */ - } - -#if !defined CMSIS_VIN -// Add user code here: - -// vioAddrIPv6[index] = ...; -#endif - - addrIPv6 = vioAddrIPv6[index]; - - return addrIPv6; -} diff --git a/external/CMSIS_5/CMSIS/Driver/VIO/Source/vio_memory.c b/external/CMSIS_5/CMSIS/Driver/VIO/Source/vio_memory.c deleted file mode 100644 index 6c432c2..0000000 --- a/external/CMSIS_5/CMSIS/Driver/VIO/Source/vio_memory.c +++ /dev/null @@ -1,208 +0,0 @@ -/****************************************************************************** - * @file vio_memory.c - * @brief Virtual I/O implementation using memory only - * @version V1.0.0 - * @date 23. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include "cmsis_vio.h" - -#include "RTE_Components.h" // Component selection -#include CMSIS_device_header - -// VIO input, output definitions -#define VIO_PRINT_MAX_SIZE 64U // maximum size of print memory -#define VIO_PRINTMEM_NUM 4U // number of print memories -#ifndef VIO_VALUE_NUM -#define VIO_VALUE_NUM 3U // number of values -#endif -#ifndef VIO_VALUEXYZ_NUM -#define VIO_VALUEXYZ_NUM 3U // number of XYZ values -#endif -#ifndef VIO_IPV4_ADDRESS_NUM -#define VIO_IPV4_ADDRESS_NUM 2U // number of IPv4 addresses -#endif -#ifndef VIO_IPV6_ADDRESS_NUM -#define VIO_IPV6_ADDRESS_NUM 2U // number of IPv6 addresses -#endif - -// VIO input, output variables -__USED uint32_t vioSignalIn; -__USED uint32_t vioSignalOut; -__USED char vioPrintMem[VIO_PRINTMEM_NUM][VIO_PRINT_MAX_SIZE]; -__USED int32_t vioValue [VIO_VALUE_NUM]; -__USED vioValueXYZ_t vioValueXYZ[VIO_VALUEXYZ_NUM]; -__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM]; -__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM]; - -// Initialize test input, output. -void vioInit (void) { - - vioSignalIn = 0U; - vioSignalOut = 0U; - - memset (vioPrintMem, 0, sizeof(vioPrintMem)); - memset (vioValue, 0, sizeof(vioValue)); - memset (vioValueXYZ, 0, sizeof(vioValueXYZ)); - memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4)); - memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6)); -} - -// Print formated string to test terminal. -int32_t vioPrint (uint32_t level, const char *format, ...) { - va_list args; - int32_t ret; - - if (level > vioLevelError) { - return (-1); - } - - if (level > VIO_PRINTMEM_NUM) { - return (-1); - } - - va_start(args, format); - - ret = vsnprintf((char *)vioPrintMem[level], sizeof(vioPrintMem[level]), format, args); - - va_end(args); - - return (ret); -} - -// Set signal output. -void vioSetSignal (uint32_t mask, uint32_t signal) { - - vioSignalOut &= ~mask; - vioSignalOut |= mask & signal; -} - -// Get signal input. -uint32_t vioGetSignal (uint32_t mask) { - uint32_t signal; - - signal = vioSignalIn; - - return (signal & mask); -} - -// Set value output. -void vioSetValue (uint32_t id, int32_t value) { - uint32_t index = id; - - if (index >= VIO_VALUE_NUM) { - return; /* return in case of out-of-range index */ - } - - vioValue[index] = value; -} - -// Get value input. -int32_t vioGetValue (uint32_t id) { - uint32_t index = id; - int32_t value = 0; - - if (index >= VIO_VALUE_NUM) { - return value; /* return default in case of out-of-range index */ - } - - value = vioValue[index]; - - return value; -} - -// Set XYZ value output. -void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) { - uint32_t index = id; - - if (index >= VIO_VALUEXYZ_NUM) { - return; /* return in case of out-of-range index */ - } - - vioValueXYZ[index] = valueXYZ; -} - -// Get XYZ value input. -vioValueXYZ_t vioGetXYZ (uint32_t id) { - uint32_t index = id; - vioValueXYZ_t valueXYZ = {0, 0, 0}; - - if (index >= VIO_VALUEXYZ_NUM) { - return valueXYZ; /* return default in case of out-of-range index */ - } - - valueXYZ = vioValueXYZ[index]; - - return valueXYZ; -} - -// Set IPv4 address output. -void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) { - uint32_t index = id; - - if (index >= VIO_IPV4_ADDRESS_NUM) { - return; /* return in case of out-of-range index */ - } - - vioAddrIPv4[index] = addrIPv4; -} - -// Get IPv4 address input. -vioAddrIPv4_t vioGetIPv4 (uint32_t id) { - uint32_t index = id; - vioAddrIPv4_t addrIPv4 = {0U, 0U, 0U, 0U}; - - if (index >= VIO_IPV4_ADDRESS_NUM) { - return addrIPv4; /* return default in case of out-of-range index */ - } - - addrIPv4 = vioAddrIPv4[index]; - - return addrIPv4; -} - -// Set IPv6 address output. -void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) { - uint32_t index = id; - - if (index >= VIO_IPV6_ADDRESS_NUM) { - return; /* return in case of out-of-range index */ - } - - vioAddrIPv6[index] = addrIPv6; -} - -// Get IPv6 address input. -vioAddrIPv6_t vioGetIPv6 (uint32_t id) { - uint32_t index = id; - vioAddrIPv6_t addrIPv6 = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, - 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; - - if (index >= VIO_IPV6_ADDRESS_NUM) { - return addrIPv6; /* return default in case of out-of-range index */ - } - - addrIPv6 = vioAddrIPv6[index]; - - return addrIPv6; -} diff --git a/external/CMSIS_5/CMSIS/Driver/VIO/cmsis_vio.scvd b/external/CMSIS_5/CMSIS/Driver/VIO/cmsis_vio.scvd deleted file mode 100644 index a25739c..0000000 --- a/external/CMSIS_5/CMSIS/Driver/VIO/cmsis_vio.scvd +++ /dev/null @@ -1,78 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Config/mem_ARMCA5.h b/external/CMSIS_5/Device/ARM/ARMCA5/Config/mem_ARMCA5.h deleted file mode 100644 index 9fe85c0..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Config/mem_ARMCA5.h +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************//** - * @file mem_ARMCA5.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_ARMCA5_H -#define __MEM_ARMCA5_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// ROM Base Address <0x0-0xFFFFFFFF:0x100000> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x80000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- RAM Configuration ----------------------------------- -// RAM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// RAM Base Address <0x0-0xFFFFFFFF:0x100000> -// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// Data Sections -// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Exceptional Modes -// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// -// - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x80200000 -#define __RAM_SIZE 0x00200000 - -#define __RW_DATA_SIZE 0x00100000 -#define __ZI_DATA_SIZE 0x000F0000 - -#define __STACK_SIZE 0x00001000 -#define __HEAP_SIZE 0x00008000 - -#define __UND_STACK_SIZE 0x00000100 -#define __ABT_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned -// The TLB L2 entries are placed after the L1 in the MMU config -// TTB Base Address <0x0-0xFFFFFFFF:0x4000> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x80500000 -#define __TTB_SIZE 0x00005000 - -#endif /* __MEM_ARMCA5_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Config/system_ARMCA5.h b/external/CMSIS_5/Device/ARM/ARMCA5/Config/system_ARMCA5.h deleted file mode 100644 index 6a2a6da..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Config/system_ARMCA5.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA5.h - * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA5_H -#define __SYSTEM_ARMCA5_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA5_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Include/ARMCA5.h b/external/CMSIS_5/Device/ARM/ARMCA5/Include/ARMCA5.h deleted file mode 100644 index 0e56100..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Include/ARMCA5.h +++ /dev/null @@ -1,138 +0,0 @@ -/****************************************************************************** - * @file ARMCA5.h - * @brief CMSIS Cortex-A5 Core Peripheral Access Layer Header File - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __ARMCA5_H__ -#define __ARMCA5_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/****** SGI Interrupts Numbers ****************************************/ - SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ - SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ - SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ - SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ - SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ - SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ - SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ - SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ - SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ - SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ - SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ - SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ - SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ - SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ - SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ - SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ - -/****** Cortex-A5 Processor Exceptions Numbers ****************************************/ - GlobalTimer_IRQn = 27, /*!< Global Timer Interrupt */ - PrivTimer_IRQn = 29, /*!< Private Timer Interrupt */ - PrivWatchdog_IRQn = 30, /*!< Private Watchdog Interrupt */ - -/****** Platform Exceptions Numbers ***************************************************/ - Watchdog_IRQn = 32, /*!< SP805 Interrupt */ - Timer0_IRQn = 34, /*!< SP804 Interrupt */ - Timer1_IRQn = 35, /*!< SP804 Interrupt */ - RTClock_IRQn = 36, /*!< PL031 Interrupt */ - UART0_IRQn = 37, /*!< PL011 Interrupt */ - UART1_IRQn = 38, /*!< PL011 Interrupt */ - UART2_IRQn = 39, /*!< PL011 Interrupt */ - UART3_IRQn = 40, /*!< PL011 Interrupt */ - MCI0_IRQn = 41, /*!< PL180 Interrupt (1st) */ - MCI1_IRQn = 42, /*!< PL180 Interrupt (2nd) */ - AACI_IRQn = 43, /*!< PL041 Interrupt */ - Keyboard_IRQn = 44, /*!< PL050 Interrupt */ - Mouse_IRQn = 45, /*!< PL050 Interrupt */ - CLCD_IRQn = 46, /*!< PL111 Interrupt */ - Ethernet_IRQn = 47, /*!< SMSC_91C111 Interrupt */ - VFS2_IRQn = 73, /*!< VFS2 Interrupt */ -} IRQn_Type; - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ - -/* Peripheral and RAM base address */ -#define VE_A5_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ -#define VE_A5_MP_FLASH_BASE1 (0x0C000000UL) /*!< (FLASH1 ) Base Address */ -#define VE_A5_MP_SRAM_BASE (0x14000000UL) /*!< (SRAM ) Base Address */ -#define VE_A5_MP_PERIPH_BASE_CS2 (0x18000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A5_MP_VRAM_BASE (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS2) /*!< (VRAM ) Base Address */ -#define VE_A5_MP_ETHERNET_BASE (0x02000000UL + VE_A5_MP_PERIPH_BASE_CS2) /*!< (ETHERNET ) Base Address */ -#define VE_A5_MP_USB_BASE (0x03000000UL + VE_A5_MP_PERIPH_BASE_CS2) /*!< (USB ) Base Address */ -#define VE_A5_MP_PERIPH_BASE_CS3 (0x1C000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A5_MP_DAP_BASE (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (LOCAL DAP ) Base Address */ -#define VE_A5_MP_SYSTEM_REG_BASE (0x00010000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (SYSTEM REG ) Base Address */ -#define VE_A5_MP_SERIAL_BASE (0x00030000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (SERIAL ) Base Address */ -#define VE_A5_MP_AACI_BASE (0x00040000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (AACI ) Base Address */ -#define VE_A5_MP_MMCI_BASE (0x00050000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (MMCI ) Base Address */ -#define VE_A5_MP_KMI0_BASE (0x00060000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (KMI0 ) Base Address */ -#define VE_A5_MP_UART_BASE (0x00090000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (UART ) Base Address */ -#define VE_A5_MP_WDT_BASE (0x000F0000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (WDT ) Base Address */ -#define VE_A5_MP_TIMER_BASE (0x00110000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (TIMER ) Base Address */ -#define VE_A5_MP_DVI_BASE (0x00160000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (DVI ) Base Address */ -#define VE_A5_MP_RTC_BASE (0x00170000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (RTC ) Base Address */ -#define VE_A5_MP_UART4_BASE (0x001B0000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (UART4 ) Base Address */ -#define VE_A5_MP_CLCD_BASE (0x001F0000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (CLCD ) Base Address */ -#define VE_A5_MP_PRIVATE_PERIPH_BASE (0x2C000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A5_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST ) Base Address */ -#define VE_A5_MP_GIC_INTERFACE_BASE (0x00000100UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */ -#define VE_A5_MP_PRIVATE_TIMER (0x00000600UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (PTIM ) Base Address */ -#define VE_A5_MP_PL310_BASE (0x000F0000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310 ) Base Address */ -#define VE_A5_MP_SSRAM_BASE (0x2E000000UL) /*!< (System SRAM) Base Address */ -#define VE_A5_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */ -#define GIC_DISTRIBUTOR_BASE VE_A5_MP_GIC_DISTRIBUTOR_BASE -#define GIC_INTERFACE_BASE VE_A5_MP_GIC_INTERFACE_BASE -#define TIMER_BASE VE_A5_MP_PRIVATE_TIMER - -//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache. -//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort. -#define L2C_310_BASE VE_A5_MP_PL310_BASE - -/* -------- Configuration of the Cortex-A5 Processor and Core Peripherals ------- */ -#define __CA_REV 0x0000U /* Core revision r0p0 */ -#define __CORTEX_A 5U /* Cortex-A5 Core */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __GIC_PRESENT 1U /* GIC present */ -#define __TIM_PRESENT 1U /* TIM present */ -#define __L2C_PRESENT 0U /* L2C present */ - -#include "core_ca.h" -#include - -#ifdef __cplusplus -} -#endif - -#endif // __ARMCA5_H__ diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct b/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct deleted file mode 100644 index 7eba725..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armcc -E -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA5.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c b/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c deleted file mode 100644 index 6dce5be..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c +++ /dev/null @@ -1,151 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((section("RESET"))); -void Reset_Handler (void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -__ASM void Vectors(void) { - PRESERVE8 - - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__ASM void Reset_Handler(void) { - PRESERVE8 - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 // Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exceptional mode - IMPORT |Image$$FIQ_STACK$$ZI$$Limit| - IMPORT |Image$$IRQ_STACK$$ZI$$Limit| - IMPORT |Image$$SVC_STACK$$ZI$$Limit| - IMPORT |Image$$ABT_STACK$$ZI$$Limit| - IMPORT |Image$$UND_STACK$$ZI$$Limit| - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - CPS #0x11 - LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit| - CPS #0x12 - LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit| - CPS #0x13 - LDR SP, =|Image$$SVC_STACK$$ZI$$Limit| - CPS #0x17 - LDR SP, =|Image$$ABT_STACK$$ZI$$Limit| - CPS #0x1B - LDR SP, =|Image$$UND_STACK$$ZI$$Limit| - CPS #0x1F - LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - // Call SystemInit - IMPORT SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __main - IMPORT __main - BL __main -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct b/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct deleted file mode 100644 index 41e562c..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA5.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c b/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c deleted file mode 100644 index 1bdd541..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL __main \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld b/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld deleted file mode 100644 index ff1f39e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld +++ /dev/null @@ -1,181 +0,0 @@ -#include "mem_ARMCA5.h" - -MEMORY -{ - ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - - Image$$VECTORS$$Base = .; - * (RESET) - KEEP(*(.isr_vector)) - Image$$VECTORS$$Limit = .; - - *(SVC_TABLE) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - Image$$RO_DATA$$Base = .; - *(.rodata*) - Image$$RO_DATA$$Limit = .; - - KEEP(*(.eh_frame*)) - } > ROM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - __copy_table_end__ = .; - } > ROM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > ROM - - __etext = .; - - .ttb : - { - Image$$TTB$$ZI$$Base = .; - . += __TTB_SIZE; - Image$$TTB$$ZI$$Limit = .; - } > L_TTB - - .data : AT (__etext) - { - Image$$RW_DATA$$Base = .; - __data_start__ = .; - *(vtable) - *(.data*) - Image$$RW_DATA$$Limit = .; - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - - .bss ALIGN(0x400): - { - Image$$ZI_DATA$$Base = .; - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; - __end__ = .; - end = __end__; - } > RAM - -#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) - .heap (NOLOAD): - { - . = ALIGN(8); - Image$$HEAP$$ZI$$Base = .; - . += __HEAP_SIZE; - Image$$HEAP$$ZI$$Limit = .; - __HeapLimit = .; - } > RAM -#endif - - .stack (NOLOAD): - { - . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; - . = ALIGN(8); - - __StackTop = .; - Image$$SYS_STACK$$ZI$$Base = .; - . += __STACK_SIZE; - Image$$SYS_STACK$$ZI$$Limit = .; - __stack = .; - - Image$$FIQ_STACK$$ZI$$Base = .; - . += __FIQ_STACK_SIZE; - Image$$FIQ_STACK$$ZI$$Limit = .; - - Image$$IRQ_STACK$$ZI$$Base = .; - . += __IRQ_STACK_SIZE; - Image$$IRQ_STACK$$ZI$$Limit = .; - - Image$$SVC_STACK$$ZI$$Base = .; - . += __SVC_STACK_SIZE; - Image$$SVC_STACK$$ZI$$Limit = .; - - Image$$ABT_STACK$$ZI$$Base = .; - . += __ABT_STACK_SIZE; - Image$$ABT_STACK$$ZI$$Limit = .; - - Image$$UND_STACK$$ZI$$Base = .; - . += __UND_STACK_SIZE; - Image$$UND_STACK$$ZI$$Limit = .; - - } > RAM -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct b/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct deleted file mode 100644 index 41e562c..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA5.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c b/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c deleted file mode 100644 index 809a949..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL _start \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf b/external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s b/external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s deleted file mode 100644 index 85babb9..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.s - * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA5 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(4) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c b/external/CMSIS_5/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c deleted file mode 100644 index 58a9480..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************//** - * @file mmu_ARMCA5.c - * @brief MMU Configuration for ARM Cortex-A5 Device Series - * @version V1.2.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map - - Memory Type -0xffffffff |--------------------------| ------------ - | FLAG SYNC | Device Memory -0xfffff000 |--------------------------| ------------ - | Fault | Fault -0xfff00000 |--------------------------| ------------ - | | Normal - | | - | Daughterboard | - | memory | - | | -0x80505000 |--------------------------| ------------ - |TTB (L2 Sync Flags ) 4k | Normal -0x80504C00 |--------------------------| ------------ - |TTB (L2 Peripherals-B) 16k| Normal -0x80504800 |--------------------------| ------------ - |TTB (L2 Peripherals-A) 16k| Normal -0x80504400 |--------------------------| ------------ - |TTB (L2 Priv Periphs) 4k | Normal -0x80504000 |--------------------------| ------------ - | TTB (L1 Descriptors) | Normal -0x80500000 |--------------------------| ------------ - | Stack | Normal - |--------------------------| ------------ - | Heap | Normal -0x80400000 |--------------------------| ------------ - | ZI Data | Normal -0x80300000 |--------------------------| ------------ - | RW Data | Normal -0x80200000 |--------------------------| ------------ - | RO Data | Normal - |--------------------------| ------------ - | RO Code | USH Normal -0x80000000 |--------------------------| ------------ - | Daughterboard | Fault - | HSB AXI buses | -0x40000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x2c002000 |--------------------------| ------------ - | Private Address | Device Memory -0x2c000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x20000000 |--------------------------| ------------ - | Peripherals | Device Memory RW/RO - | | & Fault -0x00000000 |--------------------------| -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors should place all memory in domain 0 - -#include "ARMCA5.h" -#include "mem_ARMCA5.h" - -// TTB base address -#define TTB_BASE ((uint32_t*)__TTB_BASE) - -// L2 table pointers -//---------------------------------------- -#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core - // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. - // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. - -#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space -#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF -#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF -#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization - -//--------------------- PERIPHERALS ------------------- -#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) -#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) - -//--------------------- SYNC FLAGS -------------------- -#define FLAG_SYNC 0xFFFFF000 -#define F_SYNC_BASE 0xFFF00000 //1M aligned - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; - - //Create 4GB of faulting entries - MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); - - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Define Image - MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections - MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections - - //--------------------- PERIPHERALS ------------------- - MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW); - MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE , 16, Sect_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory - MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define private address space entry. - MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - // Define L2CC entry. Uncomment if PL310 is present - // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) - MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define synchronization space entry. - MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x1 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x01 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x0 (Inner WB WA) */ - __set_TTBR0(__TTB_BASE | 0x48); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA5/Source/system_ARMCA5.c b/external/CMSIS_5/Device/ARM/ARMCA5/Source/system_ARMCA5.c deleted file mode 100644 index 5f599f6..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA5/Source/system_ARMCA5.c +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA5.c - * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Config/mem_ARMCA7.h b/external/CMSIS_5/Device/ARM/ARMCA7/Config/mem_ARMCA7.h deleted file mode 100644 index 9590595..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Config/mem_ARMCA7.h +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************//** - * @file mem_ARMCA7.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_ARMCA7_H -#define __MEM_ARMCA7_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// ROM Base Address <0x0-0xFFFFFFFF:0x100000> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x80000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- RAM Configuration ----------------------------------- -// RAM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// RAM Base Address <0x0-0xFFFFFFFF:0x100000> -// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// Data Sections -// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Exceptional Modes -// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// -// - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x80200000 -#define __RAM_SIZE 0x00200000 - -#define __RW_DATA_SIZE 0x00100000 -#define __ZI_DATA_SIZE 0x000F0000 - -#define __STACK_SIZE 0x00001000 -#define __HEAP_SIZE 0x00008000 - -#define __UND_STACK_SIZE 0x00000100 -#define __ABT_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned -// The TLB L2 entries are placed after the L1 in the MMU config -// TTB Base Address <0x0-0xFFFFFFFF:0x4000> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x80500000 -#define __TTB_SIZE 0x00005000 - -#endif /* __MEM_ARMCA7_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Config/system_ARMCA7.h b/external/CMSIS_5/Device/ARM/ARMCA7/Config/system_ARMCA7.h deleted file mode 100644 index 0405aa3..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Config/system_ARMCA7.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA7.h - * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA7_H -#define __SYSTEM_ARMCA7_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA7_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Include/ARMCA7.h b/external/CMSIS_5/Device/ARM/ARMCA7/Include/ARMCA7.h deleted file mode 100644 index b465a9e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Include/ARMCA7.h +++ /dev/null @@ -1,135 +0,0 @@ -/****************************************************************************** - * @file ARMCA7.h - * @brief CMSIS Cortex-A7 Core Peripheral Access Layer Header File - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __ARMCA7_H__ -#define __ARMCA7_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -/** Device specific Interrupt IDs */ -typedef enum IRQn -{ -/****** SGI Interrupts Numbers ****************************************/ - SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ - SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ - SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ - SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ - SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ - SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ - SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ - SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ - SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ - SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ - SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ - SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ - SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ - SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ - SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ - SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ - -/****** Cortex-A7 Processor Exceptions Numbers ****************************************/ - SecurePhyTimer_IRQn = 29, /*!< Physical Timer Interrupt */ - -/****** Platform Exceptions Numbers ***************************************************/ - Watchdog_IRQn = 32, /*!< SP805 Interrupt */ - Timer0_IRQn = 34, /*!< SP804 Interrupt */ - Timer1_IRQn = 35, /*!< SP804 Interrupt */ - RTClock_IRQn = 36, /*!< PL031 Interrupt */ - UART0_IRQn = 37, /*!< PL011 Interrupt */ - UART1_IRQn = 38, /*!< PL011 Interrupt */ - UART2_IRQn = 39, /*!< PL011 Interrupt */ - UART3_IRQn = 40, /*!< PL011 Interrupt */ - MCI0_IRQn = 41, /*!< PL180 Interrupt (1st) */ - MCI1_IRQn = 42, /*!< PL180 Interrupt (2nd) */ - AACI_IRQn = 43, /*!< PL041 Interrupt */ - Keyboard_IRQn = 44, /*!< PL050 Interrupt */ - Mouse_IRQn = 45, /*!< PL050 Interrupt */ - CLCD_IRQn = 46, /*!< PL111 Interrupt */ - Ethernet_IRQn = 47, /*!< SMSC_91C111 Interrupt */ - VFS2_IRQn = 73, /*!< VFS2 Interrupt */ -} IRQn_Type; - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ - -/* Peripheral and RAM base address */ -#define VE_A7_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ -#define VE_A7_MP_FLASH_BASE1 (0x0C000000UL) /*!< (FLASH1 ) Base Address */ -#define VE_A7_MP_SRAM_BASE (0x14000000UL) /*!< (SRAM ) Base Address */ -#define VE_A7_MP_PERIPH_BASE_CS2 (0x18000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A7_MP_VRAM_BASE (0x00000000UL + VE_A7_MP_PERIPH_BASE_CS2) /*!< (VRAM ) Base Address */ -#define VE_A7_MP_ETHERNET_BASE (0x02000000UL + VE_A7_MP_PERIPH_BASE_CS2) /*!< (ETHERNET ) Base Address */ -#define VE_A7_MP_USB_BASE (0x03000000UL + VE_A7_MP_PERIPH_BASE_CS2) /*!< (USB ) Base Address */ -#define VE_A7_MP_PERIPH_BASE_CS3 (0x1C000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A7_MP_DAP_BASE (0x00000000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (LOCAL DAP ) Base Address */ -#define VE_A7_MP_SYSTEM_REG_BASE (0x00010000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (SYSTEM REG ) Base Address */ -#define VE_A7_MP_SERIAL_BASE (0x00030000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (SERIAL ) Base Address */ -#define VE_A7_MP_AACI_BASE (0x00040000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (AACI ) Base Address */ -#define VE_A7_MP_MMCI_BASE (0x00050000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (MMCI ) Base Address */ -#define VE_A7_MP_KMI0_BASE (0x00060000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (KMI0 ) Base Address */ -#define VE_A7_MP_UART_BASE (0x00090000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (UART ) Base Address */ -#define VE_A7_MP_WDT_BASE (0x000F0000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (WDT ) Base Address */ -#define VE_A7_MP_TIMER_BASE (0x00110000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (TIMER ) Base Address */ -#define VE_A7_MP_DVI_BASE (0x00160000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (DVI ) Base Address */ -#define VE_A7_MP_RTC_BASE (0x00170000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (RTC ) Base Address */ -#define VE_A7_MP_UART4_BASE (0x001B0000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (UART4 ) Base Address */ -#define VE_A7_MP_CLCD_BASE (0x001F0000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (CLCD ) Base Address */ -#define VE_A7_MP_PRIVATE_PERIPH_BASE (0x2C000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A7_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST ) Base Address */ -#define VE_A7_MP_GIC_INTERFACE_BASE (0x00002000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */ -#define VE_A7_MP_PL310_BASE (0x000F0000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310 ) Base Address */ -#define VE_A7_MP_SSRAM_BASE (0x2E000000UL) /*!< (System SRAM) Base Address */ -#define VE_A7_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */ -#define GIC_DISTRIBUTOR_BASE VE_A7_MP_GIC_DISTRIBUTOR_BASE -#define GIC_INTERFACE_BASE VE_A7_MP_GIC_INTERFACE_BASE - -//The VE-A7 model implements L1 cache as architecturally defined, but does not implement L2 cache. -//Do not enable the L2 cache if you are running RTX on a VE-A7 model as it may cause a data abort. -#define L2C_310_BASE VE_A7_MP_PL310_BASE - -/* -------- Configuration of the Cortex-A7 Processor and Core Peripherals ------- */ -#define __CA_REV 0x0000U /* Core revision r0p0 */ -#define __CORTEX_A 7U /* Cortex-A7 Core */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __GIC_PRESENT 1U /* GIC present */ -#define __TIM_PRESENT 1U /* TIM present */ -#define __L2C_PRESENT 0U /* L2C present */ - -#include "core_ca.h" -#include - -#ifdef __cplusplus -} -#endif - -#endif // __ARMCA7_H__ diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct b/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct deleted file mode 100644 index b5677de..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armcc -E -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA7.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c b/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c deleted file mode 100644 index a5047f5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c +++ /dev/null @@ -1,151 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((section("RESET"))); -void Reset_Handler (void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -__ASM void Vectors(void) { - PRESERVE8 - - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__ASM void Reset_Handler(void) { - PRESERVE8 - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 // Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exceptional mode - IMPORT |Image$$FIQ_STACK$$ZI$$Limit| - IMPORT |Image$$IRQ_STACK$$ZI$$Limit| - IMPORT |Image$$SVC_STACK$$ZI$$Limit| - IMPORT |Image$$ABT_STACK$$ZI$$Limit| - IMPORT |Image$$UND_STACK$$ZI$$Limit| - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - CPS #0x11 - LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit| - CPS #0x12 - LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit| - CPS #0x13 - LDR SP, =|Image$$SVC_STACK$$ZI$$Limit| - CPS #0x17 - LDR SP, =|Image$$ABT_STACK$$ZI$$Limit| - CPS #0x1B - LDR SP, =|Image$$UND_STACK$$ZI$$Limit| - CPS #0x1F - LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - // Call SystemInit - IMPORT SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __main - IMPORT __main - BL __main -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct b/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct deleted file mode 100644 index d8f3716..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA7.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c b/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c deleted file mode 100644 index da8ae87..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL __main \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld b/external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld deleted file mode 100644 index 62c4ba1..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld +++ /dev/null @@ -1,181 +0,0 @@ -#include "mem_ARMCA7.h" - -MEMORY -{ - ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - - Image$$VECTORS$$Base = .; - * (RESET) - KEEP(*(.isr_vector)) - Image$$VECTORS$$Limit = .; - - *(SVC_TABLE) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - Image$$RO_DATA$$Base = .; - *(.rodata*) - Image$$RO_DATA$$Limit = .; - - KEEP(*(.eh_frame*)) - } > ROM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - __copy_table_end__ = .; - } > ROM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > ROM - - __etext = .; - - .ttb : - { - Image$$TTB$$ZI$$Base = .; - . += __TTB_SIZE; - Image$$TTB$$ZI$$Limit = .; - } > L_TTB - - .data : AT (__etext) - { - Image$$RW_DATA$$Base = .; - __data_start__ = .; - *(vtable) - *(.data*) - Image$$RW_DATA$$Limit = .; - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - - .bss ALIGN(0x400): - { - Image$$ZI_DATA$$Base = .; - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; - __end__ = .; - end = __end__; - } > RAM - -#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) - .heap (NOLOAD): - { - . = ALIGN(8); - Image$$HEAP$$ZI$$Base = .; - . += __HEAP_SIZE; - Image$$HEAP$$ZI$$Limit = .; - __HeapLimit = .; - } > RAM -#endif - - .stack (NOLOAD): - { - . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; - . = ALIGN(8); - - __StackTop = .; - Image$$SYS_STACK$$ZI$$Base = .; - . += __STACK_SIZE; - Image$$SYS_STACK$$ZI$$Limit = .; - __stack = .; - - Image$$FIQ_STACK$$ZI$$Base = .; - . += __FIQ_STACK_SIZE; - Image$$FIQ_STACK$$ZI$$Limit = .; - - Image$$IRQ_STACK$$ZI$$Base = .; - . += __IRQ_STACK_SIZE; - Image$$IRQ_STACK$$ZI$$Limit = .; - - Image$$SVC_STACK$$ZI$$Base = .; - . += __SVC_STACK_SIZE; - Image$$SVC_STACK$$ZI$$Limit = .; - - Image$$ABT_STACK$$ZI$$Base = .; - . += __ABT_STACK_SIZE; - Image$$ABT_STACK$$ZI$$Limit = .; - - Image$$UND_STACK$$ZI$$Base = .; - . += __UND_STACK_SIZE; - Image$$UND_STACK$$ZI$$Limit = .; - - } > RAM -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c b/external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c deleted file mode 100644 index 43facd8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL _start \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf b/external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s b/external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s deleted file mode 100644 index 6872e9e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA7.s - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA7 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(4) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c b/external/CMSIS_5/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c deleted file mode 100644 index 26431f3..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************//** - * @file mmu_ARMCA7.c - * @brief MMU Configuration for Arm Cortex-A7 Device Series - * @version V1.2.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map - - Memory Type -0xffffffff |--------------------------| ------------ - | FLAG SYNC | Device Memory -0xfffff000 |--------------------------| ------------ - | Fault | Fault -0xfff00000 |--------------------------| ------------ - | | Normal - | | - | Daughterboard | - | memory | - | | -0x80505000 |--------------------------| ------------ - |TTB (L2 Sync Flags ) 4k | Normal -0x80504C00 |--------------------------| ------------ - |TTB (L2 Peripherals-B) 16k| Normal -0x80504800 |--------------------------| ------------ - |TTB (L2 Peripherals-A) 16k| Normal -0x80504400 |--------------------------| ------------ - |TTB (L2 Priv Periphs) 4k | Normal -0x80504000 |--------------------------| ------------ - | TTB (L1 Descriptors) | Normal -0x80500000 |--------------------------| ------------ - | Stack | Normal - |--------------------------| ------------ - | Heap | Normal -0x80400000 |--------------------------| ------------ - | ZI Data | Normal -0x80300000 |--------------------------| ------------ - | RW Data | Normal -0x80200000 |--------------------------| ------------ - | RO Data | Normal - |--------------------------| ------------ - | RO Code | USH Normal -0x80000000 |--------------------------| ------------ - | Daughterboard | Fault - | HSB AXI buses | -0x40000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x2c002000 |--------------------------| ------------ - | Private Address | Device Memory -0x2c000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x20000000 |--------------------------| ------------ - | Peripherals | Device Memory RW/RO - | | & Fault -0x00000000 |--------------------------| -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors should place all memory in domain 0 - -#include "ARMCA7.h" -#include "mem_ARMCA7.h" - -// TTB base address -#define TTB_BASE ((uint32_t*)__TTB_BASE) - -// L2 table pointers -//---------------------------------------- -#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core - // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. - // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. - -#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space -#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF -#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF -#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization - -//--------------------- PERIPHERALS ------------------- -#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) -#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) - -//--------------------- SYNC FLAGS -------------------- -#define FLAG_SYNC 0xFFFFF000 -#define F_SYNC_BASE 0xFFF00000 //1M aligned - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; - - //Create 4GB of faulting entries - MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); - - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Define Image - MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections - MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections - - //--------------------- PERIPHERALS ------------------- - MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW); - MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE , 16, Sect_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory - MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define private address space entry. - MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - // Define L2CC entry. Uncomment if PL310 is present - // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) - MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define synchronization space entry. - MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x1 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x01 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x0 (Inner WB WA) */ - __set_TTBR0(__TTB_BASE | 0x48); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA7/Source/system_ARMCA7.c b/external/CMSIS_5/Device/ARM/ARMCA7/Source/system_ARMCA7.c deleted file mode 100644 index 803ec49..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA7/Source/system_ARMCA7.c +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA7.c - * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Config/mem_ARMCA9.h b/external/CMSIS_5/Device/ARM/ARMCA9/Config/mem_ARMCA9.h deleted file mode 100644 index 3609d7f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Config/mem_ARMCA9.h +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************//** - * @file mem_ARMCA9.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_ARMCA9_H -#define __MEM_ARMCA9_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// ROM Base Address <0x0-0xFFFFFFFF:0x100000> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x80000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- RAM Configuration ----------------------------------- -// RAM Configuration -// For compatibility with MMU config the sections must be multiple of 1MB -// RAM Base Address <0x0-0xFFFFFFFF:0x100000> -// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> -// Data Sections -// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Exceptional Modes -// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// -// - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x80200000 -#define __RAM_SIZE 0x00200000 - -#define __RW_DATA_SIZE 0x00100000 -#define __ZI_DATA_SIZE 0x000F0000 - -#define __STACK_SIZE 0x00001000 -#define __HEAP_SIZE 0x00008000 - -#define __UND_STACK_SIZE 0x00000100 -#define __ABT_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned -// The TLB L2 entries are placed after the L1 in the MMU config -// TTB Base Address <0x0-0xFFFFFFFF:0x4000> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x80500000 -#define __TTB_SIZE 0x00005000 - -#endif /* __MEM_ARMCA9_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Config/system_ARMCA9.h b/external/CMSIS_5/Device/ARM/ARMCA9/Config/system_ARMCA9.h deleted file mode 100644 index b60ce5a..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Config/system_ARMCA9.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA9.h - * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_ARMCA9_H -#define __SYSTEM_ARMCA9_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ARMCA9_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Include/ARMCA9.h b/external/CMSIS_5/Device/ARM/ARMCA9/Include/ARMCA9.h deleted file mode 100644 index 1511245..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Include/ARMCA9.h +++ /dev/null @@ -1,139 +0,0 @@ -/****************************************************************************** - * @file ARMCA9.h - * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version V1.1.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __ARMCA9_H__ -#define __ARMCA9_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -/** Device specific Interrupt IDs */ -typedef enum IRQn -{ -/****** SGI Interrupts Numbers ****************************************/ - SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ - SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ - SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ - SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ - SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ - SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ - SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ - SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ - SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ - SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ - SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ - SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ - SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ - SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ - SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ - SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ - -/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ - GlobalTimer_IRQn = 27, /*!< Global Timer Interrupt */ - PrivTimer_IRQn = 29, /*!< Private Timer Interrupt */ - PrivWatchdog_IRQn = 30, /*!< Private Watchdog Interrupt */ - -/****** Platform Exceptions Numbers ***************************************************/ - Watchdog_IRQn = 32, /*!< SP805 Interrupt */ - Timer0_IRQn = 34, /*!< SP804 Interrupt */ - Timer1_IRQn = 35, /*!< SP804 Interrupt */ - RTClock_IRQn = 36, /*!< PL031 Interrupt */ - UART0_IRQn = 37, /*!< PL011 Interrupt */ - UART1_IRQn = 38, /*!< PL011 Interrupt */ - UART2_IRQn = 39, /*!< PL011 Interrupt */ - UART3_IRQn = 40, /*!< PL011 Interrupt */ - MCI0_IRQn = 41, /*!< PL180 Interrupt (1st) */ - MCI1_IRQn = 42, /*!< PL180 Interrupt (2nd) */ - AACI_IRQn = 43, /*!< PL041 Interrupt */ - Keyboard_IRQn = 44, /*!< PL050 Interrupt */ - Mouse_IRQn = 45, /*!< PL050 Interrupt */ - CLCD_IRQn = 46, /*!< PL111 Interrupt */ - Ethernet_IRQn = 47, /*!< SMSC_91C111 Interrupt */ - VFS2_IRQn = 73, /*!< VFS2 Interrupt */ -} IRQn_Type; - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ - -/* Peripheral and RAM base address */ -#define VE_A9_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ -#define VE_A9_MP_FLASH_BASE1 (0x0C000000UL) /*!< (FLASH1 ) Base Address */ -#define VE_A9_MP_SRAM_BASE (0x14000000UL) /*!< (SRAM ) Base Address */ -#define VE_A9_MP_PERIPH_BASE_CS2 (0x18000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A9_MP_VRAM_BASE (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2) /*!< (VRAM ) Base Address */ -#define VE_A9_MP_ETHERNET_BASE (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2) /*!< (ETHERNET ) Base Address */ -#define VE_A9_MP_USB_BASE (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2) /*!< (USB ) Base Address */ -#define VE_A9_MP_PERIPH_BASE_CS3 (0x1C000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A9_MP_DAP_BASE (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (LOCAL DAP ) Base Address */ -#define VE_A9_MP_SYSTEM_REG_BASE (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (SYSTEM REG ) Base Address */ -#define VE_A9_MP_SERIAL_BASE (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (SERIAL ) Base Address */ -#define VE_A9_MP_AACI_BASE (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (AACI ) Base Address */ -#define VE_A9_MP_MMCI_BASE (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (MMCI ) Base Address */ -#define VE_A9_MP_KMI0_BASE (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (KMI0 ) Base Address */ -#define VE_A9_MP_UART_BASE (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (UART ) Base Address */ -#define VE_A9_MP_WDT_BASE (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (WDT ) Base Address */ -#define VE_A9_MP_TIMER_BASE (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (TIMER ) Base Address */ -#define VE_A9_MP_DVI_BASE (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (DVI ) Base Address */ -#define VE_A9_MP_RTC_BASE (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (RTC ) Base Address */ -#define VE_A9_MP_UART4_BASE (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (UART4 ) Base Address */ -#define VE_A9_MP_CLCD_BASE (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3) /*!< (CLCD ) Base Address */ -#define VE_A9_MP_PL310_BASE (0x1E00A000UL) /*!< (L2C-310 ) Base Address */ -#define VE_A9_MP_PRIVATE_PERIPH_BASE (0x2C000000UL) /*!< (Peripheral ) Base Address */ -#define VE_A9_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST ) Base Address */ -#define VE_A9_MP_GIC_INTERFACE_BASE (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */ -#define VE_A9_MP_PRIVATE_TIMER (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE) /*!< (PTIM ) Base Address */ -#define VE_A9_MP_SSRAM_BASE (0x2E000000UL) /*!< (System SRAM) Base Address */ -#define VE_A9_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */ -#define GIC_DISTRIBUTOR_BASE VE_A9_MP_GIC_DISTRIBUTOR_BASE -#define GIC_INTERFACE_BASE VE_A9_MP_GIC_INTERFACE_BASE -#define TIMER_BASE VE_A9_MP_PRIVATE_TIMER - -//The VE-A9 model implements L1 cache as architecturally defined, but does not implement L2 cache. -//Do not enable the L2 cache if you are running RTX on a VE-A9 model as it may cause a data abort. -#define L2C_310_BASE VE_A9_MP_PL310_BASE - -/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ -#define __CA_REV 0x0000U /*!< Core revision r0p0 */ -#define __CORTEX_A 9U /*!< Cortex-A9 Core */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __GIC_PRESENT 1U /* GIC present */ -#define __TIM_PRESENT 1U /* TIM present */ -#define __L2C_PRESENT 0U /* L2C present */ - -#include "core_ca.h" -#include - -#ifdef __cplusplus -} -#endif - -#endif // __ARMCA9_H__ diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct b/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct deleted file mode 100644 index 4bf3816..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armcc -E -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA9.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c b/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c deleted file mode 100644 index 8d3161e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c +++ /dev/null @@ -1,151 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.c - * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series - * @version V1.00 - * @date 10. January 2018 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((section("RESET"))); -void Reset_Handler (void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -__ASM void Vectors(void) { - PRESERVE8 - - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__ASM void Reset_Handler(void) { - PRESERVE8 - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 // Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exceptional mode - IMPORT |Image$$FIQ_STACK$$ZI$$Limit| - IMPORT |Image$$IRQ_STACK$$ZI$$Limit| - IMPORT |Image$$SVC_STACK$$ZI$$Limit| - IMPORT |Image$$ABT_STACK$$ZI$$Limit| - IMPORT |Image$$UND_STACK$$ZI$$Limit| - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - CPS #0x11 - LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit| - CPS #0x12 - LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit| - CPS #0x13 - LDR SP, =|Image$$SVC_STACK$$ZI$$Limit| - CPS #0x17 - LDR SP, =|Image$$ABT_STACK$$ZI$$Limit| - CPS #0x1B - LDR SP, =|Image$$UND_STACK$$ZI$$Limit| - CPS #0x1F - LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - // Call SystemInit - IMPORT SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __main - IMPORT __main - BL __main -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct b/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct deleted file mode 100644 index 3316f93..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -; This platform has 2GB SDRAM starting at 0x80000000. - -#include "mem_ARMCA9.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c b/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c deleted file mode 100644 index 88173fc..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.c - * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void) __attribute__ ((noreturn)); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL __main \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld b/external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld deleted file mode 100644 index ee3d836..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld +++ /dev/null @@ -1,181 +0,0 @@ -#include "mem_ARMCA9.h" - -MEMORY -{ - ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - - Image$$VECTORS$$Base = .; - * (RESET) - KEEP(*(.isr_vector)) - Image$$VECTORS$$Limit = .; - - *(SVC_TABLE) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - Image$$RO_DATA$$Base = .; - *(.rodata*) - Image$$RO_DATA$$Limit = .; - - KEEP(*(.eh_frame*)) - } > ROM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - __copy_table_end__ = .; - } > ROM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > ROM - - __etext = .; - - .ttb : - { - Image$$TTB$$ZI$$Base = .; - . += __TTB_SIZE; - Image$$TTB$$ZI$$Limit = .; - } > L_TTB - - .data : AT (__etext) - { - Image$$RW_DATA$$Base = .; - __data_start__ = .; - *(vtable) - *(.data*) - Image$$RW_DATA$$Limit = .; - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - - .bss ALIGN(0x400): - { - Image$$ZI_DATA$$Base = .; - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; - __end__ = .; - end = __end__; - } > RAM - -#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) - .heap (NOLOAD): - { - . = ALIGN(8); - Image$$HEAP$$ZI$$Base = .; - . += __HEAP_SIZE; - Image$$HEAP$$ZI$$Limit = .; - __HeapLimit = .; - } > RAM -#endif - - .stack (NOLOAD): - { - . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; - . = ALIGN(8); - - __StackTop = .; - Image$$SYS_STACK$$ZI$$Base = .; - . += __STACK_SIZE; - Image$$SYS_STACK$$ZI$$Limit = .; - __stack = .; - - Image$$FIQ_STACK$$ZI$$Base = .; - . += __FIQ_STACK_SIZE; - Image$$FIQ_STACK$$ZI$$Limit = .; - - Image$$IRQ_STACK$$ZI$$Base = .; - . += __IRQ_STACK_SIZE; - Image$$IRQ_STACK$$ZI$$Limit = .; - - Image$$SVC_STACK$$ZI$$Base = .; - . += __SVC_STACK_SIZE; - Image$$SVC_STACK$$ZI$$Limit = .; - - Image$$ABT_STACK$$ZI$$Base = .; - . += __ABT_STACK_SIZE; - Image$$ABT_STACK$$ZI$$Limit = .; - - Image$$UND_STACK$$ZI$$Base = .; - . += __UND_STACK_SIZE; - Image$$UND_STACK$$ZI$$Limit = .; - - } > RAM -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c b/external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c deleted file mode 100644 index 5aac600..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.c - * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series - * @version V1.0.1 - * @date 10. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((naked, section("RESET"))); -void Reset_Handler (void) __attribute__ ((naked)); -void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -void Vectors(void) { - __ASM volatile( - "LDR PC, =Reset_Handler \n" - "LDR PC, =Undef_Handler \n" - "LDR PC, =SVC_Handler \n" - "LDR PC, =PAbt_Handler \n" - "LDR PC, =DAbt_Handler \n" - "NOP \n" - "LDR PC, =IRQ_Handler \n" - "LDR PC, =FIQ_Handler \n" - ); -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) { - __ASM volatile( - - // Mask interrupts - "CPSID if \n" - - // Put any cores other than 0 to sleep - "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR - "ANDS R0, R0, #3 \n" - "goToSleep: \n" - "WFINE \n" - "BNE goToSleep \n" - - // Reset SCTLR Settings - "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register - "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache - "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache - "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU - "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction - "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs - "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register - "ISB \n" - - // Configure ACTLR - "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register - "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) - "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - "LDR R0, =Vectors \n" - "MCR p15, 0, R0, c12, c0, 0 \n" - - // Setup Stack for each exceptional mode - "CPS #0x11 \n" - "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" - "CPS #0x12 \n" - "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" - "CPS #0x13 \n" - "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" - "CPS #0x17 \n" - "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" - "CPS #0x1B \n" - "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" - "CPS #0x1F \n" - "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" - - // Call SystemInit - "BL SystemInit \n" - - // Unmask interrupts - "CPSIE if \n" - - // Call __main - "BL _start \n" - ); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf b/external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf deleted file mode 100644 index ce564bb..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf +++ /dev/null @@ -1,67 +0,0 @@ - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; -define symbol __ICFEDIT_region_IROM2_start__ = 0x0; -define symbol __ICFEDIT_region_IROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; -define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_svcstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x8000; -define symbol __ICFEDIT_size_ttb__ = 0x4000; - -define memory mem with size = 4G; -define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] - | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] - | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; -define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; - -define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; - -do not initialize { section .noinit }; - -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; -place in IROM_region { readonly }; -place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; -place in TTB_region { block TTB }; \ No newline at end of file diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s b/external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s deleted file mode 100644 index 5db9773..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCA9.s - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 01 Nov 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - MODULE ?startup_ARMCA9 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ - PUBLIC Reset_Handler - PUBWEAK Undef_Handler - PUBWEAK SVC_Handler - PUBWEAK PAbt_Handler - PUBWEAK DAbt_Handler - PUBWEAK IRQ_Handler - PUBWEAK FIQ_Handler - - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION USR_STACK:DATA:NOROOT(3) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ - - section RESET:CODE:NOROOT(2) - PUBLIC Vectors - -Vectors: - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - - section .text:CODE:NOROOT(2) - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ - EXTERN SystemInit - EXTERN __iar_program_start - -Reset_Handler: - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 - ANDS R0, R0, #3 -goToSleep: - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exception mode - CPS #0x11 - LDR SP, =SFE(FIQ_STACK) - CPS #0x12 - LDR SP, =SFE(IRQ_STACK) - CPS #0x13 - LDR SP, =SFE(SVC_STACK) - CPS #0x17 - LDR SP, =SFE(ABT_STACK) - CPS #0x1B - LDR SP, =SFE(UND_STACK) - CPS #0x1F - LDR SP, =SFE(USR_STACK) - - // Call SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __iar_program_start - BL __iar_program_start - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -Undef_Handler: -SVC_Handler: -PAbt_Handler: -DAbt_Handler: -IRQ_Handler: -FIQ_Handler: -Default_Handler: - B . - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c b/external/CMSIS_5/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c deleted file mode 100644 index 1435eb9..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************//** - * @file mmu_ARMCA9.c - * @brief MMU Configuration for Arm Cortex-A9 Device Series - * @version V1.2.0 - * @date 15. May 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map - - Memory Type -0xffffffff |--------------------------| ------------ - | FLAG SYNC | Device Memory -0xfffff000 |--------------------------| ------------ - | Fault | Fault -0xfff00000 |--------------------------| ------------ - | | Normal - | | - | Daughterboard | - | memory | - | | -0x80505000 |--------------------------| ------------ - |TTB (L2 Sync Flags ) 4k | Normal -0x80504C00 |--------------------------| ------------ - |TTB (L2 Peripherals-B) 16k| Normal -0x80504800 |--------------------------| ------------ - |TTB (L2 Peripherals-A) 16k| Normal -0x80504400 |--------------------------| ------------ - |TTB (L2 Priv Periphs) 4k | Normal -0x80504000 |--------------------------| ------------ - | TTB (L1 Descriptors) | Normal -0x80500000 |--------------------------| ------------ - | Stack | Normal - |--------------------------| ------------ - | Heap | Normal -0x80400000 |--------------------------| ------------ - | ZI Data | Normal -0x80300000 |--------------------------| ------------ - | RW Data | Normal -0x80200000 |--------------------------| ------------ - | RO Data | Normal - |--------------------------| ------------ - | RO Code | USH Normal -0x80000000 |--------------------------| ------------ - | Daughterboard | Fault - | HSB AXI buses | -0x40000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x2c002000 |--------------------------| ------------ - | Private Address | Device Memory -0x2c000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x20000000 |--------------------------| ------------ - | Peripherals | Device Memory RW/RO - | | & Fault -0x00000000 |--------------------------| -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors should place all memory in domain 0 - -#include "ARMCA9.h" -#include "mem_ARMCA9.h" - -// TTB base address -#define TTB_BASE ((uint32_t*)__TTB_BASE) - -// L2 table pointers -//---------------------------------------- -#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core - // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. - // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. - -#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space -#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF -#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF -#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization - -//--------------------- PERIPHERALS ------------------- -#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) -#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) - -//--------------------- SYNC FLAGS -------------------- -#define FLAG_SYNC 0xFFFFF000 -#define F_SYNC_BASE 0xFFF00000 //1M aligned - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; - - //Create 4GB of faulting entries - MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); - - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Define Image - MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections - MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections - - //--------------------- PERIPHERALS ------------------- - MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR - MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM - MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW); - MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE , 16, Sect_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C000000-0x1C00FFFF - MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range 0x1C100000-0x1C10FFFF - MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory - MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define private address space entry. - MMU_TTPage4k (TTB_BASE, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - // Define L2CC entry. Uncomment if PL310 is present - // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) - MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define synchronization space entry. - MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x1 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x01 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x0 (Inner WB WA) */ - __set_TTBR0(__TTB_BASE | 0x48); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCA9/Source/system_ARMCA9.c b/external/CMSIS_5/Device/ARM/ARMCA9/Source/system_ARMCA9.c deleted file mode 100644 index cdf9213..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCA9/Source/system_ARMCA9.c +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * @file system_ARMCA9.c - * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series - * @version V1.0.1 - * @date 13. February 2019 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "irq_ctrl.h" - -#define SYSTEM_CLOCK 12000000U - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s b/external/CMSIS_5/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s deleted file mode 100644 index 3220f32..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s +++ /dev/null @@ -1,147 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 ( 22) ; Interrupts 10 .. 31 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h b/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h deleted file mode 100644 index ceda93c..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************//** - * @file ARMCM0plus.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM0plus Device - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM0plus_H -#define ARMCM0plus_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 30 are left out */ - Interrupt31_IRQn = 31 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM0PLUS_REV 0x0001U /* Core revision r0p1 */ -#define __MPU_PRESENT 0U /* no MPU present */ -#define __VTOR_PRESENT 0U /* no VTOR present */ -#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_cm0plus.h" /* Processor and core peripherals */ -#include "system_ARMCM0plus.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM0plus_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h b/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h deleted file mode 100644 index 7d9f226..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************//** - * @file ARMCM0plus_MPU.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM0plus Device (configured for CM0+ with MPU) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM0plus_MPU_H -#define ARMCM0plus_MPU_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 30 are left out */ - Interrupt31_IRQn = 31 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM0PLUS_REV 0x0001U /* Core revision r0p1 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 0U /* no VTOR present */ -#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_cm0plus.h" /* Processor and core peripherals */ -#include "system_ARMCM0plus.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM0plus_MPU_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h b/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h deleted file mode 100644 index 880f420..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM0plus.h - * @brief CMSIS Device System Header File for - * ARMCM0 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM0plus_H -#define SYSTEM_ARMCM0plus_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM0plus_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct deleted file mode 100644 index e3b09b5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct deleted file mode 100644 index 0f499b2..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s deleted file mode 100644 index cb71012..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s +++ /dev/null @@ -1,168 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM0plus.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device -; * @version V1.0.1 -; * @date 23. July 2019 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; Default exception/interrupt handler - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S deleted file mode 100644 index a7ce111..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************//** - * @file startup_ARMCM0plus.S - * @brief CMSIS-Core(M) Device Startup File for Cortex-M0plus Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv6-m - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s deleted file mode 100644 index ebbe883..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s +++ /dev/null @@ -1,147 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM0plus.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 ( 22) ; Interrupts 10 .. 31 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c deleted file mode 100644 index 76d1fa8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM0plus.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM0P) - #include "ARMCM0plus.h" -#elif defined (ARMCM0P_MPU) - #include "ARMCM0plus_MPU.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c b/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c deleted file mode 100644 index f3bf3aa..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM0plus.c - * @brief CMSIS Device System Source File for - * ARMCM0plus Device - * @version V1.0.1 - * @date 01. June 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM0plus.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Include/ARMCM1.h b/external/CMSIS_5/Device/ARM/ARMCM1/Include/ARMCM1.h deleted file mode 100644 index e9b54d8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Include/ARMCM1.h +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file ARMCM1.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM1 Device - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM1_H -#define ARMCM1_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 30 are left out */ - Interrupt31_IRQn = 31 -} IRQn_Type; - - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM1_REV 0x0100U /* Core revision r1p0 */ -#define __MPU_PRESENT 0U /* no MPU present */ -#define __VTOR_PRESENT 0U /* no VTOR present */ -#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_cm1.h" /* Processor and core peripherals */ -#include "system_ARMCM1.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM1_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Include/system_ARMCM1.h b/external/CMSIS_5/Device/ARM/ARMCM1/Include/system_ARMCM1.h deleted file mode 100644 index f7b75f9..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Include/system_ARMCM1.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM1.h - * @brief CMSIS Device System Header File for - * ARMCM1 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM1_H -#define SYSTEM_ARMCM1_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM1_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct b/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct deleted file mode 100644 index e3b09b5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct deleted file mode 100644 index 82aacdd..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m1 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s b/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s deleted file mode 100644 index 0ce627b..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s +++ /dev/null @@ -1,168 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM1.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM1 Device -; * @version V1.0.1 -; * @date 23. July 2019 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; Default exception/interrupt handler - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S b/external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S deleted file mode 100644 index 74348d0..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************//** - * @file startup_ARMCM1.S - * @brief CMSIS-Core(M) Device Startup File for Cortex-M1 Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv6-m - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s b/external/CMSIS_5/Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s deleted file mode 100644 index 9691d81..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s +++ /dev/null @@ -1,147 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM1.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM1 Device -; * @version V1.0.0 -; * @date 20. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 ( 22) ; Interrupts 10 .. 31 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/startup_ARMCM1.c b/external/CMSIS_5/Device/ARM/ARMCM1/Source/startup_ARMCM1.c deleted file mode 100644 index 408ed21..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/startup_ARMCM1.c +++ /dev/null @@ -1,146 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM1.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M1 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM1) - #include "ARMCM1.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM1/Source/system_ARMCM1.c b/external/CMSIS_5/Device/ARM/ARMCM1/Source/system_ARMCM1.c deleted file mode 100644 index 75ad737..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM1/Source/system_ARMCM1.c +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM1.c - * @brief CMSIS Device System Source File for - * ARMCM1 Device - * @version V1.0.0 - * @date 20. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM1.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Debug/ARMv8MBL.dbgconf b/external/CMSIS_5/Device/ARM/ARMCM23/Debug/ARMv8MBL.dbgconf deleted file mode 100644 index d79f207..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Debug/ARMv8MBL.dbgconf +++ /dev/null @@ -1,13 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// Fixed Debug Authentication -// Use a fixed value for Debug Authentication. Only secure debug authentication configurable. -DAuthFixed = 0x1; - -// Secure Invasive Debug -// Secure Non-Invasive Debug -DAuthConfig = 0xF; - -// - -// <<< end of configuration section >>> \ No newline at end of file diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23.h b/external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23.h deleted file mode 100644 index f75490f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23.h +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file ARMCM23.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM23 Device - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM23_H -#define ARMCM23_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM23_REV 0x0100U /* Core revision r1p0 */ -#define __SAUREGION_PRESENT 0U /* SAU regions are not present */ -#define __MPU_PRESENT 1U /* MPU is present */ -#define __VTOR_PRESENT 1U /* VTOR is present */ -#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_cm23.h" /* Processor and core peripherals */ -#include "system_ARMCM23.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM23_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h b/external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h deleted file mode 100644 index 7863caf..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file ARMCM23_TZ.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM23 Device (configured for TrustZone) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM23_TZ_H -#define ARMCM23_TZ_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM23_REV 0x0100U /* Core revision r1p0 */ -#define __SAUREGION_PRESENT 1U /* SAU regions are present */ -#define __MPU_PRESENT 1U /* MPU is present */ -#define __VTOR_PRESENT 1U /* VTOR is present */ -#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_cm23.h" /* Processor and core peripherals */ -#include "system_ARMCM23.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM23_TZ_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h b/external/CMSIS_5/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h deleted file mode 100644 index 7738365..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h +++ /dev/null @@ -1,832 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM23.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 - * @version V1.0.0 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM23_H -#define PARTITION_ARMCM23_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - - -/* -// Setup behaviour of single SysTick -*/ -#define SCB_ICSR_INIT 0 - -/* -// in a single SysTick implementation, SysTick is -// <0=>Secure -// <1=>Non-Secure -// Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation -*/ -#define SCB_ICSR_STTNS_VAL 0 - -/* -// -*/ - - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) - SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | - ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); - #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM23_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Include/system_ARMCM23.h b/external/CMSIS_5/Device/ARM/ARMCM23/Include/system_ARMCM23.h deleted file mode 100644 index 141692a..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Include/system_ARMCM23.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM23.h - * @brief CMSIS Device System Header File for - * ARMCM23 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM23_H -#define SYSTEM_ARMCM23_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM23_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct deleted file mode 100644 index a0317e6..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct deleted file mode 100644 index 63b51fb..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S b/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S deleted file mode 100644 index e1c110f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S +++ /dev/null @@ -1,155 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.S - * @brief CMSIS-Core Device Startup File for Cortex-M23 Device - * @version V2.0.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.base - - #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit - #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base - #endif - - .section RESET - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - str r1,[r0,#0] - str r1,[r0,#4] - #endif - - bl SystemInit - - bl __main - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S b/external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S deleted file mode 100644 index 4373dda..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S +++ /dev/null @@ -1,200 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.S - * @brief CMSIS-Core Device Startup File for Cortex-M23 Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.base - - #define __INITIAL_SP __StackTop - #define __STACK_LIMIT __StackLimit - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL __StackSeal - #endif - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - str r1,[r0,#0] - str r1,[r0,#4] - #endif - - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s b/external/CMSIS_5/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s deleted file mode 100644 index 994bd53..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s +++ /dev/null @@ -1,168 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM23.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM23 Device -; * @version V1.1.0 -; * @date 08. April 2021 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - #define __INITIAL_SP sfe(CSTACK) - #define __STACK_LIMIT sfb(CSTACK) - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SECTION STACKSEAL:DATA:NOROOT(3) - #define __STACK_SEAL sfb(STACKSEAL) - #endif - - DATA - -__vector_table - DCD __INITIAL_SP ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (214) ; Interrupts 10 .. 224 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - ldr r0, =__INITIAL_SP - msr psp, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - str r1,[r0,#0] - str r1,[r0,#4] - #endif - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/startup_ARMCM23.c b/external/CMSIS_5/Device/ARM/ARMCM23/Source/startup_ARMCM23.c deleted file mode 100644 index 080c7a8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/startup_ARMCM23.c +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM23.c - * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM23/Source/system_ARMCM23.c b/external/CMSIS_5/Device/ARM/ARMCM23/Source/system_ARMCM23.c deleted file mode 100644 index 3381c1f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM23/Source/system_ARMCM23.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM23.c - * @brief CMSIS Device System Source File for - * ARMCM23 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM23) - #include "ARMCM23.h" -#elif defined (ARMCM23_TZ) - #include "ARMCM23_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM23.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Include/ARMCM3.h b/external/CMSIS_5/Device/ARM/ARMCM3/Include/ARMCM3.h deleted file mode 100644 index b7232a8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Include/ARMCM3.h +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************//** - * @file ARMCM3.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM3 Device - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM3_H -#define ARMCM3_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM3_REV 0x0201U /* Core revision r2p1 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_cm3.h" /* Processor and core peripherals */ -#include "system_ARMCM3.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM3_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Include/system_ARMCM3.h b/external/CMSIS_5/Device/ARM/ARMCM3/Include/system_ARMCM3.h deleted file mode 100644 index 43fd906..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Include/system_ARMCM3.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM3.h - * @brief CMSIS Device System Header File for - * ARMCM3 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM3_H -#define SYSTEM_ARMCM3_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM3_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct b/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct deleted file mode 100644 index e3b09b5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct deleted file mode 100644 index 4309a0b..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s b/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s deleted file mode 100644 index 7cba048..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s +++ /dev/null @@ -1,172 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM3.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM3 Device -; * @version V1.0.1 -; * @date 23. July 2019 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - SPACE (214 * 4) ; Interrupts 10 .. 224 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; Default exception/interrupt handler - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S b/external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S deleted file mode 100644 index da11f51..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************//** - * @file startup_ARMCM3.S - * @brief CMSIS-Core(M) Device Startup File for Cortex-M3 Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv7-m - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s b/external/CMSIS_5/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s deleted file mode 100644 index 90202f5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s +++ /dev/null @@ -1,155 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM3.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM3 Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (214) ; Interrupts 10 .. 224 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/startup_ARMCM3.c b/external/CMSIS_5/Device/ARM/ARMCM3/Source/startup_ARMCM3.c deleted file mode 100644 index b541573..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/startup_ARMCM3.c +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM3.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM3) - #include "ARMCM3.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM3/Source/system_ARMCM3.c b/external/CMSIS_5/Device/ARM/ARMCM3/Source/system_ARMCM3.c deleted file mode 100644 index 3c5eda7..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM3/Source/system_ARMCM3.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM3.c - * @brief CMSIS Device System Source File for - * ARMCM3 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33.h b/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33.h deleted file mode 100644 index 4530765..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM33.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, without TrustZone) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM33_H -#define ARMCM33_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM33_REV 0x0000U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 0U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ -#define __DSP_PRESENT 0U /* no DSP extension present */ - -#include "core_cm33.h" /* Processor and core peripherals */ -#include "system_ARMCM33.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM33_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h b/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h deleted file mode 100644 index fe486e4..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM33_DSP_FP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM33_DSP_FP_H -#define ARMCM33_DSP_FP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM33_REV 0x0000U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 0U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -#include "core_cm33.h" /* Processor and core peripherals */ -#include "system_ARMCM33.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM33_DSP_FP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h b/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h deleted file mode 100644 index 57e2e7b..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM33_DSP_FP_TZ.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension, with TrustZone) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM33_DSP_FP_TZ_H -#define ARMCM33_DSP_FP_TZ_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM33_REV 0x0000U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -#include "core_cm33.h" /* Processor and core peripherals */ -#include "system_ARMCM33.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM33_DSP_FP_TZ_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h b/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h deleted file mode 100644 index 15d31ee..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM33_TZ.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, with TrustZone) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM33_TZ_H -#define ARMCM33_TZ_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM33_REV 0x0000U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ -#define __DSP_PRESENT 0U /* no DSP extension present */ - -#include "core_cm33.h" /* Processor and core peripherals */ -#include "system_ARMCM33.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM33_TZ_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h b/external/CMSIS_5/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h deleted file mode 100644 index a7cb0d7..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM33.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 - * @version V1.1.1 - * @date 12. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM33_H -#define PARTITION_ARMCM33_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM33_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Include/system_ARMCM33.h b/external/CMSIS_5/Device/ARM/ARMCM33/Include/system_ARMCM33.h deleted file mode 100644 index 9d3145e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Include/system_ARMCM33.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM33.h - * @brief CMSIS Device System Header File for - * ARMCM33 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM33_H -#define SYSTEM_ARMCM33_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM33_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct deleted file mode 100644 index e0f60de..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct deleted file mode 100644 index 2856686..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S b/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S deleted file mode 100644 index 6189924..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.S - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.0.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.main - - #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit - #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base - #endif - - .section RESET - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (470 * 4) /* Interrupts 10 .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - bl __main - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S b/external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S deleted file mode 100644 index 2c42855..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S +++ /dev/null @@ -1,202 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.S - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.3.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.main - - #define __INITIAL_SP __StackTop - #define __STACK_LIMIT __StackLimit - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL __StackSeal - #endif - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (470 * 4) /* Interrupts 10 .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s b/external/CMSIS_5/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s deleted file mode 100644 index 2a0eb7c..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s +++ /dev/null @@ -1,177 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM33.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM33 Device -; * @version V1.1.0 -; * @date 08. April 2021 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - #define __INITIAL_SP sfe(CSTACK) - #define __STACK_LIMIT sfb(CSTACK) - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SECTION STACKSEAL:DATA:NOROOT(3) - #define __STACK_SEAL sfb(STACKSEAL) - #endif - - DATA - -__vector_table - DCD __INITIAL_SP ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler -__vector_table_0x1c - DCD SecureFault_Handler ; -9 Security Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (470) ; Interrupts 10 .. 480 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SecureFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SecureFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/startup_ARMCM33.c b/external/CMSIS_5/Device/ARM/ARMCM33/Source/startup_ARMCM33.c deleted file mode 100644 index 044feb7..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/startup_ARMCM33.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.c - * @brief CMSIS-Core Device Startup File for Cortex-M33 Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM33/Source/system_ARMCM33.c b/external/CMSIS_5/Device/ARM/ARMCM33/Source/system_ARMCM33.c deleted file mode 100644 index 919b8bd..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM33/Source/system_ARMCM33.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM33.c - * @brief CMSIS Device System Source File for - * ARMCM33 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM33) - #include "ARMCM33.h" -#elif defined (ARMCM33_TZ) - #include "ARMCM33_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#elif defined (ARMCM33_DSP_FP) - #include "ARMCM33_DSP_FP.h" -#elif defined (ARMCM33_DSP_FP_TZ) - #include "ARMCM33_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM33.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P.h b/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P.h deleted file mode 100644 index c9e5cb9..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM35P.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM35P Device (configured for ARMCM35P without FPU, without DSP extension, without TrustZone) - * @version V1.0.1 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM35P_H -#define ARMCM35P_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM35P_REV 0x0000U /* Core revision r0p0 */ -#define __SAUREGION_PRESENT 0U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ -#define __DSP_PRESENT 0U /* no DSP extension present */ - -#include "core_cm35p.h" /* Processor and core peripherals */ -#include "system_ARMCM35P.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM35P_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h b/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h deleted file mode 100644 index 7e0f1d6..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM35P_DSP_FP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM35P Device (configured for ARMCM35P with FPU, with DSP extension) - * @version V1.0.1 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM35P_DSP_FP_H -#define ARMCM35P_DSP_FP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM35P_REV 0x0000U /* Core revision r0p0 */ -#define __SAUREGION_PRESENT 0U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -#include "core_cm35p.h" /* Processor and core peripherals */ -#include "system_ARMCM35P.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM35P_DSP_FP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h b/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h deleted file mode 100644 index 2864ba3..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM35P_DSP_FP_TZ.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM35P Device (configured for ARMCM35P with FPU, with DSP extension, with TrustZone) - * @version V1.0.1 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM35P_DSP_FP_TZ_H -#define ARMCM35P_DSP_FP_TZ_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM35P_REV 0x0000U /* Core revision r0p0 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -#include "core_cm35p.h" /* Processor and core peripherals */ -#include "system_ARMCM35P.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM35P_DSP_FP_TZ_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h b/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h deleted file mode 100644 index ffb47ac..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************//** - * @file ARMCM35P_TZ.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM35P Device (configured for ARMCM35P without FPU, without DSP extension, with TrustZone) - * @version V1.0.1 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM35P_TZ_H -#define ARMCM35P_TZ_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM35P_REV 0x0000U /* Core revision r0p0 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ -#define __DSP_PRESENT 0U /* no DSP extension present */ - -#include "core_cm35p.h" /* Processor and core peripherals */ -#include "system_ARMCM35P.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM35P_TZ_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h b/external/CMSIS_5/Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h deleted file mode 100644 index 299dd18..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM35P.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P - * @version V1.0.0 - * @date 03. September 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM35P_H -#define PARTITION_ARMCM35P_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM35P_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/system_ARMCM35P.h b/external/CMSIS_5/Device/ARM/ARMCM35P/Include/system_ARMCM35P.h deleted file mode 100644 index 5c44d2a..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Include/system_ARMCM35P.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM35P.h - * @brief CMSIS Device System Header File for - * ARMCM35P Device - * @version V1.0.2 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM35P_H -#define SYSTEM_ARMCM35P_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM35P_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct deleted file mode 100644 index ab067ee..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct deleted file mode 100644 index a8b35c6..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S deleted file mode 100644 index d3dd492..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM33.S - * @brief CMSIS Core Device Startup File for Cortex-M33 Device - * @version V2.0.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.main - - #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit - #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base - #endif - - .section RESET - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (470 * 4) /* Interrupts 10 .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - bl __main - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S deleted file mode 100644 index 14886ce..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S +++ /dev/null @@ -1,202 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.S - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V1.3.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.main - - #define __INITIAL_SP __StackTop - #define __STACK_LIMIT __StackLimit - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL __StackSeal - #endif - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (470 * 4) /* Interrupts 10 .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s deleted file mode 100644 index dba9d2c..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s +++ /dev/null @@ -1,177 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM35P.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM35P Device -; * @version V2.1.0 -; * @date 08. April 2021 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - #define __INITIAL_SP sfe(CSTACK) - #define __STACK_LIMIT sfb(CSTACK) - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SECTION STACKSEAL:DATA:NOROOT(3) - #define __STACK_SEAL sfb(STACKSEAL) - #endif - - DATA - -__vector_table - DCD __INITIAL_SP ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler -__vector_table_0x1c - DCD SecureFault_Handler ; -9 Security Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (470) ; Interrupts 10 .. 480 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SecureFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SecureFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/startup_ARMCM35P.c b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/startup_ARMCM35P.c deleted file mode 100644 index d2d21d8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/startup_ARMCM35P.c +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM35P.c - * @brief CMSIS-Core Device Startup File for Cortex-M35P Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/system_ARMCM35P.c b/external/CMSIS_5/Device/ARM/ARMCM35P/Source/system_ARMCM35P.c deleted file mode 100644 index 2ccc84b..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM35P/Source/system_ARMCM35P.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM35P.c - * @brief CMSIS Device System Source File for - * ARMCM35P Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM35P) - #include "ARMCM35P.h" -#elif defined (ARMCM35P_TZ) - #include "ARMCM35P_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#elif defined (ARMCM35P_DSP_FP) - #include "ARMCM35P_DSP_FP.h" -#elif defined (ARMCM35P_DSP_FP_TZ) - #include "ARMCM35P_DSP_FP_TZ.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM35P.h" - #endif -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4.h b/external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4.h deleted file mode 100644 index a8c4253..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4.h +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file ARMCM4.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM4 Device (configured for CM4 without FPU) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM4_H -#define ARMCM4_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM4_REV 0x0001U /* Core revision r0p1 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ - -#include "core_cm4.h" /* Processor and core peripherals */ -#include "system_ARMCM4.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM4_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4_FP.h b/external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4_FP.h deleted file mode 100644 index f5912f8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4_FP.h +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file ARMCM4_FP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM4 Device (configured for CM4 with FPU) - * @version V5.3.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM4_FP_H -#define ARMCM4_FP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM4_REV 0x0001U /* Core revision r0p1 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ - -#include "core_cm4.h" /* Processor and core peripherals */ -#include "system_ARMCM4.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM4_FP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Include/system_ARMCM4.h b/external/CMSIS_5/Device/ARM/ARMCM4/Include/system_ARMCM4.h deleted file mode 100644 index 3297c18..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Include/system_ARMCM4.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM4.h - * @brief CMSIS Device System Header File for - * ARMCM4 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM4_H -#define SYSTEM_ARMCM4_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM4_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct b/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct deleted file mode 100644 index e3b09b5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct deleted file mode 100644 index eb67b5f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s b/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s deleted file mode 100644 index e898cb8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s +++ /dev/null @@ -1,172 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM4.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device -; * @version V1.0.1 -; * @date 23. July 2019 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - SPACE (214 * 4) ; Interrupts 10 .. 224 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; Default exception/interrupt handler - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S b/external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S deleted file mode 100644 index 0db5b00..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************//** - * @file startup_ARMCM4.S - * @brief CMSIS-Core(M) Device Startup File for Cortex-M4 Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv7e-m - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s b/external/CMSIS_5/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s deleted file mode 100644 index 5c1aa6b..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s +++ /dev/null @@ -1,155 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM4.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (214) ; Interrupts 10 .. 224 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/startup_ARMCM4.c b/external/CMSIS_5/Device/ARM/ARMCM4/Source/startup_ARMCM4.c deleted file mode 100644 index 2d7ca21..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/startup_ARMCM4.c +++ /dev/null @@ -1,152 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM4.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM4/Source/system_ARMCM4.c b/external/CMSIS_5/Device/ARM/ARMCM4/Source/system_ARMCM4.c deleted file mode 100644 index 9d983d2..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM4/Source/system_ARMCM4.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM4.c - * @brief CMSIS Device System Source File for - * ARMCM4 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM4) - #include "ARMCM4.h" -#elif defined (ARMCM4_FP) - #include "ARMCM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Include/ARMCM55.h b/external/CMSIS_5/Device/ARM/ARMCM55/Include/ARMCM55.h deleted file mode 100644 index 17942a9..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Include/ARMCM55.h +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************************//** - * @file ARMCM55.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM55 Device Series (configured for ARMCM55 with double precision FPU, - * DSP extension, MVE, TrustZone) - * @version V1.0.1 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM55_H -#define ARMCM55_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM55_REV 0x0001U /* Core revision r0p1 */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 1U /* double precision FPU */ -#define __DSP_PRESENT 1U /* DSP extension present */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __PMU_PRESENT 1U /* PMU present */ -#define __PMU_NUM_EVENTCNT 8U /* PMU Event Counters */ -#define __ICACHE_PRESENT 1U /* Instruction Cache present */ -#define __DCACHE_PRESENT 1U /* Data Cache present */ - -#include "core_cm55.h" /* Processor and core peripherals */ -#include "system_ARMCM55.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM55_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Include/Template/partition_ARMCM55.h b/external/CMSIS_5/Device/ARM/ARMCM55/Include/Template/partition_ARMCM55.h deleted file mode 100644 index eabaf30..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Include/Template/partition_ARMCM55.h +++ /dev/null @@ -1,1261 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM55.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 20. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM55_H -#define PARTITION_ARMCM55_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM55_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Include/system_ARMCM55.h b/external/CMSIS_5/Device/ARM/ARMCM55/Include/system_ARMCM55.h deleted file mode 100644 index 1fa72f0..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Include/system_ARMCM55.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.h - * @brief CMSIS Device System Header File for - * ARMCM55 Device - * @version V1.0.1 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2020-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM55_H -#define SYSTEM_ARMCM55_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM55_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct deleted file mode 100644 index 6f84bd3..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct deleted file mode 100644 index 2a3b3f5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Source/startup_ARMCM55.c b/external/CMSIS_5/Device/ARM/ARMCM55/Source/startup_ARMCM55.c deleted file mode 100644 index 0557c5f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Source/startup_ARMCM55.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM55.c - * @brief CMSIS-Core Device Startup File for Cortex-M55 Device - * @version V1.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM55/Source/system_ARMCM55.c b/external/CMSIS_5/Device/ARM/ARMCM55/Source/system_ARMCM55.c deleted file mode 100644 index d66624d..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM55/Source/system_ARMCM55.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM55.c - * @brief CMSIS Device System Source File for - * ARMCM55 Device - * @version V1.1.0 - * @date 28. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM55) - #include "ARMCM55.h" -#else - #error device not specified! -#endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM55.h" - #endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set low-power state for PDEPU */ - /* 0b00 | ON, PDEPU is not in low-power state */ - /* 0b01 | ON, but the clock is off */ - /* 0b10 | RET(ention) */ - /* 0b11 | OFF */ - - /* Clear ELPSTATE, value is 0b11 on Cold reset */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7.h b/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7.h deleted file mode 100644 index 5514ceb..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7.h +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************//** - * @file ARMCM7.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM7 Device (configured for CM7 without FPU) - * @version V5.3.3 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM7_H -#define ARMCM7_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM7_REV 0x0000U /* Core revision r0p0 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ -#define __FPU_DP 0U /* unused */ -#define __ICACHE_PRESENT 1U /* Instruction Cache present */ -#define __DCACHE_PRESENT 1U /* Data Cache present */ -#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */ - -#include "core_cm7.h" /* Processor and core peripherals */ -#include "system_ARMCM7.h" /* System Header */ - - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM7_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_DP.h b/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_DP.h deleted file mode 100644 index a67f1d3..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_DP.h +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************//** - * @file ARMCM7_DP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM7 Device (configured for CM7 with double precision FPU) - * @version V5.3.3 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM7_DP_H -#define ARMCM7_DP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM7_REV 0x0000U /* Core revision r0p0 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 1U /* double precision FPU */ -#define __ICACHE_PRESENT 1U /* Instruction Cache present */ -#define __DCACHE_PRESENT 1U /* Data Cache present */ -#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */ - -#include "core_cm7.h" /* Processor and core peripherals */ -#include "system_ARMCM7.h" /* System Header */ - - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM7_DP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_SP.h b/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_SP.h deleted file mode 100644 index 773b797..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_SP.h +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************//** - * @file ARMCM7_SP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM7 Device (configured for CM7 with single precision FPU) - * @version V5.3.3 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM7_SP_H -#define ARMCM7_SP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 223 are left out */ - Interrupt224_IRQn = 224 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM7_REV 0x0000U /* Core revision r0p0 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 0U /* single precision FPU */ -#define __ICACHE_PRESENT 1U /* Instruction Cache present */ -#define __DCACHE_PRESENT 1U /* Data Cache present */ -#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */ - -#include "core_cm7.h" /* Processor and core peripherals */ -#include "system_ARMCM7.h" /* System Header */ - - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM7_SP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Include/system_ARMCM7.h b/external/CMSIS_5/Device/ARM/ARMCM7/Include/system_ARMCM7.h deleted file mode 100644 index 6a0098f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Include/system_ARMCM7.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM7.h - * @brief CMSIS Device System Header File for - * ARMCM7 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM7_H -#define SYSTEM_ARMCM7_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM7_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct b/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct deleted file mode 100644 index e3b09b5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct deleted file mode 100644 index 3cba29e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct +++ /dev/null @@ -1,80 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s b/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s deleted file mode 100644 index 1eeea61..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s +++ /dev/null @@ -1,172 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM7.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM7 Device -; * @version V1.0.1 -; * @date 23. July 2019 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - SPACE (214 * 4) ; Interrupts 10 .. 224 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; Default exception/interrupt handler - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S b/external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S deleted file mode 100644 index 7af6a20..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************//** - * @file startup_ARMCM7.S - * @brief CMSIS-Core(M) Device Startup File for Cortex-M7 Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv7e-m - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s b/external/CMSIS_5/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s deleted file mode 100644 index e254520..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s +++ /dev/null @@ -1,155 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMCM7.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM7 Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (214) ; Interrupts 10 .. 224 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/startup_ARMCM7.c b/external/CMSIS_5/Device/ARM/ARMCM7/Source/startup_ARMCM7.c deleted file mode 100644 index 509cd33..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/startup_ARMCM7.c +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM7/Source/system_ARMCM7.c b/external/CMSIS_5/Device/ARM/ARMCM7/Source/system_ARMCM7.c deleted file mode 100644 index 75f9c18..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM7/Source/system_ARMCM7.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM7.c - * @brief CMSIS Device System Source File for - * ARMCM7 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Include/ARMCM85.h b/external/CMSIS_5/Device/ARM/ARMCM85/Include/ARMCM85.h deleted file mode 100644 index 03b1c75..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Include/ARMCM85.h +++ /dev/null @@ -1,135 +0,0 @@ -/**************************************************************************//** - * @file ARMCM85.h - * @brief CMSIS Device Header File for ARMCM85 Device - * (double precision FPU, DSP extension, MVE, TrustZone) - * @version V1.0.2 - * @date 01. May 2023 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMCM85_H -#define ARMCM85_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9, - /* Interrupts 10 .. 479 are left out */ - Interrupt480_IRQn = 480 -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __CM85_REV 0x0001U /* Core revision r0p1 */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 1U /* double precision FPU */ -#define __DSP_PRESENT 1U /* DSP extension present */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __PMU_PRESENT 1U /* PMU present */ -#define __PMU_NUM_EVENTCNT 8U /* PMU Event Counters */ -#define __ICACHE_PRESENT 1U /* Instruction Cache present */ -#define __DCACHE_PRESENT 1U /* Data Cache present */ - -#include "core_cm85.h" /* Processor and core peripherals */ -#include "system_ARMCM85.h" /* System Header */ - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMCM85_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Include/Template/partition_ARMCM85.h b/external/CMSIS_5/Device/ARM/ARMCM85/Include/Template/partition_ARMCM85.h deleted file mode 100644 index a3d881a..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Include/Template/partition_ARMCM85.h +++ /dev/null @@ -1,1301 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMCM85.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.0 - * @date 07. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMCM85_H -#define PARTITION_ARMCM85_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Description -*/ -#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Description -*/ -#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMCM85_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Include/system_ARMCM85.h b/external/CMSIS_5/Device/ARM/ARMCM85/Include/system_ARMCM85.h deleted file mode 100644 index 05c4312..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Include/system_ARMCM85.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.h - * @brief CMSIS Device System Header File for ARMCM85 Device - * @version V1.0.1 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMCM85_H -#define SYSTEM_ARMCM85_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM85_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct b/external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct deleted file mode 100644 index 82b1e2b..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct +++ /dev/null @@ -1,130 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct deleted file mode 100644 index 9229164..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct +++ /dev/null @@ -1,130 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> -; 0xFFFFFFFF: Place Veneers at the end of Flash (default) -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_BASE 0xFFFFFFFF -#define __CMSEVENEER_SIZE 0x00000400 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#else -#define __CV_BASE ( __CMSEVENEER_BASE ) -#endif -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMCM85/Source/GCC/gcc_arm.ld deleted file mode 100644 index 028ca8e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Source/startup_ARMCM85.c b/external/CMSIS_5/Device/ARM/ARMCM85/Source/startup_ARMCM85.c deleted file mode 100644 index 067871d..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Source/startup_ARMCM85.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM85.c - * @brief CMSIS Device Startup File for ARMCM85 Device - * @version V1.0.0 - * @date 07. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMCM85/Source/system_ARMCM85.c b/external/CMSIS_5/Device/ARM/ARMCM85/Source/system_ARMCM85.c deleted file mode 100644 index 7a16501..0000000 --- a/external/CMSIS_5/Device/ARM/ARMCM85/Source/system_ARMCM85.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM85.c - * @brief CMSIS Device System Source File for ARMCM85 Device - * @version V1.0.0 - * @date 30. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM85) - #include "ARMCM85.h" - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMCM85.h" - #endif -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Include/ARMSC000.h b/external/CMSIS_5/Device/ARM/ARMSC000/Include/ARMSC000.h deleted file mode 100644 index f0b69c5..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Include/ARMSC000.h +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************//** - * @file ARMSC000.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMSC000 Device - * @version V5.3.2 - * @date 10. Jan 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMSC000_H -#define ARMSC000_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 31 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __SC000_REV 0x0000U /* Core revision r0p0 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 0U /* no VTOR present*/ -#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_sc000.h" /* Processor and core peripherals */ -#include "system_ARMSC000.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMSC000_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Include/system_ARMSC000.h b/external/CMSIS_5/Device/ARM/ARMSC000/Include/system_ARMSC000.h deleted file mode 100644 index aeeb783..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Include/system_ARMSC000.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMSC000.h - * @brief CMSIS Device System Header File for - * ARMSC000 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMSC000_H -#define SYSTEM_ARMSC000_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMSC000_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct b/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct deleted file mode 100644 index 4c87ef8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct b/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct deleted file mode 100644 index a01fdb4..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=sc000 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s b/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s deleted file mode 100644 index 37df773..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s +++ /dev/null @@ -1,168 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMSC000.s -; * @brief CMSIS Core Device Startup File for -; * ARMSC000 Device -; * @version V1.0.1 -; * @date 23. July 2019 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; Default exception/interrupt handler - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S b/external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S deleted file mode 100644 index 2b5fcbd..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************//** - * @file startup_ARMSC000.S - * @brief CMSIS-Core(M) Device Startup File for SC000 Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv6-m - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s b/external/CMSIS_5/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s deleted file mode 100644 index 1f44905..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s +++ /dev/null @@ -1,147 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMSC000.s -; * @brief CMSIS Core Device Startup File for -; * for ARMSC000 Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 ( 22) ; Interrupts 10 .. 31 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/startup_ARMSC000.c b/external/CMSIS_5/Device/ARM/ARMSC000/Source/startup_ARMSC000.c deleted file mode 100644 index 1206133..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/startup_ARMSC000.c +++ /dev/null @@ -1,146 +0,0 @@ -/****************************************************************************** - * @file startup_ARMSC000.c - * @brief CMSIS-Core(M) Device Startup File for a SC000 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMSC000) - #include "ARMSC000.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMSC000/Source/system_ARMSC000.c b/external/CMSIS_5/Device/ARM/ARMSC000/Source/system_ARMSC000.c deleted file mode 100644 index 914bf11..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC000/Source/system_ARMSC000.c +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************//** - * @file system_ARMSC000.c - * @brief CMSIS Device System Source File for - * for ARMSC000 Device - * @version V1.0.0 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMSC000.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Include/ARMSC300.h b/external/CMSIS_5/Device/ARM/ARMSC300/Include/ARMSC300.h deleted file mode 100644 index b835e28..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Include/ARMSC300.h +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************//** - * @file ARMSC300.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMSC300 Device - * @version V5.3.2 - * @date 10. Jan 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMSC300_H -#define ARMSC300_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 224 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __SC300_REV 0x0000U /* Core revision r0p0 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_sc300.h" /* Processor and core peripherals */ -#include "system_ARMSC300.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMSC300_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Include/system_ARMSC300.h b/external/CMSIS_5/Device/ARM/ARMSC300/Include/system_ARMSC300.h deleted file mode 100644 index 3f3617e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Include/system_ARMSC300.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMSC300.h - * @brief CMSIS Device System Header File for - * ARMSC300 Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMSC300_H -#define SYSTEM_ARMSC300_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMSC300_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct b/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct deleted file mode 100644 index 4c87ef8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct b/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct deleted file mode 100644 index 475f1b7..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=sc300 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s b/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s deleted file mode 100644 index 74640ea..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s +++ /dev/null @@ -1,172 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMSC300.s -; * @brief CMSIS Core Device Startup File for -; * ARMSC300 Device -; * @version V1.0.1 -; * @date 23. July 2019 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - SPACE (214 * 4) ; Interrupts 10 .. 224 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; Default exception/interrupt handler - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld deleted file mode 100644 index 7498908..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.1.0 - * @date 04. August 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S b/external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S deleted file mode 100644 index df1a54c..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************//** - * @file startup_ARMSC300.S - * @brief CMSIS-Core(M) Device Startup File for SC300 Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv7-m - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s b/external/CMSIS_5/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s deleted file mode 100644 index 6387b71..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s +++ /dev/null @@ -1,155 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMSC300.s -; * @brief CMSIS Core Device Startup File for -; * ARMSC300 Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (214) ; Interrupts 10 .. 224 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/startup_ARMSC300.c b/external/CMSIS_5/Device/ARM/ARMSC300/Source/startup_ARMSC300.c deleted file mode 100644 index c138a71..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/startup_ARMSC300.c +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************** - * @file startup_ARMSC300.c - * @brief CMSIS-Core(M) Device Startup File for a SC300 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMSC300) - #include "ARMSC300.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMSC300/Source/system_ARMSC300.c b/external/CMSIS_5/Device/ARM/ARMSC300/Source/system_ARMSC300.c deleted file mode 100644 index cbf95db..0000000 --- a/external/CMSIS_5/Device/ARM/ARMSC300/Source/system_ARMSC300.c +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************//** - * @file system_ARMSC300.c - * @brief CMSIS Device System Source File for - * ARMSC300 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMSC300.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h b/external/CMSIS_5/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h deleted file mode 100644 index d0c95d6..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************//** - * @file ARMv81MML_DSP_DP_MVE_FP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * Armv8.1-M Mainline Device Series (configured for Armv8.1-M Mainline with double precision FPU, with DSP extension, with TrustZone) - * @version V1.1.0 - * @date 27. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv81MML_DSP_DP_MVE_FP_H -#define ARMv81MML_DSP_DP_MVE_FP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* -------------------- Armv8.1-M Mainline Processor Exceptions Numbers --------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - -/* --- Configuration of the Armv8.1-M Mainline Processor and Core Peripherals --- */ -#define __ARMv81MML_REV 0x0001U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __PMU_PRESENT 1U /* PMU present */ -#define __PMU_NUM_EVENTCNT 31U /* Number of PMU event counters */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 1U /* double precision FPU */ -#define __DSP_PRESENT 1U /* DSP extension present */ -#define __ICACHE_PRESENT 1U /* Instruction Cache present */ -#define __DCACHE_PRESENT 1U /* Data Cache present */ - -#include "core_armv81mml.h" /* Processor and core peripherals */ -#include "system_ARMv81MML.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv81MML_DSP_DP_MVE_FP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h b/external/CMSIS_5/Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h deleted file mode 100644 index 499f9e2..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h +++ /dev/null @@ -1,1261 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMv81MML.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline - * @version V1.0.1 - * @date 26. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMv81MML_H -#define PARTITION_ARMv81MML_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMv81MML_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Include/system_ARMv81MML.h b/external/CMSIS_5/Device/ARM/ARMv81MML/Include/system_ARMv81MML.h deleted file mode 100644 index fe2a52a..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Include/system_ARMv81MML.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMv81MML.h - * @brief CMSIS Device System Header File for - * Armv8.1-M Mainline Device Series - * @version V1.0.2 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMv81MML_H -#define SYSTEM_ARMv81MML_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMv81MML_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct b/external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct deleted file mode 100644 index 985948f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct deleted file mode 100644 index 0b660f6..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/startup_ARMv81MML.c b/external/CMSIS_5/Device/ARM/ARMv81MML/Source/startup_ARMv81MML.c deleted file mode 100644 index 17167b9..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/startup_ARMv81MML.c +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * @file startup_ARMv81MML.c - * @brief CMSIS-Core Device Startup File for ARMv81MML Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMv81MML_DSP_DP_MVE_FP) - #include "ARMv81MML_DSP_DP_MVE_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/system_ARMv81MML.c b/external/CMSIS_5/Device/ARM/ARMv81MML/Source/system_ARMv81MML.c deleted file mode 100644 index 2a545b0..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv81MML/Source/system_ARMv81MML.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************//** - * @file system_ARMv81MML.c - * @brief CMSIS Device System Source File for - * Armv8.1-M Mainline Device Series - * @version V1.2.1 - * @date 27. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMv81MML_DSP_DP_MVE_FP) - #include "ARMv81MML_DSP_DP_MVE_FP.h" -#else - #error device not specified! -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMv81MML.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL ( 5000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5U * XTAL) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -// Enable Loop and branch info cache -SCB->CCR |= SCB_CCR_LOB_Msk; -__ISB(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h b/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h deleted file mode 100644 index f5eedab..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************//** - * @file ARMv8MBL.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMv8MBL Device - * @version V5.3.1 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv8MBL_H -#define ARMv8MBL_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ -#define __SAUREGION_PRESENT 1U /* SAU regions are present */ -#define __MPU_PRESENT 0U /* no MPU present */ -#define __VTOR_PRESENT 0U /* no VTOR present */ -#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ - -#include "core_armv8mbl.h" /* Processor and core peripherals */ -#include "system_ARMv8MBL.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv8MBL_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h b/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h deleted file mode 100644 index f87aa84..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h +++ /dev/null @@ -1,1232 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMv8MBL.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMv8MBL - * @version V1.0.0 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMv8MBL_H -#define PARTITION_ARMv8MBL_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - - -/* -// Setup behaviour of single SysTick -*/ -#define SCB_ICSR_INIT 0 - -/* -// in a single SysTick implementation, SysTick is -// <0=>Secure -// <1=>Non-Secure -// Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation -*/ -#define SCB_ICSR_STTNS_VAL 0 - -/* -// -*/ - - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) - SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | - ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); - #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMv8MBL_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h b/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h deleted file mode 100644 index 4bd1807..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMv8MBL.h - * @brief CMSIS Device System Header File for - * ARMv8MBL Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMv8MBL_H -#define SYSTEM_ARMv8MBL_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMv8MBL_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct deleted file mode 100644 index 4baac6e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct deleted file mode 100644 index 36a82da..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.S b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.S deleted file mode 100644 index 309c1fb..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.S +++ /dev/null @@ -1,155 +0,0 @@ -/****************************************************************************** - * @file startup_ARMv8MBL.S - * @brief CMSIS-Core Device Startup File for ARMv8MBL Device - * @version V2.0.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.base - - #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit - #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base - #endif - - .section RESET - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - str r1,[r0,#0] - str r1,[r0,#4] - #endif - - bl SystemInit - - bl __main - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S deleted file mode 100644 index b8ce641..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S +++ /dev/null @@ -1,200 +0,0 @@ -/****************************************************************************** - * @file startup_ARMv8MBL.S - * @brief CMSIS-Core Device Startup File for ARMv8MBL Device - * @version V2.2.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.base - - #define __INITIAL_SP __StackTop - #define __STACK_LIMIT __StackLimit - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL __StackSeal - #endif - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (214 * 4) /* Interrupts 10 .. 224 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - str r1,[r0,#0] - str r1,[r0,#4] - #endif - - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s deleted file mode 100644 index 981885f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s +++ /dev/null @@ -1,147 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMv8MBL.s -; * @brief CMSIS Core Device Startup File for -; * ARMv8MBL Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (470) ; Interrupts 10 .. 480 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/startup_ARMv8MBL.c b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/startup_ARMv8MBL.c deleted file mode 100644 index c8e9e6e..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/startup_ARMv8MBL.c +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************** - * @file startup_ARMv8MBL.c - * @brief CMSIS-Core Device Startup File for a ARMv8MBL Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMv8MBL) - #include "ARMv8MBL.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c b/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c deleted file mode 100644 index 6bab139..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************//** - * @file system_ARMv8MBL.c - * @brief CMSIS Device System Source File for - * ARMv8MBL Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMv8MBL.h" - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMv8MBL.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__Vectors[0]); -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML.h deleted file mode 100644 index f9c60b4..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML.h +++ /dev/null @@ -1,132 +0,0 @@ -/**************************************************************************//** - * @file ARMv8MML.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMv8MML Device (configured for ARMv8MML without FPU, without DSP extension, with TrustZone) - * @version V5.4.0 - * @date 03. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv8MML_H -#define ARMv8MML_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ -#define __DSP_PRESENT 0U /* no DSP extension present */ -#define __ICACHE_PRESENT 1U -#define __DCACHE_PRESENT 1U - -#include "core_armv8mml.h" /* Processor and core peripherals */ -#include "system_ARMv8MML.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv8MML_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h deleted file mode 100644 index 3d29fa0..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************//** - * @file ARMv8MML_DP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMv8MML Device (configured for ARMv8MML with double precision FPU, without DSP extension, with TrustZone) - * @version V5.4.0 - * @date 03. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv8MML_DP_H -#define ARMv8MML_DP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 1U /* double precision FPU */ -#define __DSP_PRESENT 0U /* no DSP extension present */ -#define __ICACHE_PRESENT 1U -#define __DCACHE_PRESENT 1U - -#include "core_armv8mml.h" /* Processor and core peripherals */ -#include "system_ARMv8MML.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv8MML_DP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h deleted file mode 100644 index 40d860d..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h +++ /dev/null @@ -1,132 +0,0 @@ -/**************************************************************************//** - * @file ARMv8MML_DSP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMv8MML Mainline Device (configured for ARMv8MML without FPU, with DSP extension, with TrustZone) - * @version V5.4.0 - * @date 03. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv8MML_DSP_H -#define ARMv8MML_DSP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /* no FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ -#define __ICACHE_PRESENT 1U -#define __DCACHE_PRESENT 1U - -#include "core_armv8mml.h" /* Processor and core peripherals */ -#include "system_ARMv8MML.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv8MML_DSP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h deleted file mode 100644 index 4924332..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************//** - * @file ARMv8MML_DSP_DP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMv8MML Mainline Device (configured for Armv8-M MainlineARMv8MML - * @version V5.4.0 - * @date 03. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv8MML_DSP_DP_H -#define ARMv8MML_DSP_DP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 1U /* double precision FPU */ -#define __DSP_PRESENT 1U /* DSP extension present */ -#define __ICACHE_PRESENT 1U -#define __DCACHE_PRESENT 1U - -#include "core_armv8mml.h" /* Processor and core peripherals */ -#include "system_ARMv8MML.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv8MML_DSP_DP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h deleted file mode 100644 index ec69d17..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************//** - * @file ARMv8MML_DSP_SP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMv8MML Mainline Device (configured for ARMv8MML with single precision FPU, with DSP extension, with TrustZone) - * @version V5.4.0 - * @date 03. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv8MML_DSP_SP_H -#define ARMv8MML_DSP_SP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 0U /* single precision FPU */ -#define __DSP_PRESENT 1U /* DSP extension present */ -#define __ICACHE_PRESENT 1U -#define __DCACHE_PRESENT 1U - -#include "core_armv8mml.h" /* Processor and core peripherals */ -#include "system_ARMv8MML.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv8MML_DSP_SP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h deleted file mode 100644 index 869ddd8..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************//** - * @file ARMv8MML_SP.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMv8MML Device (configured for ARMv8MML with single precision FPU, without DSP extension, with TrustZone) - * @version V5.4.0 - * @date 03. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARMv8MML_SP_H -#define ARMv8MML_SP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Processor Exceptions Numbers ----------------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SVC Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 PendSV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ------------------- Processor Interrupt Numbers ------------------------------ */ - Interrupt0_IRQn = 0, - Interrupt1_IRQn = 1, - Interrupt2_IRQn = 2, - Interrupt3_IRQn = 3, - Interrupt4_IRQn = 4, - Interrupt5_IRQn = 5, - Interrupt6_IRQn = 6, - Interrupt7_IRQn = 7, - Interrupt8_IRQn = 8, - Interrupt9_IRQn = 9 - /* Interrupts 10 .. 480 are left out */ -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* -------- Configuration of Core Peripherals ----------------------------------- */ -#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __FPU_DP 0U /* single precision FPU */ -#define __DSP_PRESENT 0U /* no DSP extension present */ -#define __ICACHE_PRESENT 1U -#define __DCACHE_PRESENT 1U - -#include "core_armv8mml.h" /* Processor and core peripherals */ -#include "system_ARMv8MML.h" /* System Header */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ARMv8MML_SP_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h deleted file mode 100644 index f7995ef..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h +++ /dev/null @@ -1,1260 +0,0 @@ -/**************************************************************************//** - * @file partition_ARMv8MML.h - * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8-M Mainline - * @version V1.1.1 - * @date 18. March 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION_ARMv8MML_H -#define PARTITION_ARMv8MML_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_ARMv8MML_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h b/external/CMSIS_5/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h deleted file mode 100644 index c8798b2..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************//** - * @file system_ARMv8MML.h - * @brief CMSIS Device System Header File for - * ARMv8MML Device - * @version V5.3.3 - * @date 11. July 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_ARMv8MML_H -#define SYSTEM_ARMv8MML_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMv8MML_H */ diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct deleted file mode 100644 index 2c12080..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct deleted file mode 100644 index d0b468f..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc -mcmse -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.S b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.S deleted file mode 100644 index e280389..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.S +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************** - * @file startup_ARMv8MML.S - * @brief CMSIS-Core Device Startup File for Cortex-ARMv8MML Device - * @version V2.0.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.main - - #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit - #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base - #endif - - .section RESET - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (470 * 4) /* Interrupts 10 .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - bl __main - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld deleted file mode 100644 index c8f0efe..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S deleted file mode 100644 index 8bc767a..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S +++ /dev/null @@ -1,202 +0,0 @@ -/****************************************************************************** - * @file startup_ARMv8MML.S - * @brief CMSIS-Core Device Startup File for ARMv8MML evice - * @version V2.3.0 - * @date 26. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .arch armv8-m.main - - #define __INITIAL_SP __StackTop - #define __STACK_LIMIT __StackLimit - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL __StackSeal - #endif - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVC Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - - /* Interrupts */ - .long Interrupt0_Handler /* 0 Interrupt 0 */ - .long Interrupt1_Handler /* 1 Interrupt 1 */ - .long Interrupt2_Handler /* 2 Interrupt 2 */ - .long Interrupt3_Handler /* 3 Interrupt 3 */ - .long Interrupt4_Handler /* 4 Interrupt 4 */ - .long Interrupt5_Handler /* 5 Interrupt 5 */ - .long Interrupt6_Handler /* 6 Interrupt 6 */ - .long Interrupt7_Handler /* 7 Interrupt 7 */ - .long Interrupt8_Handler /* 8 Interrupt 8 */ - .long Interrupt9_Handler /* 9 Interrupt 9 */ - - .space (470 * 4) /* Interrupts 10 .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsls r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsls r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* Default exception/interrupt handler */ - - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - - Set_Default_Handler Interrupt0_Handler - Set_Default_Handler Interrupt1_Handler - Set_Default_Handler Interrupt2_Handler - Set_Default_Handler Interrupt3_Handler - Set_Default_Handler Interrupt4_Handler - Set_Default_Handler Interrupt5_Handler - Set_Default_Handler Interrupt6_Handler - Set_Default_Handler Interrupt7_Handler - Set_Default_Handler Interrupt8_Handler - Set_Default_Handler Interrupt9_Handler - - .end diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s deleted file mode 100644 index a6d7ed2..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s +++ /dev/null @@ -1,157 +0,0 @@ -;/**************************************************************************//** -; * @file startup_ARMv8MML.s -; * @brief CMSIS Core Device Startup File for -; * ARMv8MML Device -; * @version V1.0.0 -; * @date 09. July 2018 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler -__vector_table_0x1c - DCD SecureFault_Handler ; -9 Security Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVC Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - - ; Interrupts - DCD Interrupt0_Handler ; 0 Interrupt 0 - DCD Interrupt1_Handler ; 1 Interrupt 1 - DCD Interrupt2_Handler ; 2 Interrupt 2 - DCD Interrupt3_Handler ; 3 Interrupt 3 - DCD Interrupt4_Handler ; 4 Interrupt 4 - DCD Interrupt5_Handler ; 5 Interrupt 5 - DCD Interrupt6_Handler ; 6 Interrupt 6 - DCD Interrupt7_Handler ; 7 Interrupt 7 - DCD Interrupt8_Handler ; 8 Interrupt 8 - DCD Interrupt9_Handler ; 9 Interrupt 9 - - DS32 (470) ; Interrupts 10 .. 480 are left out -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - - THUMB - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SecureFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK Interrupt0_Handler - PUBWEAK Interrupt1_Handler - PUBWEAK Interrupt2_Handler - PUBWEAK Interrupt3_Handler - PUBWEAK Interrupt4_Handler - PUBWEAK Interrupt5_Handler - PUBWEAK Interrupt6_Handler - PUBWEAK Interrupt7_Handler - PUBWEAK Interrupt8_Handler - PUBWEAK Interrupt9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SecureFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler - -Interrupt0_Handler -Interrupt1_Handler -Interrupt2_Handler -Interrupt3_Handler -Interrupt4_Handler -Interrupt5_Handler -Interrupt6_Handler -Interrupt7_Handler -Interrupt8_Handler -Interrupt9_Handler -Default_Handler - B . - - - END diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/startup_ARMv8MML.c b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/startup_ARMv8MML.c deleted file mode 100644 index a91eb71..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/startup_ARMv8MML.c +++ /dev/null @@ -1,174 +0,0 @@ -/****************************************************************************** - * @file startup_ARMv8MML.c - * @brief CMSIS-Core Device Startup File for ARMv8MML Device - * @version V2.1.0 - * @date 16. December 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMv8MML) - #include "ARMv8MML.h" -#elif defined (ARMv8MML_DSP) - #include "ARMv8MML_DSP.h" -#elif defined (ARMv8MML_SP) - #include "ARMv8MML_SP.h" -#elif defined (ARMv8MML_DSP_SP) - #include "ARMv8MML_DSP_SP.h" -#elif defined (ARMv8MML_DP) - #include "ARMv8MML_DP.h" -#elif defined (ARMv8MML_DSP_DP) - #include "ARMv8MML_DSP_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 480 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c b/external/CMSIS_5/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c deleted file mode 100644 index c623277..0000000 --- a/external/CMSIS_5/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c +++ /dev/null @@ -1,98 +0,0 @@ -/**************************************************************************//** - * @file system_ARMv8MML.c - * @brief CMSIS Device System Source File for - * ARMv8MML Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMv8MML) - #include "ARMv8MML.h" -#elif defined (ARMv8MML_DSP) - #include "ARMv8MML_DSP.h" -#elif defined (ARMv8MML_SP) - #include "ARMv8MML_SP.h" -#elif defined (ARMv8MML_DSP_SP) - #include "ARMv8MML_DSP_SP.h" -#elif defined (ARMv8MML_DP) - #include "ARMv8MML_DP.h" -#elif defined (ARMv8MML_DSP_DP) - #include "ARMv8MML_DSP_DP.h" -#else - #error device not specified! -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_ARMv8MML.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__Vectors[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM1.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM1.svd deleted file mode 100644 index b51ac3b..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM1.svd +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM1 - ARM Cortex M0+ - 1.0 - ARM 32-bit Cortex-M0+ based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM1 - r0p0 - little - false - false - false - 2 - false - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM23.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM23.svd deleted file mode 100644 index 3e01f8b..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM23.svd +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM23 - ARMv8-M Baseline - 1.0 - ARM 32-bit Cortex-M23 based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM23 - r0p0 - little - true - false - true - 3 - false - 4 - - - 0x00000000 - 0x001FFFE0 - - c - - - 0x00200000 - 0x003FFFE0 - - n - - - 0x20200000 - 0x203FFFE0 - - n - - - 0x40000000 - 0x40040000 - - n - - - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM3.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM3.svd deleted file mode 100644 index 26e6acd..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM3.svd +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM3 - ARM Cortex M3 - 1.0 - ARM 32-bit Cortex-M3 based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM3 - r2p1 - little - true - false - true - 3 - false - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM33.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM33.svd deleted file mode 100644 index 0715db2..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM33.svd +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM33 - ARMv8-M Mainline - 1.0 - ARM 32-bit Cortex-M33 based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM33 - r0p0 - little - true - false - true - 3 - false - 4 - - - 0x00000000 - 0x001FFFE0 - - c - - - 0x00200000 - 0x003FFFE0 - - n - - - 0x20200000 - 0x203FFFE0 - - n - - - 0x40000000 - 0x40040000 - - n - - - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM35P.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM35P.svd deleted file mode 100644 index 1f4fab5..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM35P.svd +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM35P - ARMv8-M Mainline - 1.0 - ARM 32-bit Cortex-M35P based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM35P - r0p0 - little - true - false - true - 3 - false - 4 - - - 0x00000000 - 0x001FFFE0 - - c - - - 0x00200000 - 0x003FFFE0 - - n - - - 0x20200000 - 0x203FFFE0 - - n - - - 0x40000000 - 0x40040000 - - n - - - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM4.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM4.svd deleted file mode 100644 index a78bc8a..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM4.svd +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM4 - ARM Cortex M4 - 1.0 - ARM 32-bit Cortex-M4 based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM4 - r0p1 - little - true - false - true - 3 - false - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM55.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM55.svd deleted file mode 100644 index b5be4ec..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM55.svd +++ /dev/null @@ -1,107 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM55 - ARMv8.1-M Mainline - 1.0 - ARM 32-bit Cortex-M55 based device - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM55 - r0p0 - little - true - true - true - true - true - 3 - false - true - 12 - 4 - - - 0x00000000 - 0x001FFFE0 - - c - - - 0x00200000 - 0x003FFFE0 - - n - - - 0x20200000 - 0x203FFFE0 - - n - - - 0x40000000 - 0x40040000 - - n - - - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM7.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM7.svd deleted file mode 100644 index 7b69cb7..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM7.svd +++ /dev/null @@ -1,80 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMCM7 - ARM Cortex M7 - 1.0 - ARM 32-bit Cortex-M7 based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM7 - r1p1 - little - true - false - true - 3 - false - true - true - false - false - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMCM85.svd b/external/CMSIS_5/Device/ARM/SVD/ARMCM85.svd deleted file mode 100644 index 7187352..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMCM85.svd +++ /dev/null @@ -1,105 +0,0 @@ - - - - - ARM Ltd. - ARM - ARMCM85 - ARMv8.1-M Mainline - 1.0 - ARM 32-bit Cortex-M85 based device - - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - CM85 - r0p0 - little - true - true - true - true - true - 3 - false - true - 12 - 4 - - - 0x00000000 - 0x001FFFE0 - - c - - - 0x00200000 - 0x003FFFE0 - - n - - - 0x20200000 - 0x203FFFE0 - - n - - - 0x40000000 - 0x40040000 - - n - - - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMSC000.svd b/external/CMSIS_5/Device/ARM/SVD/ARMSC000.svd deleted file mode 100644 index 261edd1..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMSC000.svd +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMSC000 - ARM Cortex SC000 - 1.0 - ARM 32-bit Cortex-SC000 based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - SC000 - r0p0 - little - true - false - false - 2 - false - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMSC300.svd b/external/CMSIS_5/Device/ARM/SVD/ARMSC300.svd deleted file mode 100644 index 8beb8cc..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMSC300.svd +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMSC300 - ARM Cortex SC300 - 1.0 - ARM 32-bit Cortex-SC300 based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - SC300 - r0p0 - little - true - false - true - 3 - false - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMv8MBL.svd b/external/CMSIS_5/Device/ARM/SVD/ARMv8MBL.svd deleted file mode 100644 index 722ebe8..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMv8MBL.svd +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMv8MBL - ARMv8-M Baseline - 1.0 - ARM 32-bit v8-M Baseline based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - ARMV8MBL - r0p0 - little - true - false - true - 3 - false - 4 - - - 0x00000000 - 0x001FFFE0 - - c - - - 0x00200000 - 0x003FFFE0 - - n - - - 0x20200000 - 0x203FFFE0 - - n - - - 0x40000000 - 0x40040000 - - n - - - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/ARM/SVD/ARMv8MML.svd b/external/CMSIS_5/Device/ARM/SVD/ARMv8MML.svd deleted file mode 100644 index bb2c998..0000000 --- a/external/CMSIS_5/Device/ARM/SVD/ARMv8MML.svd +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - ARM Ltd. - ARM - ARMv8MML - ARMV8M - 1.0 - ARM 32-bit v8-M Baseline based device. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - - ARMV8MML - r0p0 - little - true - false - true - 3 - false - 4 - - - 0x00000000 - 0x001FFFE0 - - c - - - 0x00200000 - 0x003FFFE0 - - n - - - 0x20200000 - 0x203FFFE0 - - n - - - 0x40000000 - 0x40040000 - - n - - - - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - diff --git a/external/CMSIS_5/Device/_Template_Flash/Abstract.txt b/external/CMSIS_5/Device/_Template_Flash/Abstract.txt deleted file mode 100644 index b0ebabe..0000000 --- a/external/CMSIS_5/Device/_Template_Flash/Abstract.txt +++ /dev/null @@ -1,32 +0,0 @@ -Creating a new Algorithm ------------------------- - -Flash programming algorithms are defined with functions to erase and program -the Flash device. Special compiler and linker settings are required. Follow -these steps to create and configure a new Flash programming algorithm: -- From the toolbar, use the drop-down Select Target to define the processor - architecture. Cortex-M fits for all Arm Cortex-M0/M0+/M3/M4/M7 devices. - The configuration assumes a little-endian microcontroller. In case of a - big-endian microcontroller, select the correct processor core with - Project - Options for Target - Device. -- Open the dialog Project - Options for Target - Output and change the content - of the field Name of Executable to represent the device, for example - MyDevice. -- Adapt the programming algorithms in the file FlashPrg.c -- Adapt the device parameters in the file FlashDev.c -- Use Project - Build Target to generate the new Flash programming algorithm. - The output file (for example MyDevice.FLM) has to be added to the DFP. - -Note ----- -- Creating a Flash programming algorithm with MDK-Lite is not supported. -- Flash programming algorithms use Read-Only Position Independent and - Read-Write Position Independent program code. These options are set in the - dialogs Project - Options for Target - C/C++ and - Project - Options for Target - Asm. -- The dialog Project - Options for Target - Linker defines the linker scatter - file Target.lin. The error L6305 is disabled with –diag_suppress L6305. - -For more information, refer to the documentation available at -http://arm-software.github.io/CMSIS_5/Pack/html/flashAlgorithm.html - diff --git a/external/CMSIS_5/Device/_Template_Flash/FlashDev.c b/external/CMSIS_5/Device/_Template_Flash/FlashDev.c deleted file mode 100644 index bcdfbbd..0000000 --- a/external/CMSIS_5/Device/_Template_Flash/FlashDev.c +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************//** - * @file FlashDev.c - * @brief Flash Device Description for New Device Flash - * @version V1.0.0 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2010-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "FlashOS.h" // FlashOS Structures - - -struct FlashDevice const FlashDevice = { - FLASH_DRV_VERS, // Driver Version, do not modify! - "New Device 256kB Flash", // Device Name - ONCHIP, // Device Type - 0x00000000, // Device Start Address - 0x00040000, // Device Size in Bytes (256kB) - 1024, // Programming Page Size - 0, // Reserved, must be 0 - 0xFF, // Initial Content of Erased Memory - 100, // Program Page Timeout 100 mSec - 3000, // Erase Sector Timeout 3000 mSec - -// Specify Size and Address of Sectors - 0x002000, 0x000000, // Sector Size 8kB (8 Sectors) - 0x010000, 0x010000, // Sector Size 64kB (2 Sectors) - 0x002000, 0x030000, // Sector Size 8kB (8 Sectors) - SECTOR_END -}; diff --git a/external/CMSIS_5/Device/_Template_Flash/FlashOS.h b/external/CMSIS_5/Device/_Template_Flash/FlashOS.h deleted file mode 100644 index 350e309..0000000 --- a/external/CMSIS_5/Device/_Template_Flash/FlashOS.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************//** - * @file FlashOS.h - * @brief Data structures and entries Functions - * @version V1.0.0 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2010-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#define VERS 1 // Interface Version 1.01 - -#define UNKNOWN 0 // Unknown -#define ONCHIP 1 // On-chip Flash Memory -#define EXT8BIT 2 // External Flash Device on 8-bit Bus -#define EXT16BIT 3 // External Flash Device on 16-bit Bus -#define EXT32BIT 4 // External Flash Device on 32-bit Bus -#define EXTSPI 5 // External Flash Device on SPI - -#define SECTOR_NUM 512 // Max Number of Sector Items -#define PAGE_MAX 65536 // Max Page Size for Programming - -struct FlashSectors { - unsigned long szSector; // Sector Size in Bytes - unsigned long AddrSector; // Address of Sector -}; - -#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF - -struct FlashDevice { - unsigned short Vers; // Version Number and Architecture - char DevName[128]; // Device Name and Description - unsigned short DevType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ... - unsigned long DevAdr; // Default Device Start Address - unsigned long szDev; // Total Size of Device - unsigned long szPage; // Programming Page Size - unsigned long Res; // Reserved for future Extension - unsigned char valEmpty; // Content of Erased Memory - - unsigned long toProg; // Time Out of Program Page Function - unsigned long toErase; // Time Out of Erase Sector Function - - struct FlashSectors sectors[SECTOR_NUM]; -}; - -#define FLASH_DRV_VERS (0x0100+VERS) // Driver Version, do not modify! - -// Flash Programming Functions (Called by FlashOS) -extern int Init (unsigned long adr, // Initialize Flash - unsigned long clk, - unsigned long fnc); -extern int UnInit (unsigned long fnc); // De-initialize Flash -extern int BlankCheck (unsigned long adr, // Blank Check - unsigned long sz, - unsigned char pat); -extern int EraseChip (void); // Erase complete Device -extern int EraseSector (unsigned long adr); // Erase Sector Function -extern int ProgramPage (unsigned long adr, // Program Page Function - unsigned long sz, - unsigned char *buf); -extern unsigned long Verify (unsigned long adr, // Verify Function - unsigned long sz, - unsigned char *buf); diff --git a/external/CMSIS_5/Device/_Template_Flash/FlashPrg.c b/external/CMSIS_5/Device/_Template_Flash/FlashPrg.c deleted file mode 100644 index c2d7412..0000000 --- a/external/CMSIS_5/Device/_Template_Flash/FlashPrg.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************//** - * @file FlashPrg.c - * @brief Flash Programming Functions adapted for New Device Flash - * @version V1.0.0 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2010-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "FlashOS.h" // FlashOS Structures - -/* - Mandatory Flash Programming Functions (Called by FlashOS): - int Init (unsigned long adr, // Initialize Flash - unsigned long clk, - unsigned long fnc); - int UnInit (unsigned long fnc); // De-initialize Flash - int EraseSector (unsigned long adr); // Erase Sector Function - int ProgramPage (unsigned long adr, // Program Page Function - unsigned long sz, - unsigned char *buf); - - Optional Flash Programming Functions (Called by FlashOS): - int BlankCheck (unsigned long adr, // Blank Check - unsigned long sz, - unsigned char pat); - int EraseChip (void); // Erase complete Device - unsigned long Verify (unsigned long adr, // Verify Function - unsigned long sz, - unsigned char *buf); - - - BlanckCheck is necessary if Flash space is not mapped into CPU memory space - - Verify is necessary if Flash space is not mapped into CPU memory space - - if EraseChip is not provided than EraseSector for all sectors is called -*/ - - -/* - * Initialize Flash Programming Functions - * Parameter: adr: Device Base Address - * clk: Clock Frequency (Hz) - * fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify) - * Return Value: 0 - OK, 1 - Failed - */ - -int Init (unsigned long adr, unsigned long clk, unsigned long fnc) { - - /* Add your Code */ - return (0); // Finished without Errors -} - - -/* - * De-Initialize Flash Programming Functions - * Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify) - * Return Value: 0 - OK, 1 - Failed - */ - -int UnInit (unsigned long fnc) { - - /* Add your Code */ - return (0); // Finished without Errors -} - - -/* - * Erase complete Flash Memory - * Return Value: 0 - OK, 1 - Failed - */ - -int EraseChip (void) { - - /* Add your Code */ - return (0); // Finished without Errors -} - - -/* - * Erase Sector in Flash Memory - * Parameter: adr: Sector Address - * Return Value: 0 - OK, 1 - Failed - */ - -int EraseSector (unsigned long adr) { - - /* Add your Code */ - return (0); // Finished without Errors -} - - -/* - * Program Page in Flash Memory - * Parameter: adr: Page Start Address - * sz: Page Size - * buf: Page Data - * Return Value: 0 - OK, 1 - Failed - */ - -int ProgramPage (unsigned long adr, unsigned long sz, unsigned char *buf) { - - /* Add your Code */ - return (0); // Finished without Errors -} diff --git a/external/CMSIS_5/Device/_Template_Flash/NewDevice.uvguix b/external/CMSIS_5/Device/_Template_Flash/NewDevice.uvguix deleted file mode 100644 index b36f973..0000000 --- a/external/CMSIS_5/Device/_Template_Flash/NewDevice.uvguix +++ /dev/null @@ -1,1848 +0,0 @@ - - - - -6.1 - -
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### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - Cortex-M - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 7 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - - - - - - - - - - - BIN\UL2CM3.DLL - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - - - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - Documentation - 1 - 0 - 0 - 0 - - 1 - 1 - 5 - 0 - 0 - 0 - .\Abstract.txt - Abstract.txt - 0 - 0 - - - - - Program Functions - 1 - 0 - 0 - 0 - - 2 - 2 - 1 - 0 - 0 - 0 - .\FlashPrg.c - FlashPrg.c - 0 - 0 - - - - - Device Description - 1 - 0 - 0 - 0 - - 3 - 3 - 1 - 0 - 0 - 0 - .\FlashDev.c - FlashDev.c - 0 - 0 - - - - diff --git a/external/CMSIS_5/Device/_Template_Flash/NewDevice.uvprojx b/external/CMSIS_5/Device/_Template_Flash/NewDevice.uvprojx deleted file mode 100644 index dcdd6c4..0000000 --- a/external/CMSIS_5/Device/_Template_Flash/NewDevice.uvprojx +++ /dev/null @@ -1,420 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - Cortex-M - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - ARMCM0 - ARM - ARM.CMSIS.5.2.1-dev1 - http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - 0 - $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h - - - - - - - - - - $$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - NewDevice - 1 - 0 - 0 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - cmd.exe /C copy "Objects\%L" ".\@L.FLM" - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - - TARMCM1.DLL - -pCM0 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 2 - 0 - 0 - 1 - 0 - 3 - 3 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - - - - .\Target.lin - - - --diag_suppress L6305 - - - - - - - - Documentation - - - Abstract.txt - 5 - .\Abstract.txt - - - - - Program Functions - - - FlashPrg.c - 1 - .\FlashPrg.c - - - - - Device Description - - - FlashDev.c - 1 - .\FlashDev.c - - - - - - - - - - - - - - diff --git a/external/CMSIS_5/Device/_Template_Flash/Target.lin b/external/CMSIS_5/Device/_Template_Flash/Target.lin deleted file mode 100644 index 3190469..0000000 --- a/external/CMSIS_5/Device/_Template_Flash/Target.lin +++ /dev/null @@ -1,22 +0,0 @@ -; Linker Control File (scatter-loading) -; - -PRG 0 PI ; Programming Functions -{ - PrgCode +0 ; Code - { - * (+RO) - } - PrgData +0 ; Data - { - * (+RW,+ZI) - } -} - -DSCR +0 ; Device Description -{ - DevDscr +0 - { - FlashDev.o - } -} diff --git a/external/CMSIS_5/Device/_Template_Vendor/ReadMe.txt b/external/CMSIS_5/Device/_Template_Vendor/ReadMe.txt deleted file mode 100644 index 50f03f4..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/ReadMe.txt +++ /dev/null @@ -1,71 +0,0 @@ -/***************************************************************************** - * @file ReadMe.txt - * @brief Explanation how to use the Device folder and template files - * @version V3.0.4 - * @date 20. January 2021 - *****************************************************************************/ - -Following directory structure and template files are given: - - - - | - +-- - | - +-- Include - | +-- Template only Armv8-M/v8.1-M TrustZone - | | +- partition_.h Secure/Non-Secure configuration - | +- .h header file - | +- system_.h system include file - +-- Source - | - +- startup_.c C startup file file - +- system_.c system source file - | - +-- ARM Arm ARMCLang toolchain - | +- startup_.s ASM startup file for ARMCC (deprecated) - | +- startup_.S ASM startup file for ARMCLang (deprecated) - | +- .sct Scatter file - | - +-- GCC Arm GNU toolchain - | +- startup_.S ASM startup file (deprecated) - | +- .ld Linker description file - | - +-- IAR IAR toolchain - +- startup_.s ASM startup file - - -Copy the complete folder including files and replace: - - folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP. - - folder name 'Device' with your specific device name e.g.: LPC17xx. - - in the filenames 'Device' with your specific device name e.g.: LPC17xx. - - -The template files contain comments starting with 'ToDo: ' -There it is described what you need to do. - - -The template files contain following placeholder: - - - should be replaced with your specific device name. - e.g.: LPC17xx - - - should be replaced with a specific device interrupt name. - e.g.: TIM1 for Timer#1 interrupt. - - - should be replaced with a dedicated device family - abbreviation (e.g.: LPC for LPC17xx device family) - - Cortex-M# - Cortex-M# can be replaced with the specific Cortex-M number - e.g.: Cortex-M3 - - - -Note: - Template files (i.e. startup_Device.s, system_Device.c) are application - specific and therefore expected to be copied into the application project - folder prior to use! - \ No newline at end of file diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Device.h b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Device.h deleted file mode 100644 index 9188d13..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Device.h +++ /dev/null @@ -1,230 +0,0 @@ -/*************************************************************************//** - * @file .h - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device - * @version V1.0.0 - * @date 20. January 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _H /* ToDo: Replace '' with your device name */ -#define _H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ========================================================================= */ -/* ============ Interrupt Number Definition ============ */ -/* ========================================================================= */ - -typedef enum IRQn -{ -/* ================ Cortex-M Core Exception Numbers ================ */ - -/* ToDo: Add Cortex exception numbers according the used Cortex-Core */ - Reset_IRQn = -15, /* 1 Reset Vector - invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt - cannot be stopped or preempted */ - HardFault_IRQn = -13, /* 3 Hard Fault - all classes of Fault */ - MemoryManagement_IRQn = -12, /* 4 Memory Management - MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /* 5 Bus Fault - Pre-Fetch-, Memory Access, other address/memory Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault - i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pendable request for system service */ - SysTick_IRQn = -1, /* 15 System Tick Timer */ - -/* ================ Interrupt Numbers ================ */ -/* ToDo: Add here your device specific interrupt numbers - according the interrupt handlers defined in startup_Device.s - eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ - _IRQn = 0, /* first Device Interrupt*/ - ... - _IRQn = n /* last Device Interrupt */ -} IRQn_Type; - - -/* ========================================================================= */ -/* ============ Processor and Core Peripheral Section ============ */ -/* ========================================================================= */ - -/* ================ Start of section using anonymous unions ================ */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* ================ Configuration of Core Peripherals ================ */ -/* ToDo: Set the defines according your Device */ -/* ToDo: Define the correct core revision - valid CMSIS core revision macro names are: - __CM0_REV, __CM0PLUS_REV, __CM1_REV, __CM3_REV, __CM4_REV, __CM7_REV - __CM23_REV, __CM33_REV, __CM35P_REV, __CM55_REV - __SC000_REV, __SC300_REV */ -#define __CM#_REV 0x0201U /* Core Revision r2p1 */ -/* ToDo: define the correct core features for the */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __VTOR_PRESENT 1U /* Set to 1 if VTOR is present */ -#define __MPU_PRESENT 1U /* Set to 1 if MPU is present */ -#define __FPU_PRESENT 0U /* Set to 1 if FPU is present */ -#define __FPU_DP 0U /* Set to 1 if FPU is double precision FPU (default is single precision FPU) */ -#define __DSP_PRESENT 1U /* Set to 1 if DSP extension are present */ -#define __SAUREGION_PRESENT 1U /* Set to 1 if SAU regions are present */ -#define __PMU_PRESENT 1U /* Set to 1 if PMU is present */ -#define __PMU_NUM_EVENTCNT 8U /* Set number of PMU Event Counters */ -#define __ICACHE_PRESENT 0U /* Set to 1 if I-Cache is present */ -#define __DCACHE_PRESENT 0U /* Set to 1 if D-Cache is present */ -#define __DTCM_PRESENT 0U /* Set to 1 if DTCM is present */ - - -/* ToDo: Include the CMSIS core header file according your device. - valid CMSIS core header files are: - core_cm0.h, core_cm0plus.h, core_cm1.h, core_cm3.h, core_cm4.h, core_cm7.h - core_cm23.h, core_cm33.h, core_cm35p.h, core_cm55.h - core_sc000.h, core_sc300.h */ -#include /* Processor and core peripherals */ -/* ToDo: Include your system_.h file - replace '' with your device name */ -#include "system_.h" /* System Header */ - - - -/* ========================================================================= */ -/* ============ Device Specific Peripheral Section ============ */ -/* ========================================================================= */ - - -/* ToDo: Add here your device specific peripheral access structure typedefs - including bit definitions for Pos/Msk macros - following is an example for a timer */ - -/* ========================================================================= */ -/* ============ TMR ============ */ -/* ========================================================================= */ - -typedef struct -{ - __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Load Register */ - __IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Value Register */ - __IOM uint32_t CONTROL; /* Offset: 0x008 (R/W) Control Register */ - __OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Clear Interrupt Register */ - __IM uint32_t RIS; /* Offset: 0x010 (R/ ) Raw Interrupt Status Register */ - __IM uint32_t MIS; /* Offset: 0x014 (R/ ) Interrupt Status Register */ - __IOM uint32_t BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */ -} _TMR_TypeDef; - -/* _TMR LOAD Register Definitions */ -#define _TMR_LOAD_Pos 0 -#define _TMR_LOAD_Msk (0xFFFFFFFFUL /*<< _TMR_LOAD_Pos*/) - -/* _TMR VALUE Register Definitions */ -#define _TMR_VALUE_Pos 0 -#define _TMR_VALUE_Msk (0xFFFFFFFFUL /*<< _TMR_VALUE_Pos*/) - -/* _TMR CONTROL Register Definitions */ -#define _TMR_CONTROL_SIZE_Pos 1 -#define _TMR_CONTROL_SIZE_Msk (1UL << _TMR_CONTROL_SIZE_Pos) - -#define _TMR_CONTROL_ONESHOT_Pos 0 -#define _TMR_CONTROL_ONESHOT_Msk (1UL /*<< _TMR_CONTROL_ONESHOT_Pos*/) - - - -/* ================ End of section using anonymous unions ================ */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* ========================================================================= */ -/* ============ Device Specific Peripheral Address Map ============ */ -/* ========================================================================= */ - - -/* ToDo: Add here your device peripherals base addresses - following is an example for timer */ - -/* Peripheral and SRAM base address */ -#define _FLASH_BASE (0x00000000UL) /* (FLASH ) Base Address */ -#define _SRAM_BASE (0x20000000UL) /* (SRAM ) Base Address */ -#define _PERIPH_BASE (0x40000000UL) /* (Peripheral) Base Address */ - -/* Peripheral memory map */ -#define TIM0_BASE (_PERIPH_BASE) /* (Timer0 ) Base Address */ -#define TIM1_BASE (_PERIPH_BASE + 0x0800) /* (Timer1 ) Base Address */ -#define TIM2_BASE (_PERIPH_BASE + 0x1000) /* (Timer2 ) Base Address */ - - -/* ========================================================================= */ -/* ============ Peripheral declaration ============ */ -/* ========================================================================= */ - - -/* ToDo: Add here your device peripherals pointer definitions - following is an example for timer */ - -#define _TIM0 ((_TMR_TypeDef *) TIM0_BASE) -#define _TIM1 ((_TMR_TypeDef *) TIM0_BASE) -#define _TIM2 ((_TMR_TypeDef *) TIM0_BASE) - -#ifdef __cplusplus -} -#endif - -#endif /* _H */ diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Template/partition_Device.h b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Template/partition_Device.h deleted file mode 100644 index c020e05..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Template/partition_Device.h +++ /dev/null @@ -1,1262 +0,0 @@ -/*************************************************************************//** - * @file partition_.h - * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for - * Device - * @version V1.0.0 - * @date 20. January 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PARTITION__H /* ToDo: Replace '' with your device name */ -#define PARTITION__H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 1 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x203FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x40040000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// Interrupt 0 <0=> Secure state <1=> Non-Secure state -// Interrupt 1 <0=> Secure state <1=> Non-Secure state -// Interrupt 2 <0=> Secure state <1=> Non-Secure state -// Interrupt 3 <0=> Secure state <1=> Non-Secure state -// Interrupt 4 <0=> Secure state <1=> Non-Secure state -// Interrupt 5 <0=> Secure state <1=> Non-Secure state -// Interrupt 6 <0=> Secure state <1=> Non-Secure state -// Interrupt 7 <0=> Secure state <1=> Non-Secure state -// Interrupt 8 <0=> Secure state <1=> Non-Secure state -// Interrupt 9 <0=> Secure state <1=> Non-Secure state -// Interrupt 10 <0=> Secure state <1=> Non-Secure state -// Interrupt 11 <0=> Secure state <1=> Non-Secure state -// Interrupt 12 <0=> Secure state <1=> Non-Secure state -// Interrupt 13 <0=> Secure state <1=> Non-Secure state -// Interrupt 14 <0=> Secure state <1=> Non-Secure state -// Interrupt 15 <0=> Secure state <1=> Non-Secure state -// Interrupt 16 <0=> Secure state <1=> Non-Secure state -// Interrupt 17 <0=> Secure state <1=> Non-Secure state -// Interrupt 18 <0=> Secure state <1=> Non-Secure state -// Interrupt 19 <0=> Secure state <1=> Non-Secure state -// Interrupt 20 <0=> Secure state <1=> Non-Secure state -// Interrupt 21 <0=> Secure state <1=> Non-Secure state -// Interrupt 22 <0=> Secure state <1=> Non-Secure state -// Interrupt 23 <0=> Secure state <1=> Non-Secure state -// Interrupt 24 <0=> Secure state <1=> Non-Secure state -// Interrupt 25 <0=> Secure state <1=> Non-Secure state -// Interrupt 26 <0=> Secure state <1=> Non-Secure state -// Interrupt 27 <0=> Secure state <1=> Non-Secure state -// Interrupt 28 <0=> Secure state <1=> Non-Secure state -// Interrupt 29 <0=> Secure state <1=> Non-Secure state -// Interrupt 30 <0=> Secure state <1=> Non-Secure state -// Interrupt 31 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// Interrupt 32 <0=> Secure state <1=> Non-Secure state -// Interrupt 33 <0=> Secure state <1=> Non-Secure state -// Interrupt 34 <0=> Secure state <1=> Non-Secure state -// Interrupt 35 <0=> Secure state <1=> Non-Secure state -// Interrupt 36 <0=> Secure state <1=> Non-Secure state -// Interrupt 37 <0=> Secure state <1=> Non-Secure state -// Interrupt 38 <0=> Secure state <1=> Non-Secure state -// Interrupt 39 <0=> Secure state <1=> Non-Secure state -// Interrupt 40 <0=> Secure state <1=> Non-Secure state -// Interrupt 41 <0=> Secure state <1=> Non-Secure state -// Interrupt 42 <0=> Secure state <1=> Non-Secure state -// Interrupt 43 <0=> Secure state <1=> Non-Secure state -// Interrupt 44 <0=> Secure state <1=> Non-Secure state -// Interrupt 45 <0=> Secure state <1=> Non-Secure state -// Interrupt 46 <0=> Secure state <1=> Non-Secure state -// Interrupt 47 <0=> Secure state <1=> Non-Secure state -// Interrupt 48 <0=> Secure state <1=> Non-Secure state -// Interrupt 49 <0=> Secure state <1=> Non-Secure state -// Interrupt 50 <0=> Secure state <1=> Non-Secure state -// Interrupt 51 <0=> Secure state <1=> Non-Secure state -// Interrupt 52 <0=> Secure state <1=> Non-Secure state -// Interrupt 53 <0=> Secure state <1=> Non-Secure state -// Interrupt 54 <0=> Secure state <1=> Non-Secure state -// Interrupt 55 <0=> Secure state <1=> Non-Secure state -// Interrupt 56 <0=> Secure state <1=> Non-Secure state -// Interrupt 57 <0=> Secure state <1=> Non-Secure state -// Interrupt 58 <0=> Secure state <1=> Non-Secure state -// Interrupt 59 <0=> Secure state <1=> Non-Secure state -// Interrupt 60 <0=> Secure state <1=> Non-Secure state -// Interrupt 61 <0=> Secure state <1=> Non-Secure state -// Interrupt 62 <0=> Secure state <1=> Non-Secure state -// Interrupt 63 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION__H */ diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h deleted file mode 100644 index e28cc77..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************//** - * @file system_.h - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device - * @version V1.0.1 - * @date 11. July 2022 - *****************************************************************************/ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM__H /* ToDo: replace '' with your device name */ -#define SYSTEM__H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM__H */ diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac5.sct b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac5.sct deleted file mode 100644 index e3ea4fc..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac5.sct +++ /dev/null @@ -1,79 +0,0 @@ -#! armcc -E -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac6.sct b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac6.sct deleted file mode 100644 index 0227d5b..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac6.sct +++ /dev/null @@ -1,119 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu= -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu= -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5.s b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5.s deleted file mode 100644 index 562d500..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5.s +++ /dev/null @@ -1,137 +0,0 @@ -;/*************************************************************************//** -; * @file startup_.s -; * @brief CMSIS-Core(M) Device Startup File for -; * Device (using Arm Compiler 5 with scatter file) -; * @version V1.0.0 -; * @date 20. January 2021 -; ****************************************************************************/ -;/* -; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -; ToDo: Add Cortex exception vectors according the used Cortex-Core -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - -; ToDo: Add your device specific interrupt vectors - ; Interrupts - DCD _Handler ; first Device Interrupt - ... - DCD _Handler ; last Device Interrupt - -; ToDo: calculate the empty space according the used Cortex-Core - SPACE (x * 4) ; Interrupts x .. 224 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; ToDo: Add Cortex exception handler according the used Cortex-Core -; Default exception/interrupt handler - Set_Default_Handler NMI_Handler -; Set_Default_Handler HardFault_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - -; ToDo: Add your device specific interrupt handler - Set_Default_Handler _Handler - ... - Set_Default_Handler _Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5_noSct.s b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5_noSct.s deleted file mode 100644 index 897562a..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5_noSct.s +++ /dev/null @@ -1,164 +0,0 @@ -;/*************************************************************************//** -; * @file startup_.s -; * @brief CMSIS-Core(M) Device Startup File for -; * Device (using Arm Compiler 5 without scatter file) -; * @version V1.0.0 -; * @date 20. January 2021 -; ****************************************************************************/ -;/* -; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -__stack_limit -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000C00 - - IF Heap_Size != 0 ; Heap is provided - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - ENDIF - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -; ToDo: Add Cortex exception vectors according the used Cortex-Core -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; -14 NMI Handler - DCD HardFault_Handler ; -13 Hard Fault Handler - DCD MemManage_Handler ; -12 MPU Fault Handler - DCD BusFault_Handler ; -11 Bus Fault Handler - DCD UsageFault_Handler ; -10 Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; -5 SVCall Handler - DCD DebugMon_Handler ; -4 Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; -2 PendSV Handler - DCD SysTick_Handler ; -1 SysTick Handler - -; ToDo: Add your device specific interrupt vectors - ; Interrupts - DCD _Handler ; first Device Interrupt - ... - DCD _Handler ; last Device Interrupt - -; ToDo: calculate the empty space according the used Cortex-Core - SPACE (x * 4) ; Interrupts x .. 224 are left out -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; The default macro is not used for HardFault_Handler -; because this results in a poor debug illusion. -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -; Macro to define default exception/interrupt handlers. -; Default handler are weak symbols with an endless loop. -; They can be overwritten by real handlers. - MACRO - Set_Default_Handler $Handler_Name -$Handler_Name PROC - EXPORT $Handler_Name [WEAK] - B . - ENDP - MEND - - -; ToDo: Add Cortex exception handler according the used Cortex-Core -; Default exception/interrupt handler - Set_Default_Handler NMI_Handler -; Set_Default_Handler HardFault_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - -; ToDo: Add your device specific interrupt handler - Set_Default_Handler _Handler - ... - Set_Default_Handler _Handler - - ALIGN - - -; User setup Stack & Heap - - IF :LNOT::DEF:__MICROLIB - IMPORT __use_two_region_memory - ENDIF - - EXPORT __stack_limit - EXPORT __initial_sp - IF Heap_Size != 0 ; Heap is provided - EXPORT __heap_base - EXPORT __heap_limit - ENDIF - - END diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac6.S b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac6.S deleted file mode 100644 index 160d1b3..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac6.S +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************//** - * @file startup_.S - * @brief CMSIS-Core(M) Device Startup File for - * Device (using Arm Compiler 6 with scatter file) - * @version V1.0.0 - * @date 20. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified -/* ToDo: Set .arch to the architecture according the used Cortex-Core */ - .arch armv8-m.main - - #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit - #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base - #endif - - .section RESET - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -/* ToDo: Add Cortex exception vectors according the used Cortex-Core */ -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - -/* ToDo: Add your device specific interrupt vectors */ - /* Interrupts */ - .long _Handler /* first Device Interrupt */ - ... - .long _Handler /* last Device Interrupt */ - -/* ToDo: calculate the empty space according the used Cortex-Core */ - .space (x * 4) /* Interrupts x .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - bl __main - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* ToDo: Add Cortex exception handler according the used Cortex-Core */ -/* Default exception/interrupt handler */ - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - -/* ToDo: Add your device specific interrupt handler */ - Set_Default_Handler _Handler - ... - Set_Default_Handler _Handler - - .end diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_arm.ld b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_arm.ld deleted file mode 100644 index 4c5b690..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_arm.ld +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 20. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00040000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S deleted file mode 100644 index f27699e..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S +++ /dev/null @@ -1,194 +0,0 @@ -/**************************************************************************//** - * @file startup_.S - * @brief CMSIS-Core(M) Device Startup File for - * Device - * @version V1.0.0 - * @date 20. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified -/* ToDo: Set .arch to the architecture according the used Cortex-Core */ - .arch armv8-m.main - - #define __INITIAL_SP __StackTop - #define __STACK_LIMIT __StackLimit - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACK_SEAL __StackSeal - #endif - - .section .vectors - .align 2 - .globl __Vectors - .globl __Vectors_End - .globl __Vectors_Size -/* ToDo: Add Cortex exception vectors according the used Cortex-Core */ -__Vectors: - .long __INITIAL_SP /* Initial Stack Pointer */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* -14 NMI Handler */ - .long HardFault_Handler /* -13 Hard Fault Handler */ - .long MemManage_Handler /* -12 MPU Fault Handler */ - .long BusFault_Handler /* -11 Bus Fault Handler */ - .long UsageFault_Handler /* -10 Usage Fault Handler */ - .long SecureFault_Handler /* -9 Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* -5 SVCall Handler */ - .long DebugMon_Handler /* -4 Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* -2 PendSV Handler */ - .long SysTick_Handler /* -1 SysTick Handler */ - -/* ToDo: Add your device specific interrupt vectors */ - /* Interrupts */ - .long _Handler /* first Device Interrupt */ - ... - .long _Handler /* last Device Interrupt */ - -/* ToDo: calculate the empty space according the used Cortex-Core */ - .space (x * 4) /* Interrupts x .. 480 are left out */ -__Vectors_End: - .equ __Vectors_Size, __Vectors_End - __Vectors - .size __Vectors, . - __Vectors - - - .thumb - .section .text - .align 2 - - .thumb_func - .type Reset_Handler, %function - .globl Reset_Handler - .fnstart -Reset_Handler: - ldr r0, =__INITIAL_SP - msr psp, r0 - - ldr r0, =__STACK_LIMIT - msr msplim, r0 - msr psplim, r0 - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - ldr r0, =__STACK_SEAL - ldr r1, =0xFEF5EDA5U - strd r1,r1,[r0,#0] - #endif - - bl SystemInit - - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] /* source address */ - ldr r2, [r4, #4] /* destination address */ - ldr r3, [r4, #8] /* word count */ - lsl r3, r3, #2 /* byte count */ - -.L_loop0_0: - subs r3, #4 /* decrement byte count */ - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 -.L_loop0_done: - - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] /* destination address */ - ldr r2, [r3, #4] /* word count */ - lsl r2, r2, #2 /* byte count */ - movs r0, 0 - -.L_loop2_0: - subs r2, #4 /* decrement byte count */ - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - bl _start - - .fnend - .size Reset_Handler, . - Reset_Handler - - -/* The default macro is not used for HardFault_Handler - * because this results in a poor debug illusion. - */ - .thumb_func - .type HardFault_Handler, %function - .weak HardFault_Handler - .fnstart -HardFault_Handler: - b . - .fnend - .size HardFault_Handler, . - HardFault_Handler - - .thumb_func - .type Default_Handler, %function - .weak Default_Handler - .fnstart -Default_Handler: - b . - .fnend - .size Default_Handler, . - Default_Handler - -/* Macro to define default exception/interrupt handlers. - * Default handler are weak symbols with an endless loop. - * They can be overwritten by real handlers. - */ - .macro Set_Default_Handler Handler_Name - .weak \Handler_Name - .set \Handler_Name, Default_Handler - .endm - - -/* ToDo: Add Cortex exception handler according the used Cortex-Core */ -/* Default exception/interrupt handler */ - Set_Default_Handler NMI_Handler - Set_Default_Handler MemManage_Handler - Set_Default_Handler BusFault_Handler - Set_Default_Handler UsageFault_Handler - Set_Default_Handler SecureFault_Handler - Set_Default_Handler SVC_Handler - Set_Default_Handler DebugMon_Handler - Set_Default_Handler PendSV_Handler - Set_Default_Handler SysTick_Handler - -/* ToDo: Add your device specific interrupt handler */ - Set_Default_Handler _Handler - ... - Set_Default_Handler _Handler - - .end diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/startup_Device.c b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/startup_Device.c deleted file mode 100644 index 5fc04b6..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/startup_Device.c +++ /dev/null @@ -1,151 +0,0 @@ -/****************************************************************************** - * @file startup_.c - * @brief CMSIS-Core(M) Device Startup File for - * Device - * @version V1.0.0 - * @date 20. January 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include ".h" - -/*--------------------------------------------------------------------------- - External References - *---------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*--------------------------------------------------------------------------- - Internal References - *---------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); -__NO_RETURN void Default_Handler(void); - -/* ToDo: Add Cortex exception handler according the used Cortex-Core */ -/*--------------------------------------------------------------------------- - Exception / Interrupt Handler - *---------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* ToDo: Add your device specific interrupt handler */ -void _Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -... -void _Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -/* ToDo: Add Cortex exception vectors according the used Cortex-Core */ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; - const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - -/* ToDo: Add your device specific interrupt vectors */ - /* Interrupts */ - _Handler, /* first Device Interrupt */ - ... - _Handler /* last Device Interrupt */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*--------------------------------------------------------------------------- - Reset Handler called on controller reset - *---------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -/* ToDo: Initialize stack limit register for Armv8-M Main Extension based processors*/ - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -/* ToDo: Add stack sealing for Armv8-M based processors */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*--------------------------------------------------------------------------- - Hard Fault Handler - *---------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*--------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *---------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c deleted file mode 100644 index f8695e8..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c +++ /dev/null @@ -1,100 +0,0 @@ -/*************************************************************************//** - * @file system_.c - * @brief CMSIS-Core(M) Device Peripheral Access Layer Source File for - * Device - * @version V1.0.0 - * @date 20. January 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include ".h" - -/* ToDo: Include partition header file if TZ is used */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_.h" -#endif - - -/*--------------------------------------------------------------------------- - Define clocks - *---------------------------------------------------------------------------*/ -/* ToDo: Add here your necessary defines for device initialization - following is an example for different system frequencies */ -#define XTAL (12000000U) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5 * XTAL) - - -/*--------------------------------------------------------------------------- - Exception / Interrupt Vector table - *---------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - - -/*--------------------------------------------------------------------------- - System Core Clock Variable - *---------------------------------------------------------------------------*/ -/* ToDo: Initialize SystemCoreClock with the system core clock frequency value - achieved after system intitialization. - This means system core clock frequency after call to SystemInit() */ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/ - - -/*--------------------------------------------------------------------------- - System Core Clock function - *---------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ -/* ToDo: Add code to calculate the system frequency based upon the current - register settings. - This function can be used to retrieve the system core clock frequeny - after user changed register sittings. */ - SystemCoreClock = SYSTEM_CLOCK; -} - - -/*--------------------------------------------------------------------------- - System initialization function - *---------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* ToDo: Add code to initialize the system. - Do not use global variables because this function is called before - reaching pre-main. RW section maybe overwritten afterwards. */ - -/* ToDo: Initialize VTOR if available */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - -/* ToDo: Enable co-processor if it is used */ -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -/* ToDo: Initialize SAU if TZ is used */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h deleted file mode 100644 index b6a8dde..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h +++ /dev/null @@ -1,248 +0,0 @@ -/**************************************************************************//** - * @file .h - * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File - * @version V1.01 - * @date 23. June 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _H /* ToDo: replace '' with your device name */ -#define _H - -#ifdef __cplusplus -extern "C" { -#endif - -/* ToDo: replace '' with vendor name; add your doxyGen comment */ -/** @addtogroup - * @{ - */ - - -/* ToDo: replace '' with device name; add your doxyGen comment */ -/** @addtogroup - * @{ - */ - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum IRQn -{ -/* ======================================= ARM Cortex-A Specific Interrupt Numbers ========================================= */ - - /* Software Generated Interrupts */ - SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ - SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ - SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ - SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ - SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ - SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ - SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ - SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ - SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ - SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ - SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ - SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ - SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ - SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ - SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ - SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ - - /* Private Peripheral Interrupts */ - VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ - HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ - VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ - Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ - SecurePhyTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ - NonSecurePhyTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ - Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - - /* Shared Peripheral Interrupts */ - /* ToDo: add here your device specific external interrupt numbers */ - _IRQn = 0, /*!< Device Interrupt */ - -} IRQn_Type; - - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* =========================== Configuration of the Arm Cortex-A Processor and Core Peripherals ============================ */ -/* ToDo: set the defines according your Device */ -/* ToDo: define the correct core revision - 5U if your device is a CORTEX-A5 device - 7U if your device is a CORTEX-A7 device - 9U if your device is a CORTEX-A9 device */ -#define __CORTEX_A #U /*!< Cortex-A# Core */ -#define __CA_REV 0x0000U /*!< Core revision r0p0 */ -/* ToDo: define the correct core features for the */ -#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ -#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ -#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ -#define __L2C_PRESENT 1U /*!< Set to 1 if L2C is present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -/* ToDo: include the correct core_ca#.h file - core_ca5.h if your device is a CORTEX-A5 device - core_ca7.h if your device is a CORTEX-A7 device - core_ca9.h if your device is a CORTEX-A9 device */ -#include /*!< Arm Cortex-A# processor and core peripherals */ -/* ToDo: include your system_.h file - replace '' with your device name */ -#include "system_.h" /*!< System */ - - -/* ======================================== Start of section using anonymous unions ======================================== */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* ToDo: add here your device specific peripheral access structure typedefs - following is an example for a timer */ - -/* =========================================================================================================================== */ -/* ================ TMR ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Timer (TMR) - */ - -typedef struct -{ /*!< (@ 0x40000000) TIM Structure */ - __IOM uint32_t TimerLoad; /*!< (@ 0x00000004) Timer Load */ - __IM uint32_t TimerValue; /*!< (@ 0x00000008) Timer Counter Current Value */ - __IOM uint32_t TimerControl; /*!< (@ 0x0000000C) Timer Control */ - __OM uint32_t TimerIntClr; /*!< (@ 0x00000010) Timer Interrupt Clear */ - __IM uint32_t TimerRIS; /*!< (@ 0x00000014) Timer Raw Interrupt Status */ - __IM uint32_t TimerMIS; /*!< (@ 0x00000018) Timer Masked Interrupt Status */ - __IM uint32_t RESERVED[1]; - __IOM uint32_t TimerBGLoad; /*!< (@ 0x00000020) Background Load Register */ -} _TMR_TypeDef; - -/*@}*/ /* end of group _Peripherals */ - - -/* ========================================= End of section using anonymous unions ========================================= */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/* ToDo: add here your device peripherals base addresses - following is an example for timer */ -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -/* Peripheral and SRAM base address */ -#define _FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ -#define _SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ -#define _PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ - -/* Peripheral memory map */ -#define TIM0_BASE (_PERIPH_BASE) /*!< (Timer0 ) Base Address */ -#define TIM1_BASE (_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */ -#define TIM2_BASE (_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */ - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/* ToDo: add here your device peripherals pointer definitions - following is an example for timer */ -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define _TIM0 ((_TMR_TypeDef *) TIM0_BASE) -#define _TIM1 ((_TMR_TypeDef *) TIM0_BASE) -#define _TIM2 ((_TMR_TypeDef *) TIM0_BASE) - - -/** @} */ /* End of group */ - -/** @} */ /* End of group */ - -#ifdef __cplusplus -} -#endif - -#endif /* _H */ diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h deleted file mode 100644 index 4a116ab..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************//** - * @file mem_.h - * @brief CMSIS Cortex-A Memory base and size definitions (used in scatter file) - * @version V1.00 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MEM__H /* ToDo: replace '' with your device name */ -#define MEM__H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// ROM Base Address <0x0-0xFFFFFFFF:8> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x80000000 -#define __ROM_SIZE 0x00200000 - -/*--------------------- RAM Configuration ----------------------------------- -// RAM Configuration -// RAM Base Address <0x0-0xFFFFFFFF:8> -// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8> -// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Exceptional Modes -// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -// -// - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x80200000 -#define __RAM_SIZE 0x00200000 - -#define __RW_DATA_SIZE 0x00100000 -#define __ZI_DATA_SIZE 0x000F0000 - -#define __STACK_SIZE 0x00001000 -#define __HEAP_SIZE 0x00008000 - -#define __UND_STACK_SIZE 0x00000100 -#define __ABT_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// TTB Base Address <0x0-0xFFFFFFFF:8> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x80500000 -#define __TTB_SIZE 0x00004000 - -#endif /* MEM__H */ diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h deleted file mode 100644 index fb19dcd..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************//** - * @file system_.h - * @brief CMSIS Cortex-A Device Peripheral Access Layer - * @version V5.00 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM__H /* ToDo: replace '' with your device name */ -#define SYSTEM__H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM__H */ diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/Device.sct b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/Device.sct deleted file mode 100644 index e19bf70..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/Device.sct +++ /dev/null @@ -1,75 +0,0 @@ -#! armcc -E -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for Cortex-A - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -#include "mem_.h" - -SDRAM __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - * (+RO-DATA) ; Application RO data (.constdata) - } - - RW_DATA __RAM_BASE __RW_DATA_SIZE - { * (+RW) } ; Application RW data (.data) - - ZI_DATA (__RAM_BASE+ - __RW_DATA_SIZE) __ZI_DATA_SIZE - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP (__RAM_BASE - +__RW_DATA_SIZE - +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up - { } - - ARM_LIB_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE - -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - UND_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE - -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack - { } - - ABT_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE - -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack - { } - - SVC_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE - -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack - { } - - IRQ_STACK (__RAM_BASE - +__RAM_SIZE - -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack - { } - - FIQ_STACK (__RAM_BASE - +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack - { } - - TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU - { } -} diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c deleted file mode 100644 index d0e8384..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c +++ /dev/null @@ -1,145 +0,0 @@ -/****************************************************************************** - * @file startup_.c - * @brief CMSIS Cortex-A Device Startup - * @version V1.00 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include ".h" /* ToDo: replace '' with your device name */ - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((section("RESET"))); -void Reset_Handler (void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -__ASM void Vectors(void) { - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__ASM void Reset_Handler(void) { - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 // Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exceptional mode - IMPORT |Image$$FIQ_STACK$$ZI$$Limit| - IMPORT |Image$$IRQ_STACK$$ZI$$Limit| - IMPORT |Image$$SVC_STACK$$ZI$$Limit| - IMPORT |Image$$ABT_STACK$$ZI$$Limit| - IMPORT |Image$$UND_STACK$$ZI$$Limit| - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - CPS #0x11 - LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit| - CPS #0x12 - LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit| - CPS #0x13 - LDR SP, =|Image$$SVC_STACK$$ZI$$Limit| - CPS #0x17 - LDR SP, =|Image$$ABT_STACK$$ZI$$Limit| - CPS #0x1B - LDR SP, =|Image$$UND_STACK$$ZI$$Limit| - CPS #0x1F - LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - // Call SystemInit - IMPORT SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __main - IMPORT __main - BL __main -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c deleted file mode 100644 index 0987a12..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************//** - * @file system_Device.c - * @brief MMU Configuration - * Device - * @version V1.1.0 - * @date 23. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description - - ToDo: add in this file your device memory map description - following is an example of a Cortex-A9 Arm FVP device - - Memory Type -0xFFFFFFFF |--------------------------| ------------ - | FLAG SYNC | Device Memory -0xFFFFF000 |--------------------------| ------------ - | Fault | Fault -0xFFF00000 |--------------------------| ------------ - | | Normal - | | - | Daughterboard | - | memory | - | | -0x80505000 |--------------------------| ------------ - |TTB (L2 Sync Flags ) 4k | Normal -0x80504C00 |--------------------------| ------------ - |TTB (L2 Peripherals-B) 16k| Normal -0x80504800 |--------------------------| ------------ - |TTB (L2 Peripherals-A) 16k| Normal -0x80504400 |--------------------------| ------------ - |TTB (L2 Priv Periphs) 4k | Normal -0x80504000 |--------------------------| ------------ - | TTB (L1 Descriptors) | Normal -0x80500000 |--------------------------| ------------ - | Heap | Normal - |--------------------------| ------------ - | Stack | Normal -0x80400000 |--------------------------| ------------ - | ZI Data | Normal -0x80300000 |--------------------------| ------------ - | RW Data | Normal -0x80200000 |--------------------------| ------------ - | RO Data | Normal - |--------------------------| ------------ - | RO Code | USH Normal -0x80000000 |--------------------------| ------------ - | Daughterboard | Fault - | HSB AXI buses | -0x40000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x2C002000 |--------------------------| ------------ - | Private Address | Device Memory -0x2C000000 |--------------------------| ------------ - | Daughterboard | Fault - | test chips peripherals | -0x20000000 |--------------------------| ------------ - | Peripherals | Device Memory RW/RO - | | & Fault -0x00000000 |--------------------------| -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -// Note: You should use the Shareable attribute carefully. -// For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -// Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -// Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -// Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -// When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -// When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - -// Following MMU configuration is expected -// SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -// SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -// Domain 0 is always the Client domain -// Descriptors should place all memory in domain 0 - -#include ".h" /* ToDo: replace '' with your device name */ - -// L2 table pointers -//----------------------------------------------------- -#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space -#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization -#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 -#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 - -//--------------------- PERIPHERALS ------------------- -#define PERIPHERAL_A_FAULT (0x00000000 + 0x1C000000) -#define PERIPHERAL_B_FAULT (0x00100000 + 0x1C000000) - -//--------------------- SYNC FLAGS -------------------- -#define FLAG_SYNC 0xFFFFF000 -#define F_SYNC_BASE 0xFFF00000 //1M aligned - -//Import symbols from linker -extern uint32_t Image$$VECTORS$$Base; -extern uint32_t Image$$RW_DATA$$Base; -extern uint32_t Image$$ZI_DATA$$Base; -extern uint32_t Image$$TTB$$ZI$$Base; - -static uint32_t Sect_Normal; // outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; // outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; // as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; // as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; // device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; // as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; // generic -static uint32_t Page_L1_64k = 0x0; // generic -static uint32_t Page_4k_Device_RW; // shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; // shared device, not executable, rw, domain 0 - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; - - // Create 4GB of faulting entries - MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); - - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - // Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - // Create descriptors for peripherals - section_Device_ro(Sect_Device_RO, region); - section_Device_rw(Sect_Device_RW, region); - // Create descriptors for 64k pages - page64k_Device_rw(Page_L1_64k, Page_64k_Device_RW, region); - // Create descriptors for 4k pages - page4k_Device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - /* - * Define MMU flat-map regions and attributes - * - */ - // Define Image - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , 1U, Sect_Normal_Cod); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , 1U, Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base , 1U, Sect_Normal_RW); - - // All DRAM executable, RW, cacheable - applications may choose to divide memory into RO executable - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base , 2043U, Sect_Normal); - - //--------------------- PERIPHERALS ------------------- - MMU_TTSection (&Image$$TTB$$ZI$$Base, _FLASH_BASE0 , 64U, Sect_Device_RO); - MMU_TTSection (&Image$$TTB$$ZI$$Base, _FLASH_BASE1 , 64U, Sect_Device_RO); - MMU_TTSection (&Image$$TTB$$ZI$$Base, _SRAM_BASE , 64U, Sect_Device_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, _VRAM_BASE , 32U, Sect_Device_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, _ETHERNET_BASE , 16U, Sect_Device_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, _USB_BASE , 16U, Sect_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _DAP_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _SYSTEM_REG_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _SERIAL_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _AACI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _MMCI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _KMI0_BASE , 2U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _UART_BASE , 4U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _WDT_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (16 * 64k)=1MB faulting entries to cover peripheral range - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); - // Define peripheral range - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _TIMER_BASE , 2U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _DVI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _RTC_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _UART4_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - MMU_TTPage64k(&Image$$TTB$$ZI$$Base, _CLCD_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory - MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 256U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define private address space entry - MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 2U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - // Define L2CC entry - MMU_TTPage4k (&Image$$TTB$$ZI$$Base, _L2C_BASE , 1U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) - MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); - // Define synchronization space entry. - MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x1 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x01 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x0 (Inner WB WA) */ - __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c b/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c deleted file mode 100644 index 98a424c..0000000 --- a/external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c +++ /dev/null @@ -1,111 +0,0 @@ -/****************************************************************************** - * @file system_.c - * @brief CMSIS Cortex-A Device Peripheral Access Layer - * @version V1.00 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include ".h" /* ToDo: replace '' with your device name */ -#include "irq_ctrl.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -/* ToDo: add here your necessary defines for device initialization - following is an example for different system frequencies */ -#define XTAL (12000000U) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (5 * XTAL) - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -/* ToDo: initialize SystemCoreClock with the system core clock frequency value - achieved after system intitialization. - This means system core clock frequency after call to SystemInit() */ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/ - - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ - -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ -/* ToDo: add code to calculate the system frequency based upon the current - register settings. - This function can be used to retrieve the system core clock frequeny - after user changed register sittings. */ - SystemCoreClock = SYSTEM_CLOCK; -} - - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* ToDo: add code to initialize the system - Do not use global variables because this function is called before - reaching pre-main. RW section may be overwritten afterwards. */ - SystemCoreClock = SYSTEM_CLOCK; - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - // Enable GIC - L2C_Enable(); -#endif - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/firmware.bin b/firmware.bin index 9901c1ddff3e040480cb841ae982b2f70296c227..0e741d97f3f92c32cd6a232d2fe7340d6bf0d5f1 100644 GIT binary patch delta 716 zcmY+BOGs2<6vxjucbu`(Qq+Z*@wL&7kas4uba81>Ayi;$iy}m<=m8DV%V{u7QX9?H zWiX*&%7ukJ`6RMM&_X0(f*yl{6+$JN4~kZWQNIhe2=4Em|2f||=R4=#_K()e2kX(5 zfSNO%f$COuz`VFLl&Kor6Wv7xJC{WQUq!MZUqrXQ6WMPDx*IJLe)iOA&3&~UlMtW9)lEFS@>L{SKuO*ee_R23I6PRkqPp0sLLTw^E^WzGi}LFK9%P- z4TkL+4(i|#cm?BZ_RS}{34exy2CvR9`Y8T!IAz8LBUV8SImu>i*!H04T^m@&tr;pk z+(pDI_-_xUI8FRB&AvdKNw2~+Vgul3s$Trt=s45&pdX;Kh>u{`VV`4Pnbc6&s(p#{ z+N>q)m8NL_8qzQYlbkPtH%6NCC-5DA3Y+Xw@&}#8H5*|wY;kLc^NJmm_doYwPm(zY z2R#jE+{?pxDryqLKQh!C6Mr1>6{d;T*NappMUIf$Q7ZZ-u~CydvZ8|(;qvB+re>3$ zE(_R&+_(u!z=rMMfH)2>@9j9=2Wo+H5OrIoONv)pl<9qu^V%-gq4H2z+gqzb+p5AL aGcvuL9sK9qo&T*?9oxOXFkxbgoxZ_f2MJ^%B6&N=ryyUXv)j`!x> zOCBSqFMFz6jYIm$`QZZNpxxM2>Z@H8@yv^Op+rQrz82Z92f7+e3Vx;b8k4%NXIFtS zs{8B))7z30X@hnL+vu-$&odyQcl5WrSM_2hVNj0^hE3lGI&&Ap-%C8gl^J_^e30G!9F@< z1?o6B01eShBg^>%_(}ejm`)mE@`^%Guo)~nnkn|zpq%fyhuB2rS2%(` z2`zSKrr1d6zRVA|@kV#wi@P>X;n&xTgwrC&sJ&P&>IUAZE*e=@`LW}nV7M}-OR^Q7 zfS}iSTfqk%;pLorN|?*r%q;{3|0W)b4n*3RJ3KWzbRqtIFD1Wo^?V c(~I8xf648+-^NN3vhOTBHvw8d^<+eqU~Ts5ZFi^>2c z;36~te_P{JB@8;3OF3W+`#BWi$xXXQ=_4FMwqsrowtUAtgt^P%PO^b!<|<^czi3Es zI<^^}2d=(bak`ZrI7~Z%0_?Nhr!xal5vSIR)$Ap}M%VyfyW&(OB-WQ}VS)_%WcK38 z8M;U5Z5%?ji?R=v_su+{&L`n+jc#VfQHQX<9;9#@8lImg<-S{Sy?P!P?l^%00~1;( zzLR0A6CFrgeY;2fC|7Pcl8Y@Pz;d-#NVMyYVA}-^Onj@8k*gB{$+M-a^92E(vzf7P z0vTkEVB0&lOnmR^){9i_CBV-90AC^vR0UA8A+-D;2i0daiVXG$vn16l1~CJ^TXC;> z9vIX+fdUf{S}3SCx?Ni<{)U62Zya+25$TXH%M%%2eY;M?C|6fIl8Zi*f!ih>&4Ma{ z|DZK%$@HEymR4^sq{sUYq$(2Id;?Wg)U(9f?hOZaj8$hfrNy(k>HPr*JFLa=2Dd7c zz3a+%W3O%U%$p@VaWr$PQ^|v`;;z*>5_9Y$-1%w`YV4x z!=veL!AN%D4SFLg#_vDmzk=~Se40$g2T2APGO^G~RkZfiS|Y9vZIP(XIAoQohVbZ6 zNitDI*6e?}YCiQ{_;6%p1R|RKo^e$l z4^jEuSy1xxu`yTEe;A~$x*ja++qSUjP+vPPG^4K&)C_m?FuQwtC}|wM4pCEtiq5?q4AL2!o8!W`JUZ;hG0s_f}@f7eVe<#(y z=^61dCZYx#N)zVhIQ8!4_A`6*7~cv>5E?&`u`F%!mB}Iphy0Q)OB7c1KmZwtfbwS|`bSopq&IR7u=EEOP)O?;~UJwW( zkPCqL-%O82Fu$BDJJ%+QW3UlT*^>_T!NC*^-Gab-mPa;gw$k|s z+&c!7D@{*B)|4{6wZ`W=3yL7F2Rb@GQIw=AK+^W}XH?yP7^Q=^S7fP`;o-~|CSO7( j^SIPMndq{bxH>v1S9sQviya~iz*4nT*p;GTVcQt6mqUw1 delta 1381 zcmV-r1)BPf-UE`}1F(b!0kN}%27ws|E%Jm?SL+J14Isl_0YJ0Sey0clW|Mh`8x?s1 zCE!Xk0DrOxR0aJymrKaH4EyJ^sfS+!0qBzni&Fvhvt5fv2muYVrITL+4Jx}xl*o)= z+Y}E>e4~>QmpcVe_MRtavr(6O1qmzko+q5YTX8M3)tom26|fIXd_1Psi$vlj;A`0c zUrrBH1s9Vcpc_%X%Hd9kgJ$NSYp|crNN_p^^qwcvzguy9lpZ+ZJAnep{aOfZ+q!)o z$o_^Ba!?%V?Ge_AF!T(OZhgD)#VA)Y*OIGK&%jcBS4gxAVPN|OvyGtR0s**_aicRa z{eukq=J(>sp1VisTrEPjptTQ{2g^L9e#_xb+izyZ^=h!6#-VT;)AgPwcD`G2-m}%C zZvz$Ihp@j9OmI3o^`0l1R9jK^n;sZ+lUb)HUCqzHQe9I>w8d^<+eqU~Tq&m3i_QQg z;65|}e_P{JB@8;3OF3W+`#BWi$x*vU=_edQwqsrowtUAtguTn*PPTz&<|<^czjR1& zI<^^}2co`Pak`ZrI50bb0`Rllr!xal6{psV)$Ap}M%VyfyW&(OIM$bIWr7U*X!hdC z9lA&9VH`rXm$DC*_su+{&L`n+jc#VfRfn*@9;9#@8lImg8NFL^p?V$|(l~(v2NPN- zqLX2(6CE^MeY;2fC|7bgl8Y@Pz;d-#NVM;cVA}x=Onk4Ck*gB{&9kMe^92E#vzf7P z0vTwIVB0&lOnmR^){9i_CBV-90AC&rR0UMCA+-D;2Zk~*+YP4p4TtX z{_!(w$@HEymR4^sq{sUYq$(BLeGgSt(6hwb?hOZVj8tnirNOhg>HPr*Jgmh12DdJg zz3a+$>d@q$?4QLmS-GJ z+Pmp<(N6}m3ur%PrQs(0pNa4!I{r-4VLAr`QR2Z}Tk?|CPh{N=aFK}a7-Y4I2= zTPOb5N;tZo#!4dCY8&MBpKVdI{>96&bu2)35tZj1(OGwrU7J5>Wmjf}lC*dth96yj z6dc#FBqNA#rw=aJ4uZyZ>~^Cb*+eVyrE~?ld%-S{OL^6lZ^HJ$5(1_Fr3aQ+Us=$& z=@iFP2E;oOZzZmPPsP80_cd#pOWkHvQyN_2*I!oB^Rss%z7hzuu9|g0v(TgVwNN<# zBQ&Lt6_*TBfC%4xTz+>4(t+^#s2?IO!-BpB17RFunA6iKvN7lHjHAk?2H#{Rq z$M7~K`)|o?4!t_F>O{4>*GRG;kvU4f?sYnw%4Fo zq&^na78_3#gVsuwkMjL}FuGdR7Ak9NQIY+6IM?R2S_0iDP3QZcZBU-`jDzz#dl6Gs n?1OQ`31C*X4xlN|R42ugiya~mz)}ZSNR(M)@Y;OhO?;uI<0z3L diff --git a/main.c b/main.c index 67713d2..d2ef779 100644 --- a/main.c +++ b/main.c @@ -188,6 +188,10 @@ void Main(void) #if defined(ENABLE_UART) UART_SendText(UART_Version_str); UART_SendText("\r\n"); + { + //const unsigned long *unique = (const unsigned long *)0x1FFFF7E8; // STM32 M0 + //UART_printf("serial num %08X %08X %08X\r\n", unique[0], unique[1], unique[2]); + } #endif BootMode = BOOT_GetMode();