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using X86Disassembler.X86.Operands;
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2025-04-12 23:24:42 +03:00
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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/// Handler for floating-point load, store, and control operations (D9 opcode)
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/// </summary>
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public class LoadStoreControlHandler : InstructionHandler
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{
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// Memory operand instruction types for D9 opcode - load, store, and control operations
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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InstructionType.Fld, // 0
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InstructionType.Unknown, // 1
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InstructionType.Fst, // 2
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InstructionType.Fstp, // 3
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InstructionType.Unknown, // 4 - fldenv not in enum
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InstructionType.Fldcw, // 5
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InstructionType.Unknown, // 6 - fnstenv not in enum
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InstructionType.Fnstcw // 7
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex? OperandIndex)> RegisterOperations = new()
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{
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// FLD ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Fld, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Fld, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Fld, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Fld, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Fld, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Fld, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Fld, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Fld, FpuRegisterIndex.ST7) },
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// FXCH ST(i)
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{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Fxch, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Fxch, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Fxch, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Fxch, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Fxch, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Fxch, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Fxch, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Fxch, FpuRegisterIndex.ST7) },
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// D9E0-D9EF special instructions (reg=6)
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{ (RegisterIndex.Si, RegisterIndex.A), (InstructionType.Fchs, null) },
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{ (RegisterIndex.Si, RegisterIndex.B), (InstructionType.Fabs, null) },
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{ (RegisterIndex.Si, RegisterIndex.Si), (InstructionType.Ftst, null) },
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{ (RegisterIndex.Si, RegisterIndex.Di), (InstructionType.Fxam, null) },
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// D9F0-D9FF special instructions (reg=7)
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{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, null) }, // f2xm1 not in enum
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{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, null) }, // fyl2x not in enum
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{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, null) }, // fptan not in enum
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{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, null) }, // fpatan not in enum
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{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, null) }, // fxtract not in enum
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{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, null) }, // fprem1 not in enum
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{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, null) }, // fdecstp not in enum
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{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, null) }, // fincstp not in enum
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// D9D0-D9DF special instructions (reg=5)
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{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, null) }, // fprem not in enum
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{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, null) }, // fyl2xp1 not in enum
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{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, null) }, // fsqrt not in enum
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{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, null) }, // fsincos not in enum
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{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, null) }, // frndint not in enum
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{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, null) }, // fscale not in enum
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{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, null) }, // fsin not in enum
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{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, null) }, // fcos not in enum
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// D9C8-D9CF special instructions (reg=4)
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{ (RegisterIndex.Bp, RegisterIndex.A), (InstructionType.Unknown, null) }, // fnop not in enum
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{ (RegisterIndex.Bp, RegisterIndex.C), (InstructionType.Unknown, null) } // fwait not in enum
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};
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/// <summary>
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/// Initializes a new instance of the LoadStoreControlHandler class
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/// </summary>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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public LoadStoreControlHandler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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/// <summary>
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/// Checks if this handler can decode the given opcode
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/// </summary>
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/// <param name="opcode">The opcode to check</param>
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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return opcode == 0xD9;
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}
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/// <summary>
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/// Decodes a floating-point instruction for load, store, and control operations
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/// </summary>
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/// <param name="opcode">The opcode of the instruction</param>
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/// <param name="instruction">The instruction object to populate</param>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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{
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if (!Decoder.CanReadByte())
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{
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return false;
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}
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// Read the ModR/M byte
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var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
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// Handle based on addressing mode
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if (mod != 3) // Memory operand
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{
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// Set the instruction type based on the reg field
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instruction.Type = MemoryInstructionTypes[(int)reg];
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// Set the size based on the operation
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
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{
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// Keep the default 32-bit size for floating point operations
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memoryOperand.Size = 32;
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}
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else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fldcw, fnstcw
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{
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// Set to 16-bit for control word operations
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memoryOperand.Size = 16;
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}
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// Set the structured operands
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instruction.StructuredOperands =
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[
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memoryOperand
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];
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}
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else // Register operand (ST(i))
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{
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// Look up the instruction type in the register operations dictionary
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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instruction.Type = operation.Type;
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// Set the structured operands
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if (operation.OperandIndex.HasValue)
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{
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var operand = OperandFactory.CreateFPURegisterOperand(operation.OperandIndex.Value);
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instruction.StructuredOperands =
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[
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operand
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];
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}
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else
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{
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// No operands for instructions like fchs, fabs, etc.
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instruction.StructuredOperands = [];
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}
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}
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else
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{
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// Unknown instruction
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instruction.Type = InstructionType.Unknown;
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instruction.StructuredOperands = [];
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}
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}
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return true;
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}
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}
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