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Code Issues Releases Activity

Refactored floating point p-handlers with consistent naming convention

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This commit is contained in:
bird_egop
2025-04-18 02:31:06 +03:00
parent 2a8cf9534e
commit 18ecf31c46
19 changed files with 455 additions and 251 deletions
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30
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomiHandler.cs
View File

@@ -31,13 +31,11 @@ public class FcomiHandler : InstructionHandler
return false;
}
// Check if the ModR/M byte has reg field = 7 and mod = 3
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7);
byte mod = (byte)((modRm >> 6) & 0x3);
// Check second opcode byte
byte secondOpcode = Decoder.PeakByte();
// Only handle register operands (mod = 3) with reg = 7
return reg == 7 && mod == 3;
// Only handle F0-F7
return secondOpcode is >= 0xF0 and <= 0xF7;
}
/// <summary>
@@ -54,33 +52,17 @@ public class FcomiHandler : InstructionHandler
}
// Read the ModR/M byte
var (mod, reg, rm, _) = ModRMDecoder.ReadModRM();
var (mod, reg, rm, _) = ModRMDecoder.ReadModRMFpu();
// Set the instruction type
instruction.Type = InstructionType.Fcomi;
// Map rm field to FPU register index
FpuRegisterIndex stIndex = rm switch
{
RegisterIndex.A => FpuRegisterIndex.ST0,
RegisterIndex.C => FpuRegisterIndex.ST1,
RegisterIndex.D => FpuRegisterIndex.ST2,
RegisterIndex.B => FpuRegisterIndex.ST3,
RegisterIndex.Sp => FpuRegisterIndex.ST4,
RegisterIndex.Bp => FpuRegisterIndex.ST5,
RegisterIndex.Si => FpuRegisterIndex.ST6,
RegisterIndex.Di => FpuRegisterIndex.ST7,
_ => FpuRegisterIndex.ST0 // Default case, should not happen
};
// Create the FPU register operands
var destOperand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0);
var srcOperand = OperandFactory.CreateFPURegisterOperand(stIndex);
var srcOperand = OperandFactory.CreateFPURegisterOperand(rm);
// Set the structured operands
instruction.StructuredOperands =
[
destOperand,
srcOperand
];

30
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomipHandler.cs
View File

@@ -31,13 +31,11 @@ public class FcomipHandler : InstructionHandler
return false;
}
// Check if the ModR/M byte has reg field = 6 and mod = 3
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7);
byte mod = (byte)((modRm >> 6) & 0x3);
// Check second opcode byte
byte secondOpcode = Decoder.PeakByte();
// Only handle register operands (mod = 3) with reg = 6
return reg == 6 && mod == 3;
// Only handle F0-F7
return secondOpcode is >= 0xF0 and <= 0xF7;
}
/// <summary>
@@ -54,33 +52,17 @@ public class FcomipHandler : InstructionHandler
}
// Read the ModR/M byte
var (mod, reg, rm, _) = ModRMDecoder.ReadModRM();
var (mod, reg, rm, _) = ModRMDecoder.ReadModRMFpu();
// Set the instruction type
instruction.Type = InstructionType.Fcomip;
// Map rm field to FPU register index
FpuRegisterIndex stIndex = rm switch
{
RegisterIndex.A => FpuRegisterIndex.ST0,
RegisterIndex.C => FpuRegisterIndex.ST1,
RegisterIndex.D => FpuRegisterIndex.ST2,
RegisterIndex.B => FpuRegisterIndex.ST3,
RegisterIndex.Sp => FpuRegisterIndex.ST4,
RegisterIndex.Bp => FpuRegisterIndex.ST5,
RegisterIndex.Si => FpuRegisterIndex.ST6,
RegisterIndex.Di => FpuRegisterIndex.ST7,
_ => FpuRegisterIndex.ST0 // Default case, should not happen
};
// Create the FPU register operands
var destOperand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0);
var srcOperand = OperandFactory.CreateFPURegisterOperand(stIndex);
var srcOperand = OperandFactory.CreateFPURegisterOperand(rm);
// Set the structured operands
instruction.StructuredOperands =
[
destOperand,
srcOperand
];

2
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompFloat32Handler.cs
View File

@@ -36,7 +36,7 @@ public class FcompFloat32Handler : InstructionHandler
byte reg = (byte)((modRm >> 3) & 0x7);
// special handling of modRM for D8 D8+i FCOMP ST(i)
return reg == 3 && modRm is < 0xD8 or > 0xDE;
return reg == 3 && modRm is < 0xD8 or > 0xDF;
}
/// <summary>

2
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompStHandler.cs
View File

@@ -34,7 +34,7 @@ public class FcompStHandler : InstructionHandler
var opcodeSecond = Decoder.PeakByte();
// this is a special case of a handler, only handling FCOMP with ST(i)
if (opcodeSecond < 0xD8 || opcodeSecond > 0xDF)
if (opcodeSecond is < 0xD8 or > 0xDF)
return false;
return true;

28
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FucomiHandler.cs
View File

@@ -31,13 +31,11 @@ public class FucomiHandler : InstructionHandler
return false;
}
// Check if the ModR/M byte has reg field = 6 and mod = 3
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7);
byte mod = (byte)((modRm >> 6) & 0x3);
// Check second opcode byte
byte secondOpcode = Decoder.PeakByte();
// Only handle register operands (mod = 3) with reg = 6
return reg == 6 && mod == 3;
// Only handle F0-F7
return secondOpcode is >= 0xE8 and <= 0xEF;
}
/// <summary>
@@ -54,28 +52,14 @@ public class FucomiHandler : InstructionHandler
}
// Read the ModR/M byte
var (mod, reg, rm, _) = ModRMDecoder.ReadModRM();
var (mod, reg, rm, _) = ModRMDecoder.ReadModRMFpu();
// Set the instruction type
instruction.Type = InstructionType.Fucomi;
// Map rm field to FPU register index
FpuRegisterIndex stIndex = rm switch
{
RegisterIndex.A => FpuRegisterIndex.ST0,
RegisterIndex.C => FpuRegisterIndex.ST1,
RegisterIndex.D => FpuRegisterIndex.ST2,
RegisterIndex.B => FpuRegisterIndex.ST3,
RegisterIndex.Sp => FpuRegisterIndex.ST4,
RegisterIndex.Bp => FpuRegisterIndex.ST5,
RegisterIndex.Si => FpuRegisterIndex.ST6,
RegisterIndex.Di => FpuRegisterIndex.ST7,
_ => FpuRegisterIndex.ST0 // Default case, should not happen
};
// Create the FPU register operands
var destOperand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0);
var srcOperand = OperandFactory.CreateFPURegisterOperand(stIndex);
var srcOperand = OperandFactory.CreateFPURegisterOperand(rm);
// Set the structured operands
instruction.StructuredOperands =

30
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FucomipHandler.cs
View File

@@ -31,13 +31,11 @@ public class FucomipHandler : InstructionHandler
return false;
}
// Check if the ModR/M byte has reg field = 5 and mod = 3
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7);
byte mod = (byte)((modRm >> 6) & 0x3);
// Check second opcode byte
byte secondOpcode = Decoder.PeakByte();
// Only handle register operands (mod = 3) with reg = 5
return reg == 5 && mod == 3;
// Only handle F0-F7
return secondOpcode is >= 0xE8 and <= 0xEF;
}
/// <summary>
@@ -54,33 +52,17 @@ public class FucomipHandler : InstructionHandler
}
// Read the ModR/M byte
var (mod, reg, rm, _) = ModRMDecoder.ReadModRM();
var (mod, reg, rm, _) = ModRMDecoder.ReadModRMFpu();
// Set the instruction type
instruction.Type = InstructionType.Fucomip;
// Map rm field to FPU register index
FpuRegisterIndex stIndex = rm switch
{
RegisterIndex.A => FpuRegisterIndex.ST0,
RegisterIndex.C => FpuRegisterIndex.ST1,
RegisterIndex.D => FpuRegisterIndex.ST2,
RegisterIndex.B => FpuRegisterIndex.ST3,
RegisterIndex.Sp => FpuRegisterIndex.ST4,
RegisterIndex.Bp => FpuRegisterIndex.ST5,
RegisterIndex.Si => FpuRegisterIndex.ST6,
RegisterIndex.Di => FpuRegisterIndex.ST7,
_ => FpuRegisterIndex.ST0 // Default case, should not happen
};
// Create the FPU register operands
var destOperand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0);
var srcOperand = OperandFactory.CreateFPURegisterOperand(stIndex);
var srcOperand = OperandFactory.CreateFPURegisterOperand(rm);
// Set the structured operands
instruction.StructuredOperands =
[
destOperand,
srcOperand
];