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Fixed floating point comparison handlers for FCOM ST(i) and FCOMP ST(i) instructions

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This commit is contained in:
bird_egop 2025-04-18 01:25:34 +03:00
parent 84d5652a62
commit 2a8cf9534e
6 changed files with 47 additions and 57 deletions
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3
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomFloat32Handler.cs
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@ -35,7 +35,8 @@ public class FcomFloat32Handler : InstructionHandler
byte modRm = Decoder.PeakByte(); byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7); byte reg = (byte)((modRm >> 3) & 0x7);
return reg == 2; // special handling of modRM for D8 D0+i FCOM ST(i)
return reg == 2 && modRm is < 0xD0 or > 0xD7;
} }
/// <summary> /// <summary>

48
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomSt0Handler.cs → X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomStHandler.cs
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@ -3,15 +3,15 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint.Comparison;
using X86Disassembler.X86.Operands; using X86Disassembler.X86.Operands;
/// <summary> /// <summary>
/// Handler for FCOM ST(0), ST(i) instruction (D8 D0-D7) /// Handler for FCOM ST(i) instruction (D8 D0-D7) - compares ST(0) with ST(i)
/// </summary> /// </summary>
public class FcomSt0Handler : InstructionHandler public class FcomStHandler : InstructionHandler
{ {
/// <summary> /// <summary>
/// Initializes a new instance of the FcomSt0Handler class /// Initializes a new instance of the FcomStHandler class
/// </summary> /// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param> /// <param name="decoder">The instruction decoder that owns this handler</param>
public FcomSt0Handler(InstructionDecoder decoder) public FcomStHandler(InstructionDecoder decoder)
: base(decoder) : base(decoder)
{ {
} }
@ -23,7 +23,7 @@ public class FcomSt0Handler : InstructionHandler
/// <returns>True if this handler can decode the opcode</returns> /// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode) public override bool CanHandle(byte opcode)
{ {
// FCOM ST(0), ST(i) is D8 D0-D7 // FCOM ST(i) is D8 D0-D7 (compares ST(0) with ST(i))
if (opcode != 0xD8) return false; if (opcode != 0xD8) return false;
if (!Decoder.CanReadByte()) if (!Decoder.CanReadByte())
@ -31,17 +31,17 @@ public class FcomSt0Handler : InstructionHandler
return false; return false;
} }
// Check if the ModR/M byte has reg field = 2 and mod = 3 var opcodeSecond = Decoder.PeakByte();
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7); // this is a special case of a handler, only handling FCOM with ST(i)
byte mod = (byte)((modRm >> 6) & 0x3); if (opcodeSecond < 0xD0 || opcodeSecond > 0xD7)
return false;
// Only handle register operands (mod = 3) with reg = 2
return reg == 2 && mod == 3; return true;
} }
/// <summary> /// <summary>
/// Decodes a FCOM ST(0), ST(i) instruction /// Decodes a FCOM ST(i) instruction - compares ST(0) with ST(i)
/// </summary> /// </summary>
/// <param name="opcode">The opcode of the instruction</param> /// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param> /// <param name="instruction">The instruction object to populate</param>
@ -52,26 +52,11 @@ public class FcomSt0Handler : InstructionHandler
{ {
return false; return false;
} }
// Read the ModR/M byte
var (mod, reg, rm, _) = ModRMDecoder.ReadModRMFpu();
var stIndex = (FpuRegisterIndex)(Decoder.ReadByte() - 0xD0);
// Set the instruction type // Set the instruction type
instruction.Type = InstructionType.Fcom; instruction.Type = InstructionType.Fcom;
// Map rm field to FPU register index
FpuRegisterIndex stIndex = rm switch
{
FpuRegisterIndex.ST0 => FpuRegisterIndex.ST0,
FpuRegisterIndex.ST1 => FpuRegisterIndex.ST1,
FpuRegisterIndex.ST2 => FpuRegisterIndex.ST2,
FpuRegisterIndex.ST3 => FpuRegisterIndex.ST3,
FpuRegisterIndex.ST4 => FpuRegisterIndex.ST4,
FpuRegisterIndex.ST5 => FpuRegisterIndex.ST5,
FpuRegisterIndex.ST6 => FpuRegisterIndex.ST6,
FpuRegisterIndex.ST7 => FpuRegisterIndex.ST7,
_ => FpuRegisterIndex.ST0 // Default case, should not happen
};
// Create the FPU register operands // Create the FPU register operands
var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0); var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0);
@ -80,8 +65,7 @@ public class FcomSt0Handler : InstructionHandler
// Set the structured operands // Set the structured operands
instruction.StructuredOperands = instruction.StructuredOperands =
[ [
st0Operand, stiOperand // The instruction is FCOM ST(i), which compares ST(0) with ST(i)
stiOperand
]; ];
return true; return true;

3
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompFloat32Handler.cs
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@ -35,7 +35,8 @@ public class FcompFloat32Handler : InstructionHandler
byte modRm = Decoder.PeakByte(); byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7); byte reg = (byte)((modRm >> 3) & 0x7);
return reg == 3; // special handling of modRM for D8 D8+i FCOMP ST(i)
return reg == 3 && modRm is < 0xD8 or > 0xDE;
} }
/// <summary> /// <summary>

31
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompStHandler.cs
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@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint.Comparison;
using X86Disassembler.X86.Operands; using X86Disassembler.X86.Operands;
/// <summary> /// <summary>
/// Handler for FCOMP ST(0) instruction (DE D3) /// Handler for FCOMP ST(i) instruction (D8 D8-DF) - compares ST(0) with ST(i) and pops the register stack
/// </summary> /// </summary>
public class FcompStHandler : InstructionHandler public class FcompStHandler : InstructionHandler
{ {
@ -23,21 +23,25 @@ public class FcompStHandler : InstructionHandler
/// <returns>True if this handler can decode the opcode</returns> /// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode) public override bool CanHandle(byte opcode)
{ {
// FCOMP ST(0) is DE D3 // FCOMP ST(i) is D8 D8-DF (compares ST(0) with ST(i) and pops the register stack)
if (opcode != 0xDE) return false; if (opcode != 0xD8) return false;
if (!Decoder.CanReadByte()) if (!Decoder.CanReadByte())
{ {
return false; return false;
} }
// Check if the ModR/M byte is exactly D3 (reg = 2, rm = 3, mod = 3) var opcodeSecond = Decoder.PeakByte();
byte modRm = Decoder.PeakByte();
return modRm == 0xD3; // this is a special case of a handler, only handling FCOMP with ST(i)
if (opcodeSecond < 0xD8 || opcodeSecond > 0xDF)
return false;
return true;
} }
/// <summary> /// <summary>
/// Decodes a FCOMP ST(0) instruction /// Decodes a FCOMP ST(i) instruction - compares ST(0) with ST(i) and pops the register stack
/// </summary> /// </summary>
/// <param name="opcode">The opcode of the instruction</param> /// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param> /// <param name="instruction">The instruction object to populate</param>
@ -48,20 +52,19 @@ public class FcompStHandler : InstructionHandler
{ {
return false; return false;
} }
// Read the ModR/M byte
var (mod, reg, rm, _) = ModRMDecoder.ReadModRM();
var stIndex = (FpuRegisterIndex)(Decoder.ReadByte() - 0xD8);
// Set the instruction type // Set the instruction type
instruction.Type = InstructionType.Fcomp; instruction.Type = InstructionType.Fcomp;
// Create the FPU register operand // Create the FPU register operands
var fpuRegisterOperand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0); var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex);
// Set the structured operands // Set the structured operands
instruction.StructuredOperands = instruction.StructuredOperands =
[ [
fpuRegisterOperand stiOperand // The instruction is FCOMP ST(i), which compares ST(0) with ST(i) and pops the register stack
]; ];
return true; return true;

3
X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs
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@ -441,7 +441,8 @@ public class InstructionHandlerFactory
// D8 opcode handlers (register operations) // D8 opcode handlers (register operations)
_handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(0), ST(i) (D8 C0-C7) _handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(0), ST(i) (D8 C0-C7)
_handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(0), ST(i) (D8 C8-CF) _handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(0), ST(i) (D8 C8-CF)
_handlers.Add(new FloatingPoint.Comparison.FcomSt0Handler(_decoder)); // FCOM ST(0), ST(i) (D8 D0-D7) _handlers.Add(new FloatingPoint.Comparison.FcomStHandler(_decoder)); // FCOM ST(i) (D8 D0-D7)
_handlers.Add(new FloatingPoint.Comparison.FcompStHandler(_decoder)); // FCOMP ST(i) (D8 D8-DF)
_handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(0), ST(i) (D8 E0-E7) _handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(0), ST(i) (D8 E0-E7)
_handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(0), ST(i) (D8 E8-EF) _handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(0), ST(i) (D8 E8-EF)
_handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(0), ST(i) (D8 F0-F7) _handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(0), ST(i) (D8 F0-F7)

16
X86DisassemblerTests/TestData/fcom_tests.csv
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@ -15,16 +15,16 @@ D8D7;[{ "Type": "Fcom", "Operands": ["ST(7)"] }]
# Memory operands # Memory operands
D8142510000000;[{ "Type": "Fcom", "Operands": ["dword ptr [0x10]"] }] D8142510000000;[{ "Type": "Fcom", "Operands": ["dword ptr [0x10]"] }]
DC142510000000;[{ "Type": "Fcom", "Operands": ["qword ptr [0x10]"] }] DC142510000000;[{ "Type": "Fcom", "Operands": ["qword ptr [0x10]"] }]
D81425;[{ "Type": "Fcom", "Operands": ["dword ptr [eax]"] }] D810;[{ "Type": "Fcom", "Operands": ["dword ptr [eax]"] }]
DC1425;[{ "Type": "Fcom", "Operands": ["qword ptr [eax]"] }] DC10;[{ "Type": "Fcom", "Operands": ["qword ptr [eax]"] }]
# With segment override prefixes # With segment override prefixes
26D81425;[{ "Type": "Fcom", "Operands": ["dword ptr es:[eax]"] }] 26D810;[{ "Type": "Fcom", "Operands": ["dword ptr es:[eax]"] }]
2ED81425;[{ "Type": "Fcom", "Operands": ["dword ptr cs:[eax]"] }] 2ED810;[{ "Type": "Fcom", "Operands": ["dword ptr cs:[eax]"] }]
36D81425;[{ "Type": "Fcom", "Operands": ["dword ptr ss:[eax]"] }] 36D810;[{ "Type": "Fcom", "Operands": ["dword ptr ss:[eax]"] }]
3ED81425;[{ "Type": "Fcom", "Operands": ["dword ptr ds:[eax]"] }] 3ED810;[{ "Type": "Fcom", "Operands": ["dword ptr ds:[eax]"] }]
64D81425;[{ "Type": "Fcom", "Operands": ["dword ptr fs:[eax]"] }] 64D810;[{ "Type": "Fcom", "Operands": ["dword ptr fs:[eax]"] }]
65D81425;[{ "Type": "Fcom", "Operands": ["dword ptr gs:[eax]"] }] 65D810;[{ "Type": "Fcom", "Operands": ["dword ptr gs:[eax]"] }]
# FCOMP - Compare floating point values and pop # FCOMP - Compare floating point values and pop
D8D8;[{ "Type": "Fcomp", "Operands": ["ST(0)"] }] D8D8;[{ "Type": "Fcomp", "Operands": ["ST(0)"] }]

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