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Simplified LoadStoreFloat64Handler by replacing if-else logic with a dictionary-based approach
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bird_egop
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@ -5,18 +5,72 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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/// </summary>
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public class LoadStoreFloat64Handler : InstructionHandler
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public class LoadStoreFloat64Handler : InstructionHandler
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{
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{
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// DD opcode - load/store float64
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// Memory operand mnemonics for DD opcode - load/store float64
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private static readonly string[] Mnemonics =
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private static readonly string[] MemoryMnemonics =
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[
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[
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"fld",
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"fld", // 0
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"??",
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"??", // 1
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"fst",
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"fst", // 2
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"fstp",
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"fstp", // 3
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"frstor",
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"frstor", // 4
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"??",
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"??", // 5
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"fnsave",
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"fnsave", // 6
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"fnstsw",
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"fnstsw" // 7
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];
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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{
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// FFREE ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("ffree", "st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("ffree", "st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("ffree", "st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("ffree", "st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("ffree", "st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("ffree", "st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("ffree", "st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("ffree", "st(7)") },
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// FST ST(i)
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{ (RegisterIndex.C, RegisterIndex.A), ("fst", "st(0)") },
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{ (RegisterIndex.C, RegisterIndex.C), ("fst", "st(1)") },
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{ (RegisterIndex.C, RegisterIndex.D), ("fst", "st(2)") },
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{ (RegisterIndex.C, RegisterIndex.B), ("fst", "st(3)") },
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{ (RegisterIndex.C, RegisterIndex.Sp), ("fst", "st(4)") },
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{ (RegisterIndex.C, RegisterIndex.Bp), ("fst", "st(5)") },
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{ (RegisterIndex.C, RegisterIndex.Si), ("fst", "st(6)") },
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{ (RegisterIndex.C, RegisterIndex.Di), ("fst", "st(7)") },
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// FSTP ST(i)
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{ (RegisterIndex.D, RegisterIndex.A), ("fstp", "st(0)") },
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{ (RegisterIndex.D, RegisterIndex.C), ("fstp", "st(1)") },
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{ (RegisterIndex.D, RegisterIndex.D), ("fstp", "st(2)") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fstp", "st(3)") },
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{ (RegisterIndex.D, RegisterIndex.Sp), ("fstp", "st(4)") },
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{ (RegisterIndex.D, RegisterIndex.Bp), ("fstp", "st(5)") },
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{ (RegisterIndex.D, RegisterIndex.Si), ("fstp", "st(6)") },
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{ (RegisterIndex.D, RegisterIndex.Di), ("fstp", "st(7)") },
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// FUCOM ST(i)
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{ (RegisterIndex.Si, RegisterIndex.A), ("fucom", "st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.C), ("fucom", "st(1)") },
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{ (RegisterIndex.Si, RegisterIndex.D), ("fucom", "st(2)") },
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{ (RegisterIndex.Si, RegisterIndex.B), ("fucom", "st(3)") },
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{ (RegisterIndex.Si, RegisterIndex.Sp), ("fucom", "st(4)") },
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{ (RegisterIndex.Si, RegisterIndex.Bp), ("fucom", "st(5)") },
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{ (RegisterIndex.Si, RegisterIndex.Si), ("fucom", "st(6)") },
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{ (RegisterIndex.Si, RegisterIndex.Di), ("fucom", "st(7)") },
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// FUCOMP ST(i)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fucomp", "st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fucomp", "st(1)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fucomp", "st(2)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fucomp", "st(3)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomp", "st(4)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomp", "st(5)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomp", "st(6)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomp", "st(7)") }
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};
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/// <summary>
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/// <summary>
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/// Initializes a new instance of the LoadStoreFloat64Handler class
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/// Initializes a new instance of the LoadStoreFloat64Handler class
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@ -47,59 +101,38 @@ public class LoadStoreFloat64Handler : InstructionHandler
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/// <returns>True if the instruction was successfully decoded</returns>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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public override bool Decode(byte opcode, Instruction instruction)
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{
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{
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int position = Decoder.GetPosition();
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if (!Decoder.CanReadByte())
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if (position >= Length)
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{
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{
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return false;
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return false;
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}
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}
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// Read the ModR/M byte
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM(true);// true for 64-bit operand
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM(true); // true for 64-bit operand
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// Set the mnemonic based on the opcode and reg field
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// Handle based on addressing mode
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instruction.Mnemonic = Mnemonics[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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if (mod != 3) // Memory operand
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{
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
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{
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{
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instruction.Operands = destOperand;
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// Keep the qword ptr prefix from ModRMDecoder
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instruction.Operands = memOperand;
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}
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}
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else // frstor, fnsave, fnstsw
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else // frstor, fnsave, fnstsw
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{
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{
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// Remove the qword ptr prefix for these operations
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// Remove the qword ptr prefix for these operations
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instruction.Operands = destOperand.Replace("qword ptr ", "");
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instruction.Operands = memOperand.Replace("qword ptr ", "");
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}
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}
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}
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}
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else // Register operand (ST(i))
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else // Register operand (ST(i))
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{
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{
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// Special handling for register-register operations
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// Look up the register operation in our dictionary
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if (reg == RegisterIndex.A) // FFREE
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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{
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instruction.Mnemonic = "ffree";
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = $"st({(int)rm})";
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instruction.Operands = operation.Operands;
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}
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else if (reg == RegisterIndex.C) // FST
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{
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instruction.Mnemonic = "fst";
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instruction.Operands = $"st({(int)rm})";
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}
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else if (reg == RegisterIndex.D) // FSTP
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{
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instruction.Mnemonic = "fstp";
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instruction.Operands = $"st({(int)rm})";
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}
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else if (reg == RegisterIndex.Si) // FUCOM
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{
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instruction.Mnemonic = "fucom";
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instruction.Operands = $"st({(int)rm})";
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}
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else if (reg == RegisterIndex.Di) // FUCOMP
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{
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instruction.Mnemonic = "fucomp";
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instruction.Operands = $"st({(int)rm})";
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}
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}
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else
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else
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{
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{
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