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https://github.com/sampletext32/ParkanPlayground.git
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Simplified LoadStoreInt32Handler by replacing if-else logic with a dictionary-based approach
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bird_egop
parent
fac1339fec
commit
5daab494e1
@ -5,18 +5,86 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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/// </summary>
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public class LoadStoreInt32Handler : InstructionHandler
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public class LoadStoreInt32Handler : InstructionHandler
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{
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{
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// DB opcode - load/store int32, misc
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// Memory operand mnemonics for DB opcode - load/store int32, misc
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private static readonly string[] Mnemonics =
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private static readonly string[] MemoryMnemonics =
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[
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[
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"fild",
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"fild", // 0 - 32-bit integer
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"??",
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"??", // 1
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"fist",
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"fist", // 2 - 32-bit integer
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"fistp",
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"fistp", // 3 - 32-bit integer
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"??",
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"??", // 4
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"fld",
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"fld", // 5 - 80-bit extended precision
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"??",
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"??", // 6
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"fstp",
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"fstp" // 7 - 80-bit extended precision
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];
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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{
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// FCMOVNB ST(0), ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("fcmovnb", "st(0), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("fcmovnb", "st(0), st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("fcmovnb", "st(0), st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("fcmovnb", "st(0), st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("fcmovnb", "st(0), st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("fcmovnb", "st(0), st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("fcmovnb", "st(0), st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("fcmovnb", "st(0), st(7)") },
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// FCMOVNE ST(0), ST(i)
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{ (RegisterIndex.B, RegisterIndex.A), ("fcmovne", "st(0), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.C), ("fcmovne", "st(0), st(1)") },
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{ (RegisterIndex.B, RegisterIndex.D), ("fcmovne", "st(0), st(2)") },
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{ (RegisterIndex.B, RegisterIndex.B), ("fcmovne", "st(0), st(3)") },
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{ (RegisterIndex.B, RegisterIndex.Sp), ("fcmovne", "st(0), st(4)") },
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{ (RegisterIndex.B, RegisterIndex.Bp), ("fcmovne", "st(0), st(5)") },
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{ (RegisterIndex.B, RegisterIndex.Si), ("fcmovne", "st(0), st(6)") },
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{ (RegisterIndex.B, RegisterIndex.Di), ("fcmovne", "st(0), st(7)") },
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// FCMOVNBE ST(0), ST(i)
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{ (RegisterIndex.C, RegisterIndex.A), ("fcmovnbe", "st(0), st(0)") },
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{ (RegisterIndex.C, RegisterIndex.C), ("fcmovnbe", "st(0), st(1)") },
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{ (RegisterIndex.C, RegisterIndex.D), ("fcmovnbe", "st(0), st(2)") },
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{ (RegisterIndex.C, RegisterIndex.B), ("fcmovnbe", "st(0), st(3)") },
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{ (RegisterIndex.C, RegisterIndex.Sp), ("fcmovnbe", "st(0), st(4)") },
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{ (RegisterIndex.C, RegisterIndex.Bp), ("fcmovnbe", "st(0), st(5)") },
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{ (RegisterIndex.C, RegisterIndex.Si), ("fcmovnbe", "st(0), st(6)") },
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{ (RegisterIndex.C, RegisterIndex.Di), ("fcmovnbe", "st(0), st(7)") },
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// FCMOVNU ST(0), ST(i)
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{ (RegisterIndex.D, RegisterIndex.A), ("fcmovnu", "st(0), st(0)") },
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{ (RegisterIndex.D, RegisterIndex.C), ("fcmovnu", "st(0), st(1)") },
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{ (RegisterIndex.D, RegisterIndex.D), ("fcmovnu", "st(0), st(2)") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fcmovnu", "st(0), st(3)") },
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{ (RegisterIndex.D, RegisterIndex.Sp), ("fcmovnu", "st(0), st(4)") },
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{ (RegisterIndex.D, RegisterIndex.Bp), ("fcmovnu", "st(0), st(5)") },
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{ (RegisterIndex.D, RegisterIndex.Si), ("fcmovnu", "st(0), st(6)") },
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{ (RegisterIndex.D, RegisterIndex.Di), ("fcmovnu", "st(0), st(7)") },
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// Special cases
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{ (RegisterIndex.Si, RegisterIndex.C), ("fclex", "") },
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{ (RegisterIndex.Si, RegisterIndex.D), ("finit", "") },
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// FUCOMI ST(0), ST(i)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fucomi", "st(0), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fucomi", "st(0), st(1)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fucomi", "st(0), st(2)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fucomi", "st(0), st(3)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomi", "st(0), st(4)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomi", "st(0), st(5)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomi", "st(0), st(6)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomi", "st(0), st(7)") },
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// FCOMI ST(0), ST(i)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fcomi", "st(0), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fcomi", "st(0), st(1)") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fcomi", "st(0), st(2)") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fcomi", "st(0), st(3)") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fcomi", "st(0), st(4)") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcomi", "st(0), st(5)") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("fcomi", "st(0), st(6)") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fcomi", "st(0), st(7)") }
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};
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/// <summary>
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/// <summary>
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/// Initializes a new instance of the LoadStoreInt32Handler class
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/// Initializes a new instance of the LoadStoreInt32Handler class
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@ -47,87 +115,45 @@ public class LoadStoreInt32Handler : InstructionHandler
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/// <returns>True if the instruction was successfully decoded</returns>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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public override bool Decode(byte opcode, Instruction instruction)
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{
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{
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int position = Decoder.GetPosition();
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if (!Decoder.CanReadByte())
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if (position >= Length)
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{
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{
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return false;
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return false;
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}
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}
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// Read the ModR/M byte
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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// Set the mnemonic based on the opcode and reg field
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// Handle based on addressing mode
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instruction.Mnemonic = Mnemonics[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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if (mod != 3) // Memory operand
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{
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{
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fild, fist, fistp
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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// Get the base operand without size prefix
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string baseOperand = memOperand.Replace("dword ptr ", "");
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// Apply the appropriate size prefix based on the operation
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // 32-bit integer operations
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{
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{
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// Keep the dword ptr prefix for integer operations
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// Keep the dword ptr prefix for integer operations
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instruction.Operands = destOperand;
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instruction.Operands = memOperand;
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}
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}
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else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fld, fstp (extended precision)
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else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 80-bit extended precision operations
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{
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{
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// Replace dword ptr with tword ptr for extended precision
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instruction.Operands = $"tword ptr {baseOperand}";
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instruction.Operands = destOperand.Replace("dword ptr", "tword ptr");
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}
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}
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else
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else
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{
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{
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instruction.Operands = destOperand;
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instruction.Operands = memOperand;
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}
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}
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}
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}
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else // Register operand (ST(i))
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else // Register operand (ST(i))
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{
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{
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// Special handling for register-register operations
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// Look up the register operation in our dictionary
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if (reg == RegisterIndex.A) // FCMOVNB
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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{
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instruction.Mnemonic = "fcmovnb";
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = $"st(0), st({(int)rm})";
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instruction.Operands = operation.Operands;
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}
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else if (reg == RegisterIndex.B) // FCMOVNE
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{
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instruction.Mnemonic = "fcmovne";
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instruction.Operands = $"st(0), st({(int)rm})";
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}
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else if (reg == RegisterIndex.C) // FCMOVNBE
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{
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instruction.Mnemonic = "fcmovnbe";
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instruction.Operands = $"st(0), st({(int)rm})";
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}
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else if (reg == RegisterIndex.D) // FCMOVNU
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{
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instruction.Mnemonic = "fcmovnu";
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instruction.Operands = $"st(0), st({(int)rm})";
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}
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else if (reg == RegisterIndex.Si)
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{
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if (rm == RegisterIndex.C) // FCLEX
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{
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instruction.Mnemonic = "fclex";
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instruction.Operands = "";
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}
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else if (rm == RegisterIndex.D) // FINIT
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{
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instruction.Mnemonic = "finit";
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instruction.Operands = "";
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}
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else
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{
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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}
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}
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else if (reg == RegisterIndex.Di) // FUCOMI
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{
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instruction.Mnemonic = "fucomi";
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instruction.Operands = $"st(0), st({(int)rm})";
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}
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else if (reg == RegisterIndex.Sp) // FCOMI
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{
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instruction.Mnemonic = "fcomi";
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instruction.Operands = $"st(0), st({(int)rm})";
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}
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}
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else
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else
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{
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{
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