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Split FPU tests by instruction type for better organization and readability
This commit is contained in:
bird_egop
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60
X86DisassemblerTests/TestData/fadd_tests.csv
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X86DisassemblerTests/TestData/fadd_tests.csv
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# FADD instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# FADD - Add floating point values
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# ST(0), ST(i) form (D8 C0+i)
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D8C0;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(0)"] }]
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D8C1;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(1)"] }]
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D8C2;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(2)"] }]
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D8C3;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(3)"] }]
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D8C4;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(4)"] }]
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D8C5;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(5)"] }]
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D8C6;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(6)"] }]
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D8C7;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(7)"] }]
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# ST(i), ST(0) form (DC C0+i)
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DCC0;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(0)"] }]
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DCC1;[{ "Type": "Fadd", "Operands": ["ST(1)", "ST(0)"] }]
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DCC2;[{ "Type": "Fadd", "Operands": ["ST(2)", "ST(0)"] }]
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DCC3;[{ "Type": "Fadd", "Operands": ["ST(3)", "ST(0)"] }]
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DCC4;[{ "Type": "Fadd", "Operands": ["ST(4)", "ST(0)"] }]
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DCC5;[{ "Type": "Fadd", "Operands": ["ST(5)", "ST(0)"] }]
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DCC6;[{ "Type": "Fadd", "Operands": ["ST(6)", "ST(0)"] }]
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DCC7;[{ "Type": "Fadd", "Operands": ["ST(7)", "ST(0)"] }]
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# Memory operands
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D8042510000000;[{ "Type": "Fadd", "Operands": ["dword ptr [0x10]"] }]
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DC042510000000;[{ "Type": "Fadd", "Operands": ["qword ptr [0x10]"] }]
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D80425;[{ "Type": "Fadd", "Operands": ["dword ptr [eax]"] }]
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DC0425;[{ "Type": "Fadd", "Operands": ["qword ptr [eax]"] }]
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D8041D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebx]"] }]
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DC041D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebx]"] }]
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D8042D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebp]"] }]
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DC042D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebp]"] }]
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# With segment override prefixes
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26D80425;[{ "Type": "Fadd", "Operands": ["dword ptr es:[eax]"] }]
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2ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr cs:[eax]"] }]
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36D80425;[{ "Type": "Fadd", "Operands": ["dword ptr ss:[eax]"] }]
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3ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr ds:[eax]"] }]
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64D80425;[{ "Type": "Fadd", "Operands": ["dword ptr fs:[eax]"] }]
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65D80425;[{ "Type": "Fadd", "Operands": ["dword ptr gs:[eax]"] }]
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# FADDP - Add floating point values and pop
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DEC0;[{ "Type": "Faddp", "Operands": ["ST(0)", "ST(0)"] }]
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DEC1;[{ "Type": "Faddp", "Operands": ["ST(1)", "ST(0)"] }]
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DEC2;[{ "Type": "Faddp", "Operands": ["ST(2)", "ST(0)"] }]
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DEC3;[{ "Type": "Faddp", "Operands": ["ST(3)", "ST(0)"] }]
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DEC4;[{ "Type": "Faddp", "Operands": ["ST(4)", "ST(0)"] }]
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DEC5;[{ "Type": "Faddp", "Operands": ["ST(5)", "ST(0)"] }]
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DEC6;[{ "Type": "Faddp", "Operands": ["ST(6)", "ST(0)"] }]
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DEC7;[{ "Type": "Faddp", "Operands": ["ST(7)", "ST(0)"] }]
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# FIADD - Add integer to floating point
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DA042510000000;[{ "Type": "Fiadd", "Operands": ["dword ptr [0x10]"] }]
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DE042510000000;[{ "Type": "Fiadd", "Operands": ["word ptr [0x10]"] }]
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DA0425;[{ "Type": "Fiadd", "Operands": ["dword ptr [eax]"] }]
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DE0425;[{ "Type": "Fiadd", "Operands": ["word ptr [eax]"] }]
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DA041D;[{ "Type": "Fiadd", "Operands": ["dword ptr [ebx]"] }]
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DE041D;[{ "Type": "Fiadd", "Operands": ["word ptr [ebx]"] }]
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Can't render this file because it contains an unexpected character in line 7 and column 9.
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X86DisassemblerTests/TestData/fcom_tests.csv
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X86DisassemblerTests/TestData/fcom_tests.csv
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# FCOM/FCOMP/FCOMPP instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# FCOM - Compare floating point values
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D8D0;[{ "Type": "Fcom", "Operands": ["ST(0)"] }]
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D8D1;[{ "Type": "Fcom", "Operands": ["ST(1)"] }]
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D8D2;[{ "Type": "Fcom", "Operands": ["ST(2)"] }]
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D8D3;[{ "Type": "Fcom", "Operands": ["ST(3)"] }]
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D8D4;[{ "Type": "Fcom", "Operands": ["ST(4)"] }]
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D8D5;[{ "Type": "Fcom", "Operands": ["ST(5)"] }]
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D8D6;[{ "Type": "Fcom", "Operands": ["ST(6)"] }]
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D8D7;[{ "Type": "Fcom", "Operands": ["ST(7)"] }]
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# Memory operands
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D8142510000000;[{ "Type": "Fcom", "Operands": ["dword ptr [0x10]"] }]
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DC142510000000;[{ "Type": "Fcom", "Operands": ["qword ptr [0x10]"] }]
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D81425;[{ "Type": "Fcom", "Operands": ["dword ptr [eax]"] }]
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DC1425;[{ "Type": "Fcom", "Operands": ["qword ptr [eax]"] }]
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# With segment override prefixes
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26D81425;[{ "Type": "Fcom", "Operands": ["dword ptr es:[eax]"] }]
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2ED81425;[{ "Type": "Fcom", "Operands": ["dword ptr cs:[eax]"] }]
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36D81425;[{ "Type": "Fcom", "Operands": ["dword ptr ss:[eax]"] }]
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3ED81425;[{ "Type": "Fcom", "Operands": ["dword ptr ds:[eax]"] }]
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64D81425;[{ "Type": "Fcom", "Operands": ["dword ptr fs:[eax]"] }]
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65D81425;[{ "Type": "Fcom", "Operands": ["dword ptr gs:[eax]"] }]
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# FCOMP - Compare floating point values and pop
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D8D8;[{ "Type": "Fcomp", "Operands": ["ST(0)"] }]
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D8D9;[{ "Type": "Fcomp", "Operands": ["ST(1)"] }]
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D8DA;[{ "Type": "Fcomp", "Operands": ["ST(2)"] }]
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D8DB;[{ "Type": "Fcomp", "Operands": ["ST(3)"] }]
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D8DC;[{ "Type": "Fcomp", "Operands": ["ST(4)"] }]
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D8DD;[{ "Type": "Fcomp", "Operands": ["ST(5)"] }]
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D8DE;[{ "Type": "Fcomp", "Operands": ["ST(6)"] }]
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D8DF;[{ "Type": "Fcomp", "Operands": ["ST(7)"] }]
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# Memory operands
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D81C2510000000;[{ "Type": "Fcomp", "Operands": ["dword ptr [0x10]"] }]
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DC1C2510000000;[{ "Type": "Fcomp", "Operands": ["qword ptr [0x10]"] }]
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D81C25;[{ "Type": "Fcomp", "Operands": ["dword ptr [eax]"] }]
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DC1C25;[{ "Type": "Fcomp", "Operands": ["qword ptr [eax]"] }]
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# FCOMPP - Compare floating point values and pop twice
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DED9;[{ "Type": "Fcompp", "Operands": [] }]
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# FCOMI - Compare floating point and set EFLAGS
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DBF0;[{ "Type": "Fcomi", "Operands": ["ST(0)"] }]
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DBF1;[{ "Type": "Fcomi", "Operands": ["ST(1)"] }]
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DBF2;[{ "Type": "Fcomi", "Operands": ["ST(2)"] }]
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DBF3;[{ "Type": "Fcomi", "Operands": ["ST(3)"] }]
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DBF4;[{ "Type": "Fcomi", "Operands": ["ST(4)"] }]
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DBF5;[{ "Type": "Fcomi", "Operands": ["ST(5)"] }]
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DBF6;[{ "Type": "Fcomi", "Operands": ["ST(6)"] }]
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DBF7;[{ "Type": "Fcomi", "Operands": ["ST(7)"] }]
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# FCOMIP - Compare floating point and set EFLAGS and pop
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DFF0;[{ "Type": "Fcomip", "Operands": ["ST(0)"] }]
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DFF1;[{ "Type": "Fcomip", "Operands": ["ST(1)"] }]
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DFF2;[{ "Type": "Fcomip", "Operands": ["ST(2)"] }]
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DFF3;[{ "Type": "Fcomip", "Operands": ["ST(3)"] }]
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DFF4;[{ "Type": "Fcomip", "Operands": ["ST(4)"] }]
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DFF5;[{ "Type": "Fcomip", "Operands": ["ST(5)"] }]
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DFF6;[{ "Type": "Fcomip", "Operands": ["ST(6)"] }]
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DFF7;[{ "Type": "Fcomip", "Operands": ["ST(7)"] }]
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Can't render this file because it contains an unexpected character in line 6 and column 9.
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46
X86DisassemblerTests/TestData/fdiv_tests.csv
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X86DisassemblerTests/TestData/fdiv_tests.csv
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# FDIV instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# FDIV - Divide floating point values
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# ST(0), ST(i) form (D8 F0+i)
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D8F0;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(0)"] }]
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D8F1;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(1)"] }]
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D8F2;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(2)"] }]
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D8F3;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(3)"] }]
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D8F4;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(4)"] }]
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D8F5;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(5)"] }]
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D8F6;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(6)"] }]
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D8F7;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(7)"] }]
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# ST(i), ST(0) form (DC F8+i)
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DCF8;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(0)"] }]
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DCF9;[{ "Type": "Fdiv", "Operands": ["ST(1)", "ST(0)"] }]
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DCFA;[{ "Type": "Fdiv", "Operands": ["ST(2)", "ST(0)"] }]
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DCFB;[{ "Type": "Fdiv", "Operands": ["ST(3)", "ST(0)"] }]
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DCFC;[{ "Type": "Fdiv", "Operands": ["ST(4)", "ST(0)"] }]
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DCFD;[{ "Type": "Fdiv", "Operands": ["ST(5)", "ST(0)"] }]
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DCFE;[{ "Type": "Fdiv", "Operands": ["ST(6)", "ST(0)"] }]
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DCFF;[{ "Type": "Fdiv", "Operands": ["ST(7)", "ST(0)"] }]
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# Memory operands
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D8342510000000;[{ "Type": "Fdiv", "Operands": ["dword ptr [0x10]"] }]
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DC342510000000;[{ "Type": "Fdiv", "Operands": ["qword ptr [0x10]"] }]
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D83425;[{ "Type": "Fdiv", "Operands": ["dword ptr [eax]"] }]
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DC3425;[{ "Type": "Fdiv", "Operands": ["qword ptr [eax]"] }]
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# FDIVP - Divide floating point values and pop
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DEF8;[{ "Type": "Fdivp", "Operands": ["ST(0)", "ST(0)"] }]
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DEF9;[{ "Type": "Fdivp", "Operands": ["ST(1)", "ST(0)"] }]
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DEFA;[{ "Type": "Fdivp", "Operands": ["ST(2)", "ST(0)"] }]
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DEFB;[{ "Type": "Fdivp", "Operands": ["ST(3)", "ST(0)"] }]
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DEFC;[{ "Type": "Fdivp", "Operands": ["ST(4)", "ST(0)"] }]
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DEFD;[{ "Type": "Fdivp", "Operands": ["ST(5)", "ST(0)"] }]
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DEFE;[{ "Type": "Fdivp", "Operands": ["ST(6)", "ST(0)"] }]
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DEFF;[{ "Type": "Fdivp", "Operands": ["ST(7)", "ST(0)"] }]
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# FIDIV - Divide integer by floating point
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DA342510000000;[{ "Type": "Fidiv", "Operands": ["dword ptr [0x10]"] }]
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DE342510000000;[{ "Type": "Fidiv", "Operands": ["word ptr [0x10]"] }]
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DA3425;[{ "Type": "Fidiv", "Operands": ["dword ptr [eax]"] }]
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DE3425;[{ "Type": "Fidiv", "Operands": ["word ptr [eax]"] }]
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Can't render this file because it contains an unexpected character in line 7 and column 9.
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46
X86DisassemblerTests/TestData/fdivr_tests.csv
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X86DisassemblerTests/TestData/fdivr_tests.csv
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# FDIVR instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# FDIVR - Divide floating point values (reversed)
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# ST(0), ST(i) form (D8 F8+i)
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D8F8;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(0)"] }]
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D8F9;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(1)"] }]
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D8FA;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(2)"] }]
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D8FB;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(3)"] }]
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D8FC;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(4)"] }]
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D8FD;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(5)"] }]
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D8FE;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(6)"] }]
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D8FF;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(7)"] }]
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# ST(i), ST(0) form (DC F0+i)
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DCF0;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(0)"] }]
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DCF1;[{ "Type": "Fdivr", "Operands": ["ST(1)", "ST(0)"] }]
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DCF2;[{ "Type": "Fdivr", "Operands": ["ST(2)", "ST(0)"] }]
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DCF3;[{ "Type": "Fdivr", "Operands": ["ST(3)", "ST(0)"] }]
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DCF4;[{ "Type": "Fdivr", "Operands": ["ST(4)", "ST(0)"] }]
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DCF5;[{ "Type": "Fdivr", "Operands": ["ST(5)", "ST(0)"] }]
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DCF6;[{ "Type": "Fdivr", "Operands": ["ST(6)", "ST(0)"] }]
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DCF7;[{ "Type": "Fdivr", "Operands": ["ST(7)", "ST(0)"] }]
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# Memory operands
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D83C2510000000;[{ "Type": "Fdivr", "Operands": ["dword ptr [0x10]"] }]
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DC3C2510000000;[{ "Type": "Fdivr", "Operands": ["qword ptr [0x10]"] }]
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D83C25;[{ "Type": "Fdivr", "Operands": ["dword ptr [eax]"] }]
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DC3C25;[{ "Type": "Fdivr", "Operands": ["qword ptr [eax]"] }]
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# FDIVRP - Divide floating point values (reversed) and pop
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DEF0;[{ "Type": "Fdivrp", "Operands": ["ST(0)", "ST(0)"] }]
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DEF1;[{ "Type": "Fdivrp", "Operands": ["ST(1)", "ST(0)"] }]
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DEF2;[{ "Type": "Fdivrp", "Operands": ["ST(2)", "ST(0)"] }]
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DEF3;[{ "Type": "Fdivrp", "Operands": ["ST(3)", "ST(0)"] }]
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DEF4;[{ "Type": "Fdivrp", "Operands": ["ST(4)", "ST(0)"] }]
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DEF5;[{ "Type": "Fdivrp", "Operands": ["ST(5)", "ST(0)"] }]
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DEF6;[{ "Type": "Fdivrp", "Operands": ["ST(6)", "ST(0)"] }]
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DEF7;[{ "Type": "Fdivrp", "Operands": ["ST(7)", "ST(0)"] }]
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# FIDIVR - Divide floating point by integer (reversed)
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DA3C2510000000;[{ "Type": "Fidivr", "Operands": ["dword ptr [0x10]"] }]
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DE3C2510000000;[{ "Type": "Fidivr", "Operands": ["word ptr [0x10]"] }]
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DA3C25;[{ "Type": "Fidivr", "Operands": ["dword ptr [eax]"] }]
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DE3C25;[{ "Type": "Fidivr", "Operands": ["word ptr [eax]"] }]
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Can't render this file because it contains an unexpected character in line 7 and column 9.
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61
X86DisassemblerTests/TestData/fld_fst_tests.csv
Normal file
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X86DisassemblerTests/TestData/fld_fst_tests.csv
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# FLD/FST/FSTP instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# FLD - Load floating point value
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D9C0;[{ "Type": "Fld", "Operands": ["ST(0)"] }]
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D9C1;[{ "Type": "Fld", "Operands": ["ST(1)"] }]
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D9C2;[{ "Type": "Fld", "Operands": ["ST(2)"] }]
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D9C3;[{ "Type": "Fld", "Operands": ["ST(3)"] }]
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D9C4;[{ "Type": "Fld", "Operands": ["ST(4)"] }]
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D9C5;[{ "Type": "Fld", "Operands": ["ST(5)"] }]
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D9C6;[{ "Type": "Fld", "Operands": ["ST(6)"] }]
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D9C7;[{ "Type": "Fld", "Operands": ["ST(7)"] }]
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# Memory operands
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D9042510000000;[{ "Type": "Fld", "Operands": ["dword ptr [0x10]"] }]
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DD042510000000;[{ "Type": "Fld", "Operands": ["qword ptr [0x10]"] }]
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DB2C25;[{ "Type": "Fld", "Operands": ["tbyte ptr [eax]"] }]
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D90425;[{ "Type": "Fld", "Operands": ["dword ptr [eax]"] }]
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DD0425;[{ "Type": "Fld", "Operands": ["qword ptr [eax]"] }]
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# With segment override prefixes
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26D90425;[{ "Type": "Fld", "Operands": ["dword ptr es:[eax]"] }]
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2ED90425;[{ "Type": "Fld", "Operands": ["dword ptr cs:[eax]"] }]
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36D90425;[{ "Type": "Fld", "Operands": ["dword ptr ss:[eax]"] }]
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3ED90425;[{ "Type": "Fld", "Operands": ["dword ptr ds:[eax]"] }]
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64D90425;[{ "Type": "Fld", "Operands": ["dword ptr fs:[eax]"] }]
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65D90425;[{ "Type": "Fld", "Operands": ["dword ptr gs:[eax]"] }]
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# FST - Store floating point value
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D9D0;[{ "Type": "Fst", "Operands": ["ST(0)"] }]
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D9D1;[{ "Type": "Fst", "Operands": ["ST(1)"] }]
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D9D2;[{ "Type": "Fst", "Operands": ["ST(2)"] }]
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D9D3;[{ "Type": "Fst", "Operands": ["ST(3)"] }]
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D9D4;[{ "Type": "Fst", "Operands": ["ST(4)"] }]
|
||||
D9D5;[{ "Type": "Fst", "Operands": ["ST(5)"] }]
|
||||
D9D6;[{ "Type": "Fst", "Operands": ["ST(6)"] }]
|
||||
D9D7;[{ "Type": "Fst", "Operands": ["ST(7)"] }]
|
||||
|
||||
# Memory operands
|
||||
D9142510000000;[{ "Type": "Fst", "Operands": ["dword ptr [0x10]"] }]
|
||||
DD142510000000;[{ "Type": "Fst", "Operands": ["qword ptr [0x10]"] }]
|
||||
D91425;[{ "Type": "Fst", "Operands": ["dword ptr [eax]"] }]
|
||||
DD1425;[{ "Type": "Fst", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FSTP - Store floating point value and pop
|
||||
D9D8;[{ "Type": "Fstp", "Operands": ["ST(0)"] }]
|
||||
D9D9;[{ "Type": "Fstp", "Operands": ["ST(1)"] }]
|
||||
D9DA;[{ "Type": "Fstp", "Operands": ["ST(2)"] }]
|
||||
D9DB;[{ "Type": "Fstp", "Operands": ["ST(3)"] }]
|
||||
D9DC;[{ "Type": "Fstp", "Operands": ["ST(4)"] }]
|
||||
D9DD;[{ "Type": "Fstp", "Operands": ["ST(5)"] }]
|
||||
D9DE;[{ "Type": "Fstp", "Operands": ["ST(6)"] }]
|
||||
D9DF;[{ "Type": "Fstp", "Operands": ["ST(7)"] }]
|
||||
|
||||
# Memory operands
|
||||
D91C2510000000;[{ "Type": "Fstp", "Operands": ["dword ptr [0x10]"] }]
|
||||
DD1C2510000000;[{ "Type": "Fstp", "Operands": ["qword ptr [0x10]"] }]
|
||||
DB3C25;[{ "Type": "Fstp", "Operands": ["tbyte ptr [eax]"] }]
|
||||
D91C25;[{ "Type": "Fstp", "Operands": ["dword ptr [eax]"] }]
|
||||
DD1C25;[{ "Type": "Fstp", "Operands": ["qword ptr [eax]"] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 6 and column 9.
|
46
X86DisassemblerTests/TestData/fmul_tests.csv
Normal file
46
X86DisassemblerTests/TestData/fmul_tests.csv
Normal file
@ -0,0 +1,46 @@
|
||||
# FMUL instruction tests
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FMUL - Multiply floating point values
|
||||
# ST(0), ST(i) form (D8 C8+i)
|
||||
D8C8;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8C9;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8CA;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8CB;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
D8CC;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(4)"] }]
|
||||
D8CD;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(5)"] }]
|
||||
D8CE;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(6)"] }]
|
||||
D8CF;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(7)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC C8+i)
|
||||
DCC8;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCC9;[{ "Type": "Fmul", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCCA;[{ "Type": "Fmul", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCCB;[{ "Type": "Fmul", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DCCC;[{ "Type": "Fmul", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DCCD;[{ "Type": "Fmul", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DCCE;[{ "Type": "Fmul", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DCCF;[{ "Type": "Fmul", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D80C2510000000;[{ "Type": "Fmul", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC0C2510000000;[{ "Type": "Fmul", "Operands": ["qword ptr [0x10]"] }]
|
||||
D80C25;[{ "Type": "Fmul", "Operands": ["dword ptr [eax]"] }]
|
||||
DC0C25;[{ "Type": "Fmul", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FMULP - Multiply floating point values and pop
|
||||
DEC8;[{ "Type": "Fmulp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEC9;[{ "Type": "Fmulp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DECA;[{ "Type": "Fmulp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DECB;[{ "Type": "Fmulp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DECC;[{ "Type": "Fmulp", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DECD;[{ "Type": "Fmulp", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DECE;[{ "Type": "Fmulp", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DECF;[{ "Type": "Fmulp", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# FIMUL - Multiply integer with floating point
|
||||
DA0C2510000000;[{ "Type": "Fimul", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE0C2510000000;[{ "Type": "Fimul", "Operands": ["word ptr [0x10]"] }]
|
||||
DA0C25;[{ "Type": "Fimul", "Operands": ["dword ptr [eax]"] }]
|
||||
DE0C25;[{ "Type": "Fimul", "Operands": ["word ptr [eax]"] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 9.
|
75
X86DisassemblerTests/TestData/fpu_misc_tests.csv
Normal file
75
X86DisassemblerTests/TestData/fpu_misc_tests.csv
Normal file
@ -0,0 +1,75 @@
|
||||
# Miscellaneous FPU instruction tests
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FCHS - Change sign of floating point value
|
||||
D9E0;[{ "Type": "Fchs", "Operands": [] }]
|
||||
|
||||
# FABS - Absolute value of floating point value
|
||||
D9E1;[{ "Type": "Fabs", "Operands": [] }]
|
||||
|
||||
# FTST - Test floating point value
|
||||
D9E4;[{ "Type": "Ftst", "Operands": [] }]
|
||||
|
||||
# FXAM - Examine floating point value
|
||||
D9E5;[{ "Type": "Fxam", "Operands": [] }]
|
||||
|
||||
# FINIT - Initialize FPU (with FWAIT prefix)
|
||||
9BDBE3;[{ "Type": "Finit", "Operands": [] }]
|
||||
|
||||
# FNINIT - Initialize FPU without checking for pending unmasked exceptions
|
||||
DBE3;[{ "Type": "Fninit", "Operands": [] }]
|
||||
|
||||
# FXCH - Exchange floating point registers
|
||||
D9C8;[{ "Type": "Fxch", "Operands": ["ST(0)"] }]
|
||||
D9C9;[{ "Type": "Fxch", "Operands": ["ST(1)"] }]
|
||||
D9CA;[{ "Type": "Fxch", "Operands": ["ST(2)"] }]
|
||||
D9CB;[{ "Type": "Fxch", "Operands": ["ST(3)"] }]
|
||||
D9CC;[{ "Type": "Fxch", "Operands": ["ST(4)"] }]
|
||||
D9CD;[{ "Type": "Fxch", "Operands": ["ST(5)"] }]
|
||||
D9CE;[{ "Type": "Fxch", "Operands": ["ST(6)"] }]
|
||||
D9CF;[{ "Type": "Fxch", "Operands": ["ST(7)"] }]
|
||||
|
||||
# FCLEX - Clear floating-point exceptions
|
||||
9BDBE2;[{ "Type": "Fclex", "Operands": [] }]
|
||||
|
||||
# FNCLEX - Clear floating-point exceptions without checking for pending unmasked exceptions
|
||||
DBE2;[{ "Type": "Fnclex", "Operands": [] }]
|
||||
|
||||
# FLDCW - Load FPU control word
|
||||
D92C2510000000;[{ "Type": "Fldcw", "Operands": ["word ptr [0x10]"] }]
|
||||
D92C25;[{ "Type": "Fldcw", "Operands": ["word ptr [eax]"] }]
|
||||
|
||||
# FNSTCW - Store FPU control word without checking for pending unmasked exceptions
|
||||
D93C2510000000;[{ "Type": "Fnstcw", "Operands": ["word ptr [0x10]"] }]
|
||||
D93C25;[{ "Type": "Fnstcw", "Operands": ["word ptr [eax]"] }]
|
||||
|
||||
# FLDENV - Load FPU environment
|
||||
D92425;[{ "Type": "Fldenv", "Operands": ["dword ptr [eax]"] }]
|
||||
|
||||
# FNSTENV - Store FPU environment without checking for pending unmasked exceptions
|
||||
D93425;[{ "Type": "Fnstenv", "Operands": ["dword ptr [eax]"] }]
|
||||
|
||||
# FRSTOR - Restore FPU state
|
||||
DD2425;[{ "Type": "Frstor", "Operands": ["dword ptr [eax]"] }]
|
||||
|
||||
# FNSAVE - Save FPU state without checking for pending unmasked exceptions
|
||||
DD3425;[{ "Type": "Fnsave", "Operands": ["dword ptr [eax]"] }]
|
||||
|
||||
# F2XM1 - 2^x - 1
|
||||
D9F0;[{ "Type": "F2xm1", "Operands": [] }]
|
||||
|
||||
# FYL2X - y * log2(x)
|
||||
D9F1;[{ "Type": "Fyl2x", "Operands": [] }]
|
||||
|
||||
# FPTAN - Partial tangent
|
||||
D9F2;[{ "Type": "Fptan", "Operands": [] }]
|
||||
|
||||
# FPATAN - Partial arctangent
|
||||
D9F3;[{ "Type": "Fpatan", "Operands": [] }]
|
||||
|
||||
# FXTRACT - Extract exponent and significand
|
||||
D9F4;[{ "Type": "Fxtract", "Operands": [] }]
|
||||
|
||||
# FPREM1 - Partial remainder (IEEE)
|
||||
D9F5;[{ "Type": "Fprem1", "Operands": [] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 6 and column 9.
|
@ -1,356 +0,0 @@
|
||||
# Floating Point instruction tests
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# Basic FPU instructions
|
||||
|
||||
# FADD - Add floating point values
|
||||
# ST(0), ST(i) form (D8 C0+i)
|
||||
D8C0;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8C1;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8C2;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8C3;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
D8C4;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(4)"] }]
|
||||
D8C5;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(5)"] }]
|
||||
D8C6;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(6)"] }]
|
||||
D8C7;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(7)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC C0+i)
|
||||
DCC0;[{ "Type": "Fadd", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCC1;[{ "Type": "Fadd", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCC2;[{ "Type": "Fadd", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCC3;[{ "Type": "Fadd", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DCC4;[{ "Type": "Fadd", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DCC5;[{ "Type": "Fadd", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DCC6;[{ "Type": "Fadd", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DCC7;[{ "Type": "Fadd", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D8042510000000;[{ "Type": "Fadd", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC042510000000;[{ "Type": "Fadd", "Operands": ["qword ptr [0x10]"] }]
|
||||
D80425;[{ "Type": "Fadd", "Operands": ["dword ptr [eax]"] }]
|
||||
DC0425;[{ "Type": "Fadd", "Operands": ["qword ptr [eax]"] }]
|
||||
D8041D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebx]"] }]
|
||||
DC041D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebx]"] }]
|
||||
D8042D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebp]"] }]
|
||||
DC042D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebp]"] }]
|
||||
|
||||
# With segment override prefixes
|
||||
26D80425;[{ "Type": "Fadd", "Operands": ["dword ptr es:[eax]"] }]
|
||||
2ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr cs:[eax]"] }]
|
||||
36D80425;[{ "Type": "Fadd", "Operands": ["dword ptr ss:[eax]"] }]
|
||||
3ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr ds:[eax]"] }]
|
||||
64D80425;[{ "Type": "Fadd", "Operands": ["dword ptr fs:[eax]"] }]
|
||||
65D80425;[{ "Type": "Fadd", "Operands": ["dword ptr gs:[eax]"] }]
|
||||
|
||||
# FADDP - Add floating point values and pop
|
||||
DEC0;[{ "Type": "Faddp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEC1;[{ "Type": "Faddp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DEC2;[{ "Type": "Faddp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DEC3;[{ "Type": "Faddp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DEC4;[{ "Type": "Faddp", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DEC5;[{ "Type": "Faddp", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DEC6;[{ "Type": "Faddp", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DEC7;[{ "Type": "Faddp", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# FIADD - Add integer to floating point
|
||||
DA042510000000;[{ "Type": "Fiadd", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE042510000000;[{ "Type": "Fiadd", "Operands": ["word ptr [0x10]"] }]
|
||||
DA0425;[{ "Type": "Fiadd", "Operands": ["dword ptr [eax]"] }]
|
||||
DE0425;[{ "Type": "Fiadd", "Operands": ["word ptr [eax]"] }]
|
||||
DA041D;[{ "Type": "Fiadd", "Operands": ["dword ptr [ebx]"] }]
|
||||
DE041D;[{ "Type": "Fiadd", "Operands": ["word ptr [ebx]"] }]
|
||||
# Floating Point instruction tests (continued)
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FSUB - Subtract floating point values
|
||||
# ST(0), ST(i) form (D8 E0+i)
|
||||
D8E0;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8E1;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8E2;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8E3;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
D8E4;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(4)"] }]
|
||||
D8E5;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(5)"] }]
|
||||
D8E6;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(6)"] }]
|
||||
D8E7;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(7)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC E8+i)
|
||||
DCE8;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCE9;[{ "Type": "Fsub", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCEA;[{ "Type": "Fsub", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCEB;[{ "Type": "Fsub", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DCEC;[{ "Type": "Fsub", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DCED;[{ "Type": "Fsub", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DCEE;[{ "Type": "Fsub", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DCEF;[{ "Type": "Fsub", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D8242510000000;[{ "Type": "Fsub", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC242510000000;[{ "Type": "Fsub", "Operands": ["qword ptr [0x10]"] }]
|
||||
D82425;[{ "Type": "Fsub", "Operands": ["dword ptr [eax]"] }]
|
||||
DC2425;[{ "Type": "Fsub", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FSUBP - Subtract floating point values and pop
|
||||
DEE8;[{ "Type": "Fsubp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEE9;[{ "Type": "Fsubp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DEEA;[{ "Type": "Fsubp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DEEB;[{ "Type": "Fsubp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
|
||||
# FISUB - Subtract integer from floating point
|
||||
DA242510000000;[{ "Type": "Fisub", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE242510000000;[{ "Type": "Fisub", "Operands": ["word ptr [0x10]"] }]
|
||||
DA2425;[{ "Type": "Fisub", "Operands": ["dword ptr [eax]"] }]
|
||||
DE2425;[{ "Type": "Fisub", "Operands": ["word ptr [eax]"] }]
|
||||
|
||||
# FSUBR - Subtract floating point values (reversed)
|
||||
# ST(0), ST(i) form (D8 E8+i)
|
||||
D8E8;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8E9;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8EA;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8EB;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC E0+i)
|
||||
DCE0;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCE1;[{ "Type": "Fsubr", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCE2;[{ "Type": "Fsubr", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCE3;[{ "Type": "Fsubr", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D82C2510000000;[{ "Type": "Fsubr", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC2C2510000000;[{ "Type": "Fsubr", "Operands": ["qword ptr [0x10]"] }]
|
||||
D82C25;[{ "Type": "Fsubr", "Operands": ["dword ptr [eax]"] }]
|
||||
DC2C25;[{ "Type": "Fsubr", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FSUBRP - Subtract floating point values (reversed) and pop
|
||||
DEE0;[{ "Type": "Fsubrp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEE1;[{ "Type": "Fsubrp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DEE2;[{ "Type": "Fsubrp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DEE3;[{ "Type": "Fsubrp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
# Floating Point instruction tests (continued)
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FMUL - Multiply floating point values
|
||||
# ST(0), ST(i) form (D8 C8+i)
|
||||
D8C8;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8C9;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8CA;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8CB;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
D8CC;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(4)"] }]
|
||||
D8CD;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(5)"] }]
|
||||
D8CE;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(6)"] }]
|
||||
D8CF;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(7)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC C8+i)
|
||||
DCC8;[{ "Type": "Fmul", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCC9;[{ "Type": "Fmul", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCCA;[{ "Type": "Fmul", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCCB;[{ "Type": "Fmul", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DCCC;[{ "Type": "Fmul", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DCCD;[{ "Type": "Fmul", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DCCE;[{ "Type": "Fmul", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DCCF;[{ "Type": "Fmul", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D80C2510000000;[{ "Type": "Fmul", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC0C2510000000;[{ "Type": "Fmul", "Operands": ["qword ptr [0x10]"] }]
|
||||
D80C25;[{ "Type": "Fmul", "Operands": ["dword ptr [eax]"] }]
|
||||
DC0C25;[{ "Type": "Fmul", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FMULP - Multiply floating point values and pop
|
||||
DEC8;[{ "Type": "Fmulp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEC9;[{ "Type": "Fmulp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DECA;[{ "Type": "Fmulp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DECB;[{ "Type": "Fmulp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
|
||||
# FIMUL - Multiply integer with floating point
|
||||
DA0C2510000000;[{ "Type": "Fimul", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE0C2510000000;[{ "Type": "Fimul", "Operands": ["word ptr [0x10]"] }]
|
||||
DA0C25;[{ "Type": "Fimul", "Operands": ["dword ptr [eax]"] }]
|
||||
DE0C25;[{ "Type": "Fimul", "Operands": ["word ptr [eax]"] }]
|
||||
|
||||
# FDIV - Divide floating point values
|
||||
# ST(0), ST(i) form (D8 F0+i)
|
||||
D8F0;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8F1;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8F2;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8F3;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
D8F4;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(4)"] }]
|
||||
D8F5;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(5)"] }]
|
||||
D8F6;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(6)"] }]
|
||||
D8F7;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(7)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC F8+i)
|
||||
DCF8;[{ "Type": "Fdiv", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCF9;[{ "Type": "Fdiv", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCFA;[{ "Type": "Fdiv", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCFB;[{ "Type": "Fdiv", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DCFC;[{ "Type": "Fdiv", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DCFD;[{ "Type": "Fdiv", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DCFE;[{ "Type": "Fdiv", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DCFF;[{ "Type": "Fdiv", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D8342510000000;[{ "Type": "Fdiv", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC342510000000;[{ "Type": "Fdiv", "Operands": ["qword ptr [0x10]"] }]
|
||||
D83425;[{ "Type": "Fdiv", "Operands": ["dword ptr [eax]"] }]
|
||||
DC3425;[{ "Type": "Fdiv", "Operands": ["qword ptr [eax]"] }]
|
||||
# Floating Point instruction tests (continued)
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FDIVP - Divide floating point values and pop
|
||||
DEF8;[{ "Type": "Fdivp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEF9;[{ "Type": "Fdivp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DEFA;[{ "Type": "Fdivp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DEFB;[{ "Type": "Fdivp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
|
||||
# FIDIV - Divide integer by floating point
|
||||
DA342510000000;[{ "Type": "Fidiv", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE342510000000;[{ "Type": "Fidiv", "Operands": ["word ptr [0x10]"] }]
|
||||
DA3425;[{ "Type": "Fidiv", "Operands": ["dword ptr [eax]"] }]
|
||||
DE3425;[{ "Type": "Fidiv", "Operands": ["word ptr [eax]"] }]
|
||||
|
||||
# FDIVR - Divide floating point values (reversed)
|
||||
# ST(0), ST(i) form (D8 F8+i)
|
||||
D8F8;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8F9;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8FA;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8FB;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC F0+i)
|
||||
DCF0;[{ "Type": "Fdivr", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCF1;[{ "Type": "Fdivr", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCF2;[{ "Type": "Fdivr", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCF3;[{ "Type": "Fdivr", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D83C2510000000;[{ "Type": "Fdivr", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC3C2510000000;[{ "Type": "Fdivr", "Operands": ["qword ptr [0x10]"] }]
|
||||
D83C25;[{ "Type": "Fdivr", "Operands": ["dword ptr [eax]"] }]
|
||||
DC3C25;[{ "Type": "Fdivr", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FDIVRP - Divide floating point values (reversed) and pop
|
||||
DEF0;[{ "Type": "Fdivrp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEF1;[{ "Type": "Fdivrp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DEF2;[{ "Type": "Fdivrp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DEF3;[{ "Type": "Fdivrp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
|
||||
# FIDIVR - Divide floating point by integer (reversed)
|
||||
DA3C2510000000;[{ "Type": "Fidivr", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE3C2510000000;[{ "Type": "Fidivr", "Operands": ["word ptr [0x10]"] }]
|
||||
DA3C25;[{ "Type": "Fidivr", "Operands": ["dword ptr [eax]"] }]
|
||||
DE3C25;[{ "Type": "Fidivr", "Operands": ["word ptr [eax]"] }]
|
||||
|
||||
# FLD - Load floating point value
|
||||
D9C0;[{ "Type": "Fld", "Operands": ["ST(0)"] }]
|
||||
D9C1;[{ "Type": "Fld", "Operands": ["ST(1)"] }]
|
||||
D9C2;[{ "Type": "Fld", "Operands": ["ST(2)"] }]
|
||||
D9C3;[{ "Type": "Fld", "Operands": ["ST(3)"] }]
|
||||
D9C4;[{ "Type": "Fld", "Operands": ["ST(4)"] }]
|
||||
D9C5;[{ "Type": "Fld", "Operands": ["ST(5)"] }]
|
||||
D9C6;[{ "Type": "Fld", "Operands": ["ST(6)"] }]
|
||||
D9C7;[{ "Type": "Fld", "Operands": ["ST(7)"] }]
|
||||
|
||||
# Memory operands
|
||||
D9042510000000;[{ "Type": "Fld", "Operands": ["dword ptr [0x10]"] }]
|
||||
DD042510000000;[{ "Type": "Fld", "Operands": ["qword ptr [0x10]"] }]
|
||||
DB2C25;[{ "Type": "Fld", "Operands": ["tbyte ptr [eax]"] }]
|
||||
D90425;[{ "Type": "Fld", "Operands": ["dword ptr [eax]"] }]
|
||||
DD0425;[{ "Type": "Fld", "Operands": ["qword ptr [eax]"] }]
|
||||
# Floating Point instruction tests (continued)
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FST - Store floating point value
|
||||
D9D0;[{ "Type": "Fst", "Operands": ["ST(0)"] }]
|
||||
D9D1;[{ "Type": "Fst", "Operands": ["ST(1)"] }]
|
||||
D9D2;[{ "Type": "Fst", "Operands": ["ST(2)"] }]
|
||||
D9D3;[{ "Type": "Fst", "Operands": ["ST(3)"] }]
|
||||
D9D4;[{ "Type": "Fst", "Operands": ["ST(4)"] }]
|
||||
D9D5;[{ "Type": "Fst", "Operands": ["ST(5)"] }]
|
||||
D9D6;[{ "Type": "Fst", "Operands": ["ST(6)"] }]
|
||||
D9D7;[{ "Type": "Fst", "Operands": ["ST(7)"] }]
|
||||
|
||||
# Memory operands
|
||||
D9142510000000;[{ "Type": "Fst", "Operands": ["dword ptr [0x10]"] }]
|
||||
DD142510000000;[{ "Type": "Fst", "Operands": ["qword ptr [0x10]"] }]
|
||||
D91425;[{ "Type": "Fst", "Operands": ["dword ptr [eax]"] }]
|
||||
DD1425;[{ "Type": "Fst", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FSTP - Store floating point value and pop
|
||||
D9D8;[{ "Type": "Fstp", "Operands": ["ST(0)"] }]
|
||||
D9D9;[{ "Type": "Fstp", "Operands": ["ST(1)"] }]
|
||||
D9DA;[{ "Type": "Fstp", "Operands": ["ST(2)"] }]
|
||||
D9DB;[{ "Type": "Fstp", "Operands": ["ST(3)"] }]
|
||||
D9DC;[{ "Type": "Fstp", "Operands": ["ST(4)"] }]
|
||||
D9DD;[{ "Type": "Fstp", "Operands": ["ST(5)"] }]
|
||||
D9DE;[{ "Type": "Fstp", "Operands": ["ST(6)"] }]
|
||||
D9DF;[{ "Type": "Fstp", "Operands": ["ST(7)"] }]
|
||||
|
||||
# Memory operands
|
||||
D91C2510000000;[{ "Type": "Fstp", "Operands": ["dword ptr [0x10]"] }]
|
||||
DD1C2510000000;[{ "Type": "Fstp", "Operands": ["qword ptr [0x10]"] }]
|
||||
DB3C25;[{ "Type": "Fstp", "Operands": ["tbyte ptr [eax]"] }]
|
||||
D91C25;[{ "Type": "Fstp", "Operands": ["dword ptr [eax]"] }]
|
||||
DD1C25;[{ "Type": "Fstp", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FCOM - Compare floating point values
|
||||
D8D0;[{ "Type": "Fcom", "Operands": ["ST(0)"] }]
|
||||
D8D1;[{ "Type": "Fcom", "Operands": ["ST(1)"] }]
|
||||
D8D2;[{ "Type": "Fcom", "Operands": ["ST(2)"] }]
|
||||
D8D3;[{ "Type": "Fcom", "Operands": ["ST(3)"] }]
|
||||
D8D4;[{ "Type": "Fcom", "Operands": ["ST(4)"] }]
|
||||
D8D5;[{ "Type": "Fcom", "Operands": ["ST(5)"] }]
|
||||
D8D6;[{ "Type": "Fcom", "Operands": ["ST(6)"] }]
|
||||
D8D7;[{ "Type": "Fcom", "Operands": ["ST(7)"] }]
|
||||
|
||||
# Memory operands
|
||||
D8142510000000;[{ "Type": "Fcom", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC142510000000;[{ "Type": "Fcom", "Operands": ["qword ptr [0x10]"] }]
|
||||
D81425;[{ "Type": "Fcom", "Operands": ["dword ptr [eax]"] }]
|
||||
DC1425;[{ "Type": "Fcom", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FCOMP - Compare floating point values and pop
|
||||
D8D8;[{ "Type": "Fcomp", "Operands": ["ST(0)"] }]
|
||||
D8D9;[{ "Type": "Fcomp", "Operands": ["ST(1)"] }]
|
||||
D8DA;[{ "Type": "Fcomp", "Operands": ["ST(2)"] }]
|
||||
D8DB;[{ "Type": "Fcomp", "Operands": ["ST(3)"] }]
|
||||
D8DC;[{ "Type": "Fcomp", "Operands": ["ST(4)"] }]
|
||||
D8DD;[{ "Type": "Fcomp", "Operands": ["ST(5)"] }]
|
||||
D8DE;[{ "Type": "Fcomp", "Operands": ["ST(6)"] }]
|
||||
D8DF;[{ "Type": "Fcomp", "Operands": ["ST(7)"] }]
|
||||
|
||||
# Memory operands
|
||||
D81C2510000000;[{ "Type": "Fcomp", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC1C2510000000;[{ "Type": "Fcomp", "Operands": ["qword ptr [0x10]"] }]
|
||||
D81C25;[{ "Type": "Fcomp", "Operands": ["dword ptr [eax]"] }]
|
||||
DC1C25;[{ "Type": "Fcomp", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FCOMPP - Compare floating point values and pop twice
|
||||
DED9;[{ "Type": "Fcompp", "Operands": [] }]
|
||||
|
||||
# FCHS - Change sign of floating point value
|
||||
D9E0;[{ "Type": "Fchs", "Operands": [] }]
|
||||
|
||||
# FABS - Absolute value of floating point value
|
||||
D9E1;[{ "Type": "Fabs", "Operands": [] }]
|
||||
|
||||
# FTST - Test floating point value
|
||||
D9E4;[{ "Type": "Ftst", "Operands": [] }]
|
||||
|
||||
# FXAM - Examine floating point value
|
||||
D9E5;[{ "Type": "Fxam", "Operands": [] }]
|
||||
|
||||
# FINIT - Initialize FPU (with FWAIT prefix)
|
||||
9BDBE3;[{ "Type": "Finit", "Operands": [] }]
|
||||
|
||||
# FNINIT - Initialize FPU without checking for pending unmasked exceptions
|
||||
DBE3;[{ "Type": "Fninit", "Operands": [] }]
|
||||
|
||||
# FNSTSW AX - Store FPU status word in AX without checking for pending unmasked exceptions
|
||||
DFE0;[{ "Type": "Fnstsw", "Operands": ["ax"] }]
|
||||
|
||||
# FSTSW AX - Store FPU status word in AX
|
||||
9BDFE0;[{ "Type": "Fstsw", "Operands": ["ax"] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 9 and column 9.
|
59
X86DisassemblerTests/TestData/fstsw_tests.csv
Normal file
59
X86DisassemblerTests/TestData/fstsw_tests.csv
Normal file
@ -0,0 +1,59 @@
|
||||
# FSTSW/FNSTSW instruction tests
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FNSTSW AX - Store FPU status word in AX without checking for pending unmasked exceptions
|
||||
DFE0;[{ "Type": "Fnstsw", "Operands": ["ax"] }]
|
||||
|
||||
# FSTSW AX - Store FPU status word in AX
|
||||
9BDFE0;[{ "Type": "Fstsw", "Operands": ["ax"] }]
|
||||
|
||||
# FSTSW m2byte - Store FPU status word to memory
|
||||
9BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr [eax]"] }]
|
||||
9BDD3C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
|
||||
9BDD3C2C;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
|
||||
9BDD3C23;[{ "Type": "Fstsw", "Operands": ["word ptr [ebx]"] }]
|
||||
9BDD3C21;[{ "Type": "Fstsw", "Operands": ["word ptr [ecx]"] }]
|
||||
9BDD3C22;[{ "Type": "Fstsw", "Operands": ["word ptr [edx]"] }]
|
||||
9BDD3C26;[{ "Type": "Fstsw", "Operands": ["word ptr [esi]"] }]
|
||||
9BDD3C27;[{ "Type": "Fstsw", "Operands": ["word ptr [edi]"] }]
|
||||
|
||||
# FNSTSW m2byte - Store FPU status word to memory without checking for pending unmasked exceptions
|
||||
DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr [eax]"] }]
|
||||
DD3C24;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp]"] }]
|
||||
DD3C2C;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp]"] }]
|
||||
DD3C23;[{ "Type": "Fnstsw", "Operands": ["word ptr [ebx]"] }]
|
||||
DD3C21;[{ "Type": "Fnstsw", "Operands": ["word ptr [ecx]"] }]
|
||||
DD3C22;[{ "Type": "Fnstsw", "Operands": ["word ptr [edx]"] }]
|
||||
DD3C26;[{ "Type": "Fnstsw", "Operands": ["word ptr [esi]"] }]
|
||||
DD3C27;[{ "Type": "Fnstsw", "Operands": ["word ptr [edi]"] }]
|
||||
|
||||
# FSTSW/FNSTSW with displacement
|
||||
9BDD7C2510000000;[{ "Type": "Fstsw", "Operands": ["word ptr [eax+0x10]"] }]
|
||||
9BDD7C2520000000;[{ "Type": "Fstsw", "Operands": ["word ptr [eax+0x20]"] }]
|
||||
DD7C2510000000;[{ "Type": "Fnstsw", "Operands": ["word ptr [eax+0x10]"] }]
|
||||
DD7C2520000000;[{ "Type": "Fnstsw", "Operands": ["word ptr [eax+0x20]"] }]
|
||||
|
||||
# FSTSW/FNSTSW with SIB addressing
|
||||
9BDD3C04;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+eax*1]"] }]
|
||||
9BDD3C4C;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+ecx*2]"] }]
|
||||
9BDD3C94;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+edx*4]"] }]
|
||||
9BDD3CDC;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+ebx*8]"] }]
|
||||
DD3C04;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+eax*1]"] }]
|
||||
DD3C4C;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+ecx*2]"] }]
|
||||
DD3C94;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+edx*4]"] }]
|
||||
DD3CDC;[{ "Type": "Fnstsw", "Operands": ["word ptr [esp+ebx*8]"] }]
|
||||
|
||||
# FSTSW/FNSTSW with segment override prefixes
|
||||
269BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr es:[eax]"] }]
|
||||
2E9BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr cs:[eax]"] }]
|
||||
369BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr ss:[eax]"] }]
|
||||
3E9BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr ds:[eax]"] }]
|
||||
649BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr fs:[eax]"] }]
|
||||
659BDD3C25;[{ "Type": "Fstsw", "Operands": ["word ptr gs:[eax]"] }]
|
||||
26DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr es:[eax]"] }]
|
||||
2EDD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr cs:[eax]"] }]
|
||||
36DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr ss:[eax]"] }]
|
||||
3EDD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr ds:[eax]"] }]
|
||||
64DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr fs:[eax]"] }]
|
||||
65DD3C25;[{ "Type": "Fnstsw", "Operands": ["word ptr gs:[eax]"] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 6 and column 9.
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46
X86DisassemblerTests/TestData/fsub_tests.csv
Normal file
46
X86DisassemblerTests/TestData/fsub_tests.csv
Normal file
@ -0,0 +1,46 @@
|
||||
# FSUB instruction tests
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FSUB - Subtract floating point values
|
||||
# ST(0), ST(i) form (D8 E0+i)
|
||||
D8E0;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8E1;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8E2;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8E3;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
D8E4;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(4)"] }]
|
||||
D8E5;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(5)"] }]
|
||||
D8E6;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(6)"] }]
|
||||
D8E7;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(7)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC E8+i)
|
||||
DCE8;[{ "Type": "Fsub", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCE9;[{ "Type": "Fsub", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCEA;[{ "Type": "Fsub", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCEB;[{ "Type": "Fsub", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DCEC;[{ "Type": "Fsub", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DCED;[{ "Type": "Fsub", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DCEE;[{ "Type": "Fsub", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DCEF;[{ "Type": "Fsub", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D8242510000000;[{ "Type": "Fsub", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC242510000000;[{ "Type": "Fsub", "Operands": ["qword ptr [0x10]"] }]
|
||||
D82425;[{ "Type": "Fsub", "Operands": ["dword ptr [eax]"] }]
|
||||
DC2425;[{ "Type": "Fsub", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FSUBP - Subtract floating point values and pop
|
||||
DEE8;[{ "Type": "Fsubp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEE9;[{ "Type": "Fsubp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DEEA;[{ "Type": "Fsubp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DEEB;[{ "Type": "Fsubp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DEEC;[{ "Type": "Fsubp", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DEED;[{ "Type": "Fsubp", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DEEE;[{ "Type": "Fsubp", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DEEF;[{ "Type": "Fsubp", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# FISUB - Subtract integer from floating point
|
||||
DA242510000000;[{ "Type": "Fisub", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE242510000000;[{ "Type": "Fisub", "Operands": ["word ptr [0x10]"] }]
|
||||
DA2425;[{ "Type": "Fisub", "Operands": ["dword ptr [eax]"] }]
|
||||
DE2425;[{ "Type": "Fisub", "Operands": ["word ptr [eax]"] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 9.
|
46
X86DisassemblerTests/TestData/fsubr_tests.csv
Normal file
46
X86DisassemblerTests/TestData/fsubr_tests.csv
Normal file
@ -0,0 +1,46 @@
|
||||
# FSUBR instruction tests
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# FSUBR - Subtract floating point values (reversed)
|
||||
# ST(0), ST(i) form (D8 E8+i)
|
||||
D8E8;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
D8E9;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(1)"] }]
|
||||
D8EA;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(2)"] }]
|
||||
D8EB;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(3)"] }]
|
||||
D8EC;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(4)"] }]
|
||||
D8ED;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(5)"] }]
|
||||
D8EE;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(6)"] }]
|
||||
D8EF;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(7)"] }]
|
||||
|
||||
# ST(i), ST(0) form (DC E0+i)
|
||||
DCE0;[{ "Type": "Fsubr", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DCE1;[{ "Type": "Fsubr", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DCE2;[{ "Type": "Fsubr", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DCE3;[{ "Type": "Fsubr", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DCE4;[{ "Type": "Fsubr", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DCE5;[{ "Type": "Fsubr", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DCE6;[{ "Type": "Fsubr", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DCE7;[{ "Type": "Fsubr", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# Memory operands
|
||||
D82C2510000000;[{ "Type": "Fsubr", "Operands": ["dword ptr [0x10]"] }]
|
||||
DC2C2510000000;[{ "Type": "Fsubr", "Operands": ["qword ptr [0x10]"] }]
|
||||
D82C25;[{ "Type": "Fsubr", "Operands": ["dword ptr [eax]"] }]
|
||||
DC2C25;[{ "Type": "Fsubr", "Operands": ["qword ptr [eax]"] }]
|
||||
|
||||
# FSUBRP - Subtract floating point values (reversed) and pop
|
||||
DEE0;[{ "Type": "Fsubrp", "Operands": ["ST(0)", "ST(0)"] }]
|
||||
DEE1;[{ "Type": "Fsubrp", "Operands": ["ST(1)", "ST(0)"] }]
|
||||
DEE2;[{ "Type": "Fsubrp", "Operands": ["ST(2)", "ST(0)"] }]
|
||||
DEE3;[{ "Type": "Fsubrp", "Operands": ["ST(3)", "ST(0)"] }]
|
||||
DEE4;[{ "Type": "Fsubrp", "Operands": ["ST(4)", "ST(0)"] }]
|
||||
DEE5;[{ "Type": "Fsubrp", "Operands": ["ST(5)", "ST(0)"] }]
|
||||
DEE6;[{ "Type": "Fsubrp", "Operands": ["ST(6)", "ST(0)"] }]
|
||||
DEE7;[{ "Type": "Fsubrp", "Operands": ["ST(7)", "ST(0)"] }]
|
||||
|
||||
# FISUBR - Subtract floating point from integer (reversed)
|
||||
DA2C2510000000;[{ "Type": "Fisubr", "Operands": ["dword ptr [0x10]"] }]
|
||||
DE2C2510000000;[{ "Type": "Fisubr", "Operands": ["word ptr [0x10]"] }]
|
||||
DA2C25;[{ "Type": "Fisubr", "Operands": ["dword ptr [eax]"] }]
|
||||
DE2C25;[{ "Type": "Fisubr", "Operands": ["word ptr [eax]"] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 9.
|
@ -1,60 +0,0 @@
|
||||
# Group 3 instruction tests
|
||||
# Format: RawBytes;Instructions
|
||||
RawBytes;Instructions
|
||||
|
||||
# Group 3 instructions (opcode F6-F7 /0-/7)
|
||||
# TEST, NOT, NEG, MUL, IMUL, DIV, IDIV
|
||||
|
||||
# Group 3 with 8-bit register/memory (opcode F6)
|
||||
# TEST r/m8, imm8 (opcode F6 /0)
|
||||
F6C042;[{ "Type": "Test", "Operands": ["al", "0x42"] }]
|
||||
|
||||
# NOT r/m8 (opcode F6 /2)
|
||||
F6D0;[{ "Type": "Not", "Operands": ["al"] }]
|
||||
|
||||
# NEG r/m8 (opcode F6 /3)
|
||||
F6D8;[{ "Type": "Neg", "Operands": ["al"] }]
|
||||
|
||||
# MUL r/m8 (opcode F6 /4)
|
||||
F6E0;[{ "Type": "Mul", "Operands": ["al"] }]
|
||||
|
||||
# IMUL r/m8 (opcode F6 /5)
|
||||
F6E8;[{ "Type": "Imul", "Operands": ["al"] }]
|
||||
|
||||
# DIV r/m8 (opcode F6 /6)
|
||||
F6F0;[{ "Type": "Div", "Operands": ["al"] }]
|
||||
|
||||
# IDIV r/m8 (opcode F6 /7)
|
||||
F6F8;[{ "Type": "Idiv", "Operands": ["al"] }]
|
||||
|
||||
# Group 3 with 32-bit register/memory (opcode F7)
|
||||
# TEST r/m32, imm32 (opcode F7 /0)
|
||||
F7C078563412;[{ "Type": "Test", "Operands": ["eax", "0x12345678"] }]
|
||||
|
||||
# NOT r/m32 (opcode F7 /2)
|
||||
F7D0;[{ "Type": "Not", "Operands": ["eax"] }]
|
||||
|
||||
# NEG r/m32 (opcode F7 /3)
|
||||
F7D8;[{ "Type": "Neg", "Operands": ["eax"] }]
|
||||
|
||||
# MUL r/m32 (opcode F7 /4)
|
||||
F7E0;[{ "Type": "Mul", "Operands": ["eax"] }]
|
||||
|
||||
# IMUL r/m32 (opcode F7 /5)
|
||||
F7E8;[{ "Type": "Imul", "Operands": ["eax"] }]
|
||||
|
||||
# DIV r/m32 (opcode F7 /6)
|
||||
F7F0;[{ "Type": "Div", "Operands": ["eax"] }]
|
||||
|
||||
# IDIV r/m32 (opcode F7 /7)
|
||||
F7F8;[{ "Type": "Idiv", "Operands": ["eax"] }]
|
||||
|
||||
# Group 3 with memory operands
|
||||
F6042542;[{ "Type": "Test", "Operands": ["byte ptr [eax]", "0x42"] }]
|
||||
F7042578563412;[{ "Type": "Test", "Operands": ["dword ptr [eax]", "0x12345678"] }]
|
||||
F71425;[{ "Type": "Not", "Operands": ["dword ptr [eax]"] }]
|
||||
F71C25;[{ "Type": "Neg", "Operands": ["dword ptr [eax]"] }]
|
||||
F72425;[{ "Type": "Mul", "Operands": ["dword ptr [eax]"] }]
|
||||
F72C25;[{ "Type": "Imul", "Operands": ["dword ptr [eax]"] }]
|
||||
F73425;[{ "Type": "Div", "Operands": ["dword ptr [eax]"] }]
|
||||
F73C25;[{ "Type": "Idiv", "Operands": ["dword ptr [eax]"] }]
|
||||
|
Can't render this file because it contains an unexpected character in line 10 and column 11.
|
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Reference in New Issue
Block a user