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https://github.com/sampletext32/ParkanPlayground.git
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Updated instruction handlers to use Type and StructuredOperands instead of Mnemonic and Operands
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bird_egop
@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -5,95 +7,93 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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public class Int16OperationHandler : InstructionHandler
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{
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// Memory operand mnemonics for DE opcode - operations on int16
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private static readonly string[] MemoryMnemonics =
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// Memory operand instruction types for DE opcode - operations on int16
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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"fiadd", // 0
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"fimul", // 1
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"ficom", // 2
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"ficomp", // 3
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"fisub", // 4
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"fisubr", // 5
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"fidiv", // 6
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"fidivr" // 7
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InstructionType.Unknown, // fiadd - not in enum
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InstructionType.Unknown, // fimul - not in enum
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InstructionType.Unknown, // ficom - not in enum
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InstructionType.Unknown, // ficomp - not in enum
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InstructionType.Unknown, // fisub - not in enum
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InstructionType.Unknown, // fisubr - not in enum
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InstructionType.Unknown, // fidiv - not in enum
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InstructionType.Unknown // fidivr - not in enum
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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private static readonly Dictionary<(int Reg, int Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
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{
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// FADDP st(i), st(0)
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{ (RegisterIndex.A, RegisterIndex.A), ("faddp", "st(0), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("faddp", "st(1), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("faddp", "st(2), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("faddp", "st(3), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("faddp", "st(4), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("faddp", "st(5), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("faddp", "st(6), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("faddp", "st(7), st(0)") },
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{ (0, 0), (InstructionType.Fadd, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (0, 1), (InstructionType.Fadd, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (0, 2), (InstructionType.Fadd, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (0, 3), (InstructionType.Fadd, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (0, 4), (InstructionType.Fadd, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (0, 5), (InstructionType.Fadd, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (0, 6), (InstructionType.Fadd, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (0, 7), (InstructionType.Fadd, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FMULP st(i), st(0)
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{ (RegisterIndex.B, RegisterIndex.A), ("fmulp", "st(0), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.C), ("fmulp", "st(1), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.D), ("fmulp", "st(2), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.B), ("fmulp", "st(3), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Sp), ("fmulp", "st(4), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Bp), ("fmulp", "st(5), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Si), ("fmulp", "st(6), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Di), ("fmulp", "st(7), st(0)") },
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{ (1, 0), (InstructionType.Fmul, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (1, 1), (InstructionType.Fmul, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (1, 2), (InstructionType.Fmul, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (1, 3), (InstructionType.Fmul, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (1, 4), (InstructionType.Fmul, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (1, 5), (InstructionType.Fmul, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (1, 6), (InstructionType.Fmul, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (1, 7), (InstructionType.Fmul, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// Special cases
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{ (RegisterIndex.C, RegisterIndex.B), ("fcomp", "") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fcompp", "") },
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{ (2, 3), (InstructionType.Fcomp, FpuRegisterIndex.ST0, null) },
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{ (3, 3), (InstructionType.Fcompp, FpuRegisterIndex.ST0, null) },
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// FSUBP st(i), st(0)
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{ (RegisterIndex.Si, RegisterIndex.A), ("fsubp", "st(0), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.C), ("fsubp", "st(1), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.D), ("fsubp", "st(2), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.B), ("fsubp", "st(3), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Sp), ("fsubp", "st(4), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Bp), ("fsubp", "st(5), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Si), ("fsubp", "st(6), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Di), ("fsubp", "st(7), st(0)") },
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{ (6, 0), (InstructionType.Fsub, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (6, 1), (InstructionType.Fsub, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (6, 2), (InstructionType.Fsub, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (6, 3), (InstructionType.Fsub, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (6, 4), (InstructionType.Fsub, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (6, 5), (InstructionType.Fsub, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (6, 6), (InstructionType.Fsub, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (6, 7), (InstructionType.Fsub, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FSUBRP st(i), st(0)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fsubrp", "st(0), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fsubrp", "st(1), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fsubrp", "st(2), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fsubrp", "st(3), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fsubrp", "st(4), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fsubrp", "st(5), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fsubrp", "st(6), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fsubrp", "st(7), st(0)") },
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{ (7, 0), (InstructionType.Fsubr, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (7, 1), (InstructionType.Fsubr, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (7, 2), (InstructionType.Fsubr, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (7, 3), (InstructionType.Fsubr, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (7, 4), (InstructionType.Fsubr, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (7, 5), (InstructionType.Fsubr, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (7, 6), (InstructionType.Fsubr, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (7, 7), (InstructionType.Fsubr, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FDIVP st(i), st(0)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fdivp", "st(0), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fdivp", "st(1), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fdivp", "st(2), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fdivp", "st(3), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fdivp", "st(4), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fdivp", "st(5), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("fdivp", "st(6), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fdivp", "st(7), st(0)") },
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{ (4, 0), (InstructionType.Fdiv, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (4, 1), (InstructionType.Fdiv, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (4, 2), (InstructionType.Fdiv, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (4, 3), (InstructionType.Fdiv, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (4, 4), (InstructionType.Fdiv, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (4, 5), (InstructionType.Fdiv, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (4, 6), (InstructionType.Fdiv, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (4, 7), (InstructionType.Fdiv, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FDIVRP st(i), st(0)
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{ (RegisterIndex.Bp, RegisterIndex.A), ("fdivrp", "st(0), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.C), ("fdivrp", "st(1), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.D), ("fdivrp", "st(2), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.B), ("fdivrp", "st(3), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Sp), ("fdivrp", "st(4), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Bp), ("fdivrp", "st(5), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Si), ("fdivrp", "st(6), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Di), ("fdivrp", "st(7), st(0)") }
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{ (5, 0), (InstructionType.Fdivr, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (5, 1), (InstructionType.Fdivr, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (5, 2), (InstructionType.Fdivr, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (5, 3), (InstructionType.Fdivr, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (5, 4), (InstructionType.Fdivr, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (5, 5), (InstructionType.Fdivr, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (5, 6), (InstructionType.Fdivr, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (5, 7), (InstructionType.Fdivr, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) }
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};
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/// <summary>
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/// Initializes a new instance of the Int16OperationHandler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public Int16OperationHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public Int16OperationHandler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -121,30 +121,58 @@ public class Int16OperationHandler : InstructionHandler
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}
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// Read the ModR/M byte
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
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// Handle based on addressing mode
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if (mod != 3) // Memory operand
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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// Set the instruction type based on the reg field
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instruction.Type = MemoryInstructionTypes[(int)reg];
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// Need to modify the default dword ptr to word ptr for 16-bit integers
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instruction.Operands = memOperand.Replace("dword ptr", "word ptr");
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// For memory operands, we need to set the size to 16-bit
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// Create a new memory operand with 16-bit size
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var int16Operand = memoryOperand;
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int16Operand.Size = 16;
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// Set the structured operands
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instruction.StructuredOperands =
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[
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int16Operand
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];
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}
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else // Register operand (ST(i))
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{
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// Look up the register operation in our dictionary
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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// Look up the instruction type in the register operations dictionary
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if (RegisterOperations.TryGetValue(((int)reg, (int)rm), out var operation))
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{
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = operation.Operands;
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instruction.Type = operation.Type;
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// Create the FPU register operands
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var destOperand = OperandFactory.CreateFPURegisterOperand(operation.DestIndex);
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// Set the structured operands
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if (operation.SrcIndex.HasValue)
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{
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var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex.Value);
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instruction.StructuredOperands =
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[
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destOperand,
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srcOperand
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];
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}
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else
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{
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instruction.StructuredOperands =
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[
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destOperand
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];
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}
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}
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else
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{
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// Unknown instruction
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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instruction.Type = InstructionType.Unknown;
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instruction.StructuredOperands = [];
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}
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}
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