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https://github.com/sampletext32/ParkanPlayground.git
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Updated instruction handlers to use Type and StructuredOperands instead of Mnemonic and Operands
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bird_egop
@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -5,74 +7,72 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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public class Int32OperationHandler : InstructionHandler
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{
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// Memory operand mnemonics for DA opcode - operations on int32
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private static readonly string[] MemoryMnemonics =
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// Memory operand instruction types for DA opcode - operations on int32
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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"fiadd", // 0
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"fimul", // 1
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"ficom", // 2
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"ficomp", // 3
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"fisub", // 4
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"fisubr", // 5
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"fidiv", // 6
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"fidivr" // 7
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InstructionType.Unknown, // fiadd - not in enum
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InstructionType.Unknown, // fimul - not in enum
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InstructionType.Unknown, // ficom - not in enum
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InstructionType.Unknown, // ficomp - not in enum
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InstructionType.Unknown, // fisub - not in enum
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InstructionType.Unknown, // fisubr - not in enum
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InstructionType.Unknown, // fidiv - not in enum
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InstructionType.Unknown // fidivr - not in enum
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex SrcIndex)> RegisterOperations = new()
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{
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// FCMOVB st(0), st(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("fcmovb", "st(0), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("fcmovb", "st(0), st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("fcmovb", "st(0), st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("fcmovb", "st(0), st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("fcmovb", "st(0), st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("fcmovb", "st(0), st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("fcmovb", "st(0), st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("fcmovb", "st(0), st(7)") },
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{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCMOVE st(0), st(i)
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{ (RegisterIndex.B, RegisterIndex.A), ("fcmove", "st(0), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.C), ("fcmove", "st(0), st(1)") },
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{ (RegisterIndex.B, RegisterIndex.D), ("fcmove", "st(0), st(2)") },
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{ (RegisterIndex.B, RegisterIndex.B), ("fcmove", "st(0), st(3)") },
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{ (RegisterIndex.B, RegisterIndex.Sp), ("fcmove", "st(0), st(4)") },
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{ (RegisterIndex.B, RegisterIndex.Bp), ("fcmove", "st(0), st(5)") },
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{ (RegisterIndex.B, RegisterIndex.Si), ("fcmove", "st(0), st(6)") },
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{ (RegisterIndex.B, RegisterIndex.Di), ("fcmove", "st(0), st(7)") },
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{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCMOVBE st(0), st(i)
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{ (RegisterIndex.C, RegisterIndex.A), ("fcmovbe", "st(0), st(0)") },
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{ (RegisterIndex.C, RegisterIndex.C), ("fcmovbe", "st(0), st(1)") },
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{ (RegisterIndex.C, RegisterIndex.D), ("fcmovbe", "st(0), st(2)") },
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{ (RegisterIndex.C, RegisterIndex.B), ("fcmovbe", "st(0), st(3)") },
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{ (RegisterIndex.C, RegisterIndex.Sp), ("fcmovbe", "st(0), st(4)") },
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{ (RegisterIndex.C, RegisterIndex.Bp), ("fcmovbe", "st(0), st(5)") },
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{ (RegisterIndex.C, RegisterIndex.Si), ("fcmovbe", "st(0), st(6)") },
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{ (RegisterIndex.C, RegisterIndex.Di), ("fcmovbe", "st(0), st(7)") },
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{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCMOVU st(0), st(i)
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{ (RegisterIndex.D, RegisterIndex.A), ("fcmovu", "st(0), st(0)") },
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{ (RegisterIndex.D, RegisterIndex.C), ("fcmovu", "st(0), st(1)") },
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{ (RegisterIndex.D, RegisterIndex.D), ("fcmovu", "st(0), st(2)") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fcmovu", "st(0), st(3)") },
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{ (RegisterIndex.D, RegisterIndex.Sp), ("fcmovu", "st(0), st(4)") },
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{ (RegisterIndex.D, RegisterIndex.Bp), ("fcmovu", "st(0), st(5)") },
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{ (RegisterIndex.D, RegisterIndex.Si), ("fcmovu", "st(0), st(6)") },
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{ (RegisterIndex.D, RegisterIndex.Di), ("fcmovu", "st(0), st(7)") },
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{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// Special case
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{ (RegisterIndex.Di, RegisterIndex.B), ("fucompp", "") }
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{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) }
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};
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/// <summary>
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/// Initializes a new instance of the Int32OperationHandler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public Int32OperationHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public Int32OperationHandler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -100,30 +100,43 @@ public class Int32OperationHandler : InstructionHandler
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}
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// Read the ModR/M byte
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
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// Handle based on addressing mode
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if (mod != 3) // Memory operand
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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// Set the instruction type based on the reg field
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instruction.Type = MemoryInstructionTypes[(int)reg];
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// Set the operands (already has dword ptr prefix for int32)
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instruction.Operands = memOperand;
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// Set the structured operands
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instruction.StructuredOperands =
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[
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memoryOperand
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];
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}
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else // Register operand (ST(i))
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{
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// Look up the register operation in our dictionary
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// Look up the instruction type in the register operations dictionary
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = operation.Operands;
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instruction.Type = operation.Type;
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// Create the FPU register operands
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var destOperand = OperandFactory.CreateFPURegisterOperand(operation.DestIndex);
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var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex);
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// Set the structured operands
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instruction.StructuredOperands =
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[
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destOperand,
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srcOperand
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];
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}
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else
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{
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// Unknown instruction
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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instruction.Type = InstructionType.Unknown;
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instruction.StructuredOperands = [];
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}
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}
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