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https://github.com/sampletext32/ParkanPlayground.git
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Updated instruction handlers to use Type and StructuredOperands instead of Mnemonic and Operands
This commit is contained in:
bird_egop
@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -18,68 +20,79 @@ public class LoadStoreFloat64Handler : InstructionHandler
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"fnstsw" // 7
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];
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// Memory operand instruction types for DD opcode
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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InstructionType.Fld, // 0
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InstructionType.Unknown, // 1
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InstructionType.Fst, // 2
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InstructionType.Fstp, // 3
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InstructionType.Unknown, // 4 - frstor not in enum
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InstructionType.Unknown, // 5
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InstructionType.Unknown, // 6 - fnsave not in enum
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InstructionType.Fnstsw // 7
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex OperandIndex)> RegisterOperations = new()
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{
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// FFREE ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("ffree", "st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("ffree", "st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("ffree", "st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("ffree", "st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("ffree", "st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("ffree", "st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("ffree", "st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("ffree", "st(7)") },
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{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) },
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// FST ST(i)
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{ (RegisterIndex.C, RegisterIndex.A), ("fst", "st(0)") },
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{ (RegisterIndex.C, RegisterIndex.C), ("fst", "st(1)") },
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{ (RegisterIndex.C, RegisterIndex.D), ("fst", "st(2)") },
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{ (RegisterIndex.C, RegisterIndex.B), ("fst", "st(3)") },
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{ (RegisterIndex.C, RegisterIndex.Sp), ("fst", "st(4)") },
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{ (RegisterIndex.C, RegisterIndex.Bp), ("fst", "st(5)") },
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{ (RegisterIndex.C, RegisterIndex.Si), ("fst", "st(6)") },
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{ (RegisterIndex.C, RegisterIndex.Di), ("fst", "st(7)") },
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{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Fst, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Fst, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Fst, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Fst, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Fst, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Fst, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Fst, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Fst, FpuRegisterIndex.ST7) },
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// FSTP ST(i)
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{ (RegisterIndex.D, RegisterIndex.A), ("fstp", "st(0)") },
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{ (RegisterIndex.D, RegisterIndex.C), ("fstp", "st(1)") },
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{ (RegisterIndex.D, RegisterIndex.D), ("fstp", "st(2)") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fstp", "st(3)") },
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{ (RegisterIndex.D, RegisterIndex.Sp), ("fstp", "st(4)") },
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{ (RegisterIndex.D, RegisterIndex.Bp), ("fstp", "st(5)") },
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{ (RegisterIndex.D, RegisterIndex.Si), ("fstp", "st(6)") },
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{ (RegisterIndex.D, RegisterIndex.Di), ("fstp", "st(7)") },
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{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Fstp, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Fstp, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Fstp, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Fstp, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Fstp, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Fstp, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Fstp, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Fstp, FpuRegisterIndex.ST7) },
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// FUCOM ST(i)
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{ (RegisterIndex.Si, RegisterIndex.A), ("fucom", "st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.C), ("fucom", "st(1)") },
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{ (RegisterIndex.Si, RegisterIndex.D), ("fucom", "st(2)") },
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{ (RegisterIndex.Si, RegisterIndex.B), ("fucom", "st(3)") },
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{ (RegisterIndex.Si, RegisterIndex.Sp), ("fucom", "st(4)") },
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{ (RegisterIndex.Si, RegisterIndex.Bp), ("fucom", "st(5)") },
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{ (RegisterIndex.Si, RegisterIndex.Si), ("fucom", "st(6)") },
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{ (RegisterIndex.Si, RegisterIndex.Di), ("fucom", "st(7)") },
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{ (RegisterIndex.Si, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.Si, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.Si, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.Si, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.Si, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.Si, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) },
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// FUCOMP ST(i)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fucomp", "st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fucomp", "st(1)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fucomp", "st(2)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fucomp", "st(3)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomp", "st(4)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomp", "st(5)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomp", "st(6)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomp", "st(7)") }
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{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) }
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};
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/// <summary>
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/// Initializes a new instance of the LoadStoreFloat64Handler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public LoadStoreFloat64Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public LoadStoreFloat64Handler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -94,54 +107,75 @@ public class LoadStoreFloat64Handler : InstructionHandler
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}
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/// <summary>
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/// Decodes a floating-point instruction for load/store float64 operations
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/// Decodes a floating point instruction with the DD opcode
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/// </summary>
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/// <param name="opcode">The opcode of the instruction</param>
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/// <param name="instruction">The instruction object to populate</param>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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{
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// Check if we have enough bytes for the ModR/M byte
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if (!Decoder.CanReadByte())
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{
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return false;
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}
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// Read the ModR/M byte
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM(true); // true for 64-bit operand
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var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
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// Handle based on addressing mode
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// Set the instruction type based on the mod and reg fields
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if (mod != 3) // Memory operand
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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instruction.Type = MemoryInstructionTypes[(int)reg];
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
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// For memory operands, the instruction depends on the reg field
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switch (reg)
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{
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// Keep the qword ptr prefix from ModRMDecoder
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instruction.Operands = memOperand;
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}
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else // frstor, fnsave, fnstsw
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{
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// Remove the qword ptr prefix for these operations
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instruction.Operands = memOperand.Replace("qword ptr ", "");
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case RegisterIndex.A: // FLD m64real
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// Set the structured operands
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memoryOperand.Size = 64; // Set size to 64 bits for double precision
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instruction.StructuredOperands =
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[
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memoryOperand
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];
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return true;
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case RegisterIndex.C: // FST m64real
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case RegisterIndex.D: // FSTP m64real
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// Set the structured operands
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memoryOperand.Size = 64; // Set size to 64 bits for double precision
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instruction.StructuredOperands =
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[
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memoryOperand
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];
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return true;
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default:
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// For unsupported instructions, just set the type to Unknown
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instruction.Type = InstructionType.Unknown;
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return true;
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}
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}
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else // Register operand (ST(i))
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else // Register operand (mod == 3)
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{
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// Look up the register operation in our dictionary
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// Look up the instruction type in the register operations dictionary
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = operation.Operands;
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}
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else
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{
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// Unknown instruction
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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instruction.Type = operation.Type;
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// Create the FPU register operand
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var fpuRegisterOperand = OperandFactory.CreateFPURegisterOperand(operation.OperandIndex);
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// Set the structured operands
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instruction.StructuredOperands =
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[
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fpuRegisterOperand
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];
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return true;
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}
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}
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return true;
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return false;
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}
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}
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